W48S87-04_技术文档

PRELIMINARY

W48S87-04

Spread Spectrum 3 DIMM Desktop Clock

Features

Key Specifications

• Outputs

±0.5% Spread Spectrum Modulation: ......................... ±0.5%

— 4 CPU Clock (2.5V or 3.3V, 50 to 83.3 MHz)

— 7 PCI (3.3V)

— 1 48-MHz for USB (3.3V)

— 1 24-MHz for Super I/O (3.3V)

— 2 REF (3.3V)

Jitter (Cycle-to-Cycle):.................................................250 ps

Duty Cycle: ................................................................ 45-55%

CPU-PCI Skew:........................................................1 to 4 ns

PCI-PCI or CPU-CPU Skew:.......................................250 ps

[1]

— 1 IOAPIC (2.5V or 3.3V)

— 12 SDRAM

Table 1. Pin Selectable Frequency

Input Address

CPU, SDRAM

Clocks (MHz)

PCI Clocks

(MHz)

• Serial data interface provides additional frequency

selection, individual clock output disable, and other

functions

• Smooth transition supports dynamic frequency

assignment

• Frequency selection not affected during power

down/up cycle

• Supports a variety of power-saving options

• 3.3V operation

FS2

0

FS1

0

FS0

0

50.0

75.0

83.3

68.5

55.0

75.0

60.0

66.8

25.0

32.0

41.65

34.25

27.5

37.5

30.0

33.4

0

1

0

1

0

1

0

1

0

1

• Available in 48-pin SSOP (300 mils)

1

0

1

Pin Configuration^[2]

Block Diagram

Device

Control

SDATA

SCLOCK

Serial Port

XTAL OSC

VDDL1

IOAPIC

REF1(CPU_STOP#)

GND

CPU0

CPU1

VDDL2

CPU2

CPU3

VDD1

REF0/CPU3.3#_2.5

GND

1

2

3

4

5

6

7

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

PLL Ref

Freq

X1

X2

VDD2

X1

X2

VDD1

REF0/CPU3.3#_2.5

REF1(CPU_STOP#)

CPU Clock

PCI_F/FS1

PCI0/FS2

GND

I/O

CPU3.3#_2.5

Mode Control

8

9

FS0

FS1

FS2

MODE

Freq

Select

PCI1

PCI2

PCI3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

GND

VDDL1

IOAPIC

SDRAM0

SDRAM1

VDD3

SDRAM2

SDRAM3

GND

SDRAM4

SDRAM5

VDD3

SDRAM6

SDRAM7

GND

PCI4

VDD2

PCI5(PWR_DWN#)

PLL1

VDDL2

CPU0:3

GND

Stop

Clock

Cntrl

4

SDRAM11

SDRAM10

VDD3

SDRAM9

SDRAM8

GND

VDD3

CPU_STOP#

12

SDRAM0:11

48MHZ/FS0

24MHZ/MODE

SDATA

SCLOCK

÷2

VDD2

PCI_F/FS1

PCI0/FS2

PCI1:4

I/O

4

PCI5(PWR_DWN#)

MODE

Power Down

Control

PWR_DWN#

VDD1

÷2

PLL2

48MHZ/FS0

I/O

24MHZ/MODE

÷4

Notes:

1. Additional frequency selections provided by serial data interface; refer to Table 5 on page 10.

2. Signal names in parenthesis denotes function is selectable through mode pin register strapping.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

October 19, 1999, rev. **

PRELIMINARY

W48S87-04

Pin Definitions

No.

Type

Pin Name

Pin Description

CPU0:3

44, 43, 41,

40

O

CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled

by the CPU_STOP# control pin. Output voltage swing is controlled by voltage

applied to VDDL2 and output characteristics are adjusted by input

CPU3.3#_2.5.

PCI_F/FS1

PCI0/FS2

7

8

I/O

Fixed PCI Clock Output and Frequency Selection Bit 1: As an output, this

pin works in conjunction with PCI0:5. Output voltage swing is controlled by

voltage applied to VDD2.

When an input, this pin functions as part of the frequency selection address.

The value of FS0:2 determines the power-up default frequency of device output

clocks as per the Table 1, “Pin Selectable Frequency” on page 1.

I/O

PCI Bus Clock Output 0 and Frequency Selection Bit 2: As an output, this

pin works in conjunction with PCI1:5 and PCI_F. Output voltage swing is con-

trolled by voltage applied to VDD2.

When an input, this pin functions as part of the frequency selection address.

The value of FS0:2 determines the power-up default frequency of device output

clocks as per the Table 1, “Pin Selectable Frequency” on page 1.

PCI1:4

10, 11, 12,

13

O

PCI Bus Clock Outputs 1 through 4: Output voltage swing is controlled by

voltage applied to VDD2.

PCI5(PWR_DWN#)

15

I/O

PCI Bus Clock Output5 or Power-Down Control: As an output, this pin works

in conjunction with PCI0:4 and PCI_F. Output voltage swing is controlled by

voltage applied to VDD2.

If programmed as an input (refer to MODE pin description), this pin is used for

power-down control. When LOW, the device goes into a low-power standby

condition. All outputs are actively held LOW while in power-down. CPU,

SDRAM, and PCI clock outputs are stopped LOW after completing a full clock

cycle (2–4 CPU clock cycle latency). When brought HIGH, CPU, SDRAM, and

PCI outputs start with a full clock cycle at full operating frequency (3 ms max-

imum latency).

SDRAM0:11

38, 37, 35,

34, 32, 31,

29, 28, 21,

20, 18, 17

O

SDRAM Clock Outputs 0 through 11: These twelve SDRAM clock outputs

run synchronous to the CPU clock outputs. Output voltage swing is controlled

by voltage applied to VDD3.

IOAPIC

47

O

I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output

voltage swing is controlled by VDDL1.

48MHZ/FS0

26

I/O

48-MHz Output and Frequency Selection Bit 0: Fixed clock output that de-

faults to 48 MHz following device power-up. Output voltage swing is controlled

by voltage applied to VDD1.

When an input, this pin functions as part of the frequency selection address.

The value of FS0:2 determines the power-up default frequency of device output

clocks as per the Table 1, “Pin Selectable Frequency” on page 1.

24MHZ/MODE

25

I/O

24-MHz Output and Mode Control Input: Fixed clock output that defaults to

24 MHz following device power-up. Output voltage swing is controlled by volt-

age applied to VDD1.

When an input, this pin is used for pin programming selection. It determines

the functions for pins 15 and 46:

MODE

Pin 15

Pin 46

0

1

PWR_DWN# (input)

PCI5 (output)

CPU_STOP# (input)

REF1 (output)

2

PRELIMINARY

W48S87-04

Pin Definitions (continued)

No.

Type

Pin Name

Pin Description

REF0/CPU3.3#_2.5

2

I/O

Fixed 14.318-MHz Output 0 and CPU Output Voltage Swing Selection

Input: As an output, this pin is used for various system applications. Output

voltage swing is controlled by voltage applied to VDD1. REF0 is stronger than

REF1 and should be used for driving ISA slots.

When an input, this pin selects the CPU clock output buffer characteristics that

are optimized for either 3.3V or 2.5V operation.

CPU3.3#_2.5

VDDQ2 Voltage (CPU0:3 Swing)

0

1

3.3V

2.5V

This input adjusts CPU clock output impedance so that a nominal 20Ω output

impedance is maintained. This eliminates or reduces the need to adjust exter-

nal clock tuning components when changing VDDL2 voltage. CPU clock phase

is also adjusted so that both CPU and SDRAM and CPU-to-PCI clock skew is

maintained over the two VDDL2 voltage options. This input does not adjust

IOAPIC clock output characteristics.

REF1(CPU_Stop#)

46

I/O

Fixed 14.318-MHz Output 0 or CPU Clock Output Stop Control: Used for

various system applications. Output voltage swing is controlled by voltage ap-

plied to VDD1. REF0 is stronger than REF1 and should be used for driving ISA

slots.

If programmed as an input (refer to MODE pin description), this pin is used for

stopping the CPU clock outputs. When brought LOW, clock outputs CPU0:3

are stopped LOW after completing a full clock cycle (2–3 CPU clock latency).

When brought HIGH, clock outputs CPU0:3 are starting beginning with a full

clock cycle (2–3 CPU clock latency).

X1

4

I

Crystal Connection or External Reference Frequency Input: This pin has

dual functions. It can be used as an external 14.318-MHz crystal connection

or as an external reference frequency input.

X2

5

I

Crystal Connection: An input connection for an external 14.318-MHz crystal.

If using an external reference, this pin must be left unconnected.

SDATA

SCLOCK

VDD1

VDD2

VDDL1

VDDL2

VDD3

GND

23

I

Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data

Interface section that follows.

24

I

Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data

Interface section that follows.

1

6,14

P

G

Power Connection: Power supply for crystal oscillator and REF0:1 output

buffers. Connected to 3.3V supply.

Power Connection: Power supply for PCI clock output buffers. Connected to

3.3V supply.

48

Power Connection: Power supply for IOAPIC output buffer. Connected to 2.5V

or 3.3V supply.

42

Power Connection: Power supply for CPU clock output buffers. Connected to

2.5V or 3.3V supply.

19, 30, 36

Power Connection: Power supply for SDRAM clock output buffers. Connected

to 3.3V supply.

3, 9, 16, 22,

27, 33, 39,

45

Ground Connection: Connect all ground pins to the common system ground

plane.

3

PRELIMINARY

W48S87-04

I/O pins are three-stated, allowing the output strapping resistor

on each l/O pin to pull the pin and its associated capacitive

clock load to either a logic HIGH or LOW state. At the end of

the 2-ms period, the established logic 0 or 1 condition of each

l/O is pin is then latched. Next the output buffers are enabled,

which converts the l/O pins into operating clock outputs. The

Overview

The W48S87-04, a motherboard clock synthesizer, can pro-

vide either a 2.5V or 3.3V CPU clock swing, making it suitable

for a variety of CPU options. Twelve SDRAM clocks are pro-

vided in phase with the CPU clock outputs. This provides clock

support for up to three SDRAM DlMMs. Fixed output frequency

clocks are provided for other system functions.

2-ms timer is started when V

reaches 2.0V. The input bits

DD

can only be reset by turning V off and then back on again.

DD

It should be noted that the strapping resistors have no signifi-

cant effect on clock output signal integrity. The drive imped-

ance of both clock outputs is <40Ω (nominal) which is minimal-

Functional Description

I/O Pin Operation

ly affected by the 10-kΩ strap to ground or V . As with the

DD

Pins 2, 7, 8, 25, and 26 are dual-purpose l/O pins. Upon power-

up these pins act as logic inputs, allowing the determination of

assigned device functions. A short time after power-up, the

logic state of these pins is latched and the pins then become

clock outputs. This feature reduces device pin count by com-

bining clock outputs with input select pins.

series termination resistor, the output strapping resistor should

be placed as close to the l/O pin as possible in order to keep

the interconnecting trace short. The trace from the resistor to

ground or VDD should be kept less than two inches in length

to prevent system noise coupling during input logic sampling.

When the clock outputs are enabled following the 2-ms input

period, target (normal) output frequency is delivered assuming

An external 10-kΩ “strapping” resistor is connected between

each l/O pin and ground or V

. Connection to ground sets a

sets a latch to “1”. Figure 1 and

DD3

that V has stabilized. If V

has not yet reached full value,

DD

latch to “0”, connection to V

DD3

output frequency initially may be below target but will increase

Figure 2 show two suggested methods for strapping resistor

connection.

to target once V voltage has stabilized. In either case, a

DD

short output clock cycle may be produced from the CPU clock

outputs when the outputs are enabled.

Upon W48S87-04 power-up, the first 2 ms of operation is used

for input logic selection. During this period, these dual-purpose

V_DD

Output Strapping Resistor

Series Termination Resistor

10 k

Ω

(Load Option 1)

Clock Load

W48S87-04

Output

22

Ω

Buffer

Power-on

Reset

Timer

Hold

Output

Low

Output Three-state

10 k

Ω

(Load Option 0)

Q

D

Data

Latch

Figure 1. Input Logic Selection Through Resistor Load Option

Jumper Options

Output Strapping Resistor

Series Termination Resistor

V_DD

10 k

Ω

Clock Load

W48S87-04

R

Output

Buffer

Power-on

Reset

Timer

Resistor Value R

Output

IOAPIC, SDRAM

All other clock outputs

Hold

Output

Low

Output Three-state

39

33

Ω

Q

D

Data

Latch

Figure 2. Input Logic Selection Through Jumper Option

4

PRELIMINARY

W48S87-04

CPU/PCI Frequency Selection

the internal crystal oscillator. When using an external clock

signal, pin X1 is used as the clock input and pin X2 is left open.

CPU frequency is selected with I/O pins 26, 7, and 8

(48MHz/FS0, PCI_F/FS1, and PCI0/FS2, respectively). Refer

to Table 1 for CPU/PCI frequency programming information.

Additional frequency selections are available through the seri-

al data interface. Refer to Table 5 on page 10.

The input threshold voltage of pin X1 is V /2.

DD

The internal crystal oscillator is used in conjunction with a

quartz crystal connected to device pins X1 and X2. This forms

a parallel resonant crystal oscillator circuit. The W48S87-04

incorporates the necessary feedback resistor and crystal load

capacitors. Including typical stray circuit capacitance, the total

load presented to the crystal is approximately 20 pF. For opti-

mum frequency accuracy without the addition of external ca-

pacitors, a parallel-resonant mode crystal specifying a load of

20 pF should be used. This will typically yield reference fre-

quency accuracies within ±100 ppm.

Output Buffer Configuration

Clock Outputs

All clock outputs are designed to drive serial terminated clock

lines. The W48S87-04 outputs are CMOS-type, which provide

rail-to-rail output swing. To accommodate the limited voltage

swing required by some processors, the output buffers of

CPU0:3 use a special VDDL2 power supply pin that can be

tied to 2.5V nominal.

Dual Supply Voltage Operation

The W48S87-04 is designed for dual power supply operation.

Supply pins VDD1, VDD2, and VDD3 are connected to a 3.3V

supply and supply power to the internal core circuit and to the

clock output buffers, except for outputs CPU0:3 and IOAPIC.

Supply pins VDDL1 and VDDL2 may be connected to either a

2.5V or 3.3V supply.

Crystal Oscillator

The W48S87-04 requires one input reference clock to synthe-

size all output frequencies. The reference clock can be either

an externally generated clock signal or the clock generated by

5

PRELIMINARY

W48S87-04

The output clock is modulated with a waveform depicted in

Figure 4. This waveform, as discussed in “Spread Spectrum

Clock Generation for the Reduction of Radiated Emissions” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions. The

deviation selected for this chip is ±0.5% of the center frequen-

cy. Figure 4 details the Cypress spreading pattern. Cypress

does offer options with more spread and greater EMI reduc-

tion. Contact your local Sales representative for details on

these devices.

Spread Spectrum Generator

The device generates a clock that is frequency modulated in

order to increase the bandwidth that it occupies. By increasing

the bandwidth of the fundamental and its harmonics, the am-

plitudes of the radiated electromagnetic emissions are re-

duced. This effect is depicted in Figure 3.

As depicted in Figure 3, a harmonic of a modulated clock has

a much lower amplitude than that of an unmodulated signal.

The reduction in amplitude is dependent on the harmonic num-

ber and the frequency deviation or spread. The equation for

the reduction is

Spread Spectrum clocking is activated or deactivated by se-

lecting the appropriate values for bits 1–0 in data byte 0 of the

2

I C data stream. Refer to Table 4 for more details.

dB = 6.5 + 9*log (P) + 9*log (F)

10

Where P is the percentage of deviation and F is the frequency

in MHz where the reduction is measured.

5dB/div

SSFTG

Typical Clock

Frequency Span (MHz)

+1.0

-SS%

+SS%

Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation

MAX (+.0.5%)

MIN. (–0.5%)

Figure 4. Typical Modulation Profile

6

PRELIMINARY

W48S87-04

of the chipset. Clock device register changes are normally

made upon system initialization, if any are required. The inter-

face can also be used during system operation for power man-

agement functions. Table 2 summarizes the control functions

of the serial data interface.

Serial Data Interface

The W48S87-04 features a two-pin, serial data interface that

can be used to configure internal register settings that control

particular device functions. Upon power-up, the W48S87-04

initializes with default register settings, therefore the use of this

serial data interface is optional. The serial interface is write-

only (to the clock chip) and is the dedicated function of device

pins SDATA and SCLOCK. In motherboard applications,

SDATA and SCLOCK are typically driven by two logic outputs

Operation

Data is written to the W48S87-04 in ten bytes of eight bits

each. Bytes are written in the order shown in Table 3.

Table 2. Serial Data Interface Control Functions Summary

Control Function

Description

Common Application

Clock Output Disable

Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI

abled outputs are actively held LOW.

and system power. Examples are clock out-

puts to unused SDRAM DIMM socket or PCI

slot.

CPU Clock Frequency

Selection

ProvidesCPU/PCIfrequency selections beyond the For alternate CPU devices, and power man-

50- and 66.8-MHz selections that are provided by agement options. Smooth frequency transi-

the FS0:2 power-on default selection. Frequency is tion allows CPU frequency change under nor-

changed in a smooth and controlled fashion.

mal system operation.

Output Three-state

Test Mode

Puts all clock outputs into a high-impedance state. Production PCB testing.

All clock outputs toggle in relation with X1 input,

Production PCB testing.

internal PLL is bypassed. Refer to Table 4.

(Reserved)

Reserved function for future device revision or pro- No user application. Register bit must be writ-

duction device testing.

ten as 0.

Table 3. Byte Writing Sequence

Byte Sequence

Byte Name

Bit Sequence

Byte Description

1

Slave Address 11010010

Commands the W48S87-04 to accept the bits in Data Bytes 0–6 for

internal register configuration. Since other devices may exist on the

same common serial data bus, it is necessary to have a specific slave

address for each potential receiver. The slave receiver address for the

W48S87-04 is 11010010. Register setting will not be made if the Slave

Address is not correct (or is for an alternate slave receiver).

2

3

Command

Code

Don’t Care

Unused by the W48S87-04, therefore bit values are ignored (“don’t

care”). This byte must be included in the data write sequence to maintain

proper byte allocation. The Command Code Byte is part of the standard

serial communication protocol and may be used when writing to another

addressed slave receiver on the serial data bus.

Byte Count

Unused by the W48S87-04, therefore bit values are ignored (“don’t

care”). This byte must be included in the data write sequence to maintain

proper byte allocation. The Byte Count Byte is part of the standard serial

communication protocol and may be used when writing to another ad-

dressed slave receiver on the serial data bus.

4

5

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Refer to Table 4 The data bits in these bytes set internal W48S87-04 registers that con-

trol device operation. The data bits are only accepted when the Address

Byte bit sequence is 11010010, as noted above. For description of bit

control functions, refer to Table 4, Data Byte Serial Configuration Map.

6

7

8

9

10

7

PRELIMINARY

W48S87-04

Writing Data Bytes

7. Table 4 gives the bit formats for registers located in Data

Bytes 0–6. Table 5 details additional frequency selections that

are available through the serial data interface. Table 6 details

the select functions for Byte 0, bits 1 and 0.

Each bit in the data bytes control a particular device function

except for the “reserved” bits which must be written as a logic

0. Bits are written MSB (most significant bit) first, which is bit

Table 4. Data Bytes 0–6 Serial Configuration Map

Affected Pin

Bit Control

Bit(s)

Pin No.

Pin Name

Control Function

0

1

Default

Data Byte 0

7

6

5

4

3

--

(Reserved)

--

0

BYT0_SEL2

BYT0_SEL1

BYT0_SEL0

BYT0 _FS#

Refer to Table 5

Frequency

Controlled by

FS (2:0)

Controlled by

BYT0_SEL (2:0)

2

22

--

(Reserved)

Bit 1 Bit 0

0

1–0

--

Function (See Table 6 for function details)

Normal Operation

Test Mode

Spread Spectrum On

All Outputs Three-stated

00

0

1

0

1

0

1

Data Byte 1

7

26

25

--

48MHZ

24MHZ

--

Clock Output Disable

(Reserved)

Low

--

Active

--

1

0

1

6

5

4

--

(Reserved)

--

3

40

41

43

44

CPU3

CPU2

CPU1

CPU0

Clock Output Disable

Low

Active

2

1

0

Data Byte 2

7

6

5

4

3

2

1

0

--

7

--

(Reserved)

--

0

1

PCI_F

PCI5

PCI4

PCI3

PCI2

PCI1

PCI0

Clock Output Disable

Low

Active

15

13

12

11

10

8

PRELIMINARY

W48S87-04

Table 4. Data Bytes 0–6 Serial Configuration Map (continued)

Affected Pin

Bit Control

Bit(s)

Pin No.

Pin Name

Control Function

0

1

Default

Data Byte 3

7

28

29

31

32

34

35

37

38

SDRAM7

SDRAM6

SDRAM5

SDRAM4

SDRAM3

SDRAM2

SDRAM1

SDRAM0

Clock Output Disable

Low

Active

1

6

5

4

3

2

1

0

Data Byte 4

7

--

(Reserved)

--

0

1

6

5

--

4

--

3

17

18

20

21

SDRAM11 Clock Output Disable

SDRAM10 Clock Output Disable

Low

Active

2

1

SDRAM9

SDRAM8

Clock Output Disable

0

Data Byte 5

7

--

(Reserved)

--

0

1

0

1

5

(Reserved)

5

--

(Reserved)

--

4

47

--

IOAPIC

--

Clock Output Disable

(Reserved)

Low

--

Active

--

3

2

--

(Reserved)

--

1

46

2

REF1

REF0

Clock Output Disable

Low

Active

0

Data Byte 6

7

6

5

4

3

2

1

0

--

(Reserved)

--

0

9

PRELIMINARY

W48S87-04

Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes

Input Conditions

Output Frequency

Data Byte 0, Bit 3 = 1

Bit 6

BYT0_SEL2

Bit 5

BYT0_SEL1

Bit 4

BYT0_SEL0

CPU, SDRAM Clocks

(MHz)

PCI Clocks

(MHz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

50

25

32

75.0

83.3

68.5

55.0

75.0

60.0

66.8

41.65

34.25

27.5

37.5

30.0

33.4

Table 6. Select Function for Data Byte 0, Bits 0:1

Input Conditions

Output Conditions

PCI_F,

Data Byte 0

CPU0:3,

Function

Normal Operation

Test Mode

Bit 1

Bit 0

SRAM0:11

PCI0:5

Note 3

X1/4

REF0:1, IOAPIC

48/24MHZ

0

1

0

1

0

Note 3

X1/2

14.318 MHz

X1

48/24 MHz

Note 4

Spread Spectrum

Note 3

14.318 MHz

48/24 MHz

SS±0.5%

Three-state

1

Hi-Z

Note:

3. CPU, SDRAM, and PCI frequency selections are listed in Table 1 and Table 5.

4. In Test Mode, the 48/24MHz clock outputs are:

- X1/2 for 48-MHz output.

- X1/4 for 24-MHz output.

10

PRELIMINARY

W48S87-04

Although the W48S87-04 is a receive-only device (no data

write-back capability), it does transmit an “acknowledge” data

pulse after each byte is received. Thus, the SDATA line can

both transmit and receive data.

How To Use the Serial Data Interface

Electrical Requirements

Figure 5 illustrates electrical characteristics for the serial inter-

face bus used with the W48S87-04. Devices send data over

the bus with an open drain logic output that can (a) pull the bus

line LOW, or (b) let the bus default to logic 1. The pull-up resis-

tors on the bus (both clock and data lines) establish a default

logic 1. All bus devices generally have logic inputs to receive

data.

The pull-up resistor should be sized to meet the rise and fall

times specified in AC parameters, taking into consideration to-

tal bus line capacitance.

VDD

Ω

~ 2k

SERIAL BUS DATA LINE

SERIAL BUS CLOCK LINE

SDCLK

SDATA

SCLOCK

SDATA

CLOCK IN

DATA IN

CLOCK IN

DATA IN

N

CLOCK OUT

DATA OUT

CHIP SET

(SERIAL BUS MASTER TRANSMITTER)

CLOCK DEVICE

(SERIAL BUS SLAVE RECEIVER)

Figure 5. Serial Interface Bus Electrical Characteristics

11

PRELIMINARY

W48S87-04

Signaling Requirements

Sending Data to the W48S87-04

As shown in Figure 6, valid data bits are defined as stable logic

0 or 1 condition on the data line during a clock HIGH (logic 1)

pulse. A transitioning data line during a clock HIGH pulse may

be interpreted as a start or stop pulse (it will be interpreted as

a start or stop pulse if the start/stop timing parameters are

met).

The device accepts data once it has detected a valid start bit

and address byte sequence. Device functionality is changed

upon the receipt of each data bit (registers are not double buff-

ered). Partial transmission is allowed meaning that a transmis-

sion can be truncated as soon as the desired data bits are

transmitted (remaining registers will be unmodified). Transmis-

sion is truncated with either a stop bit or new start bit (restart

condition).

A write sequence is initiated by a “start bit” as shown in Figure

7. A “stop bit” signifies that a transmission has ended.

As stated previously, the W48S87-04 sends an “acknowledge”

pulse after receiving eight data bits in each byte as shown in

Figure 8.

SDATA

SCLOCK

Valid

Data

Bit

Change

of Data Allowed

Figure 6. Serial Data Bus Valid Data Bit

SDATA

SCLOCK

Start

Bit

Stop

Bit

Figure 7. Serial Data Bus Start and Stop Bit

12

PRELIMINARY

W48S87-04

Absolute Maximum Ratings

Stresses greater than those listed in this table may cause per-

manent damage to the device. These represent a stress rating

above those specified in the operating sections of this specifi-

cation is not implied. Maximum conditions for extended peri-

ods may affect reliability.

only. Operation of the device at these or any other conditions

.

Parameter

Description

Voltage on any pin with respect to GND

Storage Temperature

Rating

–0.5 to +7.0

–65 to +150

0 to +70

Unit

V

, V

DD IN

T

°C

kV

STG

T

Operating Temperature

A

T

Ambient Temperature under Bias

Input ESD Protection

–55 to +125

2 (min.)

B

ESD

PROT

Crystal Oscillator

Parameter

Description

Test Condition

Min.

Typ.

1.65

20

Max.

Unit

V

[5]

V

X1 Input Threshold Voltage

TH

C

Load Capacitance, Imposed on

pF

LOAD

[6]

External Crystal

[7]

C

X1 Input Capacitance

Pin X2 unconnected

40

pF

IN,X1

(CPU3.3#_2.5 Input = 0)

3.3V DC Electrical Characteristics

T = 0°C to +70°C, VDD1:3 = VDDL1:2 = 3.3V±5% (3.135–3.465V)

A

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Supply Current

I

Combined 3.3V Supply Current

CPU0:3 =66.8 MHz

Outputs Loaded

160

mA

DD

[8]

Logic Inputs (All referenced to V

= 3.3V)

DDQ3

V

Input Low Voltage

Input High Voltage

0.8

V

IL

2.0

IH

[9]

I

Input Low Current

Input High Current

10

µA

IL

IH

[9]

Clock Outputs

Output Low Voltage

V

I

= 1 mA

50

mV

V

OL

V

Output High Voltage

Output Low Current

= –1 mA

3.1

55

OH

[10]

I

CPU0:3

V

= 1.5V

75

110

75

105

155

105

190

90

mA

OL

SDRAM0:11

PCI_F, PCI0:5

IOAPIC

80

55

100

60

135

75

REF0

REF1

45

60

75

48/24MHZ

55

75

105

Notes:

5. X1 input threshold voltage (typical) is V_DD/2.

6. The W48S87-04 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal

is 20 pF; this includes typical stray capacitance of short PCB traces to crystal.

7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

8. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.

9. W48S87-04 logic inputs have internal pull-up devices.

10. CPU0:3 loaded by 60Ω, 6-inch long transmission lines ending with 20-pF capacitors.

14

PRELIMINARY

W48S87-04

(CPU3.3#_2.5 Input = 0) (continued)

3.3V DC Electrical Characteristics

T = 0°C to +70°C, VDD1:3 = VDDL1:2 = 3.3V±5% (3.135–3.465V)

A

Parameter

Description

Output High Current CPU0:3

Test Condition

Min.

55

Typ.

85

Max.

125

175

125

220

110

90

Unit

[10]

I

V

= 1.5V

mA

OH

SDRAM0:11

PCI_F, PCI0:5

IOAPIC

80

120

85

55

100

60

150

85

REF0

REF1

45

65

48/24MHZ

55

85

125

Pin Capacitance/Inductance

C

Input Pin Capacitance

Output Pin Capacitance

Input Pin Inductance

Except X1 and X2

5

6

7

pF

nH

IN

OUT

IN

L

Serial Input Port

V

Input Low Voltage

Input High Voltage

Input Low Current

V

= 3.3V

0.3V

DD

V

IL

DD

0.7V

IH

DD

I

No internal pull-up/down

on SCLOCK

10

µA

IL

Input High Current

No internal pull-up/down

on SCLOCK

µA

mA

pF

IH

Sink Current into SDATA,

Open Drain N-Channel Device On

I

= 0.3V

DD

6

OL

C

Input Capacitance of SDATA and

SCLOCK

10

IN

C

Total Capacitance of SDATA Bus

Total Capacitance of SCLOCK Bus

400

pF

SDATA

SCLOCK

(CPU3.3#_2.5 Input = 1)

2.5V DC Electrical Characteristics

T = 0°C to +70°C, VDD1:3 = 3.3V±5% (3.135–3.456V), VDDL1:2 = 2.5V±5% (2.375–2.625V)

A

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Supply Current

I

3.3V Supply Current

CPU0:3 = 66.4 MHz

Outputs Loaded

300

50

mA

DD-3.3V

[8]

I

2.5V Supply Current

CPU0:3= 66.4 MHz

DD-2.5

[8]

Outputs Loaded

Logic Inputs

V

Input Low Voltage

Input High Voltage

0.8

V

IL

2.0

IH

[9]

I

Input Low Current

10

µA

IL

IH

[9]

I

Input High Current

15

PRELIMINARY

W48S87-04

(CPU3.3#_2.5 Input = 1) (continued)

2.5V DC Electrical Characteristics

T = 0°C to +70°C, VDD1:3 = 3.3V±5% (3.135–3.456V), VDDL1:2 = 2.5V±5% (2.375–2.625V)

A

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Clock Outputs

V

Output Low Voltage

I

= 1 mA

50

mV

V

OL

V

Output High Voltage

Output Low Current

= –1 mA

2.2

45

55

40

50

OH

[10]

I

CPU0:3

IOAPIC

CPU0:3

IOAPIC

V

= 1.25V

70

85

65

80

105

130

95

mA

OL

V

OL

I

Output High Current

V

mA

OH

V

120

OH

Pin Capacitance/Inductance

C

Input Pin Capacitance

Output Pin Capacitance

Input Pin Inductance

Except X1 and X2

5

6

7

pF

nH

IN

OUT

IN

L

Serial Input Port

V

Input Low Voltage

Input High Voltage

V

= 2.5V

0.3V

DD

V

IL

DD

0.7V

IH

DD

(CPU3.3#_2.5 Input = 0)

3.3V AC Electrical Characteristics

T = 0°C to +70°C, VDD1:3 = VDD1:3 = 3.3V±5% (3.135–3.465V), f

= 14.31818 MHz

A

XTL

Spread Spectrum function turned off

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the

clock output.

CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)

CPU = 66.8 MHz

CPU = 60 MHz

Parameter

Description

Period

Test Condition/Comments

Measured on rising edge at 1.5V

Determined by PLL divider ratio

Duration of clock cycle above 2.4V

Duration of clock cycle below 0.4V

Min. Typ. Max. Min. Typ. Max. Unit

t

f

t

15

16.7

ns

MHz

ns

P

Frequency, Actual

High Time

66.8

59.876

5.2

5

6

5.8

1

H

L

Low Time

ns

Output Rise Edge Rate Measured from 0.4V to 2.4V

Output Fall Edge Rate Measured from 2.4V to 0.4V

1

4

V/ns

%

R

F

D

1

Duty Cycle

Measured on rising and falling edge at 45

1.5V

55

45

55

t

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Max-

imum difference of cycle time between

two adjacent cycles.

250

ps

JC

t

f

Output Skew

Measured on rising edge at 1.5V

250

3

250

3

ps

SK

ST

Frequency Stabilization Assumes full supply voltage reached

ms

from Power-up (cold

start)

within 1 ms from power-up. Short cy-

cles exist prior to frequency stabiliza-

tion.

Z

AC Output Impedance Average value during switching transi- 15

tion. Used for determining series termi-

nation value.

20

30

15

20

30

Ω

o

16

PRELIMINARY

W48S87-04

(CPU3.3#_2.5 Input = 0) (continued)

3.3V AC Electrical Characteristics

SDRAM Clock Outputs, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)

CPU = 66.8 MHz

CPU = 60 MHz

Parameter

Description

Period

Frequency, Actual

Test Condition/Comments

Measured on rising edge at 1.5V

Determined by PLL divider ratio

Min. Typ. Max. Min. Typ. Max. Unit

t

15

16.7

ns

MHz

V/ns

%

P

f

t

66.8

59.876

Output Rise Edge Rate Measured from 0.4V to 2.4V

Output Fall Edge Rate Measured from 2.4V to 0.4V

1

4

1

4

R

F

Duty Cycle

Measured on rising and falling edge at

1.5V

45

55

45

55

D

t

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Max-

imum difference of cycle time between

two adjacent cycles.

250

ps

JC

t

Output Skew

Measured on rising edge at 1.5V

100

ps

SK

CPU to SDRAM Clock Covers all CPU/SDRAM outputs. Mea-

Skew sured on rising edge at 1.5V.

500

3

500

3

SK

f

FrequencyStabilization Assumes full supply voltage reached

ms

ST

from Power-up (cold

start)

within 1 ms from power-up. Short cy-

cles exist prior to frequency stabiliza-

tion.

Z

AC Output Impedance Average value during switching transi- 10

tion. Used for determining series ter-

mination value.

15

20

10

15

20

Ω

o

PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF)

CPU = 66.8 MHz

Min. Typ. Max. Min. Typ. Max. Unit

CPU = 60 MHz

Parameter

Description

Period

Test Condition/Comments

Measured on rising edge at 1.5V

Determined by PLL divider ratio

Duration of clock cycle above 2.4V

Duration of clock cycle below 0.4V

t

f

t

30

33.3

ns

MHz

ns

P

Frequency, Actual

High Time

33.4

29.938

12

1

13.3

1

H

L

Low Time

ns

Output Rise Edge Rate Measured from 0.4V to 2.4V

Output Fall Edge Rate Measured from 2.4V to 0.4V

4

V/ns

%

R

F

D

1

Duty Cycle

Measured on rising and falling edge at

1.5V

45

55

45

55

t

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Max-

imum difference of cycle time between

two adjacent cycles.

250

ps

JC

t

Output Skew

Measured on rising edge at 1.5V

250

4

250

4

ps

ns

SK

CPU to PCI Clock Skew Covers all CPU/PCI outputs. Mea-

sured on rising edge at 1.5V. CPU

leads PCI output.

1

O

f

FrequencyStabilization Assumes full supply voltage reached

3

ms

ST

from Power-up (cold

start)

within 1 ms from power-up. Short cy-

cles exist prior to frequency stabiliza-

tion.

Z

AC Output Impedance Average value during switching transi- 15

tion. Used for determining series termi-

nation value.

20

30

15

20

30

Ω

o

17

PRELIMINARY

W48S87-04

(CPU3.3#_2.5 Input = 0) (continued)

3.3V AC Electrical Characteristics

IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)

CPU = 60/66.8 MHz

Parameter

Description

Frequency, Actual

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

Test Condition/Comments

Frequency generated by crystal oscillator

Measured from 0.4V to 2.4V

Min.

Typ.

Max.

Unit

MHz

V/ns

%

f

14.31818

t

f

1

4

R

Measured from 2.4V to 0.4V

F

Measured on rising and falling edge at 1.5V

Assumes full supply voltage reached within

45

55

1.5

D

Frequency Stabilization

ms

ST

from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to

frequency stabilization.

Z

AC Output Impedance

Average value during switching transition.

8

12

15

Ω

o

Used for determining series termination value.

REF0 Clock Output (Lump Capacitance Test Load = 45 pF)

CPU = 60/66.8 MHz

Parameter

Description

Frequency, Actual

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

Test Condition/Comments

Frequency generated by crystal oscillator

Measured from 0.4V to 2.4V

Min.

Typ.

Max.

Unit

MHz

V/ns

%

f

14.31818

t

f

1

4

R

Measured from 2.4V to 0.4V

F

Measured on rising and falling edge at 1.5V

Assumes full supply voltage reached within

40

60

1.5

D

Frequency Stabilization

ms

ST

from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to

frequency stabilization.

Z

AC Output Impedance

Average value during switching transition.

17

20

25

Ω

o

Used for determining series termination value.

REF1 Clock Output (Lump Capacitance Test Load = 20 pF)

CPU = 60/66.8 MHz

Parameter

Description

Frequency, Actual

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

Test Condition/Comments

Frequency generated by crystal oscillator

Measured from 0.4V to 2.4V

Min.

Typ.

Max.

Unit

MHz

V/ns

%

f

14.31818

t

f

1

4

R

Measured from 2.4V to 0.4V

F

Measured on rising and falling edge at 1.5V

40

55

1.5

D

Frequency Stabilization

Assumes full supply voltage reached within

ms

ST

from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to

frequency stabilization.

Z

AC Output Impedance

Average value during switching transition.

Used for determining series termination value.

20

25

35

Ω

o

18

PRELIMINARY

W48S87-04

(CPU3.3#_2.5 Input = 0) (continued)

3.3V AC Electrical Characteristics

48-/24-MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF)

CPU = 60/66.8 MHz

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

f

Frequency, Actual

Determined by PLL divider ratio

(see n/m below)

48.008/24.004

MHz

f

Deviation from 48 MHz

PLL Ratio

(48.008 – 48)/48

+167

ppm

D

m/n

(14.31818 MHz x 57/17 = 48.008 MHz)

Measured from 0.4V to 2.4V

57/17

t

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

1

4

V/ns

%

R

Measured from 2.4V to 0.4V

F

Measured on rising and falling edge at 1.5V

40

55

500

D

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Maximum

difference of cycle time between two adjacent

cycles.

ps

JC

f

Frequency Stabilization

from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to

frequency stabilization.

Assumes full supply voltage reached within

3

ms

ST

Z

AC Output Impedance

Average value during switching transition.

Used for determining series termination value.

15

20

30

Ω

o

Serial Input Port

Parameter

Description

Test Condition

Min.

0

Typ.

Max.

Unit

kHz

µs

f

t

SCLOCK Frequency

Start Hold Time

Normal Mode

100

SCLOCK

STHD

LOW

4.0

4.7

4.0

250

0

µs

SCLOCK Low Time

SCLOCK High Time

Data Setup Time

Data Hold Time

µs

HIGH

DSU

ns

(Transmitter should provide a 300-ns hold

time to ensure proper timing at the receiver.)

ns

DHD

t

Rise Time, SDATA and

SCLOCK

From 0.3V to 0.7V

1000

300

ns

R

F

DD

Fall Time, SDATA and

SCLOCK

From 0.7V to 0.3V

DD

µs

t

Stop Setup Time

4.0

4.7

STSU

Bus Free Time between

Stop and Start Condition

SPF

ns

t

Allowable Noise Spike

Pulse Width

50

SP

19

PRELIMINARY

W48S87-04

(CPU3.3#_2.5 Input = 1)

2.5V AC Electrical Characteristics

T = 0°C to +70°C, VDD1:3 = 3.3V±5% (3.135–3.465V), VDDL1:2 = 2.5V±5% (2.375–2.625V),

A

XTL

f

= 14.31818 MHz

Spread Spectrum function turned off

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the

clock output.

CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)

CPU = 66.8 MHz

CPU = 60 MHz

Parameter

Description

Period

Test Condition/Comments

Measured on rising edge at 1.25V

Determined by PLL divider ratio

Duration of clock cycle above 2.0V

Duration of clock cycle below 0.4V

Min. Typ. Max. Min. Typ. Max. Unit

t

f

t

15

16.7

ns

MHz

ns

P

Frequency, Actual

High Time

66.8

59.876

5.2

5

6

H

L

Low Time

5.8

0.8

45

ns

Output Rise Edge Rate Measured from 0.4V to 2.0V

Output Fall Edge Rate Measured from 2.0V to 0.4V

0.8

45

3

V/ns

%

R

F

D

Duty Cycle

Measured on rising and falling edge at

55

1.25V

t

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.25V. Max-

imum difference of cycle time between

two adjacent cycles.

250

ps

JC

t

f

Output Skew

Measured on rising edge at 1.25V

250

3

250

3

ps

SK

Frequency Stabiliza-

tion from Power-up

(cold start)

Assumes full supply voltage reached

within 1 ms from power-up. Short cycles

exist prior to frequency stabilization.

ms

ST

Z

AC Output Impedance Average value during switching transi-

tion. Used for determining series termi-

nation value.

12

20

30

12

20

30

Ω

o

IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)

CPU = 60/66.8 MHz

Parameter

Description

Frequency, Actual

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

Test Condition/Comments

Min.

Typ.

Max.

Unit

f

Frequency generated by crystal oscillator

Measured from 0.4V to 2.0V

14.31818

MHz

V/ns

%

t

f

1

4

R

Measured from 2.0V to 0.4V

F

Measured on rising and falling edge at 1.25V

45

55

1.5

D

Frequency Stabilization

Assumes full supply voltage reached within

ms

ST

from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to

frequency stabilization.

Z

AC Output Impedance

Average value during switching transition. Used

for determining series termination value.

10

15

25

Ω

o

Ordering Information

Freq. Mask

Code

Package

Name

Ordering Code

Package Type

W48S87

04

H

48-pin SSOP (300 mils)

Document #: 38-00859

20

PRELIMINARY

W48S87-04

Package Diagram

48-Pin Small Shrink Outline Package (SSOP, 300 mils)

Summary of nominal dimensions in inches:

Body Width: 0.296

Lead Pitch: 0.025

Body Length: 0.625

Body Height: 0.102

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.


型号：	W48S87-04
厂家：	CYPRESS
描述：	Spread Spectrum 3 DIMM Desktop Clock 扩频3 DIMM桌面时钟外围集成电路光电二极管时钟
文件：	总21页 (文件大小：203K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W48S87-04 [CYPRESS]

相关型号：

W48S87-04H

W48S87-04HT

W48S87-72

W48S87-72H

W48S87-72XT

W49

W49180

W49180-08

W49C65-01H

W49C65-01H

W49F002

W49F002A-12