Z9951_技术文档

Z9951

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Product Features

Frequency Table

SEL (A:D)

QA

QB

QC (0,1) QD (0:4)

•

180MHz Clock Support

Supports PowerPC^TM, Intel and RISC Processors

9 Clock Outputs: Frequency Configurable

Two Reference Clock Inputs for Dynamic Toggling

Oscillator or PECL Reference Input

Output Disable Control

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

VCO/2

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

Spread Spectrum Compatible

3.3V Power Supply

Pin Compatible with MPC951

Industrial Temp. Range: -40°C to +85°C

32-Pin TQFP Package

Block Diagram

SELA

PLL_EN

TCLK

Table 1

REF_SEL

VCO

200-

480MHz

Phase

Detector

QA

QB

2/

4/

4

8

Pin Configuration

PECL_CLK

PECL_CLK#

LPF

FB_IN

SELB

QC0

QC1

4/

8

SELC

VDD

FB_IN

SELA

SELB

SELC

1

2

3

4

5

6

7

8

24

23

22

21

QC0

MR/OE#

Power-On Reset

VDDC

QC1

VSS

QD0

QD1

Z9951 20 QD0

SELD

VSS

PECL_CLK

19

18

17

VDDC

QD1

VSS

SELD

QD2

QD3

QD4

Figure 1

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07084 Rev. *B

12/22/2002

Page 1 of 9

Z9951

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Pin Description

NAME

PECL_CLK

PECL_CLK#

TCLK

PWR

I/O

I

TYPE

PU

Description

PECL Input Clock.

8

9

30

I

External Test Clock Input.

28

26

VDDC

O

Clock Output. See Frequency Table.

Clock Outputs. See Frequency Table.

QA

QB

QC(1,0)

QD(4:0)

22, 24

12, 14, 16,

18, 20

2

Feedback Clock Input. Connect to an output for normal operation.

I

PD

FB_IN

MR/OE#

10

Master Reset/Output Enable Input. When asserted high, resets

all of the internal flip-flops and also disables all of the outputs.

When pulled low, releases the internal flip-flops from reset and

enables all of the outputs.

31

I

PLL Enable Input. When asserted high, PLL is enabled. And

when set low, PLL is bypassed.

Reference Select Input. When high, TCLK is the reference clock

and when low, PECL clock is selected.

Frequency Select Inputs. See Frequency Table.

If SEL_ = 1, then QA divider = ÷4, QB:D divider = ÷8

If SEL_ = 0, then QA divider = ÷2, QB:D divider = ÷4

3.3V Power Supply for Output Clock Buffers.

PLL_EN

32

REF_SEL

SEL(A:D)

3, 4, 5, 6

11, 15, 19,

23, 27

VDDC

1

3.3V Power Supply for PLL

Common Ground

VDD

VSS

7, 13, 17, 21,

25, 29

PD = Internal Pull-Down, PU = Internal Pull-Up.

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07084 Rev. *B

12/22/2002

Page 2 of 9

Z9951

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Maximum Ratings¹

This device contains circuitry to protect the inputs

against damage due to high static voltages or electric

field; however, precautions should be taken to avoid

application of any voltage higher than the maximum

rated voltages to this circuit. For proper operation, Vin

and Vout should be constrained to the range:

Maximum Input Voltage Relative to VSS: VSS - 0.3V

Maximum Input Voltage Relative to VDD: VDD + 0.3V

Storage Temperature:

Operating Temperature:

Maximum ESD protection

-65°C to + 150°C

-40°C to +85°C

2KV

VSS<(Vin or Vout)<VDD

Maximum Power Supply:

Maximum Input Current:

5.5V

±20mA

Unused inputs must always be tied to an appropriate

logic voltage level (either VSS or VDD).

DC Parameters

Characteristic

Symbol Min

Typ

Max

0.8

Units

V

Conditions

Input Low Voltage

VIL

VIH

IIL

VSS

2.0

-

Input High Voltage

VDD

-120

120

V

Input Low Current (@VIL = VSS)

Input High Current (@VIL =VDD)

Peak-to-Peak Input Voltage

PECL_CLK

µA

mV

Note 2

Note 3

IIH

VPP

300

1000

Common Mode Range

PECL_CLK

VCMR

VDD-

2.0

-

VDD-

0.6

V

Output Low Voltage

Output High Voltage

Quiescent Supply Current

PLL Supply Current

Input Capacitance

VOL

VOH

IDDC

IDD

0.5

V

IOL = 40mA, Note 4

IOH = -40mA, Note 4

All VDDC and VDD

VDD only

2.4

-

15

-

20

4

mA

pF

Cin

VDD = VDDC = 3.3V ±5%, TA = -40°C to +85°C

Note 1: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT

required.

Note 2: Inputs have pull-up, pull-down resistors that affect input current.

Note 3: The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when

the “High” input is within the VCMR range and the input lies within the VPP specification.

Note 4: Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Output buffers are dual staged to control

drive strength in order to reduce over / under shoot.

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07084 Rev. *B

12/22/2002

Page 3 of 9

Z9951

3.3V, 180MHz, Multi-Output Zero Delay Buffer

AC Parameters¹

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

CONDITIONS

Tr / Tf

TCLK Input Rise / Fall

3.0

ns

MHz

%

Fref

FrefDC

Fvco

Reference Input Frequency

Reference Input Duty Cycle

PLL VCO Lock Range

Note 2

25

Note 2

75

200

480

MHz

ms

Tlock

Tr / Tf

Fout

Maximum PLL lock Time

Output Clocks Rise / Fall Time^4,5

10

0.10

-

1.0

ns

0.8V to 2.0V

QA = (÷2)

Maximum Output Frequency

180

120

MHz

QA/QB = (÷4)

QB = (÷8)

60

FoutDC

Output Duty Cycle^4,5

TCYCLE/2 –

1

TCYCLE/2 + 1

ns

tpZL, tpZH

tpLZ, tpHZ

TCCJ

Output enable time (all outputs)

Output disable time (all outputs)

Cycle to Cycle Jitter (peak to peak)^4,5

TCLK to FB_IN Delay³

PECL_CLK to FB_IN Delay³

Any Output to Any Output Skew^4,5

6

7

ns

ps

+/- 100

250

Tpd

50

-950

-

400

-600

350

Fref = 50MHz,

Feedback = VCO/8

-770

200

TSKEW0

VDD = VDDC = 3.3V +/- 5%, TA = -40°C to +85°C

Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production.

Note 2: Maximum and minimum input reference is limited by the VCO lock range.

Note 3: The Tpd window is specified for a 50MHz input reference clock. The window will enlarge/reduce proportionally from the

minimum limits with an increase/decrease of the input reference clock period.

Note 4: Driving series or parallel terminator 50Ω (or 50Ω to VDD/2) transmission lines.

Note 5: Outputs loaded with 30pF each

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07084 Rev. *B

12/22/2002

Page 4 of 9

Z9951

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Description

The Z9951 has an integrated PLL that provides low skew and low jitter clock outputs for high performance

microprocessors. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480

MHz. This allows a wide range of output frequencies from 25MHz to 180MHz.

The phase detector compares the input reference clock to the external feedback input. For normal operation, the

external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input

reference clock set by SEL(A:D) select inputs, see Table 2. The VCO frequency is then divided down to provide the

required output frequencies. The use of even dividers ensures that the output duty cycle remains at 50%.

SELA

QA

SELB

QB

SELC

QC

SELD

QD

0

1

0

1

0

1

0

1

÷2

÷4

÷8

÷4

÷8

÷4

÷8

Table 2

Zero Delay Buffer

When used as a zero delay buffer the Z9951 will likely be in a nested clock tree application. For these applications the

Z9951 offers a low voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary

clock distribution device to take advantage of its far superior skew performance. The Z9951 then can lock onto the

LVPECL reference and translate with near zero delay to low skew outputs.

By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated. The PLL

works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency

affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static

phase offset is a function of the reference clock the Tpd of the Z9951 is a function of the configuration used.

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07084 Rev. *B

12/22/2002

Page 5 of 9

Z9951

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Package Drawing and Dimensions

32 Pin TQFP Outline Dimensions

INCHES

MILLIMETERS

SYMBOL

MIN

NOM

MAX

0.047

0.006

0.041

-

MIN

-

NOM

MAX

A

A₁

A2

D

-

1.20

0.15

1.05

-

0.002

0.037

-

0.05

0.95

-

D

-

0.354

9.00

D₁

b

-

0.276

-

7.00

-

0.012

-

0.018

0.30

-

0.45

e

0.031 BSC

-

0.80 BSC

-

D₁

L

0.018

0.030

0.45

0.75

12°

A₁

A

L

e

b

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07084 Rev. *B

12/22/2002

Page 6 of 9

Z9951

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Ordering Information

Part Number

Package Type

Production Flow

Z9951AA

32 PIN TQFP

Industrial, -40°C to +85°C

Note:

The ordering part number is formed by a combination of device number, device revision, package style, and

screening as shown below.

Marking: Example: Cypress

Z9951AA

Date Code, Lot #

Z9951AA

Package

A = TQFP

Revision

Device Number

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07084 Rev. *B

12/22/2002

Page 7 of 9

Z9951

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Notice

Cypress Semiconductor Corp. reserves the right to make changes to its products in order to improve design,

performance or reliability. Cypress Semiconductor Corp. assumes no responsibility for the use of its products in life

supporting and medical applications where the failure or malfunction of the product could cause failure of the life

supporting and medical systems. Products are not authorized for use in such applications unless a written approval is

requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corp. for the use of its

products in the life supporting and medical applications.

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07084 Rev. *B

12/22/2002

Page 8 of 9

Z9951

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Document Title: Z9951 3.3V, 180 MHz, Multi-Output Zero Delay Buffer

Document Number: 38-07084

Rev. ECN

No.

Issue

Date

Orig. of

Change

Description of Change

**

*A

107120

108063

06/12/01 IKA

07/03/01 NDP

Convert from IMI to Cypress

Changed Commercial to Industrial (See page 7)

Delete Pull down in pin 9,10,30& 32; Delete Pull up in pin

3,4,5,6, & 31 (See page 2)

*B

122769

12/22/02 RBI

Add power up requirements to maximum ratings

information

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07084 Rev. *B

12/22/2002

Page 9 of 9


型号：	Z9951
厂家：	CYPRESS
描述：	3.3V, 180MHz, Multi-Output Zero Delay Buffer 3.3V ， 180MHz的，多输出零延迟缓冲器
文件：	总9页 (文件大小：53K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Z9951 [CYPRESS]

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