DEI1117-PES-G [DEIAZ]
Transceiver Family;
| 型号： | DEI1117-PES-G |
| 厂家： | 
Device Engineering Incorporated |
| 描述： | Transceiver Family PC 驱动 接口集成电路 驱动器 |
| 文件： | 总14页 (文件大小：587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Device
Engineering
Incorporated
DEI1116 / DEI1117 ARINC 429
Transceiver Family
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: info@deiaz.com
Features
General Description
The DEI1116/DEI1117 provides an interface between a
standard avionics type serial digital data bus and a 16-bit-
•
•
•
•
•
Two Receivers and One Transmitter
3.3V or 5V supply operation
wide digital data bus. The interface circuit consists of a
single channel transmitter with an 8X32 bit buffer, two
independent receive channels, and a host programmable
control register to select operating options. The two receiver
Pin compatible with DEI1016, HI3282 and HI8282A
Wraparound Self-Test mode
Word length can be configured for 25 bit or 32 bits
operation
channels operate identically, each providing
electrical interface to an ARINC data bus.
a direct
•
Parity Status and generation of Receive and Transmit
Words
•
•
•
•
•
•
8 Word Transmitter buffer
Low Power CMOS
The transmitter circuit contains an 8 word by 32 bit buffer
memory and control logic which allows the host to write a
block of data into the transmitter. The block of data is
transmitted automatically by enabling the transmitter with no
further attention by the host computer. Data is transmitted in
TTL format on the DO(A)/DO(B) output pins. The signal
format is compatible with DEI’s extensive line of ARINC
429 Line drivers for easy connection to the ARINC data bus.
Supports multiple ARINC protocols: 429, 571, 575, 706
Temperature range options: -55/+85°C and -55/+125°C
Package options: 44L MQFP and 44L PLCC
Lightning Protection options: DEI1117 operates with
10K Ohm series resistor on A429 inputs.
Pin and software compatible with the DEI1016 ARINC
429 Transceiver
•
The DEI1116 and DEI1117 differ in their A429 RX input
characteristics. The DEI1116 interfaces directly to the A429
bus signals; the DEI1117 operates with 10K ohm series
resistors. The series resistors support implementation of
lightning transient protection.
ARINC 429
Receive
/DR1, /DR2
Receive 0
Decoder
32
TXR
/OE1, /OE2
/LD1, /LD2
ENTX
/LDCW
/DBCEN
/MR
Control
Host
Interface
16
Register
ARINC 429
Receive
Receive 1
Decoder
32
16
DATA BUS
32
TX FIFO
8 Words X 32 Bits
Transmit
Encoder
ARINC 429
Transmit
32
Figure 1: Block Diagram
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 1 of 14
Table 1: Pin Definitions
DEFINITION
SYMBOL
VDD
GND
Power Input. +5VDC ±10%
Power Return and Signal Ground.
DI1(A)
DI1(B)
DI2(A)
DI2(B)
/LDCW
SEL
ARINC 429 Input. Receiver Channel 1, “A” input
ARINC 429 Input. Receiver Channel 1, “B” input
ARINC 429 Input. Receiver Channel 2, “A” input
ARINC 429 Input. Receiver Channel 2, “B” input
Logic Input. Load Control Register. A Low input pulse loads the Control Register from D[15:0].
Logic Input. Receiver word select. A Low input selects receiver Word 1; Hi selects Word 2 to be read
on D [15:0] port.
/LD1
/LD2
Logic Input. Load Transmitter Word 1. A Low input pulse loads Word 1 into the Transmitter FIFO
from D [15:0].
Logic Input. Load Transmitter Word 2. A Low input pulse loads Word 2 into the Transmitter FIFO
from D [15:0].
ENTX
Logic Input. Enable Transmitter. A Hi input enables the Transmitter to send data from the Transmitter
FIFO. This must be Low while writing data into Transmitter FIFO. Transmitter memory is cleared by
high-to-low transition.
D[15:0]
/OE1
Logic Input / Tri-state Output. This 16-bit bi-directional data port is the uP data interface. Receiver
data is read from this port. Control Register and Transmitter FIFO data is written into this port.
Logic Input. Receiver 1 Output Enable. A Low input enables the D [15:0] port to output Receiver 1
data. Word 1 or Word 2 will be output as determined by the SEL input.
/OE2
Logic Input. Receiver 2 Output Enable. A Low input enables the D [15:0] port to output Receiver 2
data. Word 1 or Word 2 will be output as determined by the SEL input.
/DR1
/DR2
TXR
Logic Output. Data Ready, Receiver 1. A Low output indicates valid data in receiver 1.
Logic Output. Data Ready, Receiver 2. A Low output indicates valid data in receiver 2.
Logic Output. Transmitter Ready. A Hi output indicates the Transmitter FIFO is empty and ready to
accept new data.
DO(A), DO(B)
Logic Outputs. Transmitter serial data outputs.
This is a return-to-zero format signal which will normally feed an ARINC 429 Line Driver IC.
A Hi output on DO(A) indicates the Transmitter data bit is a 1.
A Hi output on DO(B) indicates the Transmitter data bit is a 0.
The signal returns to zero for second half of bit time.
TXCK
Logic Output. Transmitter Clock. This outputs a clock frequency equal to the transmit data rate. The
clock is always enabled and in phase with the data. The output is Hi during the first half of the data bit
time.
1MCK
/MR
Logic Input. External Clock. Master clock used by both the Receivers and Transmitter. The 1MHz
rate is an X10 clock for the HI data rate (100 kbps), and a X80 clock for LO data rate (12.5 kbps).
Logic Input. Master Reset. A Lo input resets the Transmitter FIFO, bit counters, word counter, gap
timers, /DRx, and TXR. The Control Register is not affected. Used on power up and system reset.
/DBCEN
Logic Input with internal pull up to VDD. Data Bit Control Enable. A Low input enables the
transmitter parity bit control function as defined by control register bit 4 (PAREN). A Hi input forces
transmitter parity bit insertion regardless of PAREN value. The pin is normally left open or tied to
ground.
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 2 of 14
Figure 2: Terminal Connections
Table 2: DC Electrical Characteristics
Conditions: Ta = -55 to +125 ºC, Vdd = 3.3V ± 10% or Vdd = 5V ± 10%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
ARINC INPUTS: DI[1A/1B/2A/2B] (DEI1116) or
DI[1A/1B/2A/2B]E with external 10K Ohm resistors (DEI1117)
Differential Input Voltage
ONE
ZERO
NULL
Vil
Vil
6.5
-13.0
-2.5
10.0
-10.0
0
13.0
-6.5
2.5
V
V
V
Vnull
Common Mode Input Voltage
Input Resistance:
Vcm
-10
10
V
Differential
To GND
RI
RG
RH
CI
24
12
12
132
67
200
100
KOhm
KOhm
KOhm
pF
To VDD
7500
Input Capacitance
Input Voltage: HI
20
LOGIC INPUTS
Vdd = 3.0V to 5.5V 0.7*Vdd
VIH
Vdd+0.5
V
Input Voltage: LO
VIL
Vdd = 3.0V to 5.5V
0V to Vdd
0V
-0.5
-10
0.8
10
V
µA
µA
Hi-Z Input Current:
Iin
Input Pull-up Current, /DBCEN
IPU
-100
LOGIC OUTPUTS
IOH = -4ma
Output Voltage: TTL Logic 1
Output Voltage: CMOS Logic 1
Output Voltage: TTL Logic 0
Output Voltage: CMOS Logic 0
VOH-T
VOH-C
VOL-T
VOL-C
Vdd -0.5
Vdd -0.1
V
V
V
V
IOH = -100ua
IOL = 4ma
0.4
0.1
10
IOL = 100ua
Output Capacitance:
Cout
pF
OPERATING SUPPLY CURRENT
Supply Current at VDD = 3.3V or 5V
Supply Voltage
IDD
Fck = 1MHZ
IDD ~
12
mA
V
4*(VDD-2.7)
VDD
3.0
5.5
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 3 of 14
Table 3: Absolute Maximum Ratings
PARAMETER
Supply Voltage
DC Input Voltage, Logic inputs
SYMBOL
VDD
VIN-logic
MIN
-0.5
-0.6
MAX
+7.0
VCC+0.6
UNITS
V
V
DC Input Voltage, RX pins: DI[1A/1B/2A/2B]
DEI1116
VIN-rx
±40
±40
V
DEI1117 with external 10K ohm series resistors
VIN-rxe
DO160 Sect 22 Lightning Immunity pin injection
WF4 & WF5A
±300
±600
WF3
Clamp diode current, any pin except RX inputs
DC Output Current per pin
Storage Temperature
±25
±25
+150
+145
mA
mA
°C
Tstg
-65
Junction Temperature, operating
TJmax
°C
Table 4: AC Electrical Characteristics
SYMBOL
PARAMETER
1MCK Frequency
1MCK Duty Cycle
1MCK Rise/Fall Time
Data Rate 100kbpsData Rate 12.5kbps
MIN
0.99
40
MAX
1.01
60
MIN
0.99
40
MAX
1.01
60
UNITS
MHz
%
ns
ns
kbps
f1MCK
CKDC
TCRF
TMR
10
10
Master Reset Pulse Width
Transmitter Data Rate (1MCK = 1MHz)
200
99
200
12.4
TDR
101
105
12.6
14.5
Receiver Data Rate (1MCK = 1MHz),
RDR
95
8.0
kbps
(DATA = 50% BIT/ 50% NULL TIME)
Functional Description:
Table 5: Control Register Format
The DEI1116/1117 supports a number of various options
which are selected by data written into the control register.
Data is written into the control register from the 16-bit data
bus when the /LDCW signal is pulsed to a logic “0”. The
twelve control bits control the following functions:
BIT
SYMBOL
WLSEL
RCVSEL
TXSEL
PARCK
Y2
BIT
D7
D6
D5
D4
D3
D2
D1
D0
SYMBOL
X1
SDENB1
/SLFTST
PAREN
NOT USED
NOT USED
NOT USED
NOT USED
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
1) Word Length (32 or 25 bits)
2) Transmitter bit 32 (Parity or Data)
3) Wrap around self test.
4) Source Destination code checking of received data.
5) Transmitter parity (even or odd)
X2
6) Transmitter and Receiver data rate (100 or 12.5 kbps)
SDENB2
Y1
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 4 of 14
Table 6: Control Word
DESCRIPTION
NAME
PAREN
DATA BIT
D4
Transmitter Parity Enable. Enables parity bit insertion into transmitter data bit 32. Parity is always
inserted if /DBCEN is open or HI. If /DBCEN is LO, Logic “0” on PAREN inserts data on bit 32, and
Logic “1” on PAREN inserts parity on bit 32.
Self Test Enable. Logic “0” enables a “wrap around” test mode which internally connects the transmitter
outputs to both receiver inputs, bypassing the receiver front end. The test data is inverted before going
into receiver 2 so that its data is the complement of that received by receiver 1. The transmitter output is
active during test mode.
/SLFTST1
SDEN12
X1, Y12
SDEN22
X2, Y22
D5
D6
S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for receiver 1.
S/D compare code RX1. If the receiver 1 S/D code check is enabled (SDEN1=1), then incoming receiver
data S/D fields will be compared to X1, Y1. If they match, the word will be accepted by receiver 1; if
not, it will be ignored. X1 (D7) is compared to serial data bit 9, Y1 (D8) is compared to serial data bit 10.
D7, D8
D9
S/D Code Check Enable for receiver 2. Logic “1” enables the Source/Destination Decoder for receiver 2.
S/D compare code RX2. If the receiver 2 S/D code check is enabled (SDEN2=1), then incoming receiver
data S/D fields will be compared to X2, Y2. If they match, the word will be accepted by receiver 2; if
not, it will be ignored. X2 (D10) is compared to serial data bit 9, Y2 (D11) is compared to serial data bit
10.
D10, D11
Parity Check Enable. Logic “1” inverts the transmitter parity bit for test of parity circuits. Logic “0”
PARCK
TXSEL3
D12
D13
selects normal odd parity; logic “1” selects even parity.
Transmitter Data Rate Select. Logic “0” sets the transmitter to the HI data rate. HI rate is equal to the
clock rate divided 10. Logic “1” sets the transmitter to the LO data rate. LO rate is equal to the clock rate
divided by 80.
Receiver Data Rate Select. Logic “0” sets both receivers to accept the HI data rate. The nominal HI data
rate is the input clock divided by 10. Logic “1” sets both receivers to the LO data rate. The nominal LO
data rate is the input clock divided by 80.
RCVSEL4
WLSEL5
D14
D15
Word Length Select. Logic “0” sets the transmitter and receivers to a 32 bit word format. Logic “1” sets
them to a 25 bit word format.
When writing to the control register, the four “not used bits” are “don’t care” bits. These four bits will not
be used on the chip.
NOT USED D0-D3
NOTES
1) The test mode should always conclude with ten null’s. This step prevents both receivers from accepting invalid data.
2) SDENn, Xn & Yn should be changed within 20 bit times after /DRn goes low and the bit stream has been read, or within 30 bit times after a
master reset has been removed.
3) TXSEL should only be changed during the time that TXR is high or Master Reset is low.
4) RCVSEL should be changed only during a Master Reset pulse. If changed at any other time, then the next bit stream from both Receiver 1 and
Receiver 2 should be ignored.
5) When the control word is written the effect of the WLSEL bit will take effect immediately on the first complete ARINC word received or
transmitted following the control word write operation.
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 5 of 14
Data Format:
The ARINC serial data is shuffled and formatted into two 16 bit words (WORD1 and WORD2) used by the bi-directional data bus
interface. Figure 3a shows the mapping between the 32 bit ARINC serial data and the two data words. Figure 3b describes the
mapping for the 25 bit serial word used when control register bit WLSEL is set to logic “1”.
32 Bit ARINC Serial Data Format (Bit 1 is Transmitted First)
S/D
SSM
DATA
or
LABEL
FUNCTION
BIT
DATA
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
S/D
9
8
7
6
5
4
3
2
1
0
BIT
FUNCTION
DATA
DATA
or
SSM
LABEL
DATA
Word 2 Format
Word 1 Format
Figure 3a: Mapping of Serial Data to/from Word 1 and Word 2 in 32 bit format.
25 Bit ARINC Serial Data Format (Bit 1 is Transmitted First)
DATA
LABEL
FUNCTION
BIT
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
NOT USED
9
8
7
6
5
4
3
2
1
0
BIT
FUNCTION
DATA
LABEL
Word 2 Format
Word 1 Format
Figure 3b: Mapping of Serial Data to/from Word 1 and Word 2 in 25 bit format.
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 6 of 14
and Word 2 together have an even number of 1’s, then data bit
32 is a logic “1”. Otherwise, it is a logic “0”.
Receiver Operation:
Since the receivers function identically, only one will be
discussed in detail. The receiver consists of the following
circuits.
Line Receiver
The front end of the Line Receiver functions as a voltage level
translator. It transforms the ±10 volt differential ARINC data
signals into 5 Volt internal logic levels. The line receivers are
protected against shorts to ±40 Volts and provide common
mode voltage rejection.
The DEI1116 and 1117 differ in their A429 RX input
characteristics. The DEI1116 interfaces directly to the A429
bus signals. DEI1117 version bypasses some of the on-chip
resistance and thus operates with 10K ohm series resistors.
The series resistors support implementation of lightning
transient protection. The 1117 withstands Level 3 pin
injection levels with only the resistors. Higher levels are
achieved with a TVS shunt placed between the series resistor
and 1117 DIxx pin.
The outputs of the Line Receiver are one of two inputs to the
Self-Test Data Selector. The other input to the Data Selector
is the self-test signal from the transmitter section. The self-
test signals are inverted going into Receiver 2. The data
selector is controled by Control Register bit D5 (/SLFTST).
DO(A)
DI1(A)
Self-Test
To
Data Selector
Receive
DI1(B)
Decoder
Comparator
SLFTST
Figure 4: Line Receiver Block Diagram
Incoming Data
The incoming data (either self test or ARINC) is triple
sampled by the word gap timer to generate a data clock. The
start of each bit is first detected and then verified two receive-
clock cycles later. The receive clock is 1MHz for HI speed
and 125 KHz for LO speed operation and is generated by the
Receiver/Transmitter timing circuit. The receive clock is ten
times the normal data rate to ensure no data ambiguity.
Parity Control
The parity of the incoming message is checked when either
word of the receiver is read. Logic “0” indicates the received
word has an odd number of 1’s (no error). Logic “1” indicates
the received word has an even number of 1’s (error condition).
If the data format has data in bit 32 instead of parity, the user
software must calculate the value of the 32nd bit. If Word 1
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 7 of 14
S/D Decoder
Transmitter Operation:
The Source/Destination decoder compares the user set code (X
and Y) with bits 9 and 10 of the data word. The decoder can
be enabled and disabled by the SDENn bits of the Control
Register. If the two codes are matched, a signal is generated
to latch in the received data into the receiver buffer.
Otherwise the data word is ignored and not latched into the
receive buffer. If the data is latched, the data ready flag
(/DRn) is set to indicate to the user that a valid data word is
ready to be read.
The transmitter section consists of an 8 word by 32 bit FIFO,
parity generator, transmitter word gap timer, and a TTL output
circuit.
FIFO Buffer
The 8x32 buffer memory allows the user to load up to 8 words
into the transmitter, enable it, and then ignore it while the
transmitter ships out the data without further attention. Data is
loaded into the buffer by pulsing /LD1 to load the first 16 bits
(WORD 1) from the data bus, and pulsing /LD2 to load WORD
2. /LD1 must always precede /LD2. The transmitter must always
be disabled while loading the buffer (ENTX = logic "0").
Data Clock
The derived data clock then shifts the data down a 32 bit long
Data Shift Register. The data word length is selectable for
either 25 or 32 bits long by Control Register Bit WLSEL. As
soon as the data word is completely received, an internal
signal is generated by the word gap timer circuit to enable
loading data into the 32 bit receive buffer latch.
If the buffer is full and new data is pulsed with /LD1 and /LD2,
the last 32 bit word in the buffer will be overwritten. Data will
remain in the buffer until ENTX is pulsed to a logic “1”, which
will activate the FIFO clock and data is shifted out serially to the
transmitter driver.
Data Access
The buffer data is transmitted until the last word in the buffer is
shifted out. At this time a transmitter ready signal (TXR) is set to
a logic “1” indicating that the buffer is empty and ready to receive
up to eight more data words. Writing into the buffer memory is
disabled when ENTX is set to logic “1”.
To access the receiver data, the user sets the receiver data
select input (SEL) to a logic “0” and pulses the output enable
(/OEn) line with a logic “0”. This causes Data Word 1 to be
placed on the 16 bit data bus. To read Word 2, the user sets
the data select input (SEL) to a logic “1” and pulses the output
enable (/OEn) low to place Word 2 on the data bus. When
both Word 1 and Word 2 have been read, DRn will be reset.
This reset is triggered by the leading edge of the final /OEn
pulse.
Transmitter Ready Signal (TXR)
The transmitter ready flag (TXR) is set to logic “0” with the first
occurrence of an /LD2 pulse to indicate that the buffer is not
empty.
If a new data word is received before the previous data has
been read from the receiver buffer (as indicated by the /DRn
signal flip-flop), the receive buffer will not be over written by
the new data. The new data will remain in the shift register
until either the /DRn signal is reset and it can be written into
the receive buffer or it is overwritten by the next incoming
data word. Data in the shift register will be overwritten by
new incoming data, while data that has been latched into the
receive buffer can not be overwritten.
Output Register
The output register is designed such that it can shift out a word of
25 bits or 32 bits. The length is controlled by control register bit
"WLSEL".
Parity Generator
The parity generator calculates either odd or even parity as
specified by control register bit "PARCK". Odd parity is normally
used; even parity is available to test the receiver parity check
circuit. Odd parity means that there is an odd number of 1's in the
25 or 32 bit serial word. Bit 8 of word one is replaced with a
parity bit if parity is selected by the control register bit "PAREN"
and the /DBCEN pin. Otherwise, bit 8 is passed through as data.
Data Error Conditions
If the receiver input data word string is broken before the
entire data word is received, the receiver will reset and ignore
the partially received data word.
Transmitter Output
The transmitter driver outputs three TTL compatible signals: 1)
DO(A), 2) DO(B), and 3) TXCLK. DO(A) and DO(B) are the
transmitter data in two rail, return-to-zero format. DO(A)
indicates a logic "1" data bit by going to a "1" for the 1st half of a
bit time, then returning to "0" for the 2nd half; DO(B) remains at
"0" for the whole bit time. In the same fashion, DO(B) indicates a
logic "0" data bit by pulsing HI while DO(A) remains LO. A null
bit is indicated when both signals remain LO. It is illegal for both
signals to be logic "1". The TXCLK is a free running clock signal
of 50% duty cycle and in phase with transmitter data. The clock
will always be logic "1" during the first half of a bit time.
If the receiver input data word string is not properly framed
with at least 1 null bit before the word and 1 null bit after the
word, the receiver will reset and ignore the improperly framed
data word.
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 8 of 14
Power-Up Reset
Power-up reset and Master Reset:
An internal power-up reset circuit prevents erroneous data
transmission before an external master reset has been applied.
The user must apply an active Lo pulse to the Master Reset pin
(/MR) after power up or upon system reset. Preceding the master
reset at power-up an internal power-up reset occurs which will
clear the transmitter such that no erroneous serial data stream will
be transmitted before master reset. Receivers, control register, and
internal control logic are reset by master reset.
TX Word Gap Timer
The TX word gap timer circuit inserts a 4 bit time gap between
words. This gives a minimum requirement of a 29 bit time or a 36
bit time for each word transmission. The 4 bit time gap is also
automatically maintained when the next new block of data is
loaded into the buffer, which may take less than one bit time.
After resetting the device, the user must program the control
register before beginning normal operation. The control register
may be reprogrammed without additional reset pulses.
25-bit Word Operation:
The TRANSCEIVER implements a 25 bit word format which
may be used in non-ARINC applications to enhance data transfer
rate. The format is a simplified version of the 32 bit ARINC word
and is described in Figure 3. It consists of an 8 bit label, a 16 bit
data word, and a parity bit. The parity bit can optionally be
replaced with a 17th data bit. The Source/Destination code
checking option can be enabled in either receiver. It will operate
on bits 9 and 10 of the 25 bit word.
Serial Interface:
The DEI1116/1117 consists of two receive channels and one
transmit channel.
Each receive channel operates
independently of each other and the transmitter. The receive
data is asynchronous to the transmitter data and can also be at
a different data rate than the transmitter.
Transmitter
The transmitter clock is free running and in phase with the
transmitter data. The transmitter data (DO(A) and DO(B)) are
TTL level signals. There are always at least 4 null bits
between data words. An external ARINC line driver is
required to interface the transmitter to the ARINC serial data
bus. See ARINC 429 LINE DRIVERS below.
Self-Test Operation:
By selecting the control register bit (/SLFTST) self test option,
the user may perform a functional test of the TRANSCEIVER
and support circuitry. The user can write data into the transmitter
and it will be internally wrapped around into both receivers. The
user can then verify reception and integrity of the data. The
receiver line interface and the user's line drivers will not be tested.
Receiver
By setting the transmitter to use even parity, the user can test the
receiver's parity circuit operation.
The receiver signals (DI(A) and DI(B)) are differential,
bipolar, return-to-zero logic signals. The ARINC channels
can be connected directly to the receiver with no external
components on the DEI1116. The DEI1117 requires external
10K ohm series resistors.
Processor Interface:
Figure 7 shows a typical reset and initialization sequence. The
user must pulse the /MR pin low to reset the device. To load the
Control Register from the data bus, the /LDCW pin is pulsed low
while the desired control data is applied on the data bus.
ARINC 429 Line Driver
Device Engineering offers a complete line of ARINC line
drivers ICs that support the ARINC 429, 571, and 575
standards. Refer to DEI website at: http://www.deiaz.com.
Figure 5 shows a typical transmitter loading sequence. It begins
with the transmitter completing transmission of the previous data
block. The TXR flag goes HI to notify the user that data may be
loaded into the buffer. The user sets ENTX to LO to disable the
Transmitter and proceeds to load a total of six ARINC words into
the buffer. (Note that up to eight words could have been loaded).
The user then enables the transmitter by setting ENTX to a logic
"1" and the transmitter begins it's sequence of sending out data
words. Although not shown in the figure, the transmitter loading
sequence can be interrupted by receiver reading cycle with no
interference between the two operations.
Figure 6 shows a typical receiver reading sequence. Both
receivers notify the user of valid data ready by setting their
respective /DRn lines to logic "0". The user responds by first
reading the two data words from Receiver 1 and then from
Receiver 2. The SEL line is normally a system address line and
may assume any state, but must be valid when the /OEn line is
pulsed low.
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 9 of 14
Transmitter Ready
(TXR)
Enable Transmitter
(ENTX)
Load Word 1
(/LD1)
Load Word 2
(/LD2)
Data Bus
(D0 - D15)
(W1) (W2) (W1) (W2) (W1) (W2) (W1) (W2) (W1) (W2) (W1) (W2)
Transmitter Data
(DO(A)/DO(B))
Word 8
Word 1
TX Starts First Word
User Enables TX
User Loads 6th Word
User Loads 5th Word
User Loads 4th Word
User Loads 3rd Word
User Loads 2nd Word
TXR low indicates TX not Empty
User Loads 1st Word
User Disables TX
TXR HIGH indicates TX is empty and
user may load data
TXR transmitts last word from buffer
Figure 5: Typical Transmitter Load Sequence
Data Ready 1
(/DR1)
Data Ready 2
(/DR2)
Data Enable 1
(/OE1)
Data Enable 2
(/OE2)
Receiver Select
(SEL)
XXXXXXX
XXX
XXX
XXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXX
Data Bus (out)
(D0 - D15)
Word 1
Word 2
Word 1
Word 2
DR2 HIGH indicates
RX2 is empty
User Reads Word 1 and
Word 2 from RX2
DR1 HIGH indicates RX1
is Empty
User reads Word 1 and Word
2 from RX1
DR2 LOW indicates reception
of valid data from RX2
DR1 LOW indicates RX1 is
empty
Figure 6: Typical Receiver Read Sequence
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 10 of 14
MR
LDCW
D[15:0]
tMR
tPWLD
tHDW
tSDW
Valid Data
Figure 7: Reset and Initialization Sequence
BIT 31
BIT 32
ARINC DATA
/DR1, /DR2
SEL
tDDRN
tHSEL
tSSEL
/OE1, /OE2
D[15:0]
tPWOE
tOEOE
tDDROE
tDOEDR
Word 1 Valid
Word 2 Valid
tDTS
tDDR
Figure 8: Receiver Read Operation and Timing
Figure 9: Transmitter Write Operation and Timing
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 11 of 14
Figure 10: Transmitter Timing Diagram
Figure 11: Typical Transceiver/Line Driver Interconnect Configuration
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 12 of 14
Table 8: DEI1116/DEI1117 Ordering Information
DEI PART NUMBER (2)
MARKING (1)
REQUIRES EXT PACKAGE TEMP RANGE
DIxx 10K RES
PROCESSING (3)
DEI1116-QES-G
DEI1116-QMS-G
DEI1116-PMS-G
DEI1116-PES-G
DEI1117-QES-G
DEI1117-QMS-G
DEI1117-PMS-G
DEI1117-PES-G
Notes:
DEI1116-QES e3
DEI1116-QMS e3
DEI1116-PMS e3
DEI1116-PES e3
DEI1117-QES e3
DEI1117-QMS e3
DEI1117-PMS e3
DEI1117-PES e3
No
No
44 PQFP G
44 PQFP G
44 PLCC G
44 PLCC G
44 PQFP G
44 PQFP G
44 PLCC G
44 PLCC G
-55 / +85 °C
-55 / +125 °C
-55 / +125 °C
-55 / +85 °C
-55 / +85 °C
-55 / +125 °C
-55 / +125 °C
-55 / +85 °C
PLASTIC STANDARD
PLASTIC STANDARD
PLASTIC STANDARD
PLASTIC STANDARD
PLASTIC STANDARD
PLASTIC STANDARD
PLASTIC STANDARD
PLASTIC STANDARD
No
No
Yes
Yes
Yes
Yes
1. All packages marked with Lot Code and Date Code. “e3” or “e4” after Date Code denotes Pb Free category.
2. Suffix legend: -XYZ-G: X = package code, Y = temperature range code, Z = process flow code, -G = Green (Pb Free)
3. Contact factory for screening method of other packages
Table 9: Screening Process
Other Packages
PLASTIC STANDARD
-xxS
WAFER PROBE
Room Temp
THERMAL CYCLE -MIL-STD-883B M1010.4 Condition B
GROSS & FINE LEAK
NO
NO
NO
BURN IN -MIL-STD-883B M1015 Condition A
ELECTRICAL TEST
100%
ROOM TEMPERATURE
ELECTRICAL TEST
100% +125°C (-xMx)
100% +85°C (-xEx)
HIGH TEMPERATURE
ELECTRICAL TEST
0.65% AOQL @-55°C
LOW TEMPERATURE
Note: AOQL samples use a Zero Acceptance Number sampling plan per AS9100
Table 10: Package Characteristics
JEDEC
LEAD FINISH
THERMAL
RESIST
MOISTURE
SENSITIVITY
LEVEL
MATERIAL /
JEDEC
PACKAGE
REF
Pb Free
PACKAGE TYPE
JEDEC MO
θJC / θJA
(ºC/W)
DESIGNATION
Pb-Free
CODE
Matte Sn
e3
Matte Sn
e3
& PEAK
BODY TEMP
MSL 3
44L PLASTIC QUAD
FLAT PACK, GREEN
44L PLASTIC CHIP
CARRIER, GREEN
44 PQFP G
44 PLCC G
21/65
21/46
RoHS Compliant M0-112-AA-1
RoHS Compliant MS-018-AC
260ºC
MSL 3
245ºC
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 13 of 14
Figure 12: 44 Lead 13.90mm PQFP Mechanical Outline (44 PQFP)
Figure 13: 44 Lead PLCC Mechanical Outline
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding
suitability of its products for any particular purpose.
© 2012 Device Engineering Inc.
DS-MW-01117-01 Rev B
02/09/2012
Page 14 of 14
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