DEI1167-TMS-G [DEIAZ]
OCTAL GND/OPEN INPUT PARALLEL OUTPUT INTERFACE IC;
| 型号： | DEI1167-TMS-G |
| 厂家： | 
Device Engineering Incorporated |
| 描述： | OCTAL GND/OPEN INPUT PARALLEL OUTPUT INTERFACE IC 输入元件 输出元件 |
| 文件： | 总8页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Device
Engineering
Incorporated
DEI1167
OCTAL GND/OPEN INPUT,
PARALLEL OUTPUT INTERFACE IC
385 E. Alamo Dr.
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
FEATURES
x
Eight GND/OPEN discrete inputs
o
o
o
o
o
Meet electrical requirements for ABD0100 GND/OPEN discrete input.
Hysteresis provides noise immunity.
Internal pull up resistor
Internal isolation diode
Inputs protected from Lightning Induced Transients per DO160D, Section 22, Cat A3 and B3.
x
3.3V or 5V TTL/CMOS compatible digital IO
o
o
8 tri-state outputs
/CS & /OE control inputs
x
x
x
Logic Supply:
Analog Supply:
24L TSSOP package
3.3V or 5V
12V
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DO1
DO2
GND
DO3
DO4
VCC
DO5
DO6
DO7
DO8
GND
VDD
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
NC
DEI1167
Figure 1 DEI1167 Pin Assignment
(24 Lead TSSOP)
9
16
15
14
13
10
11
12
NC
/CS
/OE
Table 1 Pin Descriptions
Pins
Name
Description
8-1
DIN[8:1]
Discrete Inputs. Eight Ground/Open format discrete signals. These have an internal pull-
up to VDD. The threshold and hysteresis characteristics are determined by the applied
VDD voltage.
9-10
11
12
NC
/CS
/OE
Not Connected.
Chip Select Logic Input. Low input selects the device. Internal pull-up to VCC.
Output Enable Logic Input. Low input when /CS is low will enable the tri-state outputs.
Internal pull-up to VCC.
13
14
VDD
GND
Analog Supply. +12V
Analog Ground.
19
22
VCC
GND
Logic Supply. +3.3V or +5V
Logic Ground.
15-18,20,21,23,24
DO[8:1]
Logic Outputs. Eight tri-state data outputs.
©2015 Device Engineering Inc
Page 1 of 8
DS-MW-01167-01 Rev B
02/17/2015
FUNCTIONAL DESCRIPTION
The DEI1167 is an eight-channel parallel-output discrete-to-digital interface BICMOS device. It senses eight Ground/Open
discrete signals of the type commonly found in avionic systems. The data is read from the device via a parallel 3-state output.
O E
V C C
C E
V D D
2 K
2 K
2 K
1 2 K
1 2 K
D IN 1
+
D O 1
D O 2
T H R E S H O L D
A N D
H Y S T E R E S I S
-
D IN 2
D IN 3
+
-
T H R E S H O L D
A N D
H Y S T E R E S IS
1 2 K
+
-
D O 3
T H R E S H O L D
A N D
2 K
2 K
H Y S T E R E S IS
1 2 K
1 2 K
+
-
D IN 4
D IN 5
D O 4
D O 5
T H R E S H O L D
A N D
H Y S T E R E S IS
+
-
T H R E S H O L D
A N D
H Y S T E R E S IS
2 K
2 K
1 2 K
1 2 K
1 2 K
D IN 6
+
-
D O 6
D O 7
T H R E S H O L D
A N D
H Y S T E R E S IS
D IN 7
D IN 8
+
-
T H R E S H O L D
A N D
H Y S T E R E S IS
2 K
+
-
D O 8
G N D
T H R E S H O L D
A N D
H Y S T E R E S IS
Figure 2 DEI1167 Function Diagram
Table 2 Truth Table
/CE
L
L
H
X
/OE
L
L
X
H
DIN[8:1]
Open
Ground
X
DO[8:1]
L
H
High Z
High Z
X
©2015 Device Engineering Inc
Page 2 of 8
DS-MW-01167-01 Rev B
02/17/2015
DIN[8:1] INPUT STRUCTURE
Refer to Figure 2. Each DINn signal is conditioned by the resistor / diode network and presented to the comparator IN+. The
reference and hysteresis voltage is developed at the comparator IN-. Notable features:
x
x
When Vdd is +12V, the circuit shall source ~0.9mA to a grounded input. This current will prevent a “dry” relay
contact.
The input threshold voltage and hysteresis with Vdd = 12V ±10%:
o
o
o
The falling Vth > 3.5V
The rising Vth < 7.5V
Hysteresis > 1.5V
x
x
The comparator includes an RC filter to provide noise rejection of transient pulses of up to several us. Thus there is a
relatively large DINx setup time of several us (Refer to timing parameter tsu2).
The inputs can withstand continuous input voltages of 40V minimum. The isolation diode breakdown voltage is
greater than 50V. The 12K Ohm input resistor is designed to limit diode breakdown current to safe levels during
transient events.
TIMING DIAGRAMS
7.5
INPUT
3.5
tHL
tHL
1.5
OUTPUT
LO
CL = 30pF
Figure 3 Input to Output Delay
3.0
3.0
OE or CE
1.5
1.5
0
0
tZL
tHZ
tLZ
tZH
HIGH Z
HIGH Z
HI
0.2
1.3
1.3
OUTPUT
0.2
LO
HIGH Z
HIGH Z
VIN = VSS
RL = 1K: to VSS
CL = 30pF
VIN = VDD
RL = 1K: to VCC
CL = 30pF
Figure 4 Chip Select or Output Enable to Output Delay
©2015 Device Engineering Inc
Page 3 of 8
DS-MW-01167-01 Rev B
02/17/2015
LIGHTNING PROTECTION
DINn inputs are designed to survive lightning induced transients as defined by RTCA DO160D, Section 22, Cat A3 and B3,
Waveforms 3, 4, and 5A, Level 3. See waveforms below.
V
V/I
Peak
25% to 75%
of Largest Peak
T1 = 6.4uS
T2 = 70uS
50%
0
t
50%
F = 1MHZ and 10MHZ
0
t
T1
T2
Figure 5 Voltage / Current Waveform 3
Figure 6 Voltage Waveform 4
V/I
Peak
T1=40uS
T2=120uS
Waveform Source Impedance characteristics:
x
x
x
Waveform 3 Voc/Isc = 600V / 24A => 25 Ohms
Waveform 4 Voc/Isc = 300 V / 60 A => 5 Ohms
Waveform 5A Voc / Isc = 300V / 300A => 1 Ohm
50%
0
t
T1
T2
Figure 7 Current/Voltage Waveform 5A
©2015 Device Engineering Inc
Page 4 of 8
DS-MW-01167-01 Rev B
02/17/2015
ELECTRICAL DESCRIPTION
Table 3 Absolute Maximum Ratings
PARAMETER
MIN
-0.3
-0.3
MAX
+7.0
20
UNITS
Vcc Supply Voltage
Vdd Supply Voltage
V
V
Operating Temperature
Plastic Package
Storage Temperature
Plastic Package
-55
-55
+125
+150
°C
°C
Input Voltage
DIN[8:1]
Continuous
DO160D, Waveform 3, Level 3
DO160D, Waveform 4 and 5, Level 3
-5
+40
+600
+300
-600
-300
-1.5
-0.5
V
Logic Inputs
DO[8:1]
VCC + 1.5
VCC + 0.5
Power Dissipation @ 85 °C: (> 10 Sec)
24L TSSOP
Junction Temperature:
Tjmax, Plastic Packages
ESD per JEDEC A114-A Human Body Model
Logic and Supply pins
0.8
W
°C
V
145
2000
1000
260
DIN pins
Peak Body Soldering Temperature (10 sec duration)
°C
Notes:
1. Stresses above absolute maximum ratings may cause permanent damage to the device.
2. Voltages referenced to Ground
Table 4 Recommended Operating Conditions
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
VCC
VDD
5.0V±10%, 3.3V±10%
12V±10%
Logic Inputs
/CS, /OE
0 to VCC
Discrete Inputs
DIN[8:1]
0 to 40V
Operating Temperature
-TES
-TMS
-55 to +85 ºC
-55 to +125 ºC
©2015 Device Engineering Inc
Page 5 of 8
DS-MW-01167-01 Rev B
02/17/2015
Table 5 DC Electrical Characteristics
LIMITS
Symbol
Parameter
Test Conditions
VCC (V)
Unit
MAX
MIN
LOGIC INPUTS AND OUTPUTS
VIH
VIL
High level input voltage
Low level input voltage
High level output voltage
3.6
5.5
3.0
4.5
3.0
4.5
2.0
V
V
0.8
VOH
IOH = -20uA
VCC –
0.1
V
IOH = -4.5mA
IOL = 20uA
4.5
3.0
4.5
4.5
3.0
V
V
VOL
Low level output voltage
0.1
0.40
+10
-50
IOL = 4.5mA
V
IOZ
IIIL
3-state leakage current
Low level input current
Output in Hi Impedance state.
Vout = 0V and 5V
VIN = 0V
5.5
5.5
-10
uA
uA
-300
DISCRETE INPUTS
VDD = +12V
VIH
RIH
High level input voltage
High level Din-to-GND
resistance
Low level input voltage
Low level Din-to-GND
resistance
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
7.5
V
Ohm
V
Resistor from Din to GND to
guarantee HI input condition
50K
VIL
RIL
3.5
Resistor from Din to GND to
guarantee LO input condition
500
Ohm
V
VIhst
IIH
Input hysteresis voltage
High level input current
1.3
-420
-1.2
Vin =7.5V
Vin = 0V
-190
-0.6
uA
IIL
Low level input current
mA
SUPPLY VOLTAGES
VDD = +12V
ICC
IDD
Quiescent logic supply current
Vin(logic) = Vcc or GND
VIN[8:1] = open
Vin(logic) = Vcc or GND
DIN[8:1] = Open
5.5
800
uA
Quiescent analog supply current
5.5
5.5
11
24
mA
DIN[8:1] = GND
Notes:
1. Current flowing into DUT is positive. Current flowing out of DUT is negative. Voltages are referenced to GND.
©2015 Device Engineering Inc
Page 6 of 8
DS-MW-01167-01 Rev B
02/17/2015
Table 6 AC Electrical Characteristics
Symbol
Parameter
VCC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
5.0
Limits
Unit
-55 to 85ÛC -55 to 125ÛC
tZLmax
tZHmax
Maximum propagation delay, /CSĻ and /OEĻ to DO. (1) (3)
166
88
70
166
118
108
0.4
183
98
76
183
130
120
0.4
ns
tHZmax
tLZmax
Maximum propagation delay, /CSĹ or / OEĹ to DO HI-Z.
from D0 Low or high. (1) (2) (3)
ns
tHLmin
tLHmin
tHlmax
tLHmax
Cin-max
Minimum data propagation delay, Din to DO (4) (5)
Maximum data propagation delay, Din to DO (4) (5)
Maximum logic input Capacitance. (6)
us
us
5.0
420
630
10
15
10
15
pF
pF
Cout-max Maximum DO pin capacitance, output in HI-Z state. (6)
Notes:
1. DO is loaded with 50pF to GND.
2. DO is loaded with 1K Ohms to GND for High output, 1K Ohms to VCC for Low output.
3. Timing measured from VIN=1.5V to 'VOUT=200mV. See Figure 4
4. See Figure 3
5. The delay is due to both the on chip filter circuits and VDD.
6. Guaranteed by design.
7. All measurements at VDD = 12V
ORDERING INFORMATION
Part Number
DEI1167-TES-G
DEI1167-TMS-G
Marking
DEI1167-TES
DEI1167-TMS
Package
24 TSSOP
24 TSSOP
Temperature
-55 / +85 ºC
-55 / +125 ºC
Note: Part is marked with “E4” after date code to denote lead free category
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or
guarantee regarding suitability of its products for any particular purpose.
©2015 Device Engineering Inc
Page 7 of 8
DS-MW-01167-01 Rev B
02/17/2015
PACKAGE DESCRIPTION
24L TSSOP
Moisture Sensitivity:
Ĭja:
Ĭjc:
Level 2 /260ÛC per JEDEC J-STD-020A (1yr floor life)
84ÛC/W (Mounted on 4 layer PCB)
16ÛC/W
Lead Finish:
Materials:
NiPdAu plated
RoHS compliant
Figure 8 24 Lead TSSOP Outline Drawing
©2015 Device Engineering Inc
Page 8 of 8
DS-MW-01167-01 Rev B
02/17/2015
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