DEI1184-SMS [DEIAZ]
8CH PROGRAMMABLE DISCRETE INTERFACE W/ EXT HV PROTECTION;
| 型号： | DEI1184-SMS |
| 厂家： | 
Device Engineering Incorporated |
| 描述： | 8CH PROGRAMMABLE DISCRETE INTERFACE W/ EXT HV PROTECTION 光电二极管 接口集成电路 |
| 文件： | 总14页 (文件大小：786K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Device
Engineering
Incorporated
DEI1184
8CH PROGRAMMABLE DISCRETE
INTERFACE W/ EXT HV
PROTECTION
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
FEATURES
·
Eight discrete inputs
o
o
Individually configurable as either GND/OPEN or 28V/OPEN (or 28V/GND) format input.
Input threshold and hysteresis per Airbus ABD0100H specification.
§
§
GND/OPEN mode: 4.5 V / 10.5 V input levels, 3 V hysteresis
28V/OPEN mode: 6 V / 12 V input levels, 3V hysteresis
o
o
o
1mA input current to prevent dry relay contacts.
Internal isolation diode in GND/OPEN mode.
Uses external series 3 kΩ resistors on inputs to implement lightning transient immunity of DO160, Section 22
Level 3, and higher levels with the addition of small TVS devices.
·
Serial I/O interface to read data register and write configuration register
o
o
o
o
Direct interface to Serial Peripheral Interface (SPI) port.
TTL/CMOS compatible inputs and Tristate output
10 MHZ Max Data Rate
Serial input to expand Shift Register
·
·
·
Logic Supply Voltage (VCC):
Analog Supply Voltage (VDD):
16L SOIC EP package
3.3 V +/-5%
15 V +/-10%
PIN ASSIGNMENTS
1
16
VDD
GND
VCC
SEL
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DEI1184
SDI
/CS
SCLK
SDO
Figure 1 DEI1184 Pin Assignment (16 Lead SOIC)
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FUNCTIONAL DESCRIPTION
DEI1184 is an eight-channel discrete-to digital interface IC implemented in an HV DIMOS technology. It senses eight discrete
signals of the type commonly found in avionic systems and converts them to serial logic data. Each input can be individually
configured as either GND/OPEN or 28V/OPEN format input via a serial data input. The discrete data is read from the device via
an eight-bit serial shift register with 3-state output. This serial interface is compatible with the industry standard Serial Peripheral
Interface (SPI) bus.
The discrete input circuits are designed to achieve a high level of lightning transient immunity. The application design provides
a series 3 kΩ resistor on each discrete input to achieve DO160E Level 3 and WF5A 500 V immunity. Higher immunity levels
can be achieved (i.e. Level 5) with the addition of a TVS between the resistor and the input pin.
Table 1 Pin Descriptions
PINS
NAME
DESCRIPTION
1-8
DIN[1:8]
Discrete Inputs. Eight discrete signals which can be individually
configured as either GND/OPEN or 28V/OPEN format inputs. Inputs are
connected to the external series 3 kΩ resistor as part of front end
Lightning Transients protection circuit.
9
SDO
Logic Output. Serial Data Output. This pin is the output from MSB (Bit
8) of the selected shift register (Data/Configuration). It is clocked by the
rising edge of SCLK. This is a 3-state output enabled by /CS.
Logic Input. Serial Shift Clock. A low-to-high transition on this input
shifts data on the serial data input into Bit 1 of the selected shift register.
The selected shift register is shifted from Bit 1 to Bit 8. Bit 8 of the
selected shift register is driven on DOUT.
10
SCLK
11
12
/CS
SDI
Logic Input. Chip Select. A low level on this input enables the SDO 3-
state output and the selected shift register. A high level on this input
forces DOUT to the high impedance state and disables the shift registers
so SCLK transitions have no effect. When the Data Register is selected,
a high-to-low transition causes the Discrete Input data to be loaded into
the Data Register. When the Configuration Register is selected, a low-to-
high transition causes the Serial Configuration Register data to be loaded
into the parallel configuration outputs.
Logic Input. Serial Data Input. Data on this input is shifted into the LSB
(Bit 1) of the selected shift register on the rising edge of the SCLK when
/CS input is low.
13
14
SEL
Logic Input with weak pull-up. Selects between the Data Register and
Configuration Register. H = DATA, L = CONF.
Logic Supply Voltage. 3.3 V +/-5%
VCC
15
16
GND
VDD
Logic/Signal Ground
Analog Supply Voltage. 15 V +/-10%
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Figure 2 Function Diagram
Figure 3 Discrete AFE Function Diagram
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Table 2 Truth Table
Serial Interface Operation
SEL
X
H
/CS SCLK
SDI
X
X
DIN[1:8]
SDO
HI Z
DIN[8]
DR[8]
Description
Not Selected
DR[1:8]← DIN[1:8]
H
↓
X
L
↑
X
Valid
X
H
L
DR[1]
DR[n+1] ← DR[n], DR[1] ← SDI
L
L
L
↑
↑
L
CR[1]
X
X
X
CR[8]
HI Z
CR[n+1] ← CR[n], CR[1] ← SDI
CL[1:8]← CR[1:8]
Legend:
DR = Data Register
CR = Configuration Register
CL = Configuration Latch
X = Don’t Care
DIN[1:8] Discrete AFE
The Discrete Input Analog Front End circuit function is represented in Figure 3. Each DINn signal is conditioned by the resistor
/ diode network and presented to a comparator with hysteresis. The external 3 kΩ resistor is part of the front-end circuitry for
achieving threshold and hysteresis requirements while protecting the chip from Lightning Induced Transients. When the input is
configured for GND/OPEN operation (By programming the channel’s configuration register bit to 1), the pull-up resistor and
diode is enabled by turning PMOS switch on and BJT switch off. The comparator reference voltage corresponding to DINn
input threshold (shown below) is generated from resistive network. When configured for 28V/OPEN operation, the pull-down
resistor is enabled by turning BJT on and PMOS off. The comparator reference voltages for 28V/OPEN operation are configured
corresponding to DINn input threshold voltages described below.
Some notable features are:
·
·
The input current is ~1 mA. This current will prevent a “dry” relay contact.
The input threshold voltage and hysteresis:
o
o
28V/OPEN
·
·
·
Low- level input voltage:
High level input voltage:
Hysteresis:
-3.0 V to 6.0 V
12 V to 49 V
Vhys > 3V
GND/OPEN
·
·
·
Low- level input voltage:
High level input voltage:
Hysteresis:
-3.0 V to 4.5 V
10.5 V to 49 V
Vhys > 3 V
·
·
Input noise immunity is maximized with a combination of voltage hysteresis and use of a slow input voltage comparator.
The inputs can withstand continuous input voltages of 49 V. The isolation diode breakdown voltage is greater than
42V. The 10 kΩ input resistance, which consists of a 7 kΩ on-chip resistor and a 3 kΩ off-chip resistor, is designed to
limit diode breakdown current to safe levels during transient events.
Data Register
The 8-bit Data Register is a “parallel-input, serial-output” register that samples the input channels and reads-out the data to the
Serial Data Output. The register is read via the SDO output as described in Figure 4 and Figure 5. A low DIN input level
results in a Logic 0, and a high input level results in a Logic 1.
Configuration Register
The 8-bit Configuration Register is a “serial-input, parallel-output with data latch” register that individually configures each
AFE input as either GND/OPEN or 28V/OPEN format. The register is programmed via the serial data input as described in
Figure 6 and Figure 7. Logic 0 sets the respective input to 28V/OPEN mode (pull-down); Logic 1 sets the respective input to
GND/OPEN mode (pull-up). The register is reset to 0’s when the VCC Logic Supply voltage transitions from low to high.
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Serial Interface
The DEI1184 incorporates a serial IO interface for programming the Discrete Input configuration and for reading the Discrete
Input status. Refer to Figure 2. The interface is SPI compatible and consists of /CS, SEL, SCLK, SDO, and SDI signals.
Waveform Figures 4 – 7 depict the Data Read sequence and Configuration Write sequence for both 8-Bit cycles and also 16 bit
“daisy chain” applications.
Power Up Initialization
The DEI1184 incorporates an on-chip power-on reset (POR) circuit and power sequencing provisions to force the DIN inputs to
a high impedance state at power up; the AFE pull-up (PMOS switch in Figure 3) and pull-down (BJT switch in Figure 3) circuits
are disabled. The reset circuit monitors the VCC logic supply and forces the AFE to the high impedance state while VCC is
stabilizing. It will remain in this state until the Configuration Register is programmed by the first Write Configuration Register
cycle, when the pull-up or pull-down state is determined.
SEL
/CS
X
SCLK
X
VALID
X
X
DIN[1:8]
X
X
SDI
SDO
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN inputs latched into DATA S-Reg
Figure 4 Read Data Register
SEL
/CS
X
SCLK
X
VALID
X
X
DIN[1:8]
SI8
SI7
SI6
SI5
SI4
SI3
SI2
SI1
X
X
SDI
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
SI8
Si7
SI6
SI5
SI4
SI3
SI2
SI1
SDO
DIN inputs latched into DATA S-Reg
SDI data shifted to SDO after 8 bit delay
Figure 5 Read Data Register, 16 Bit Daisy Chain
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SEL
/CS
X
SCLK
X
X
DIN[1:8]
NCD
8
NCD
7
NCD
6
NCD
5
NCD
4
NCD
3
NCD
2
NCD
1
X
X
SDI
PCD
8
PCD
7
PCD
6
PCD
5
PCD
4
PCD
3
PCD
2
PCD
1
NCD
8
SDO
PDO[1:8]
Internal Config Latch
New
Configuration
Present Configuration
NCDn = New Configuration Data Bits
PCDn = Present Configuration Bits
Figure 6 Write Configuration Register
SEL
/CS
X
SCLK
X
X
DIN[1:8]
DCD
8
DCD
7
DCD
6
DCD
5
DCD
4
DCD
3
DCD
2
DCD
1
NCD
8
NCD
7
NCD
6
NCD
5
NCD
4
NCD
3
NCD
2
NCD
1
X
X
SDI
PCD
8
PCD
7
PCD
6
PCD
5
PCD
4
PCD
3
PCD
2
PCD
1
DCD
8
DCD
7
DCD
6
DCD
5
DCD
4
DCD
3
DCD
2
DCD
1
NCD
8
SDO
New
Configuration
PDO[1:8]
Internal
Config
Latch
Present Configuration
DCDn = Daisy Chain Data Bits
NCDn = New Configuration Data Bits
PCDn = Present Configuration Bits
Figure 7 Write Configuration Register, 16 bit Daisy Chain
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LIGHTNING PROTECTION
DINn inputs are designed to survive lightning induced transients as defined by RTCA DO160E, Section 22 Cat A3 and B3,
Waveforms 3, 4, and 5A. They can withstand Level 3 stress (see waveforms below) with only the external 3 kΩ series resistor
for current limiting. Protection for higher stress levels can be achieved with the addition of transient voltage suppressor (TVS)
devices at the DINn pins. Select TVS clamp voltage <450 V. The 3 kΩ series resistors limit the TVS surge current.
V
V/I
Peak
25% to 75%
of Largest Peak
T1 = 6.4 us
T2 = 70 us
50%
0
t
50%
F = 1 MHZ and 10 MHZ
0
t
T1
T2
Figure 8 Voltage / Current Waveform 3
Figure 9 Voltage Waveform 4
V/I
Peak
T1 = 40 us
T2 = 120 us
Level 3 Waveform Source Impedance characteristics:
·
·
·
·
Waveform 3 Voc/Isc = 600 V / 24A => 25 Ω
Waveform 4 Voc/Isc = 300 V / 60 A => 5 Ω
Waveform 5A Voc / Isc = 300 V / 300 A => 1 Ω
Waveform 5A Voc / Isc = 500 V / 500 A => 1 Ω
50%
0
t
T1
T2
Figure 10 Current/Voltage Waveform 5A
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ELECTRICAL DESCRIPTION
Table 3 Absolute Maximum Ratings
PARAMETER
MIN
-0.3
-0.3
MAX
+5.0
18
UNITS
VCC Supply Voltage
VDD Supply Voltage
V
V
Operating Temperature
Storage Temperature
-55
-55
+125
+150
°C
°C
Input Voltage (3)
DIN[1:8]
Continuous
DO160E, Waveform 3, Level 3
DO160E, Waveform 4 and 5, Level 3
DO160E, Waveform 4 and 5
DO160E, Abnormal Surge Voltage, 100 ms
-10
+49
+600
+300
+500
80
V
V
V
V
V
V
V
-600
-300
-500
Logic Inputs
DOUT
-1.5
-0.5
VCC + 1.5
VCC + 0.5
Power Dissipation @ 125 °C, steady state
Junction Temperature, Tjmax
0.5
W
145
°C
ESD per JEDEC A114-A Human Body Model
Logic and Supply pins
2000
1000
V
DIN pins
Peak Body Temperature (10 sec duration)
235
°C
Notes:
1. Stresses above absolute maximum ratings may cause permanent damage to the device.
2. Voltages referenced to Ground
3. Stress applied to external 3 kΩ series resistor in series with DINn pin.
Table 4 Recommended Operating Conditions
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
VCC
VDD
3.3 V ±5%
15 V ±10%
Logic Inputs and Outputs
Discrete Inputs
0 to VCC
-3 to 49 V
DIN[1:8]
Ta
Operating Temperature
-55 to +125 ºC
-55 to +85 ºC
-SMS
-SES
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Table 5 DC Electrical Characteristics
CONDITIONS (1)
SYMBOL
PARAMETER
LIMITS
NOM
UNIT
MIN
MAX
Logic Inputs/Outputs
VCC = 3.3 V
VIH
VIL
HI level input voltage
LO level input voltage
2.0
50
V
V
0.8
VIhst
Input hysteresis voltage,
SCLK input
(3)
mV
VOH
VOL
HI level output voltage
IOUT = -20 uA
VCC – 0.1
2.4
V
V
IOUT = -4 mA, VCC = 3 V
IOUT = 20 uA
LO level output voltage
0.1
0.4
10
V
IOUT = 4 mA, VCC = 3 V
VIN = VCC or GND
V
IIN
Input leakage, except SEL
Input leakage, SEL
-10
uA
uA
IIN-SEL
VIN = VCC
VIN = GND
-10
-50
10
10
IOZ
3-state leakage current
Output in Hi Impedance state.
VOUT = VIHmin, VILmax
-10
10
49.0
1
uA
Discrete Inputs, Configured as Ground/Open (internal pull-up) (4)
VIH
RIH
HI level input voltage
10.5
50
V
HI level Din-to-GND
resistance
Resistor from Din to GND to
guarantee HI input condition.
kΩ
IIH
HI level input current
VIN = 28 V, VDD = 15 V
VIN = 49 V, VDD = 15 V
0.66
0.8
mA
mA
VIL
RIL
LO level input voltage
-3.0
4.5
V
LO level Din-to-GND
resistance
Resistor from Din to GND to
guarantee LO input condition.
500
Ω
IIL
LO level input current
Input hysteresis voltage
VIN = 0V, VDD = 15 V
-0.8
3
-1.3
-1.8
mA
V
VIhst
Discrete Inputs, Configured as 28V/Open (internal pull-down) (4)
VIH
IIH
HI level input voltage
12.0
0.8
49.0
1.8
6.0
50
V
mA
V
HI level input current
LO level input voltage
LO level input current
Input hysteresis voltage
VIN = 28 V, VDD = 15 V
VIN = 1 V, VDD = 15 V
Power Supply
1.3
25
VIL
IIL
-3.0
uA
V
VIhst
3
ICC
IDD
Max quiescent logic supply
current
VIN(logic) = VCC or GND
VIN[1:8]= open
1.8
3
mA
mA
Max quiescent analog supply VIN(logic) = VCC or GND
current
VIN[1:8]= Open
VIN[1:8]= GND, All
configured as Ground/Open
15
22
24
33
Notes:
1. Ta = -55 to +125 ºC. VDD = 15 V ±10%, VCC = 3.3 V +/-5% unless otherwise noted.
2. Current flowing into device is ‘+’. Current flowing out of device is ‘- ‘. Voltages are referenced to Ground.
3. Guaranteed by design. Not production tested.
4. With 3 kΩ, 2% resistor in series with DIN input pin.
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Table 6 AC Electrical Characteristics (4)
PARAMETER CONDITIONS (6,7)
LIMITS
SYMBOL
UNIT
MIN
0.1
MAX
10
fMAX
tW
SCLK frequency. (50% duty cycle) (5)
SCLK pulse width. (5)
MHZ
ns
50
tsu1
th1
tsu2
th2
tsu3
th3
tsu4
th4
tp1
tp2
tp3
Setup time, SCLK low to /CS↓.
Hold time, /CS↓ to SCLK↑.
30
25
500
15
25
25
30
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup time, DIN valid to /CS↓.
Hold time, /CS↓ to DIN not valid.
Setup time, SDIN valid to SCLK↑.
Hold time, SCLK↑ to SDIN not valid.
Setup time, SEL valid to /CS↓.
Hold time, SEL valid to /CS↑.
Propagation delay, /CS↓ to DOUT valid. (1)
Propagation delay, SCLK↑ to DOUT valid. (1)
Propagation delay, /CS↑ to DOUT HI-Z. (1)
(2) (3)
105
90
80
tp4
Cin
Cout
Delay time between /CS active. (5)
Maximum logic input pin Capacitance. (5)
Maximum DOUT pin capacitance, output in
HI-Z state. (5)
20
ns
pf
pf
10
15
Notes:
1. DOUT loaded with 50 pF to GND.
2. DOUT loaded with 1 kΩ to GND for Hi output, 1 kΩ to VCC for Low output.
3. Timing measured at 25% VCC for “0” to Hi-Z, 75% VCC for “1” to Hi-Z.
4. Sample tested on lot basis.
5. Not tested
6. Ta = -55 to +125 ºC. VCC = 3 V, VDD = 15 V, VIL = 0 V, VIH = VCC unless otherwise noted.
7. Measurements made at 50% VCC.
th4
tsu4
SEL
/CS
tp4
th1
tW
tsu1
SCLK
1/fmax
tsu2
th2
valid
X
X
DIN[1:8]
tsu3
th3
X
valid
X
SDI
tp2
tp1
tp3
D/C0
D/C1
SDO
Figure 11 Switching Waveforms
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APPLICATION INFORMATION
Discrete Input Filtering
The DEI1184 Analog Front End provides a moderate level of noise immunity via a combination hysteresis and limited bandwidth.
The Hysteresis is 3 V minimum and the comparator bandwidth is approximately 10 MHZ.
Many applications provide additional noise immunity by means of debounce/filtering in software or in digital circuitry (i.e.:
FPGA). Common input debounce techniques are readily found with a web search of the term “software debounce” and range
from simple detectors of two or more sequential stable readings to FIR filters emulating RC time constants.
Input Current Characteristics
The DIN Input Current vs. Voltage characteristics for the 28V/OPEN Mode and GND/OPEN Mode are shown in Figure 12 and
Figure 13.
Discrete Input Characteristics (28V/OPEN)
2.50
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-10.00
0.00
10.00
20.00
30.00
40.00
50.00
Discrete Input Voltage (V)
Figure 12 28V/Open Mode Input IV Characteristics (VDD=15 V)
Discrete Input Characteristics (GND/OPEN)
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-10.0
0.0
10.0
20.0
30.0
40.0
50.0
Discrete Input Voltage (V)
Figure 13 GND/OPEN Mode Input IV Characteristics (VDD=15 V)
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Package Power Dissipation
The DEI1184 package power dissipation varies with channel configuration and operating conditions. Figure 14 shows the
device package power dissipation for various conditions. This includes the contributions from Supply currents and Input
currents. The four curves are as follows:
Table 7 Legend for Power Dissipation Curves
CURVE ID
+28V/OPEN-Nom
+28V/OPEN-Wst
GND/OPEN-Nom
GND/OPEN-Wst
SUPPLY VOLTAGE, TEMPERATURE,
IC VARIATION
3.3 V, 12 V / 27 ºC / typical IC parameters
3.3 V, 16.5 V / 125 ºC /
Worst case IC parameters
3.3 V, 12 V / 27 ºC / typical IC parameters
3.3 V, 16.5 V / 125 ºC /
Worst case IC parameters
Notes: The active channels are forced to Ground for GND/OPN type and forced to 28 V for 28V/OPN
type.
Figure 14 Power Dissipation for Various Conditions
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PACKAGE DESCRIPTION - 16L Narrow Body EP SOIC
Moisture Sensitivity:
Θja:
Level 1 / 260 ˚C per JEDEC J-STD-020
~40 ˚C/W (Mounted on 4 layer PCB with exposed pad soldered to PCB land with
thermal vias to internal GND plane)
~10 ˚C/W
Θjc:
Lead Finish:
Exposed Pad:
SnPb plated
Electrically Isolated from IC terminals.
The PCB design and layout is a significant factor in determining thermal resistance (Θja) of the IC package. Use maximum trace
width on all power and signal connections at the IC. These traces serve as heat spreaders which improve heat flow from the IC
leads. The exposed heat sink pad of the SOIC package should be soldered to a heat-spreader land pattern on the PCB. The IC
exposed pad is electrically isolated, so the PCB land may be at any potential, typically GND, for the best heat sink. Maximize
the PCB land size by extending it beyond the IC outline if possible. A grid of thermal VIAs, which drop down and connect to
the buried copper plane(s), should be placed under the heat-spreader land. A typical VIA grid is 12 mil holes on a 50 mil pitch.
The barrel is plated to about 1.0-ounce copper. Use as many VIAs as space allows. VIAs should be plugged to prevent voids
being formed between the exposed pad and PCB heat-spreader land due to solder escaping by the capillary effect. This can be
avoided by tenting the VIAs with solder mask.
Figure 15 16 Lead Narrow Body EP SOIC Outline Drawing
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ORDERING INFORMATION
Table 8 Ordering Information
Part Number
DEI1184-SMS
DEI1184-SES
Marking
Package
Temperature
-55 / +125 ºC
-55 / +85 ºC
DEI1184-SMS
DEI1184-SES
16 EP SOIC
16 EP SOIC
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