DA16200MOD-AAE4WA32_技术文档

DA16200MOD

Final

Ultra Low Power Wi-Fi Module

General Description

The DA16200MOD is a fully integrated Wi-Fi^®module with ultra-low power consumption, best RF

performance and easy development environment. Such low power operation can extend the battery

life as longer as a year or more depending on the application.

This module series included DA16200-00000A32, 40 MHz crystal oscillator, 32.768 KHz RTC clock,

RF Lumped RF filter, 4 M-byte flash memory and chip antenna or u.FL connector. The

DA16200MOD has chip antenna type (DA16200MOD-AAC4WA32) and u.FL connector type

(DA16200MOD-AAE4WA32) for external antenna.

The Module is built from the ground up for the Internet of Things (IoT) and is ideal for door locks,

thermostats, sensors, pet trackers, asset trackers, sprinkler systems, connected lighting, video

cameras, video door bells, wearables and other IoT devices.

The modules certified Wi-Fi alliance for IEEE802.11b/g/n, Wi-Fi Direct, WPS functionalities and it has

been approved by many countries including the United States (FCC), Canada (IC) and China

(SRRC). Using the Wi-Fi Alliance transfer policy, the Wi-Fi Certifications can be transferred without

being tested again.

For more information on DA16200MOD, please refer to DA16200-00000A32 datasheet.

Key Features

■

Module variants

■

Built-in 4-channel auxiliary ADC for sensor

interfaces

□

DA16200MOD-AAC4WA32 (chip Antenna)

DA16200MOD-AAE4WA32 (u.FL cont.)

□

12-bit SAR ADC: single-ended four

channels

■

Highly integrated ultra-low power Wi-Fi^®

system module

□

Provides dynamic auto switching function

Supports various interfaces

□

Sleep current: 3.5 uA, VBAT=3.3 V

□

eMMC/SD expanded memory

SDIO Host/Slave function

QSPI for external flash control

Three UARTs

Best RF Performance

□

Tx Power: +19 dBm, 1 Mbps DSSS

Rx Sensitivity: -98.5 dBm, 1 Mbps DSSS

■

Full offload: SoC runs full networking OS and

TCP/IP stack

SPI Master/Slave interface

I2C Master/Slave interface

I2S for digital audio streaming

4-channel PWM

Wi-Fi processor

□

IEEE 802.11b/g/n, 1x1, 20 MHz channel

bandwidth, 2.4 GHz

□

IEEE 802.11s Wi-Fi mesh

Individually programmable, multiplexed

GPIO pins

Wi-Fi security: WPA/WPA2-

Enterprise/Personal, WPA2 SI, WPA3

SAE, and OWE

□

JTAG and SWD

■

Wi-Fi Alliance certifications:

□

Vendor EAP types: EAP-

TTLS/MSCHAPv2, PEAPv0/EAP-

MSCHAPv2, PEAPv1, EAP-FAST, and

EAP-TLS

□

Wi-Fi CERTIFIED™ b, g, n

WPA™ - Enterprise, Personal

WPA2™ - Enterprise, Personal

WPA3™ - Enterprise, Personal

□

Operating modes: Station, SoftAP, and

Wi-Fi Direct^®Modes (GO, GC, GO fixed)

■

RF Regulatory certifications

FCC, IC, CE, KC, TELEC, SRRC

□

WPS-PIN/PBC for easy Wi-Fi provisioning

□

Connection manager for autonomous and

fast Wi-Fi connections

CPU core subsystem

□

Bluetooth coexistence

□

Arm® Cortex®-M4F core w/ clock

frequency of 30~160 MHz

Antenna switching diversity

Datasheet

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■

Hardware accelerators

□

ROM: 256 KB, SRAM: 512 KB, OTP: 8

KB, Retention Memory: 48 KB

□

General HW CRC engine

■

SPI flash Memory

32 M-bit / 4 M-byte

External Clock source

HW zeroing function for fast booting

□

Pseudo random number generator

(PRNG)

■

Complete software stack

□

40 MHz crystal (± 25 ppm) for master

clock (initial + temp + aging)

□

Comprehensive networking software stack

□

32.768 kHz crystal (± 250 ppm) for RTC

clock

Provides TCP/IP stack: in the form of

network socket APIs

■

Supply

Advanced security

□

Operating voltage: 2.1 V to 3.6 V (typical:

3.3 V)

□

Secure booting

Secure debugging using JTAG/SWD and

UART ports

□

2 Digital I/O Supply Voltage: 1.8 V / 3.3 V

Black-out and brown-out detector

□

Secure asset storage

■

Module Dimensions

13.8 mm × 22.1 mm x 3.3 mm, 37 Pins,

Operating temperature range

□ -40 °C to 85 °C

■

Built-in hardware crypto engines for advanced

security

□

TLS/DTLS security protocol functions

Crypto engine for key deliberate generic

security functions: AES (128,192,256),

DES/3DES, SHA1/224/256, RSA, DH,

ECC, CHACHA, and TRNG

Power management unit

□

On-Chip RTC

Wake-up control of fast booting or full

booting with minimal initialization time

□

Supports three ultra-low power sleep

modes

Datasheet

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Applications

DA16200MOD is a full offload SoC for IoT Applications, such as:

■

Security systems

Door locks

Thermostats

Garage door openers

Blinds

Lighting control

Sprinkler systems

Video camera security systems

Smart appliances

Video door bell

Asset tracker

System Diagram

Figure 1: System Diagram

Datasheet

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Contents

General Description ............................................................................................................................ 1

Key Features ........................................................................................................................................ 1

Applications ......................................................................................................................................... 3

System Diagram .................................................................................................................................. 3

1

2

3

4

Terms and Definitions................................................................................................................... 8

References ..................................................................................................................................... 8

Block Diagram ............................................................................................................................... 9

Pinout ........................................................................................................................................... 11

4.1 Pin-out Description (37 pins)............................................................................................... 11

4.2 Pin Multiplexing................................................................................................................... 13

5

Electrical Specification............................................................................................................... 15

5.1 Absolute Maximum Ratings ................................................................................................ 15

5.2 Recommended Operating Conditions................................................................................. 15

5.3 Electrical Characteristics..................................................................................................... 15

5.3.1

5.3.2

5.3.3

5.3.4

DC Parameters, 1.8 V IO..................................................................................... 15

DC Parameters, 3.3 V IO..................................................................................... 16

DC Parameters for RTC Block ............................................................................ 16

DC Parameters for Digital Wake-up .................................................................... 16

5.4 Radio Characteristics.......................................................................................................... 17

5.4.1

5.4.2

WLAN Receiver Characteristics .......................................................................... 17

WLAN Transceiver Characteristics...................................................................... 17

5.5 Current Consumption.......................................................................................................... 18

5.6 Radiation Performance ....................................................................................................... 19

5.7 ESD Ratings........................................................................................................................ 19

5.8 Clock Electrical Characteristics........................................................................................... 19

5.8.1

5.8.2

RTC Clock Source............................................................................................... 19

Main Clock Source............................................................................................... 19

6

7

Power Management..................................................................................................................... 20

6.1 Power On Sequence........................................................................................................... 20

6.2 Low Power Operation Mode ............................................................................................... 20

6.2.1

6.2.2

6.2.3

Sleep Mode 1....................................................................................................... 20

Sleep Mode 2....................................................................................................... 21

Sleep Mode 3....................................................................................................... 21

Core System ................................................................................................................................ 22

7.1 ARM Cortex-M4F Processor............................................................................................... 22

7.2 Wi-Fi Processor................................................................................................................... 22

7.3 RTC..................................................................................................................................... 22

7.3.1

7.3.2

Wake-up Controller.............................................................................................. 23

Retention I/O Function......................................................................................... 23

7.4 Pulse Counter ..................................................................................................................... 24

7.4.1

7.4.2

Introduction .......................................................................................................... 24

Functional Description ......................................................................................... 24

8

Peripherals................................................................................................................................... 25

Datasheet

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8.1 QSPI: Master with XIP Feature........................................................................................... 25

8.2 SPI Master .......................................................................................................................... 27

8.3 SPI Slave ............................................................................................................................ 28

8.4 SDIO.................................................................................................................................... 30

8.5 I2C Interface........................................................................................................................ 32

8.5.1

8.5.2

I2C Master ........................................................................................................... 32

I2C Slave ............................................................................................................. 33

8.6 SD/SDeMMC....................................................................................................................... 35

8.6.1 Block Diagram ..................................................................................................... 35

8.7 I2S....................................................................................................................................... 36

8.7.1

8.7.2

8.7.3

Block Diagram ..................................................................................................... 37

I2S Clock Scheme ............................................................................................... 37

I2S Transmit and Receive Timing Diagram......................................................... 38

8.8 ADC (Aux 12-bit)................................................................................................................. 39

8.8.1

8.8.2

8.8.3

8.8.4

8.8.5

Overview.............................................................................................................. 39

Timing Diagram ................................................................................................... 40

DMA Transfer ...................................................................................................... 40

Sensor Wake-up.................................................................................................. 41

ADC Ports............................................................................................................ 41

8.9 GPIO ................................................................................................................................... 41

8.9.1

Antenna Switching Diversity ................................................................................ 41

............................................................................................................................. 43

8.10 UART

8.10.1 RS-232................................................................................................................. 44

8.10.2 RS-485................................................................................................................. 45

8.10.3 Baud Rate............................................................................................................ 45

8.10.4 Hardware Flow Control........................................................................................ 46

8.10.5 Interrupts.............................................................................................................. 46

8.10.6 DMA Interface...................................................................................................... 47

8.11 PWM

............................................................................................................................. 48

8.11.1 Timing Diagram ................................................................................................... 48

8.12 Debug Interface................................................................................................................... 49

8.13 Bluetooth Coexistence ........................................................................................................ 50

8.13.1 Interface Configuration ........................................................................................ 50

8.13.2 Operation Scenario.............................................................................................. 50

9

Applications Schematic.............................................................................................................. 52

10 Package Information................................................................................................................... 53

10.1 Dimension: DA16200MOD-AAC......................................................................................... 53

10.2 Dimension: DA16200MOD-AAE ......................................................................................... 53

10.3 PCB Land Pattern ............................................................................................................... 54

10.4 4-Layer PCB Example......................................................................................................... 55

10.5 Soldering Information.......................................................................................................... 56

10.5.1 Condition for Reflow Soldering ............................................................................ 56

11 Ordering Information .................................................................................................................. 58

Revision History ................................................................................................................................ 59

Datasheet

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Figures

Figure 1: System Diagram..................................................................................................................... 3

Figure 2: Hardware Block Diagram ....................................................................................................... 9

Figure 3: Software Block Diagram......................................................................................................... 9

Figure 4: DA16200MOD 37 pins Pin-out Diagram (Top View)............................................................ 11

Figure 5: TIS 3D

Figure 6: TRP 3D................................................................................... 19

Figure 7: Power on Sequence............................................................................................................. 20

Figure 8: Pulse Counter Block Diagram.............................................................................................. 24

Figure 9: QSPI Master Block Diagram ................................................................................................ 26

Figure 10: QSPI Master Timing Diagram (Mode 0)............................................................................. 26

Figure 11: SPI Master Timing Diagram (Mode 0)................................................................................ 27

Figure 12: SPI Slave Block Diagram ................................................................................................... 28

Figure 13: 8-byte Control Type............................................................................................................ 28

Figure 14: 4-byte Control Type............................................................................................................ 28

Figure 15: SPI Slave Timing Diagram ................................................................................................. 30

Figure 16: SDIO Slave Block Diagram................................................................................................ 31

Figure 17: SDIO Slave Timing Diagram .............................................................................................. 31

Figure 18: I2C Master Timing Diagram ............................................................................................... 32

Figure 19: I2C Slave Timing Diagram ................................................................................................. 34

Figure 20: SD/eMMC Block Diagram .................................................................................................. 35

Figure 21: SD/eMMC Master Timing Diagram .................................................................................... 35

Figure 22: I2S Block Diagram.............................................................................................................. 37

Figure 23: I2S Clock Scheme.............................................................................................................. 37

Figure 24: I2S Timing Diagram ........................................................................................................... 38

Figure 25: Left Justified Mode Timing Diagram................................................................................... 38

Figure 26: Right Justified Mode Timing Diagram ................................................................................ 38

Figure 27: I2S Transmit Timing Diagram ............................................................................................ 39

Figure 28: I2S Receive Timing Diagram ............................................................................................. 39

Figure 29: ADC Control Block Diagram............................................................................................... 40

Figure 30: 12-bit ADC Timing Diagram ............................................................................................... 40

Figure 31: Antenna Switching Internal Block Diagram........................................................................ 42

Figure 32: Antenna Switching Timing Diagram................................................................................... 43

Figure 33: DA16200 UART Block Diagram......................................................................................... 44

Figure 34: Serial Data Format............................................................................................................. 44

Figure 35: Receiver Serial Data Sampling Points ............................................................................... 45

Figure 36: UARTTXDOE Output Signal for UART RS-485................................................................. 45

Figure 37: UART Hardware Flow Control............................................................................................ 46

Figure 38: PWM Block Diagram .......................................................................................................... 48

Figure 39: PWM Timing Diagram ........................................................................................................ 48

Figure 40: JTAG Timing Diagram........................................................................................................ 49

Figure 41: Bluetooth Coexistence Interface ........................................................................................ 50

Figure 42: Application Schematic........................................................................................................ 52

Figure 43: AAC Module Dimension..................................................................................................... 53

Figure 44: AAE Module Dimension ..................................................................................................... 53

Figure 45: PCB Land Pattern (Top View)............................................................................................ 54

Figure 46: PCB Land Pattern (Bottom View)....................................................................................... 54

Figure 47: 4-Layer PCB Example........................................................................................................ 55

Figure 48: Typical PCB Mounting Process Flow................................................................................. 56

Figure 49: Reflow Condition ................................................................................................................ 57

Tables

Table 1: Pin Description ...................................................................................................................... 12

Table 2: DA16200MOD Pin Multiplexing............................................................................................. 14

Table 3: Absolute Maximum Ratings................................................................................................... 15

Table 4: Recommended Operating Conditions ................................................................................... 15

Table 5: DC Parameters, 1.8 V IO ...................................................................................................... 15

Datasheet

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Table 6: DC Parameters, 3.3 V IO ...................................................................................................... 16

Table 7: DC Parameters for RTC block, 3.3 V VBAT.......................................................................... 16

Table 8: DC Parameters for RTC block, 2.1 V VBAT.......................................................................... 16

Table 9: DC Parameters for Digital Wake-up, 3.3 V VBAT & 1.8/3.3 V IO ......................................... 16

Table 10: DC Parameters for Digital Wake-up, 2.1 V VBAT & 1.8 V IO ............................................. 17

Table 11: WLAN Receiver Characteristics.......................................................................................... 17

Table 12: WLAN Transmitter Characteristics...................................................................................... 17

Table 13: Current Consumption in Active State .................................................................................. 18

Table 14: Current Consumption in Low Power Operation................................................................... 18

Table 15: ESD Performance................................................................................................................ 19

Table 16: Power on Sequence Timing Requirements......................................................................... 20

Table 17: RTC Pin Description............................................................................................................ 22

Table 18: Wake-up Sources................................................................................................................ 23

Table 19: I/O Power Domain ............................................................................................................... 24

Table 20: QSPI Master Timing Parameters ........................................................................................ 27

Table 21: SPI Master Pin Configuration.............................................................................................. 27

Table 22: SPI Master Timing Parameters ........................................................................................... 28

Table 23: Control Field of the 8-byte Control Type ............................................................................. 29

Table 24: Control Field of the 4-byte Control Type ............................................................................. 29

Table 25: SPI Slave Pin Configuration................................................................................................ 29

Table 26: SPI Slave Timing Parameters ............................................................................................. 30

Table 27: SDIO Slave Pin Configuration............................................................................................. 31

Table 28: SDIO Slave Timing Parameters .......................................................................................... 31

Table 29: I2C Master Pin Configuration .............................................................................................. 32

Table 30: I2C Master Timing Parameters ........................................................................................... 32

Table 31: I2C Slave Pin Configuration ................................................................................................ 33

Table 32: I2C Slave Timing Parameters ............................................................................................. 34

Table 33: SD/eMMC Master Pin Configuration ................................................................................... 35

Table 34: SD/eMMC Master Timing Parameters ................................................................................ 36

Table 35: I2S Pin Configuration .......................................................................................................... 36

Table 36: I2S Clock Selection Guide................................................................................................... 38

Table 37: I2S Transmit Timing Parameters......................................................................................... 39

Table 38: I2S Receive Timing Parameters.......................................................................................... 39

Table 39: DC Specification.................................................................................................................. 40

Table 40: ADC Pin Configuration ........................................................................................................ 41

Table 41: Control bits to enable and disable hardware flow control ................................................... 46

Table 42: UART Interrupt Signals ....................................................................................................... 47

Table 43: UART Pin Configuration...................................................................................................... 47

Table 44: PWM Pin Configuration....................................................................................................... 48

Table 45: PWM Timing Diagram Description ...................................................................................... 49

Table 46: JTAG Timing Parameters.................................................................................................... 49

Table 47: JTAG Pin Configuration....................................................................................................... 50

Table 48: Component for RTC POWER KEY ..................................................................................... 52

Table 49: Typical Reflow Profile (Lead Free): J-STD-020C................................................................ 57

Table 50: Ordering Information (Production)....................................................................................... 58

Datasheet

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1

Terms and Definitions

API

Application Programming Interface

CRC

DMA

GPIO

HW

Cyclic Redundancy Check

Direct Memory Access

General Purpose Input/Output

Hardware

I2C

Inter-Integrated Circuit

Inter-IC Sound

I2S

IoT

Internet of Things

JTAG

LDO

LLI

Joint Test Action Group

Low-dropout Regulator

Linked-List Item

NVIC

NVRAM

PLL

Nested Vectored Interrupt Controller

Non-Volatile RAM

Phase-locked Loop

PRNG

PWM

QSPI

RTC

SAR ADC

SPI

Pseudo Random Number Generator

Pulse Width Modulation

Quad-lane SPI

Real-time Clock

Successive Approximation Analog-to-Digital Converter

Serial Peripheral Interface

Software

SW

SWD

UART

XIP

Serial Wire Debug

Universal Asynchronous Receivers and Transmitter

eXecutein Place

TAP

Test Access Port

2

References

[1] ARM Cortex M4 Processor Technical Reference Manual

[2] ITU-T O.150, General Requirements for Instrumentation for Performance Measurements on

Digital Transmission Equipment, 1996

[3] Arm^®TrustZone^®CryptoCell-312, Revision r1p1, Software Integrators Manual

[4] IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture

[5] DA16200_SDK_Programmer_Guide.pdf

[6] AMBA AHB bus specification, Rev 3.0 https://developer.arm.com/documentation/ihi0033/bb

Datasheet

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3

Block Diagram

Figure 2 shows the DA16200MOD hardware (HW) block diagram.

VBAT_3V3

VDD_DIO1

VDD_DIO2

Chip Antenna type

DA16200MOD-AAC

PIN Mux

Quad-SPI

SPI

32.768KHz

Crystal

2.4GHzRF filter

& Matching

UART

GPIOs

PWM

RTC Control

External Antenna type

(u.FL connector)

DA16200MOD-AAE

I²C

40MHz

Crystal

SD/eMMC

SDIO

UART

For debugging

I²S

4ch 12bit ADC

JTAG/

4Mbyte

Serial flash

Figure 2: Hardware Block Diagram

Figure 3 shows the DA16200 SoC software (SW) block diagram.

User Application

Home Appliance/Sensor Network/Door Lock/Light, IoT.

Provisioning

Protocol

mDNS / xmDNS / DNS-SD / CoAP / Jason

NetX-APP

DHCP/ DNS/ HTTP1.0 / HTTP1.1

Afafa

CLI Handler

U

upper Level

TLS / DTLS

Wi-Fi

Supplicant

TCP/UDP

NetX-Duo

80211 Link Layer

IP

802.11 Upper MAC

802.11 Lower MAC

ThreadX

RTOS

Wi-Fi PHY

Device Driver

Figure 3: Software Block Diagram

Datasheet

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The following descriptions are about the SW block diagrams.

●

Kernel layer

○

Real Time Operating System

The Wi-Fi layer is divided into four layers:

○

Lower MAC

– SW module to control/handle HW Wi-Fi MAC/PHY and interfaces with Upper MAC layer

Upper MAC

○

– SW module to control/handle Wi-Fi control/handle to interface with supplicant

– Wi-Fi Link Layer: Interface layer between Upper MAC and supplicant

– Supplicant: SW module to control/management to operate Wi-Fi operation

Network subsystem layer

○

– Used to control/handle network operation

– Main protocols are IP, TCP, and UDP

– Other necessary protocols are supported

Security Layer

– Crypto operation engine is ported to use crypto HW engine

●

TLS/TCP and DTLS/UDP APIs are supported to handle security operation:

○

User application layer

– Variable sample codes are supported in SDK – sample codes use supported APIs

– TCP Client/Server, UDP Client/Server, TLS Client/Server

– HTTP/HTTPs download, OTA Update usage, and MQTT usage

Customer applications can be included and implemented easily in SDK

Datasheet

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Pinout

4.1 Pin-out Description (37 pins)

DA16200MOD series

37

36

NC

1

2

NC

GND

35

34

33

32

31

30

29

28

27

26

25

24

VBAT_3V3

VDD_DIO1

GPIOA0

GPIOA1

GPIOA2

GPIOA3

GPIOA4

GPIOA5

GPIOA6

GPIOA7

GPIOA8

GPIOA9

RTC_PWR_KEY

RTC_WAKE_UP

RTC_SENSOR

NC

3

4

GND

5

6

JTAG_TMS

JTAG_TCLK

GPIOC8

7

8

9

GPIOC7

10

11

12

13

GPIOC6

UART0_TXD

UART0_RXD

14 15 16 17 18 19 20 21 22 23

Figure 4: DA16200MOD 37 pins Pin-out Diagram (Top View)

Datasheet

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Table 1: Pin Description

#Pin

1

Pin Name

NC

Type

NC

Drive(mA)

Reset State

Description

NOT CONNECT

RF VDD

2

GND

DI

3

RTC_PWR_KEY

RTC_WAKE_UP

RTC_SENSOR

NC

RTC block enable signal

RTC block wake-up signal

Sensor control signal

NOT CONNECT

JTAG I/F, SWDIO

4

DI

5

DO

NC

6

7

JTAG_TMS

JTAG_TCLK

GPIOC8

DIO

DO

DI

2/4/8/12

I-PU

I-PD

O

8

JTAG I/F, SWCLK, General Purpose I/O

General Purpose I/O

9

10

11

12

13

14

15

GPIOC7

General Purpose I/O

GPIOC6

General Purpose I/O

UART_TXD

UART_RXD

RTC_WAKE_UP2

VDD_DIO2

UART transmit data

I

UART receive data

DI

RTC block wake-up signal

VDD

Supply power for digital I/O

GPIOC6~GPIOC8, TMS/TCLK, TXD/RXD

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

F_CSN

F_IO1

DIO

External Flash Memory I/F

External Flash Memory I/F (F_SI)

External Flash Memory I/F (F_WP)

External Flash Memory I/F (F_SO)

External Flash Memory I/F (F_HOLD)

External Flash Memory I/F

General Purpose I/O

DIO

F_IO2

DIO

F_IO0

DIO

F_IO3

DIO

F_CLK

DIO

GPIOA11

GPIOA10

GPIOA9

GPIOA8

GPIOA7

GPIOA6

GPIOA5

GPIOA4

GPIOA3

GPIOA2

GPIOA1

GPIOA0

VDD_DIO1

VBAT_3V3

NC

DIO

2/4/8/12

I-PD

DIO

General Purpose I/O

DIO

General Purpose I/O

DIO

General Purpose I/O

DIO

General Purpose I/O

DIO

General Purpose I/O

DIO

General Purpose I/O

DIO

General Purpose I/O

AI/DIO

VDD

NC

Aux.ADC input/General Purpose I/O

Supply power for digital I/O

Supply power for integrated power amplifier

NOT CONNECT

NC

NOT CONNECT

Datasheet

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4.2 Pin Multiplexing

This device provides various interfaces to support many kinds of applications. It is possible to control

each pin according to the required application in reference to the pin multiplexing illustrated in Table

2. Pin control can be realized through register setting. This device can use a maximum of 16 GPIO

pins and each of the GPIO pins multiplexes signals of various functions. In particular, four pins from

GPIOA0 to GPIOA3 multiplex analog signals, which also can be realized through register setting.

Datasheet

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5

Electrical Specification

5.1 Absolute Maximum Ratings

Table 3: Absolute Maximum Ratings

Parameter

VBAT_3V3

VDD_DIO1

VDD_DIO2

Pins

35

Min

VSS

Max

Units

3.9

V

34

VSS

15

Operating temperature range (TA)

-40

+85

°C

5.2 Recommended Operating Conditions

Table 4: Recommended Operating Conditions

Parameter

VBAT_3V3

VDD_DIO1

VDD_DIO2

Pins

35

Min

2.1

Typ

Max

3.6

Units

V

34

1.62

3.6

15

Operating temperature range (TA)

-40

+85

°C

5.3 Electrical Characteristics

5.3.1 DC Parameters, 1.8 V IO

Table 5: DC Parameters, 1.8 V IO

Parameter

Symbol Condition

Min

Typ

Max

Units

Guaranteed logic Low

level

0.3 ×

DVDD

Input Low Voltage

V_IL

V_IH

VSS

V

Guaranteed logic High

level

Input High Voltage

0.7 × DVDD

DVDD

V

0.2 ×

DVDD

Output Low Voltage V_OL

Output High Voltage V_OH

DVDD=Min.

VSS

V

DVDD=Min.

0.8 × DVDD

DVDD

32.4

Pull-up Resistor

R_PU

R_PD

V_PAD=V_IH, DIO=Min.

V_PAD=VIL, DIO=Min.

kΩ

Pull-down Resistor

32.4

Note 1 DVDD = 1.8 V, VDD_DIO1, VDD_DIO2 Logic Level

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5.3.2

DC Parameters, 3.3 V IO

Table 6: DC Parameters, 3.3 V IO

Parameter

Symbol Condition

Min

Typ

Max

Units

Guaranteed logic Low

level

Input Low Voltage

V_IL

V_IH

VSS

0.8

V

Guaranteed logic High

level

Input High Voltage

2.0

DVDD

V

Output Low Voltage V_OL

Output High Voltage V_OH

DVDD=Min.

VSS

2.4

0.4

DVDD

19.4

V

DVDD=Min.

Pull-up Resistor

R_PU

R_PD

VPAD=VIH, DIO=Min.

V_PAD=V_IL, DIO=Min.

kΩ

Pull-down Resistor

16.0

Note 1 DVDD= 3.3 V, VDD_DIO1, VDD_DIO2 Logic Level

5.3.3

DC Parameters for RTC Block

There are several control pins in RTC block, see Section 7.3 RTC for detail.

Table 7: DC Parameters for RTC block, 3.3 V VBAT

Parameter

Symbol Condition

Min

Typ

Max

Units

Guaranteed logic Low

level

Input Low Voltage

V_IL

V_IH

VSS

0.6

V

Guaranteed logic High

level

Input High Voltage

2.2

VBAT

V

(RTC block: RTC_PWR_KEY, RTC_WAKE_UP, RTC_WAKE_UP2)

Table 8: DC Parameters for RTC block, 2.1 V VBAT

Parameter

Symbol Condition

Min

Typ

Max

Units

Guaranteed logic Low

level

Input Low Voltage

V_IL

V_IH

VSS

0.3

V

Guaranteed logic High

level

Input High Voltage

1.6

VBAT

V

(RTC block: RTC_PWR_KEY, RTC_WAKE_UP, RTC_WAKE_UP2)

5.3.4

DC Parameters for Digital Wake-up

Several GPIOs can be used for wake-up, see Section 7.3.1 Wake-up Controller for detail.

To use Digital Wake-up, IO voltage should not be over VBAT.

Table 9: DC Parameters for Digital Wake-up, 3.3 V VBAT & 1.8/3.3 V IO

Parameter

Symbol Condition

Min

Typ

Max

Units

Guaranteed logic Low

level

Input Low Voltage

V_IL

V_IH

VSS

0.5

V

Guaranteed logic High

level

Input High Voltage

1.4

DVDD

V

(DVDD= 1.8/3.3V, VDD_DIO1, VDD_DIO2 Logic Level, DVDD should not be over VBAT)

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Table 10: DC Parameters for Digital Wake-up, 2.1 V VBAT & 1.8 V IO

Parameter

Symbol Condition

Min

Typ

Max

Units

Guaranteed logic Low

level

Input Low Voltage

V_IL

V_IH

VSS

0.3

V

Guaranteed logic High

level

Input High Voltage

1.3

DVDD

V

(DVDD= 1.8V, VDD_DIO1, VDD_DIO2 Logic Level, DVDD should not be over VBAT)

5.4 Radio Characteristics

5.4.1

WLAN Receiver Characteristics

TA = +25 °C, VBAT = 3.3 V, CH1(2412 MHz)

Table 11: WLAN Receiver Characteristics

Parameter

Condition

Min

-99.5

-95

-90

-91

-89

-82

-76

-91

-73

-4

Typ

-98.5

-94

-89

-90

-88

-81

-75

-90

-72

0

Max

-96.5

-92

-87

-88

-86

-79

-73

-88

-70

0

Units

1 Mbps DSSS

2 Mbps DSSS

11 Mbps CCK

6 Mbps OFDM

9 Mbps OFDM

18 Mbps OFDM

36 Mbps OFDM

54 Mbps OFDM

MCS0(GF)

Sensitivity

(8 % PER for 11b rates, 10 %

PER for 11g/11n rates)

dBm

MCS7(GF)

Maximum input level

802.11b

(8 % PER for 11b rates, 10 %

PER for 11g/11n rates)

802.11g

-10

-4

-3

5.4.2

WLAN Transceiver Characteristics

TA = +25 °C, VBAT = 3.3 V, CH1(2412 MHz)

Table 12: WLAN Transmitter Characteristics

Parameter

Condition

Min

16.5

15.5

14.5

Typ

19.0

18.0

17.0

Max

20

19

18

Units

1 Mbps DSSS

2 Mbps DSSS

5.5 Mbps CCK

11 Mbps CCK

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

Maximum Output Power measured

form IEEE spectral mask and EVM

dBm

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Parameter

Condition

Min

14.5

13

Typ

17.0

15.5

14.5

18.0

14.5

Max

18

Units

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

MCS0 OFDM

MCS7 OFDM

16.5

15.5

19

12

15.5

12

15.5

+25

Transmit center frequency accuracy

-25

ppm

5.5 Current Consumption

TA = +25 °C, VBAT = 3.3 V, w/ CPU clock is 80 MHz.

Table 13: Current Consumption in Active State

Parameter

Condition

1 Mbps DSSS

Min

260

240

180

25

Typ

280

260

200

29

Max

320

300

240

51

Units

@ 19.0 dBm

@ 18.0 dBm

@ 14.5 dBm

6 Mbps OFDM

54 Mbps OFDM

MCS7

TX

RX

ACTIVE

No signal (Note 1)

mA

1 Mbps DSSS (Note 1)

1 Mbps DSSS

54 Mbps OFDM

MCS7

26.5

27

30.5

37.5

38.5

53

54

29

54

29

54

Note 1 Low Power Mode& CPU clock 30 MHz

TA = +25 °C, VBAT = 3.3 V

Table 14: Current Consumption in Low Power Operation

Parameter

Condition

Sleep 1

Sleep 2

Sleep 3

Min

Typ

Max

Units

0.2

1.8

3.5

Low Power Operation

µA

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5.6 Radiation Performance

Figure 5: TIS 3D

Figure 6: TRP 3D

5.7 ESD Ratings

Table 15: ESD Performance

Reliability Test

Standards

Test Conditions

± 2,000 V

Result

Pass

Human Body Model (HBM)

Charge Device Mode (CDM)

ANSI/ESDA/JEDEC JS-001-2017

ANSI/ESDA/JEDEC JS-002-2018

± 500 V

Pass

5.8 Clock Electrical Characteristics

DA16200MOD is including two clock sources. One is the 32.768 kHz clock used by the RTC block,

and the other is the 40 MHz clock for the internal processor and Wi-Fi system. More specifically, the

40 MHz clock is used as a source clock for the internal PLL while the PLL output is used for the

internal processor and Wi-Fi system block.

5.8.1

RTC Clock Source

The 32.768 kHz RTC clock source is necessary for the free-running counter in the RTC block. The

RTC block of the SoC contains an internal 32.768 kHz RC oscillator as well, which is used as a clock

for chip initialization before the external 32.768 kHz crystal reaches the stable time in the initial stage.

It is necessary to convert it into an external clock for accurate clock counting after the initialization

stage. This process is executed through the register setting.

5.8.2

Main Clock Source

DA16200MOD contains a crystal oscillator for the main clock source which supports the external

crystal clock. Basically, the external clock is 40 MHz.

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6

Power Management

DA16200MOD has an RTC block which provides power management and function control for low

power operation. In normal operation, the RTC block is always powered on when RTC_PWR_KEY is

enabled.

6.1 Power On Sequence

The sequence after the initial switching from power-off to power-on is shown in Figure 7.

The RTC_PWR_KEY of DA16200 is a pin that enables the RTC block. Once RTC_PWR_KEY is

enabled after VBAT power is supplied, all the internal regulators are switched on automatically in the

sequence pre-defined by the RTC block.

Once RTC_PWR_KEY is switched on, LDOs for both XTAL and digital I/O are switched on shortly

and then the DC-DC regulator is switched on according to the pre-defined interval. The enabling

intervals can also be modified in the register settings after initial power-up.

VBAT

50% VBAT

T0

IO Voltage

50% IO

POWER_KEY

CLK_32K

50% VBAT

T1

T2

T3

Figure 7: Power on Sequence

Table 16: Power on Sequence Timing Requirements

Name

T0

Description

Min

Typ

Max

Unit

ms

VBAT power-on time from 10 % to 90% of VBAT

IO voltage and VCC supply

T1

0

ms

T2

RTC_PWR_KEY switch-on time from 50 % VBAT to 50 %

POWER_KEY * Note 1

5*T0

ms

T3

Internal RC oscillator wake-up time

217

µs

Note 1 If the T0 = 10 ms to switch on VBAT, the recommended T2 is 50 ms for the safe booting operation. It

would be externally controlled by MCU or it would be implemented using RC filter at the input of

RTC_PWR_KEY. The recommended C is 470 nF or 1uF (not to exceed 1 uF) and R value is chosen

to have T2 delay. For example, R and C values will be 82 kΩ and 1 uF when T0 = 10 ms.

6.2 Low Power Operation Mode

DA16200MOD provides three Sleep modes as low power operation modes.

6.2.1

Sleep Mode 1

Sleep mode 1 is an operational mode in which the RTC_PWR_KEY is not switched to high yet. The

RTC_PWR_KEY is in the low state and the DA16200MOD is only supplied with VBAT power. With all

the internal blocks off in Sleep mode 1, only the leakage current from a minimal number of internal

blocks connected to VBAT remains.

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6.2.2

Sleep Mode 2

Sleep mode 2 is an operational mode in which the RTC_PWR_KEY is set to high and the RTC block

is running. Sleep mode 2 is activated by setting RTC registers for controlling the power management

unit via a command from the CPU.

To switch Sleep mode 2 back to Sleep mode 1, RTC_PWR_KEY should be set to low.

Changing the state of the device from Sleep mode 2 to an ACTIVE state happens in one of two

ways:

1. The counter value that has been set by the CPU prior to entering Sleep mode 2 is reached.

2. An external wake-up event occurs via the RTC_WAKE_UP pin.

6.2.3

Sleep Mode 3

Sleep Mode 3 is a low power, but fully connected Wi-Fi mode of operation. Sleep Mode 3 checks for

incoming Wi-Fi network data traffic at regular intervals set by the user, for example, every one

second, three seconds, five seconds, and so on. The exact time interval is programmable.

Sleep Mode 3 is activated by software commands. See the SDK documentation for more information.

A device can come out of Sleep Mode 3 and into a fully ACTIVE state before the next targeted

wakeup time interval via a GPIO wakeup.

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7

Core System

7.1 ARM Cortex-M4F Processor

The Cortex-M4F processor is a low-power processor that features low gate count, low interrupt

latency, low-cost debug, and includes floating point arithmetic functionality. The processor is

intended for deeply embedded applications that require fast interrupt response features.

The features of the Cortex-M4F processor in DA16200 are summarized below:

■

Operation clock frequency is up to 160 MHz

32-bit ARM Cortex-M4F architecture optimized for embedded applications

Thumb-2 mixed 16/32-bit instruction set

Hardware division and fast multiplication

Includes Nested Vectored Interrupt Controller (NVIC)

SysTick timer provided by Cortex-M4F processor

Supports both standard JTAG (5-wire) and the low-pin-count ARM SWD (2-wire, TCLK/TMS)

debug interfaces

■

Cortex-M4F is binary compatible with Cortex-M3

For more information on the ARM Cortex-M4F, see the ARM Cortex-M4F r0p1 technical reference

manual Error! Reference source not found..

7.2 Wi-Fi Processor

DA16200 includes an internal MCU (ARM Cortex-M4F) to completely offload the host MCU along

with an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast and secure

WLAN and Internet connections with 256-bit encryption. It supports the station, SoftAP, and Wi-Fi

Direct modes. It also supports WPA/WPA2 personal and enterprise security, WPA2 SI, WPA3 SAE,

OWE, and WPS 2.0. It includes an embedded IPv4 and IPv6 TCP/IP stack.

7.3 RTC

Among the pins in DA16200MOD, four special pins are directly connected to the RTC block, which

are RTC_PWR_KEY, RTC_GPO, RTC_WAKE_UP, and RTC_WAKE_UP2.

Table 17: RTC Pin Description

Pin Name

Pin Number

Description

RTC_PWR_KEY represents a power key for the RTC block. When

this pin is enabled, the RTC starts to work by following a pre-

defined power-up sequence and eventually all the necessary

power is supplied to all the sub-blocks including the main digital

block in DA16200. When disabled, all blocks are powered off and

this mode is defined as Sleep mode 1.

RTC_PWR_KEY

3

Minimum leakage current in Sleep mode 1.

This pin is an output and high level is 'VBAT'.

It has three different functions.

●

GPO function: output value can be set as 1 or 0 via register

setting. It can keep the value even in Sleep mode

Flash control function: when in Sleep mode, it becomes 0;

when in Active mode, it is 1

RTC_SENSOR

5

Sensor wakeup function: when used in sensor wake-up

function (Section 8.8.4), it provides a programmable periodic

signal for an external device. Inside the RTC, there are

registers for setting count values

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Pin Name

Pin Number

Description

This pin is an input pin for receiving an external event signal from

an external device like a sensor. The RTC block detects an

external event signal via this pin and wakes up DA16200 from

Sleep mode 2 or Sleep mode 3.

RTC_WAKE_UP

4

RTC_WAKE_UP2

14

RTC block has a 36-bit real time counter. Its resolution is equal to one clock period of 32.768 kHz.

The count value can be read via the register read command.

7.3.1

Wake-up Controller

The wake-up controller is designed to wake up DA16200MOD from a Sleep mode by an external

signal. It detects an edge trigger of the wake-up signal and selects either the rising edge or the falling

edge. Also, the wake-up signal must be maintained for at least 200 µs upon occurrence of transition

on one side.

When it comes to the source of wake-up, 11 digital I/Os in addition to the two pins directly connected

to the RTC block can be used. Although up to 11 digital I/Os are available for use, the maximum

number of digital I/Os that are simultaneously available is eight. Table 18 describes the digital I/Os

that are available for simultaneous use.

Table 18: Wake-up Sources

Input Selection = 0

GPIOA4

Input Selection = 1

X

GPIOA5

X

GPIOA6

GPIOA7

X

GPIOA8

X

GPIOA9

GPIOC6

GPIOC7

GPIOC8

GPIOA10

GPIOA11

For more on wake-up source selection, refer to input selection register: 0x50091008[25:16].

The wake-up controller is located in the RTC block. Several parameters can be set by RTC registers

and they identify which pin is used to wake up the SoC by checking the status register after wake-up.

DA16200MOD has another wake-up function using analog sources, which is described in Section

8.8.4. Using the Aux-ADC, DA16200 detects whether it exceeds the pre-defined threshold value. If it

detects the wanted condition, it will wake up from a Sleep mode. Four ports (GPIOA[3:0]) are used

for this function.

7.3.2

Retention I/O Function

DA16200MOD I/O has a retention mode. During this mode, I/O cells retain the previous state values

at the core side inputs. When it is required to maintain the value of a specific GPIO in Sleep mode,

this function will be used. For example, in order to maintain HIGH value on GPIOA4 in Sleep mode, it

is required to set the value of GPIOA4 to HIGH and set the register bit of RTC block

(0x5009_1018:BIT[27:24]) to enable retention to the proper value described in Table 19 before going

to the Sleep mode. For GPIOA4, BIT[25] should be set to HIGH, then GPIOA4 can keep the value

HIGH during the Sleep mode.

The retention enable register is comprised of three bits in total, and the I/O power domains covered

by each of the bits are described in Table 19.

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Table 19: I/O Power Domain

[25] DIO1

[26] DIO2

GPIOC[8:6]

[27] FDIO

F_CLK

GPIOA[11:4]

TCLK/TMS

F_CSN

UART0_RXD/UART0_TXD

F_IO0 to F_IO3

7.4 Pulse Counter

7.4.1

Introduction

The pulse counter is a module which counts the number of rising or falling edges of input signals.

And this counter module can run even in Sleep mode. It includes one 32-bit up-counter. The input

channel can be chosen by register setting among the 11 digital I/Os. It also has a glitch filter which is

designed to remove the unwanted trigger of an input signal.

7.4.2

Functional Description

Pulse

Count

CLK_32kHz

PCLK

Int

Counter

Int

Pulse

Edge

Ext.

Pad

Mux.

Glitch

Filter

Edge

Select

ㅣ

Gli_En

Gli_Thresh

Count_En

Count_Rst

Int_Clr

Int_Thresh

Edge_Sel

Mux_SEL

Figure 8: Pulse Counter Block Diagram

7.4.2.1

Input

Available input channels are described in Table 18. It uses the same input sources with the wake-up

controller. By register setting, input channels can be selected among 11 digital I/Os.

7.4.2.2

Clock

The operation clock of the pulse counter is 32 kHz.

7.4.2.3

Counter

As described in Figure 8, the pulse counter is activated by several counter control signals. By register

setting, input signals can be selected on either the rising edges or falling edges. In order to enable

the glitch filter module, Gli_En and Gli_Thresh register values need to be set. The pulses whose

cycles are shorter than the Gli_Thresh value are removed. The counter is a 32-bit up-counter and the

counter value can be reset to zero by Count_Rst.

7.4.2.4

Interrupts

An interrupt occurs when the counter values reaches the Interrupt Threshold value (Int_Thresh). In

Sleep mode, this interrupt can be used as a wake-up source.

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8

Peripherals

This section describes the peripherals that are supported by the DA16200MOD.

8.1 QSPI: Master with XIP Feature

QSPI master supports 4-line SPI communication with commercial flash memory devices and uses

Motorola SPI-compatible interface among SPI communication modes. The highest communication

speed is the same as the AMBA bus clock, and the speed is adjustable in integer multiples. The

designed QSPI supports 4-/2-/1-line types depending on the purpose. These types should be

combined. Especially when the 1-line communication mode is used, it can be used as the SPI

master.

QSPI master is an IP for communication between the flash memory and AMBA AHB bus and is

designed to support XIP. The features of the QSPI master are summarized as follows:

Serial Flash Interface:

●

SPI compatible serial bus interface

○

Configurable SPI I/O modes:

– Single I/O mode

– Dual I/O mode

– Quad I/O mode

○

JEDEC Standard: JESD216B

24-bit and 32-bit addressing

Supports to access flash with XIP mode

– Read access without command

– Read access without address and command

Programmable SPI clock phase and polarity

Maximum number of SPI CS is four that can be operated

○

AMBA Slave Interface

●

Compliance to the AMBA AHB bus specification, Rev 3.0 [6]

Direct code execution: directly addressable access without additional driver software

Supports single and incrementing burst transfer (SINGLE, INCR, INCR4, INCR8, INCR16)

Supports byte, half-word, and word transaction

AMBA slave interface is optional to access configuration and status registers

Simple timer is used to check the completion time of flash operation

XIP path of QSPI master supports HW remapping function to execute selected boot image for

over-the-air programming (OTA)

AMBA Master Interface

●

Compliance to the AMBA AHB bus specification, Rev 3.0 [6]

Supports DMA operation to access serial flash devices

○

Automatic copy of code image from serial flash to system RAM

Automatic programming of code image from system RAM to serial flash

●

Performs a mem-to-mem copy in units of 32 bits, regardless of the address and length

Supports single and incrementing burst transfer (SINGLE, INCR, INCR4, INCR8, INCR16)

Supports byte, half-word, and word transaction

Figure 9 shows the QSPI Master Block Diagram.

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AHB

BusMatrix

XIP path

Configuration

DMA

I-Cache

Controller

S

M

S0

S1

AHB

Bus

AHB

Bus

QSPI

Master

External

Serial

NOR Flash

AHB

Bus

with XIP feature

M

DMA

AHB

Bus

Figure 9: QSPI Master Block Diagram

Figure 10 shows the timing diagram for the QSPI master.

T_CSB.OF

T_CLK.ON

T_DO.DLY

T_DI.SU

F

QSPI_CSB

QSPI_CLK

QSPI_D[3:0]

Figure 10: QSPI Master Timing Diagram (Mode 0)

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Table 20 lists the timing parameters for the QSPI master.

Table 20: QSPI Master Timing Parameters

Parameter

Symbol

Min

Typ

Max

Unit

MHz

%

QSPI_CLK frequency

QSPI_CLK clock duty

F_CLK

10

120

50

T_CLK

1st CLK active rising transition time

T_CLK.ON

0.5 ×T_CLK

ns

(Note 1)

QSPI_CSB non-active rising transition time T_CSB.OFF

0

6

T_CLK

ns

QSPI_D[3:0] input setup time

QSPI_D[3:0] output delay time

Note 1 T_CLK= (F_CLK× 10⁶)^-1seconds

T_DI.SU

T_DO.DLY

2

8.2 SPI Master

QSPI can use the SPI master by means of single line interface. Table 21 shows the pin definition of

the SPI master interface. SPI signal timing is the same as QSPI.

To use DA16200MOD as an SPI master, the CSB signal can be used with any of the GPIO pins.

CSB [3:1] can be selected from GPIO special function by setting the registers in the GPIO.

Table 21: SPI Master Pin Configuration

Pin Name

GPIOx

Pin Number

I/O

O

Function Name

E_SPI_CSB[3:1]

E_SPI_CSB[0]

GPIOA6

GPIOA7

GPIOA8

GPIOA9

GPIOA10

GPIOA11

27

26

25

24

23

22

O

E_SPI_CLK

I/O

E_SPI_MOSI or E_SPI_D[0]

E_SPI_MISO or E_SPI_D[1]

E_SPI_D[2]

E_SPI_D[3]

T_CSB.OF

T_CLK.ON

T_DO.DLY

T_DI.SU

F

E_SPI_CSB

E_SPI_CLK

E_SPI_D[3:0]

Figure 11: SPI Master Timing Diagram (Mode 0)

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Table 22: SPI Master Timing Parameters

Parameter

Symbol

Min

Typ

Max

Unit

MHz

%

QSPI_CLK frequency

F_CLK

5

60

QSPI_CLK clock duty

50

T_CLK

1st CLK active rising transition time

T_CLK.ON

0.5 × T_CLK

ns

(Note 1)

QSPI_CSB non-active rising transition time T_CSB.OFF

0

6

T_CLK

ns

QSPI_D[3:0] input setup time

QSPI_D[3:0] output delay time

Note 1 T_CLK= (F_CLK× 10⁶)^-1seconds

T_DI.SU

T_DO.DLY

2

8.3 SPI Slave

SPI slave interface supports the control of DA16200 by an external host. The range of SPI clock

speed is the same as that of the internal bus clock speed. The SPI slave supports both the burst

mode and non-burst mode. In the burst mode, SPI_CSB remains active from the start to the end of

communication. In the non-burst mode, SPI_CLK remains active at every eight bits.

Address

Decoder

Command

Decoder

APB bus

Controller

SPI Signals

Data

Decoder

Figure 12: SPI Slave Block Diagram

Communication protocols of the SPI slave interface use either 4-byte or 8-byte control signals.

Between the two available communication protocols, the CPU chooses one before initiating the

control.

Figure 13 and Figure 14 shows the 8-byte and 4-byte control types.

SPI_CSB

SPI_CLK

C [ 7 : 0 ]

L [ 23 : 16 ]

L [ 15 : 8 ]

D [ 7 : 0 ]

D [ 15 : 8 ]

D [ 23 : 16 ]

D [ 31 : 24 ]

SPI_MOSI

A [ 31 : 24 ]

A [ 23 : 16 ]

A [ 15 : 8 ]

A [ 7 : 0 ]

L [ 7 : 0 ]

Figure 13: 8-byte Control Type

SPI_CSB

SPI_CLK

L [ 7 : 0 ]

D [ 23 : 16 ]

D [ 31 : 24 ]

SPI_MOSI

A [ 15 : 8 ]

A [ 7 : 0 ]

C [ 7 : 0 ]

D [ 7 : 0 ]

D [ 15 : 8 ]

Figure 14: 4-byte Control Type

Datasheet

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The 8-byte control type uses 4-byte address, 1-byte control, and 3-byte length. The 4-byte address

displays the address of registers subject to internal access. The 1-byte control is for communication

control and 3-byte length shows the length of data subject to continuous access in bytes. Hence,

when the 8-byte control type is applied, the maximal length of data subject to continuous access is

16 MB.

The 4-byte control type uses 2-byte address, 1-byte control, and 1-byte length. The 2-byte address

displays the address of registers subject to internal access. The 1-byte control is for communication

control and 1-byte length shows the length of data subject to continuous access in bytes. Since the

32-bit address map is used internally, the 2-byte address is not enough to express everything. Thus,

the upper 2-byte base address is designated, and then the lower 2-byte address is used.

Table 23 and Table 24 shows the meaning of each bit in the 1-byte control in the 8-byte control type

and the 4-byte control type, respectively.

Table 23: Control Field of the 8-byte Control Type

Control Bit

Abr.

Description

1 = Internal Address auto-increment

1 = Read

7

6

Auto Inc.

Read/Write

0 = Address fixed

0 = Write

5:0

Not used. Set all bits to ‘0’

Table 24: Control Field of the 4-byte Control Type

Control Bit

Abr.

Description

1 = Internal address auto-increment

1 = Read

7

6

Auto Inc.

0 = Address fixed

0 = Write

Read/Write

Common

5

1 = Refer base address as common area

1 = Refer to register value

Length field upper

0 = Refer base address

0 = Refer to length field

4

Length section

Length[12:8]

3:0

Table 25 shows the pin definition of the SPI slave interface.

Table 25: SPI Slave Pin Configuration

Pin Name

GPIOA2

GPIOA6

GPIOA3

GPIOA7

GPIOA1

GPIOA9

GPIOA11

GPIOA0

GPIOA8

GPIOA10

Pin Number

I/O

Function Name

31

27

30

26

32

24

22

33

25

23

I

SPI_CSB

I

SPI_CLK

I

SPI_MOSI

I

O

SPI_MISO

Figure 15 shows the timing diagram for the SPI slave.

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SPI_CSB

T_SCLKOFF

T_CSBOFF

T_SCLKL

T_SCLKH

T_SCLKON

SPI_CLK

(CPOL=0)

T_SCLKL

T_SCLKH

SPI_CLK

(CPOL=1)

T_MSU

T_SSU

T_MHD

SPI_MOSI

MSB

LSB

SPI_MISO

LSB

T_TR

Figure 15: SPI Slave Timing Diagram

Table 26 lists the timing parameters for the SPI slave.

Table 26: SPI Slave Timing Parameters

Parameter

Symbol Min

Typ

Max

Unit

MHz

%

SCLK frequency

F_SCLK

-

50

SCLK clock duty

40

Non active duration

T_SCLKOFF400

T_SCLKL(CPOL=0)

-

ns

1st CLK active rising transition time

CSB non active rising transition time

MOSI setup time

T_SCLKON

T_CSBOFF

T_MSU

ns

T_SCLKH(CPOL=1)

T_SCLKH(CPOL=0)

T_SCLKL(CPOL=1)

-

T_SCLK

8

(Note 1)

MOSI hold time

T_MHD

T_SSU

T_TR

8

-

T_SCLK

ns

MISO delay time

-

8

5

MISO transition time(10% to 90% transition)

Note 1 T_SCLK= 0.5 × (F_SCLKx 10⁶)^-1second

-

4

8.4 SDIO

SDIO is a full/high speed card suitable for memory card and I/O card applications with low power

consumption. The full/high speed card supports SPI, 1-bit SD, and 4-bit SD transfer modes at the full

clock range of 0 to 50 MHz. To be compatible with the serviceable SDIO clock, the internal BUS

clock needs to be set to minimum 50 MHz. The CIS and CSA area is located inside the internal

memory and the SDIO registers(CCCR and FBR) are programmed by the SD host.

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Command

Decoder

Fn0 / Fn1

Decoder

DAT

Decoder

APB bus

Interface

Response

Generator

CRC

Generator

REG.

2 port

DMA

Control

Memory

Controller

Figure 16: SDIO Slave Block Diagram

Table 27 shows the pin definition of the SDIO interface.

The GPIOA4 and GPIOA5 pins are set to SDIO CMD and CLK by default. If SDIO initialization is

performed and SDIO communication is enabled, SDIO data pin setting is performed automatically. In

other words, when the SDIO communication is detected, the pin used as the SDIO data among the

GPIO pins is automatically activated in the SDIO use mode. However, the auto setting function is not

supported for the F_xxx pin used as the flash function.

Table 27: SDIO Slave Pin Configuration

Pin Name

GPIOA4

GPIOA5

GPIOA9

GPIOA8

GPIOA7

GPIOA6

Pin Number

I/O

I

Function Name

SDIO_CMD

SDIO_CLK

SDIO_D0

29

28

24

25

26

27

I/O

SDIO_D1

SDIO_D2

SDIO_D3

Figure 17 shows the timing diagram for the SDIO slave.

T_CO.DLY

T_DO.DLY

T_CI.SU

T_DI.SU

SDIO_CLK

SDIO_D[3:0]

SDIO_CMD

Figure 17: SDIO Slave Timing Diagram

Table 28 lists the timing parameters for the SDIO slave.

Table 28: SDIO Slave Timing Parameters

Parameter

Symbol

Min

Typ

-

Max

Unit

MHz

%

SDIO_CLK frequency

SDIO_CLK clock duty

SDIO_CMD input setup time

F_SCLK

-

50

T_CI.SU

3

ns

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Parameter

Symbol

T_CO.DLY

T_DI.SU

Min

Typ

Max

Unit

ns

SDIO_CMD output delay time

SDIO_D[3:0] input setup time

SDIO_D[3:0] output delay time

11 (Note 1)

3

ns

T_DO.DLY

11 (Note 1)

ns

Note 1 SDIO signals can set previous output from half cycle.

8.5 I2C Interface

8.5.1

I2C Master

DA16200MOD includes an I2C master module. Three ranges of clock speed are supported: standard

(100 kHz), fast (400 kHz), and high (1.0 MHz) speed mode. Table 29 shows the pin definition of the

I2C master interface.

Table 29: I2C Master Pin Configuration

Pin Name

GPIOA1

GPIOA5

GPIOA9

GPIOA0

GPIOA4

GPIOA8

Pin Number

I/O

O

Function Name

32

28

24

33

29

25

O

I2C_CLK

O

I/O

I2C_SDA

Figure 18 shows the I2C timing diagram. The timing diagram is the same as that of I2C slave timing

diagram.

T_R

...

SDA

T_R

T_SU;DAT

T_VD;ACK

cont.

...

T_LOW

SCL

T_HD;STA

T_HD;DAT

T_HIGH

S

T_BUF

...

SDA

SCL

cont.

...

T_HD;STA

T_SU;STO

T_SU;STA

S_r

P

S

Figure 18: I2C Master Timing Diagram

Table 30 lists the I2C master timing parameters.

Table 30: I2C Master Timing Parameters

Fast Mode

High Speed Mode

Parameter

Symbol

Unit

MHz

Min

30

Max

Min

Max

Bus clock frequency

F_{op_clk}

160

30

160

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Fast Mode

High Speed Mode

Parameter

Symbol

Unit

Min

Max

Min

Max

1000

(Note 2)

SCL clock frequency

F_SCLK

100

400

100

kHz

Clock Duty (Note 1)

Hold time of START

40

0.2

60

-

40

60

-

%

μs

T_HD;STA

T_LOW

0.2

Low period of the SCL clock

High period of the SCL clock

Setup time for START condition

1.27

1.23

1.1

-

0.55

0.45

0.37

-

T_HIGH

-

T_SU;STA

-

3x T_{op_clk}

(Note 4)

3x T_{op_clk}

(Note 4)

Data hold time

Data setup time

T_HD;DAT

-

μs

T_LOW

T_SU;DAT

-

- T_HD;DAT

Rise time of both SDAand SCL

Setup time for STOP condition

T_R(Note 3)

T_SU;STO

0.02

0.36

0.3

-

0.05

0.45

0.05

-

μs

3x T_{op_clk}

(Note 4)

3x T_{op_clk}

(Note 4)

Data valid acknowledge time

T_VD;ACK

-

μs

Buffer free time between

START and STOP condition

T_BUF

0.5

Note 1 Clock duty ratio = (T_HIGH/T_SCLK) × 100[%], T_SCLK= 1/ F_SCLK

Note 2 Max. clock = 1.0 MHz (clock period = 1000 ns)

Note 3 T_Rdepends on a pull-up resistor value.

Note 4 T_{op_clk = (}1 / F_{op_clk}) x 10^6 usec

8.5.2

I2C Slave

I2C slave interface supports the control of DA16200MOD by an external host. Pin mux condition is

defined in Table 31. Three ranges of clock speed are supported: standard (100 kHz), fast (400 kHz),

and high (1.0 MHz) speed mode.

Table 31: I2C Slave Pin Configuration

Pin Name

GPIOA1

GPIOA3

GPIOA5

GPIOA7

GPIOA0

GPIOA2

GPIOA4

GPIOA6

Pin Number

I/O

I

Function Name

32

30

28

26

33

31

29

27

I

I2C_CLK

I

I/O

I2C_SDA

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Figure 19 shows the I2C slave timing diagram.

T_R

...

SDA

T_R

T_SU;DAT

T_VD;ACK

cont.

...

T_LOW

SCL

T_HD;STA

T_HD;DAT

T_HIGH

S

T_BUF

...

SDA

SCL

cont.

...

T_HD;STA

T_SU;STO

T_SU;STA

S_r

P

S

Figure 19: I2C Slave Timing Diagram

Table 32 lists the I2C slave timing parameters.

Table 32: I2C Slave Timing Parameters

Fast Mode

High Speed Mode

Parameter

Symbol

Unit

Min

Max

Min

Max

SCL clock frequency

0

400

0

1000

(Note 2)

kHz

F_SCLK

Clock Duty (Note 1)

Hold time of START

40

0.6

1.3

0.6

0

60

40

0.26

0.5

0.26

0

60

%

μs

ns

μs

T_HD;STA

T_LOW

-

Low period of the SCL clock

High period of the SCL clock

Setup time for START condition

Data hold time

-

T_HIGH

-

T_SU;STA

T_HD;DAT

T_SU;DAT

T_R

-

Data setup time

100

20

0.6

-

50

-

Rise time of both SDA and SCL

Setup time for STOP condition

Data valid acknowledge time

300

-

120

T_SU;STO

T_VD;ACK

-

0.26

-

Buffer free time between

START and STOP condition

T_BUF

1.3

-

0.5

-

μs

Note 1 Clock duty ratio = (T_HIGH/T_SCLK) × 100[%], TSCLK = 1/FSCLK

Note 2 Max. clock = 1.0 MHz (clock period = 1000 ns)

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8.6 SD/SDeMMC

The SD/eMMC host IP provides the function for DA16200MOD to access SD or eMMC cards. This

SD/eMMC host IP only supports a 4-bit data bus and the maximum clock rate is 50 MHz. The

maximum data rate is 25 MB/s (200 Mbps) under the 4-bit data bus and 50 MHz clock.

SD/eMMC pin mux condition is defined in Table 33.

Table 33: SD/eMMC Master Pin Configuration

Pin Name

GPIOA4

GPIOA5

GPIOA9

GPIOA8

GPIOA7

GPIOA6

GPIOA10

GPIOA1

Pin Number

I/O

O

Function Name

SD/eMMC_CMD

SD/eMMC_CLK

SD/eMMC_D0

SD/eMMC_D1

SD/eMMC_D2

SD/eMMC_D3

29

28

24

25

26

27

23

32

I/O

I

SD/eMMC_WRP

I

8.6.1

Block Diagram

Figure 20 shows the block diagram of SD/eMMC host IP and it includes the control register, clock

control, command/response pipe, data pipe, and AHB master interface blocks.

HCLK

AHB

Control

Clock

Slave

Registers

Control

32

HCMD

CMD/RSP

Pipe

HDATA[3:0]

4

AHB

Master

AHB

FIFO

Data

Pipe

32

Figure 20: SD/eMMC Block Diagram

Figure 21 shows the timing diagram for the SD/eMMC master.

T_CO.DLY

T_DO.DLY

T_CI.SU

T_DI.SU

SD/eMMC_CLK

SD/eMMC_D[3:0]

SD/eMMC_CMD

Figure 21: SD/eMMC Master Timing Diagram

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Table 34 lists the timing parameters for the SD/eMMC master.

Table 34: SD/eMMC Master Timing Parameters

Parameter

Symbol

Min

Typ

-

Max

Unit

MHz

%

SD/eMMC_CLK frequency

F_SCLK

-

50

SD/eMMC_CLK clock duty

50

SD/eMMC_CMD input setup time

SD/eMMC_CMD output delay time

SD/eMMC_D[3:0] input setup time

SD/eMMC_D[3:0] output delay time

T_CI.SU

T_CO.DLY

T_DI.SU

8

ns

3

8

ns

T_DO.DLY

ns

8.7 I2S

DA16200MOD provides an I2S interface. Once an I2S block receives audio data through the DMA, it

sends audio data to the external port according to the I2S standard. To use the external DAC, output

through the GPIO port is possible through the register setting according to the pin configuration

(Table 35).

The I2S also provides a receive function. However, I2S transmission and reception functions cannot

be used at the same time. The transmit and receive functions can be selected by register setting. If

the I2S signal is input from outside after the reception function is set, the audio signal can be

decoded, stored in the FIFO, and read out through the DMA. The decodable reception function

provides 8/16/24/32-bit modes and can receive either mono or stereo.

Using the I2S clock divider register, the internal PLL clock can be variably applied to the I2S clock

source. The available I2S clock source is 24/48 MHz. There is also a way to apply the I2S clock

source directly from outside using the GPIO pin. For accurate I2S audio sampling, I2S clock source

can be input to external GPIO pins. It needs to select the GPIO pin setting as the I2S clock input and

apply appropriate clock source. The available I2S clock pins are shown in Table 35.

Table 35: I2S Pin Configuration

Pin Name

GPIOA1

GPIOA5

GPIOA9

GPIOA0

GPIOA4

GPIOA8

GPIOA3

GPIOA7

GPIOA2

GPIOA6

GPIOA3

GPIOA10

Pin Number

I/O

O

I/O

I

Function Name

32

28

24

33

29

25

30

26

31

27

30

23

I2S_MCLK

I2S_BCLK

I2S_LRCK

I2S_SDO

I2S_CLK_IN

I

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8.7.1

Block Diagram

I2S has the following features:

■

Master Clock Mode only

I2S Data pin can work in either input mode or output mode

Clock source can be "internal 480 MHz/N" (currently using 24 MHz) or "external clock source"

Max Sampling Rate: 48 KHz

Mono/Stereo Mode

Figure 22: I2S Block Diagram

8.7.2

I2S Clock Scheme

The I2S uses a 24 MHz clock as default from the RF reference clock (40 MHz), so it can support

46.875 KHz of sampling rate. External clock sources are needed to support the standard sampling

rate. See Table 36.

Figure 23: I2S Clock Scheme

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Table 36: I2S Clock Selection Guide

Parameter

Units

KHz

LRCK

BCLK

MCLK

Fs

8

12

16

24

32

44.1

46.875

48

64Fs

512Fs

0.512

4.096

0.768

6.144

1.024

1.536

2.048

2.8224

3

3.072

MHz

8.192 12.288 16.384 22.5792

24

24.576 MHz

1

N

Clk Div2

6

4

3

2

1

(=1,2,3…)

24

I2S_CLK

24.576 24.576 24.576 24.576 32.768 22.5792

(Internal

PLL)

24.576 MHz

NOTE

To confirm the exact LRCK operation, drive the Clock source at I2S_CLK.

8.7.3

I2S Transmit and Receive Timing Diagram

I2S output is possible in the following three modes. The main clock (MCLK) always outputs in 512×fs.

I2S Mode

●

Right Channel

LRCK

Left Channel

SCLK

SDATA

-1

+1

-1

+1

MSB

-2

-3

+3

+2

LSB

MSB

-2

-3

-4

+3

+2

LSB

Figure 24: I2S Timing Diagram

●

Left Justified Mode

Left Channel

LRCK

Right Channel

SCLK

SDATA

-1

+1

LSB

-1

+1

LSB

MSB

-2

-3

+3

+2

MSB

-2

-3

-4

+3

+2

Figure 25: Left Justified Mode Timing Diagram

●

Right Justified Mode

Right Channel

Left Channel

LRCK

SCLK

14

15

14

SDATA

15

13

2

1

0

2

1

0

Figure 26: Right Justified Mode Timing Diagram

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T₂

f_BCLK

T₃

I2S_BCLK

T₄

I2S_SDO

(falling edge)

T₅

I2S_SDO

(rising edge)

Figure 27: I2S Transmit Timing Diagram

T₄

T₂

f_BCLK

T₃

I2S_BCLK

I2S_SDO

T₅

Figure 28: I2S Receive Timing Diagram

Table 37: I2S Transmit Timing Parameters

Description

Timing

f_BCLK

T₂

Min

Typ

Max

3.072

½ f_BCLK

-

Unit

MHz

ns

I2S_BCLK frequency

-

High period of the BCLK clock

Low period of the BCLK clock

I2S_SDO output hold (falling edge)

I2S_SDO output hold (rising edge)

T₃

-

ns

T₄

160

ns

T₅

-

ns

Table 38: I2S Receive Timing Parameters

Description

Timing

f_BCLK

T₂

Min

-

Typ

Max

3.072

½ f_BCLK

-

Unit

MHz

ns

I2S_BCLK frequency

High period of the BCLK clock

Low period of the BCLK clock

I2S_SDO input setup time

I2S_SDO input hold time

-

T₃

-

ns

T₄

15

60

ns

T₅

-

ns

8.8 ADC (Aux 12-bit)

8.8.1

Overview

DA16200MOD includes a high precision, ultra-low power, and wide dynamic range SAR ADC with a

12-bit resolution. It has a 4-channel single-end ADC.

Analog input is measured by four pins from GPIOA0 to GPIOA3, and pin selection is changed

through the register setting.

Figure 29 shows the control block diagram.

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VI_N[1]

VI_N[2]

VI_N[3]

VI_N[4]

ADC

12b

Max : 1Ms

CH_SEL

Ready

Counter

16-bit

Figure 29: ADC Control Block Diagram

8.8.2

Timing Diagram

The input is digitized at a maximum of 1.0 Msps throughput rate. And the maximum input clock rate

is 15 MHz.

Figure 30 shows the conversion timing, and Table 39 describes DC specifications.

CLK

15MHz

15*CLK

AUXADC_EN

OSC_EN

N+1

N+4

N+2

N+3

N

SAMPLE

1M

D<11:0>

N

N+1

N+2

N+3

CLKOUT

1M

Figure 30: 12-bit ADC Timing Diagram

Table 39: DC Specification

Description

Min

Typ

Max

12

15

1

Unit

Bits

Resolution

4

12

Max clock input

Conversion frequency

Accuracy:

MHz

●

SNR

●

61.7

67.2

●

dB

SNDR

Analog input range

0

1.4

V

8.8.3

DMA Transfer

There are four ADC channel settings available. Once the input data of each channel reaches the

FIFO level, it is possible to read the data through the DMA path.

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8.8.4

Sensor Wake-up

DA16200MOD provides an external sensor wake-up function using the analog input signal through

this Aux ADC. Even in Sleep modes, it detects the change of external analog signal, wakes up from a

Sleep mode, and converts DA16200MOD into a normal operation. This function can be used in up to

four channels. Also, when multiple external sensors are used, it detects analog signals while

changing the channel automatically. For example, if it sets all four channels as input sources which

have their threshold register respectively, in measures the channels sequentially from 0 to 3.

If one of the four values exceed the allowed range of values set by the threshold register,

DA16200MOD is awaken from Sleep modes. The setting value of input change can be of two types,

over threshold and under threshold.

8.8.5

ADC Ports

Table 40 shows the pin definition of the ADC.

Table 40: ADC Pin Configuration

Pin Name

GPIOA3

GPIOA2

GPIOA1

GPIOA0

Pin Number

I/O

A

Function Name

Analog signal

30

31

32

33

A

8.9 GPIO

All digital pads can be used as GPIO, and each GPIO port is mixed with a multi-functional interface.

The GPIO features of DA16200MOD are listed below:

●

Input or output lines in a programmable direction

Word and half word read/write access

Address-masked byte writes to facilitate quick bit set and clear operations

Address-based byte reads to facilitate quick bit test operations

Maskable interrupt generation based on input value change

Possible to be output signal of PWM[3:0], external interrupt, QSPI_CSB[3:1], RF_SW[1:0], and

UART_TXDOE[2:0] on the GPIO pins:

○

It provides special functions for GPIO pin use. PWM [3:0], external interrupt, QSPI_CSB [3:1],

RF_SW [1:0], and UART_TXDOE [2:0] signals can be output by selecting unused pins

among the GPIO pins. It is possible to select the function to be output from the GPIO register

setting and select the remaining GPIO pin without using it to output the specific function to

the desired GPIO pins

8.9.1

Antenna Switching Diversity

DA16200MOD-AAE4WA32 (u.FL connector type module) provides the antenna switching diversity

function for performance improvement in multi-path environment. Phy block measures the RSSI of

each antenna and selects the antenna with the largest RSSI. The selected antenna is also used for

transmission. To use this function, an external switching element is required, and switching control is

performed through the GPIO. Two GPIOs can be used for switching control, and any unused pins

among the GPIO pins can be selected for this purpose. The control signal can be changed by

register setting to suit the external switching device.

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Antenna1

RF Switch

FC9050

DA16200MOD-AAE

RF Switch

Antenna2

ANT

GPIO

2

Figure 31: Antenna Switching Internal Block Diagram

If the Antenna Switching Diversity function is enabled, the function is automatically done by PHY

hardware block. The basic operation scheme is as follows:

●

Antenna's RSSI decision is made for 11b PPDU, except for 11g/n PPDU

When PHY hardware detects the existence of 11b PPDU, it stores RSSI

After it switch to another antenna, the RSSI stored and decision is made which antenna has

better RSSI

●

This operation is done during 11b PPDU's preamble duration to protect corruption of 11b PPDU

data reception

The decided antenna is not changed until there is a new 11b PPDU

Datasheet

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Figure 32: Antenna Switching Timing Diagram

For reference, this antenna switching diversity is different from MRC. (Maximum Ratio Combining)

8.10 UART

DA16200MOD provides 3 UARTs, features of which are described below:

●

Programmable use of UART (UART1 and UART2)

Compliance to the AMBA AHB bus specification [6] for easy integration into SoC implementation

Supports both byte and word access for reduction of bus burden

Supports both RS-232 and RS-485

Separate 32×8 bit transmit and 32×12 bit receive FIFO memory buffers to reduce CPU interrupts

Programmable FIFO disabling for 1-byte depth

Programmable baud rate generator

Standard asynchronous communication bits (start, stop and parity), which are added prior to

transmission and removed on reception

●

Independent masking of transmit FIFO, receive FIFO, and receive timeout

Supports for DMA

False start bit detection

Programmable flow control (CTS/RTS, UART1)

Fully programmable serial interface characteristics:

○

Data can be of 5,6,7, or 8 bits

Even, odd, stick, or no-parity bit generation and detection

1- or 2- stop bit generation

Baud rate generation

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Figure 33: DA16200 UART Block Diagram

8.10.1 RS-232

As the serial communication between the UART and the selected device is asynchronous, additional

bits (start and stop) are inserted to the data line to indicate the beginning and end. By these bits, two

devices can be synchronized. This structure of serial data accompanied by start and stop bits is

referred to as a character, as shown in Figure 34.

Bit Time

Data

Start

Data bits

5 - 8

Parity

Stop

1- or 2-

One Character

Figure 34: Serial Data Format

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An additional parity bit may be added to the serial character. This bit appears between the last data

bit and the stop bit(s) in the character structure. It provides the UART with the ability to perform

simple error checking on the received data.

The UART Line Control Register is used to control the serial character characteristics. The individual

bits of the data word are sent after the start bit, starting with the least significant bit (LSB). These are

followed by the optional parity bit, followed by the stop bit(s), which can be 1 or 2.

Serial Data In

Start

Data Bit 0 (LSB)

Data Bit 1

8

16

Figure 35: Receiver Serial Data Sampling Points

All the bits in the transmission are transmitted for exactly the same time duration. This is referred to

as a Bit Period or Bit Time. One Bit Time equals 16 baud clocks. To ensure stability on the line, the

receiver samples the serial input data at approximately the mid-point of the Bit Time, once the start

bit has been detected. As the exact number of baud clocks that each bit was transmitted for is

known, calculating the mid-point for sampling is not difficult, that is every 16 baud clocks after the

mid-point sample of the start bit. Figure 35 shows the sampling points of the first couple of bits in a

serial character.

8.10.2 RS-485

DA16200MOD UART supports RS-485. UART485EN register (0x054) is required to be assigned to

one to enable the RS-485. In order to use RS-485, additional signal (UARTTXDOE) is required to

notice TXD intervals. This signal can be an output by selecting any unused pins among the GPIO

pins.

Figure 36: UARTTXDOE Output Signal for UART RS-485

8.10.3 Baud Rate

UART clock frequency (FUARTCLK) is fixed to 80 MHz. Baud Rate Divisor can be calculated as

(FUARTCLK / (16 x Baud Rate)). Baud Rate Divisor is comprised of the integer part

(UART_INTBRDIV) and fractional part (UART_FRABRDIV). The maximum baud rate of DA16200

UART is 2.5 MBaud.

The following example shows how to calculate the divisor value.

Example:

If the required baud rate is 921600 with 80 MHz FUARTCLK, the Baud Rate Divisor becomes

(8 x 107) / (16 x 921600) = 5.425.

This means the integer value is 5 and the fractional value is 0.425.

Then, the fraction part becomes integer ((0.425 x 64) + 0.5) = 27.

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Then, generated baud rate divider is 5 + 27/64 = 5.422.

Finally, generated baud rate becomes (8 x 107) / (16 x 5.422) = 922169.

And the error between required baud rate and generated baud rate is

(922169 – 921600) / 921600 x100 = 0.062%.

8.10.4 Hardware Flow Control

Hardware flow control feature is fully selectable, and serial data flow is controlled by using

nUARTRTS output and nUARTCTS input signals. Figure 37 shows how two different UART can

communicate using hardware flow control.

Figure 37: UART Hardware Flow Control

When RTS flow control is enabled, nUARTRTS signal is asserted until the receive FIFO is filled up to

programmed level. When CTS flow control is enabled, transmitter can transmit the data when

nUARTCTS signal is asserted. CTSEn (CTS enable) and RTSEn (RTS enable) bits are determined

by 14th (RTS) and 15th bit (CTS) of UARTCR register.

Table 41: Control bits to enable and disable hardware flow control

CTSEn

RTSEn

Description

1

0

1

0

1

0

Both RTS and CTS flow control are enabled

Only CTS flow control is enabled

Only RTS flow control is enabled

Both RTS and CTS flow control are disabled

8.10.5 Interrupts

DA16200MOD UART block provides five interrupt signals by separate interrupt lines. Each interrupt

conditions are Modem Status, Receive FIFO Request, Transmit FIFO Request, Receive Timeout and

Reception Error. These conditions are logically OR'ed to provide a single combined interrupt,

UARTINTR. Table 42 shows the interrupt signals.

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Table 42: UART Interrupt Signals

Signal Name

Description

UARTMSINTR

UARTRXINTR

UARTTXINTR

UARTRTINTR

UARTEINTR

UARTINTR

UART Modem Status Interrupt

UART Receive FIFO Interrupt

UART Transmit FIFO Interrupt

UART Receive Timeout Interrupt

UART Error Interrupt

UART Interrupt. Five Interrupt signals are combined by OR function

8.10.6 DMA Interface

DA16200MOD UART block can generate DMA request signals with register settings by using DMA

interrupt generator module to connect to DA16200 DMA Controller (DMA1). DMA operation of the

UART is controlled using DMA Control Register.

DA16200MOD UART provides four DMA signals and receives two DMA signals, two signals to

transmit (TXDMASREQ, TXDMABREQ) which are cleared by TX clear signal (TXDMACLR) and two

signals to receive (RXDMASREQ, RXDMABREQ), which are cleared by RX clear signal

(RXDMACLR).

When the DMA interface is not used, the TXDMACLR and RXDMACLR lines should be connected to

a logic ‘0’.

Table 43 shows the pin definition of the UART interface.

Table 43: UART Pin Configuration

Pin Name

UART0_RXD

UART0_TXD

GPIOA7

Pin Number

I/O

I

Function Name

UART0_RXD

UART0_TXD

13

12

26

28

30

32

27

29

31

33

28

29

22

10

23

11

O

I

GPIOA5

I

UART1_RXD

UART1_TXD

GPIOA3

I

GPIOA1

I

GPIOA6

O

I

GPIOA4

GPIOA2

GPIOA0

GPIOA5

UART1_CTS

UART1_RTS

GPIOA4

O

I

GPIOA11

GPIOC7

GPIOA10

GPIOC6

UART2_RXD

UART2_TXD

I

O

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8.11 PWM

Pulse Width Modulation (PWM) is a modulation technique used to encode a message into a pulse

signal. The blocks are designed to adjust output pulse duration by the CPU bus clock (HCLK).

Figure 38 shows the structure of the PWM block.

Counter

PWM OUT

PWM Block 0

Counter (Period)

PWM OUT

PWM Block 1

HCLK

Counter (Period)

^CounterP^(HW^igM^{h Du}B^tylo⁾ck 2

Register

Counter (Period)

^CounterP^(HW^ighM^DuB^tylo⁾ck 3

AHB

Bus

Matrix

Counter (Period)

Counter (High Duty)

Register

AHB Bus

Counter (High Duty)

Register

Figure 38: PWM Block Diagram

Table 44 shows the pin definition of the PWM interface. GPIOx means that PWM signals can go out

through any GPIO pins via register setting.

Table 44: PWM Pin Configuration

Pin Name

Pin Number

I/O

Function Name

GPIOx

PWM[3:0] output

8.11.1 Timing Diagram

Table 45 shows the relation between the internal bus clock and PWM output wave patterns. Figure

39 show the conversion timing diagram. ‘a’ and ‘b’ can be adjusted through the register setting, and

PWM wave patterns vary depending on the ratio. ‘a’ controls the high width of pulses (nCycle High),

while ‘b’ controls the general cycle (nCycle Period).

BUS CLK

a

PWM

b

Figure 39: PWM Timing Diagram

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Table 45: PWM Timing Diagram Description

Time

Description

a

b

Bus Clock Period × (nCycle High + 1)

Bus Clock Period × (nCycle Period + 1)

8.12 Debug Interface

DA16200MOD supports both IEEE Standard 1149.1 JTAG (5-wire) and the low-pin-count ARM SWD

(2-wire, TCLK/TMS) debug interfaces. The SWD protocol can handle the same debug features as

the JTAG.

The JTAG port is an IEEE standard that defines a test access port (TAP) and boundary scan

architecture for digital integrated circuits and provides a standardized serial interface to control the

associated test logic. For detailed information on the operation of the JTAG port and TAP controller,

see [4].

Figure 40 shows the JTAG timing diagram.

Figure 40: JTAG Timing Diagram

Table 46 shows the JTAG timing parameters.

Table 46: JTAG Timing Parameters

Parameter Number

Parameter

f_TCK

Parameter Name

Clock Frequency

Clock Period

Min

Max

15

Unit

MHz

ns

J1

J2

t_TCK

1/f_TCK

t_TCK/2

J3

t_CL

Clock Low Period

Clock High Period

TMS Setup Time

TMS Hold Time

TDI Setup Time

TDI Hold Time

ns

J4

t_CH

ns

J7

t_{TMS_SU}

t_{TMS_HO}

t_{TDI_SU}

t_{TDI_HO}

t_{TDO_HO}

1

16

1

J8

J9

J10

J11

16

TDO Hold Time

15

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Table 47 shows the pin definition of the JTAG interface.

Table 47: JTAG Pin Configuration

Pin Name

TMS

Pin Number

I/O

Function Name

Data

7

8

I/O

TCLK

I

Clock

GPIOC8

GPIOC7

GPIOC6

9

TDI: Data Input

TDO: Data Output

nTRST: Reset

10

11

O

I

8.13 Bluetooth Coexistence

DA16200MOD provides the Bluetooth coexistence function to be properly aligned with external

devices activated at 2.4 GHz.

8.13.1 Interface Configuration

The following three pins can be set in pin multiplexing:

●

BT_sig0 (oWlanAct)

It indicates that Output, WLAN is currently active

BT_sig1 (iBtAct)

It indicates that Input, BT/BLE is currently active

BT_sig2 (iBTPri)

It indicates that Input (Optional), BT/BLE has a higher priority

○

A variety of configurable settings are available, including active high/low, manual force mode, use

status of the optional iBTPri function, and whether or not to switch oWlanAct to Active in the event of

TX/RX/TRX.

oWlanAct

iBtAct

iBtPri

DA16200MOD

BT/BLE

Figure 41: Bluetooth Coexistence Interface

8.13.2 Operation Scenario

The Bluetooth coexistence can be switched on/off by the configurable register, and the activation

scenarios based on the status of each pin are described below:

●

BT_sig0 (oWlanAct)

When asserted, external BT/BLE is expected to stop occupying RF

BT_sig1 (iBtAct)

When asserted, DA16200MOD stops occupying RF

BT_sig2 (iBTPri)

It is optional and thus may not be used

○

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○

If it is used and DA16200’s iBtAct = Active while iBTPri = Non-Active, DA16200 may ignore

iBtAct

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9

Applications Schematic

37

36

NC

1

NC

Note : Remove R1 and C1

1uF

10uF

C1

when MCU controls 'RTC_PWR_KEY'

2

3

35

34

33

32

31

30

29

28

27

26

25

24

VBAT_3V3

GND

VBAT_3V3

VDD_DIO1

GPIOA0

GPIOA1

GPIOA2

GPIOA3

GPIOA4

GPIOA5

GPIOA6

GPIOA7

GPIOA8

GPIOA9

R1

External Power Control

External Wake-up Control

RTC Sensor Out

RTC_PWR_KEY

RTC_WAKE_UP

RTC_SENSOR

NC

VDD_DIO1, (1.8V or 3.3V)

4

5

GPIO Interface

6

4.7KΩ

7

JTAG_TMS

JTAG_TCLK

GPIOC8

DA16200MOD

JTAG interface

GPIO Interface

8

UART1_TXD

UART1_RXD

WPS

9

10

11

12

13

GPIOC7

GPIOC6

Factory_reset

UART0_TXD

UART0_RXD

UART interface for debugging

GPIO Interface

4.7KΩ

14

15 16 17 18 19 20 21 22 23

If you use it as GPIO function, you don't need full-up resistor

If the RTC_WAKE_UP2 function is not uesd,

it can be connected to the GND

4.7KΩ

1uF

Figure 42: Application Schematic

Table 48: Component for RTC POWER KEY

Quantity Part Reference

Value

Description

Remove when MCU control ‘RTC_PWR_KEY’.

This value should be chosen by customer application

to achieve the enough delay time depending on the

power-on time of VBAT.

1

R1

C1

470 kΩ

For detail information, See 6.1

Remove when MCU control ‘RTC_PWR_KEY’.

This value should be chosen by customer application

to achieve the enough delay time depending on the

power-on time of VBAT. Not to exceed 1uF.

1uF

For detail information, See 6.1

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10 Package Information

10.1 Dimension: DA16200MOD-AAC

Unit: mm

Tolerance: 13.8(±0.2) x 22.1(±0.2) x 3.3(±0.1)

Figure 43: AAC Module Dimension

10.2 Dimension: DA16200MOD-AAE

Unit: mm

Tolerance: 13.8(±0.2) x 22.1(±0.2) x 3.3(±0.1)

Figure 44: AAE Module Dimension

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10.3 PCB Land Pattern

Unit: mm

Figure 45: PCB Land Pattern (Top View)

Figure 46: PCB Land Pattern (Bottom View)

Ant GND is only needed on the bottom of the PCB. GND must be removed for all layers including the

inner layer except the bottom. See Figure 47 for detail.

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10.4 4-Layer PCB Example

Figure 47: 4-Layer PCB Example

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10.5 Soldering Information

10.5.1 Condition for Reflow Soldering

Figure 48 shows the typical process flow for mounting surface mount packages to PCB.

The reflow profile depends on the solder paste being used and the recommendations from the paste

manufacture should be followed to determine the proper reflow profile. Figure 49 shows a typical

reflow profile when a no-clean paste is used. Oven time above liquidus (260 °C for lead-free solder)

is 20 to 40 seconds.

The rework process involves the following steps:

1. Component removal

2. Site redress

3. Solder paste application

4. Component placement

5. Component attachment

Figure 48: Typical PCB Mounting Process Flow

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Table 49: Typical Reflow Profile (Lead Free): J-STD-020C

Profile Feature

Lead Free SMD

3 °C/s Max.

Average ramp up rate (Ts_maxto T_p)

Preheat

●

Temperature Min (Ts_min

Temperature Max (Ts_max

Time (Ts_maxto Ts_min

)

●

150 °C

)

200 °C

)

60 to 180 seconds

Time maintained above

●

Temperature (T_L)

Time (t_L)

●

217 °C

60 to 150 seconds

Peak/Classification temperature (T_p)

Time within 5 °C of peak temperature (tp)

Ramp down rate

260 °C

20 to 40 seconds

6 °C/s Max.

8 minutes Max.

Time from 25 °C to peak temperature

Figure 49: Reflow Condition

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11 Ordering Information

The ordering number consists of the part number followed by a suffix indicating the packing method.

For details and availability, please consult Dialog Semiconductor’s Website or your local sales

representative.

Table 50: Ordering Information (Production)

Part Number

Pins

37

Size (mm)

Shipment Form

Reel

Pack Quantity

MOQ: 500 pcs

DA16200MOD-AAC4WA32

DA16200MOD-AAE4WA32

13.8 x 22.1 x 3.3

37

Reel

Part Number Legend:

DA16200MOD-AAC4WA32

AA: Module revision number

C: Select module type

[C] Chip antenna, [E] u.FL connector

4: Flash memory

[4] 4Mbyte, [2] 2Mbyte

W: Voltage range

[W] 3.3 V, [L] 1.8 V

A3: Package No.

2: T&R packing

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Revision History

Revision

Date

Description

●

Editorial

Removed BOR part

Added Note for Power on Sequence in the Section 6.1, Updated Figure 7

and Table 16

3.1

03-Fab-21

●

Section 8.7.3 Fixed typo

Added Section 8.7.1 and 8.7.2

Updated Applications Schematic

●

Sync with SoC datasheet v3.1

Modified Chapter 3 description to Network subsystem layer.

Modified DA16200MOD pin Mux (Table 2)

○

Added module default pin conditions

I2C CLK GPIOA2 -> GPIOA3

●

Added chapter 5.3.3, 5.3.4

Modified Rx max input level in chapter 5.4.1(Table 11)

Updated Chapter Note 1 Sleep mode description

Updated RTC_PWR_KEY description and remove one sentence which

leads to misunderstanding. Table 17

3.0

23-Jul-20

●

Modified I2C timing in table Table 30, Table 32

Added description of chapter 8.9.1

Updated Chapter 9 application schematics

Changed Module dimension picture Error! Reference source not found.,

Error! Reference source not found.

●

Removed F_xx pins

Changed the link from customer support portal to Dialog website

Added PCB land pattern Figure 46, Figure 47

●

Added Tolerance of dimension

Added min/max Radio characteristics in Table 11, Table 12and Table 13

Modified Chapter 8.10.3 Baud rate

2.0

08-May-20

Updated Reach and ROHS compliance

●

Updated Key Features

Modified DA16200MOD pin Mux Table 2

Chapter 7.4 Pulse Counter added

Chapter 8.10.1 RS-232 added

0.4

0.3

07-Apr-20

23-Mar-20

●

Added ESD performance, Table 15

AC characteristics and current consumption of data updated in Table 11,

Table 12 and Table 13

●

Updated Key Features, about clock source & embedded memory

Modified module size

0.2

0.1

22-Oct-19

03-Oct-19

Preliminary datasheet

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Status Definitions

Revision

Datasheet Status

Product Status

Definition

This datasheet contains the design specifications for product development.

Specifications may be changed in any manner without notice.

1.<n>

Target

Development

This datasheet contains the specifications and preliminary characterization

data for products in pre-production. Specifications may be changed at any

time without notice in order to improve the design.

2.<n>

3.<n>

Preliminary

Qualification

This datasheet contains the final specifications for products in volume

production. The specifications may be changed at any time in order to

improve the design, manufacturing and supply. Major specification changes

are communicated via Customer Product Notifications. Datasheet changes

are communicated via www.dialog-semiconductor.com.

Final

Production

Archived

This datasheet contains the specifications for discontinued products. The

information is provided for reference only.

4.<n>

Obsolete

Disclaimer

Unless otherwise agreed in writing, the Dialog Semiconductor products (and any associated software) referred to in this document are not

designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications

where failure or malfunction of a Dialog Semiconductor product (or associated software) can reasonably be expected to result in personal injury,

death or severe property or environmental damage. Dialog Semiconductor and its suppliers accept no liability for inclusion and/or use of Dialog

Semiconductor products (and any associated software) in such equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or

warranties, express or implied, as to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no

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Dialog Semiconductor reserves the right to change without notice the information published in this document, including, without limitation, the

specification and the design of the related semiconductor products, software and applications. Notwithstanding the foregoing, for any automotive

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limitation, the specification and the design of the related semiconductor products, software and applications, in accordance with its standard

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Applications, software, and semiconductor products described in this document are for illustrative purposes only. Dialog Semiconductor makes

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Dialog, Dialog Semiconductor and the Dialog logo are trademarks of Dialog Semiconductor Plc or its subsidiaries. All other product or service

names and marks are the property of their respective owners.

Reach and RoHS Compliance

Dialog Semiconductor’s suppliers certify that its products are in compliance with the requirements of REACH and Directive 2015/863/EU of the

European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from

our suppliers are available on request. Module does not have to be HF.

Contacting Dialog Semiconductor

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Phone: +44 1793 757700

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www.dialog-semiconductor.com

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型号：	DA16200MOD-AAE4WA32
厂家：	Dialog Semiconductor
描述：	Ultra Low Power Wi-Fi Module
文件：	总60页 (文件大小：2205K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DA16200MOD-AAE4WA32 [DIALOG]

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