DA9070 [DIALOG]
Ultra-Low Quiescent Current PMIC;型号: | DA9070 |
厂家: | Dialog Semiconductor |
描述: | Ultra-Low Quiescent Current PMIC 集成电源管理电路 |
文件: | 总130页 (文件大小:3031K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DA9070
Ultra-Low Quiescent Current PMIC
General Description
DA9070 is a highly integrated, configurable, low quiescent current PMIC that integrates the most
common needs for wearables, home automation and low power battery applications.
The Power Management IC (PMIC) comprises a linear charger with Power Path management, ultra-
low quiescent current (Iq) buck regulator and LDO/Load Switches, wide output voltage boost
regulator, analog battery monitor, watchdog and protection features in an I2C configurable compact
WLCSP package.
DA9070 has several power saving modes to increase battery life whether the product sits on the
shelf or is in operation. Further savings in power are achieved with the ultra-low Iq buck converter
that is efficient down to 10 µA load currents and low Iq LDOs. The uncommitted inputs of LDOs can
be connected to either the battery or buck output.
The integrated, high-efficiency boost regulator supports both sensors and display supply needs with
a wide range configurable output voltage.
DA9070 provides charge current up to 500 mA to speed up the charge cycle. The charge profile is
programmable by external resistors or in software, allowing either stand-alone operation or host
control.
DA9070 includes dynamic power path management which automatically balancing current delivered
to the system and battery charging.
Suitable for small battery applications, the battery monitor facilitates on-demand battery voltage and
discharge current monitors to an external MCU’s ADC for supporting software fuel gauging.
Key Features
■
Increased battery life
■ High integration and configurability
□
800 nA (no load, total battery current) buck
converter, programmable down to 0.6 V,
300 mA-capable
□
□
□
Wide output voltage boost regulator
(4.5V to 18 V)
I2C enabled analog battery monitors for
Software Fuel Gauging
□
Three configurable 800nA Quiescent
Current LDOs/Load Switches, 150 mA-
capable
Watchdog input and power-cycling to
prevent system stall
■
■
Power saving modes optimized for storage
and operation
□
□
□
Reset input and status outputs
Low external component count
Battery protection
Compact, 42 pin, 2.97 mm x 2.66 mm
WLCSP package
□
Battery thermal- and over-discharge
protection
■
Fast charge
□
□
20 V tolerant input
□
□
500 mA (max) charge current; 2 mA (min)
Automatic battery temperature monitoring
in all operation modes
Programmable pre-charge, fast charge,
and termination voltage
■
Configurable battery monitors
□
□
□
Dynamic power path balances multiple
power sources
□
□
□
Battery current (IMON)
Battery voltage (VBAT_DIV)
Battery temperature (TEMP_SNS)
Termination current programmable down
to 500 µA
±0.5 % accurate termination voltage
Datasheet
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© 2020 Dialog Semiconductor
DA9070
Ultra-Low Quiescent Current PMIC
Applications
■
Wearable devices - Fitness trackers, smart
watches, wireless headphones
■
■
■
Health monitoring medical accessories
Rechargeable toys
■
Home automation devices - Smoke detectors,
Smart thermostats, Smart door locks
High efficiency, ultra-low power
applications
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
Contents
General Description ............................................................................................................................ 1
Key Features ........................................................................................................................................ 1
Applications ......................................................................................................................................... 2
Contents ............................................................................................................................................... 3
Figures.................................................................................................................................................. 6
Tables ................................................................................................................................................... 7
1
2
3
4
5
6
System Diagram ............................................................................................................................ 9
Pinout ........................................................................................................................................... 10
Absolute Maximum Ratings ....................................................................................................... 13
Recommended Operating Conditions....................................................................................... 14
ESD Ratings................................................................................................................................. 15
Electrical Characteristics ........................................................................................................... 16
6.1 Battery Charger................................................................................................................... 16
6.2 Battery Temperature Monitor .............................................................................................. 17
6.3 LDO / Load Switches .......................................................................................................... 18
6.4 Digital Inputs (MODE and WD) ........................................................................................... 21
6.5 I2C Interface ........................................................................................................................ 21
6.6 Input Currents ..................................................................................................................... 22
6.7 Power-Path Management and Current Limit ...................................................................... 22
6.8 Protection ............................................................................................................................ 23
6.9 Pushbutton Timer (RIN_N).................................................................................................. 24
6.10 Digital Outputs (SYS_FLT, PWR_FLT, and ROUT_N)....................................................... 24
6.11 Buck Regulator.................................................................................................................... 25
6.12 Boost Regulator .................................................................................................................. 26
6.13 Battery Monitors (VBAT_DIV and IMON)............................................................................ 27
7
8
9
Thermal Characteristics ............................................................................................................. 28
Typical Performance................................................................................................................... 29
Functional Description ............................................................................................................... 36
9.1 Overview ............................................................................................................................. 36
9.2 Battery-Powered Operation ................................................................................................ 37
9.2.1
9.2.2
9.2.3
Ship Mode............................................................................................................ 37
Active Battery and High Impedance Modes ........................................................ 37
Battery Protection ................................................................................................ 38
9.2.3.1
9.2.3.2
9.2.3.3
VBAT Over-Current Protection (OCP)............................................. 38
VBAT_UVLO and SHORT............................................................... 38
Battery Temperature Sensing.......................................................... 38
9.3 Analog Battery Monitor Functions....................................................................................... 43
9.4 Battery Charging ................................................................................................................. 44
9.4.1
Battery Charging Process.................................................................................... 44
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DA9070
Ultra-Low Quiescent Current PMIC
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
Charge In-Progress ............................................................................................. 45
Pre-charge and Termination Current................................................................... 45
Fast Charge Current............................................................................................ 46
CV Voltage Regulation and Termination ............................................................. 46
Charge Done and Recharge................................................................................ 46
Charge Faults ...................................................................................................... 46
Safety Timers....................................................................................................... 47
9.5 USB Powered Operation and Power Path Management.................................................... 48
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
9.5.8
Under-Voltage Lockout (VDD_PWR_UVLO)....................................................... 48
Sleep Mode.......................................................................................................... 48
VDD_PWR Current Limit (IDD_PWR_LIM)......................................................... 48
Input Voltage Dynamic Power Management (DPM)............................................ 48
Dynamic Power Path Mode (DPPM) ................................................................... 49
Battery Supplement Mode ................................................................................... 49
Input Over-Voltage Protection (VDD_PWR_OVP) .............................................. 49
VDD_PWR Input Supply Impedance................................................................... 49
9.6 Power-Cycling..................................................................................................................... 51
9.6.1
9.6.2
Requested Power-Cycle...................................................................................... 51
Fault Triggered Power-Cycle............................................................................... 52
9.7 Standalone Mode................................................................................................................ 54
9.7.1
9.7.2
9.7.3
Termination and Pre-Charge Current Programming (ITER_CHG) ..................... 54
Input Current Limit Programming (ILIM_PWR) ................................................... 55
Charge Current Programming (ILIM_CHG)......................................................... 55
9.8 Host and Pushbutton Communication ................................................................................ 56
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.6
Watchdog Input and Timer .................................................................................. 57
VDDIO.................................................................................................................. 58
Interrupt Events and Status Control (SYS_FLT, PWR_FLT) .............................. 58
Pushbutton Reset Timer and Reset Output (RIN_N and ROUT_N) ................... 59
System Status Register ....................................................................................... 60
I2C Programming ................................................................................................. 60
9.9 Buck Regulator.................................................................................................................... 62
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6
9.9.7
9.9.8
9.9.9
Buck Output Voltage Programmability................................................................. 62
Buck Enable and Soft Start Operation................................................................. 62
Power Saving Mode Operation............................................................................ 62
Dynamic Voltage Control..................................................................................... 62
Over-Current Protection....................................................................................... 63
Output Under-Voltage Protection ........................................................................ 63
Output Over-Voltage Protection .......................................................................... 63
Automatic Output voltage Discharge................................................................... 63
External Component Selection ............................................................................ 63
9.10 Boost Regulator .................................................................................................................. 64
9.10.1 Startup ................................................................................................................. 64
9.10.2 Switch Node Anti-Ringing.................................................................................... 65
9.10.3 Protection............................................................................................................. 65
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DA9070
Ultra-Low Quiescent Current PMIC
9.10.4 Low Output Voltage Settings ............................................................................... 66
9.11 LDO / Load Switches .......................................................................................................... 66
9.12 Thermal Protection.............................................................................................................. 67
9.13 PCB Layout Guidelines....................................................................................................... 68
10 Registers ...................................................................................................................................... 70
10.1 Register Map....................................................................................................................... 70
10.1.1 System................................................................................................................. 70
10.1.2 Charger................................................................................................................ 71
10.1.3 Buck, Boost, and LDO Control ............................................................................ 72
10.2 Register Definitions............................................................................................................. 74
10.2.1 System................................................................................................................. 74
10.2.2 Config................................................................................................................... 87
10.2.3 Charger................................................................................................................ 88
10.2.3.1
Charger and Power-Path................................................................. 88
10.2.4 Buck, Boost, and LDO Control .......................................................................... 107
10.2.4.1
10.2.4.2
Vout User Registers....................................................................... 107
Vout Opt Registers ........................................................................ 127
11 Package Information................................................................................................................. 128
11.1 Package Outlines.............................................................................................................. 128
11.2 Moisture Sensitivity Level.................................................................................................. 128
11.3 Soldering Information........................................................................................................ 128
12 Ordering Information ................................................................................................................ 129
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DA9070
Ultra-Low Quiescent Current PMIC
Figures
Figure 1: System Diagram..................................................................................................................... 9
Figure 2: Connection Diagram (bottom view)...................................................................................... 10
Figure 3: Buck Efficiency, VOUT = 1.8 V ............................................................................................... 29
Figure 4: Boost Efficiency, VOUT = 12 V, VIN = VDD_BST......................................................................... 29
Figure 5: Buck Efficiency, VOUT = 0.9 V ............................................................................................... 29
Figure 6: Buck Regulation, VOUT = 1.8 V.............................................................................................. 29
Figure 7: Buck Regulation, VOU = 0.9 V............................................................................................... 30
Figure 8: Boost Efficiency, VOUT = 5 V, VIN = VDD_BST .......................................................................... 30
Figure 9: Boost Efficiency, VOUT = 12 V, VIN = VBAT ............................................................................. 30
Figure 10: Boost Efficiency, VOUT = 5 V, VIN = VBAT ............................................................................. 30
Figure 11: Boost Regulation, VOUT = 12 V........................................................................................... 31
Figure 12: Boost Regulation, VOUT = 5 V............................................................................................. 31
Figure 13: Boost Maximum Load Current Capability .......................................................................... 31
Figure 14: LDO_0 Dropout, VIN = 3.15 V, VOUT Setting = 3.15 V ........................................................ 31
Figure 15: LDO_1 and LDO_2 Dropout, VIN = 3.3 V, VOUT Setting = 3.3 V......................................... 32
Figure 16: LDO_0 Regulation and Dropout, VOUT = 1.80 V................................................................. 32
Figure 17: LDO_0 Regulation and Dropout, VOUT = 3.15 V................................................................. 32
Figure 18: LDO_1 Regulation and Dropout, VOUT = 3.30 V................................................................. 32
Figure 19: LDO_1 Regulation and Dropout, VOUT = 1.80 V................................................................. 33
Figure 20: LDO2 Load Regulation, VOUT = 3.30 V............................................................................... 33
Figure 21: LDO_2 Regulation and Dropout, VOUT = 1.80 V................................................................. 33
Figure 22: Typical Buck Startup, VBAT = 3.6 V, VBUCK = 1.8 V and 0.9 V, 0 A ..................................... 33
Figure 23: Typical Boost Startup, VDD_BST = 3.6 V, VOUT = 5 V and 12 V, 0 A..................................... 34
Figure 24: VBAT IQ, Buck Switching, no load, Hi-Z mode.................................................................. 34
Figure 25: VBAT IQ, Ship Mode.......................................................................................................... 34
Figure 26: VDD_LDO IQ, no load........................................................................................................ 34
Figure 27: Charger Efficiency, VDD_PWR = 5 V...................................................................................... 35
Figure 28: Regions of Operation ......................................................................................................... 36
Figure 29: Battery Temperature Sensing with NTC ............................................................................ 39
Figure 30: Battery Temperature Sense Timing ................................................................................... 42
Figu re 31: Example 70mAh Charge Cycle......................................................................................... 44
Figure 32: VDD_PWR DPM setting recommendations....................................................................... 50
Figure 33: Power-Cycle by Pushbutton Timer..................................................................................... 51
Figure 34: Power-Cycle by VDD_PWR Insertion ................................................................................ 52
Figure 35: Digital Pin Connections ...................................................................................................... 56
Figure 36: Watchdog Behaviour.......................................................................................................... 57
Figure 37: PWR_FLT Configured as RIN_N Monitor, 0x11:[4]=1 ....................................................... 58
Figure 38: PWR_FLT Configured as VDD_PWR Status Indicator, 0x11:[4]=0................................... 58
Figure 39: RIN_N Pushbutton Reset Timer Timing Diagram.............................................................. 59
Figure 40: I2C Start and Stop Conditions ............................................................................................ 61
Figure 41: Maximum Boost Load at Startup vs VBAT......................................................................... 65
Figure 42: Example PCB Layout, Top Layer....................................................................................... 69
Figure 43: Example PCB Layout, Layer-2........................................................................................... 69
Figure 44: WLCSP-42 Package Outline Drawing ............................................................................. 128
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
Tables
Table 1: Pin Description ...................................................................................................................... 11
Table 2: Pin Type Definition ................................................................................................................ 12
Table 3: Absolute Maximum Ratings................................................................................................... 13
Table 4: Recommended Operating Conditions ................................................................................... 14
Table 5: Recommended External Components .................................................................................. 14
Table 6: Battery Charger ..................................................................................................................... 16
Table 7: Battery Temperature Monitor ................................................................................................ 17
Table 8: LDO0/Loadswitch (LV) .......................................................................................................... 18
Table 9: LDO1/Loadswitch .................................................................................................................. 19
Table 10: LDO2/Loadswitch ................................................................................................................ 20
Table 11: Digital Input Pins (MODE,WD) ............................................................................................ 21
Table 12: I2C Interface........................................................................................................................ 21
Table 13: Input Currents...................................................................................................................... 22
Table 14: Power-Path Management and ILIM..................................................................................... 22
Table 15: Protection ............................................................................................................................ 23
Table 16: Pushbutton Timer(RIN_N)................................................................................................... 24
Table 17: Digital Output Pins (SYS_FLT, PWR_FLT, and ROUT_N)................................................. 24
Table 18: Buck..................................................................................................................................... 25
Table 19: Boost ................................................................................................................................... 26
Table 20: Battery Monitors (VBAT_DIV and IMON)............................................................................ 27
Table 21: Thermal Characteristics ...................................................................................................... 28
Table 22: MODE Functionality ............................................................................................................ 38
Table 23: Battery Thermal Protection Measures................................................................................ 39
Table 24: VBAT_DIV Ratios................................................................................................................ 43
Table 25: Charge Status...................................................................................................................... 44
Table 26: Charging Modes .................................................................................................................. 45
Table 27: Charge Faults...................................................................................................................... 46
Table 28. Safety Timer Register Settings (0x21) ................................................................................ 48
Table 29: Power Cycle Trigger Settings.............................................................................................. 51
Table 30: Power-Cycle Faults ............................................................................................................. 52
Table 31: BUCK Power Cycle Faults .................................................................................................. 53
Table 32: Enabling External Resistor Setting Mode............................................................................ 54
Table 33: ITER_CHG Recommended Resistor Values ...................................................................... 54
Table 34: ILIM_PWR Recommended Resistor Values ....................................................................... 55
Table 35: ILIM_CHG Recommended Resistor Values........................................................................ 55
Table 36: Digital Pins for Host and Pushbutton Interface ................................................................... 56
Table 37: WD_EN Register 0x14 [1:0] ................................................................................................ 57
Table 38: WD_CLR_SEL Register 0x14 [3:2] ..................................................................................... 57
Table 39: SYS_FLT Configuration, 0x11: [0]....................................................................................... 58
Table 40: RIN_N Pushbutton wake-up timer control (0x10)................................................................ 59
Table 41: RIN_N Reset Timer Configuration....................................................................................... 60
Table 42: I2C Interface Configuration .................................................................................................. 60
Table 43: External Buck Components................................................................................................. 64
Table 44: Recommended External Boost Components ...................................................................... 64
Table 45: Register SYS_STS_0.......................................................................................................... 74
Table 46: Register SYS_ISR_0........................................................................................................... 74
Table 47: Register SYS_ISR_1........................................................................................................... 75
Table 48: Register SYS_ISR_2........................................................................................................... 76
Table 49: Register SYS_ISR_3........................................................................................................... 76
Table 50: Register SYS_ISR_4........................................................................................................... 77
Table 51: Register SYS_IMR_0 .......................................................................................................... 77
Table 52: Register SYS_IMR_1 .......................................................................................................... 78
Table 53: Register SYS_IMR_2 .......................................................................................................... 79
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
Table 54: Register SYS_IMR_3 .......................................................................................................... 79
Table 55: Register SYS_IMR_4 .......................................................................................................... 80
Table 56: Register SYS_SYS_0.......................................................................................................... 80
Table 57: Register SYS_BAT_0.......................................................................................................... 81
Table 58: Register SYS_BAT_1.......................................................................................................... 82
Table 59: Register SYS_RIN_N_0...................................................................................................... 82
Table 60: Register SYS_STS_OUT_0 ................................................................................................ 83
Table 61: Register SYS_PWR_CYC_0............................................................................................... 84
Table 62: Register SYS_PWR_CYC_1............................................................................................... 85
Table 63: Register SYS_WD_0........................................................................................................... 86
Table 64: Register SYS_I2C_0 ........................................................................................................... 87
Table 65: Register SYS_CFG_I2C_0.................................................................................................. 87
Table 66: Register CHG_CHG_0........................................................................................................ 88
Table 67: Register CHG_CHG_1........................................................................................................ 89
Table 68: Register CHG_ICHG_0....................................................................................................... 89
Table 69: Register CHG_IPRETERM_0 ............................................................................................. 93
Table 70: Register CHG_VBREG_0 ................................................................................................... 96
Table 71: Register CHG_VBPRECHG_0.......................................................................................... 102
Table 72: Register CHG_BAT_TS_0 ................................................................................................ 103
Table 73: Register CHG_VDD_PWR_0............................................................................................ 103
Table 74: Register CHG_VDD_PWR_1............................................................................................ 105
Table 75: Register CHG_IDISCHG_0............................................................................................... 106
Table 76: Register VOUT_BUCK...................................................................................................... 107
Table 77: Register VOUT_BUCK_CFG ............................................................................................ 109
Table 78: Register VOUT_LS_LDO0 ................................................................................................ 110
Table 79: Register VOUT_LS_LDO1 ................................................................................................ 113
Table 80: Register VOUT_LS_LDO2 ................................................................................................ 115
Table 81: Register VOUT_LS_LDO_CFG......................................................................................... 118
Table 82: Register VOUT_BOOST ................................................................................................... 119
Table 83: Register VOUT_BOOST_CFG0........................................................................................ 123
Table 84: Register VOUT_BOOST_CFG1........................................................................................ 124
Table 85: Register VOUT_BOOST_CFG2........................................................................................ 125
Table 86: Register VOUT_BUCK_OPT0........................................................................................... 127
Table 87: MSL Classification............................................................................................................. 128
Table 88: Ordering Information ......................................................................................................... 129
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
1 System Diagram
vdd_sys
VDD_SYS
VDD_PWR
4.7µF
USB
1.0µF
VTEMP
VTEMP Control
NTC Monitor
+
-
TEMP_SNS
20V OVP
Protection
Charger and
Power Path
Control
VBAT
vdd_sys
VDD_BUCK
SW_BUCK
VBAT_SNS
2.2µH
ILIM_PWR
ILIM_CHG
ITER_CHG
Vo_buck
0.6V – 2.1V
300mA
Buck
Standalone Mode
10µF
BATTERY
PACK
PGND_BUCK
FB_BUCK
GND
AGND
vdd_sys
VDD_BST
Vo buck
4.7µH
SW_BST
VDDIO
VOUT_BST
Vo_boost
4.5V – 18V
SCL
SDA
10µF
Boost
PGND_BST
FB_BST
PWR_FLT
SYS_FLT
ROUT_N
MODE
Host
Communication
Vo_buck
VDD_LDO0
WD
Host
1µF
LDO 0
(LV)
VLDO0
LDO0
VBAT_DIV
0.8V – 3.15V
150mA
2.2µF
ADC
(fuel gauge)
GND_DIV
IMON
VDD_LDO1
Analog Battery
Monitors
vdd_sys
LDO 1
(HV)
VLDO1
LDO1
0.8V – 3.3V
150mA
DA9070
VDD_LDO2
PUSHBUTTON RESET
RIN_N
LDO 2
(HV)
VLDO2
LDO2
0.8V – 3.3V
150mA
Figure 1: System Diagram
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DA9070
Ultra-Low Quiescent Current PMIC
2
Pinout
7
6
5
4
3
2
1
A
B
C
D
E
F
PGND_BUCK SW_BUCK VDD_BUCK
VDD_SYS
TEMP_SNS
WD
VDD_SYS
IMON
VDD_PWR
VBAT
GND
FB_BUCK
AGND
SDA
SCL
SYS_FLT
RIN_N
MODE
VBAT
ILIM_CHG
GND
ITER_CHG
ILIM_PWR
VTEMP
VBAT_SNS
VDD_BST
PGND_BST
SW_BST
PWR_FLT
ROUT_N
VBAT_DIV
GND_DIV
GND
VDD_LDO0 VDD_LDO1 VDD_LDO2
VDDIO
FB_BST
VLDO0
VLDO1
VLDO2
VOUT_BST
COLOR KEY:
Charger/Power Path
Buck
LDO2
Boost
Reset/Timer
Temp Sense Common
LDO0 LDO1
Control
Figure 2: Connection Diagram (Bottom View)
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
Table 1: Pin Description
Type
Pin No. Pin Name
Description
(Table 2)
A1, D3,
GND
F4
GND
Ground connection. Connect to the ground plane
Input power supply. VDD_PWR is a 20V-tolerant input. Bypass to
GND with a minimum 1uF ceramic capacitor.
A2
VDD_PWR
VDD_SYS
POWER
POWER
VDD_SYS is the intermediate rail which typically supplies
VDD_BUCK and VDD_BST. Bypass to ground with a 4.7uF ceramic
capacitor.
A3, A4
Input of the buck converter. Bypass to PGND_BUCK with a
minimum 2.2uF ceramic capacitor.
A5
A6
A7
VDD_BUCK
SW_BUCK
POWER
POWER
Buck switching node. Connect to the buck inductor.
Power ground for the buck. Connect to the buck input capacitor and
ground plane.
PGND_BUCK POWER
Battery connection. Connect to the positive terminal of the battery.
Bypass to ground with a minimum 1uF ceramic capacitor.
B1,B2
B3
VBAT
POWER
AO
IMON
Battery discharge current monitor output
Battery Pack NTC monitor. Connect to a resistive network and
thermistor.
B4
TEMP_SNS
AI
Open drain status output. Connect to VDDIO through a 1K to
100KOhm pull-up resistor.
B5
SYS_FLT
DOD
I2C Interface Data. Connect SDA to VDDIO through a 2k to10k pull-
up resistor.
B6
B7
C1
SDA
DIO
AI
FB_BUCK
VBAT_SNS
Buck output voltage feedback connection.
Battery voltage sense connection. Connect to the positive battery
terminal.
AI
Termination current setting pin. Connect a resistor between
ITER_CHG and ground to set the pre-charge and termination
currents (ITER). Alternatively, short this pin to ground to allow ITER
to be programmed by register setting.
C2
C3
ITER_CHG
ILIM_CHG
AI
AI
Fast-Charge current setting pin. Connect a resistor between
ILIM_CHG and ground to set the fast-charge current (ICHG).
Alternatively, short this pin to ground to allow ICHG to be
programmed by register setting
Watchdog input. Toggle WD within the watchdog time-out period to
avoid power reset.
C4
C5
C6
WD
DI
DI
DI
Manual reset input pin. RIN_N is internally pulled high. Pulling this
pin low wakes the device from Ship Mode or performs a reset.
RIN_N
SCL
I2C interface clock. Connect SCL to VDDIO through a 2k to10k pull-
up resistor.
C7
D1
AGND
GND
Quiet ground connection. Connect to a quiet ground area.
VDD_BST
POWER
Input for Boost FET driver. Bypass with a minimum 1uF capacitance.
Input current limit setting pin. Connect a resistor between ILIM_PWR
and ground to set the VDD_PWR current limit (ILIM). Alternatively,
short this pin to ground to allow ILIM to be programmed by register.
D2
ILIM_PWR
AI
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DA9070
Ultra-Low Quiescent Current PMIC
Type
(Table 2)
Pin No. Pin Name
Description
D4
D5
VBAT_DIV
MODE
AO
Battery voltage divider, positive output
Mode control input pin. MODE is internally pulled low. If VDD_PWR
is powered, driving MODE high disables charging. If VDD_PWR is
unpowered, driving MODE low enables Hi-Z mode.
DI
Reset output pin. Connect this open-drain output to VDDIO through
a 1k to 100k ohm pull-up resistor.
D6
D7
E1
ROUT_N
DOD
DOD
POWER
Power status indicator output. Connect this open-drain output to
VDDIO through a 1K to 100KOhm pull-up resistor. PWR_FLT pulls
low when VDD_PWR is plugged into a valid power source.
PWR_FLT
PGND_BST
Power ground for the boost regulator. Connect to the boost output
capacitors and ground plane.
E2
E3
E4
VTEMP
VDDIO
AO
Switched VDD_SYS supply for battery temp sense resistor divider
IO voltage
POWER
AO
GND_DIV
Battery voltage divider, ground reference.
Input to Load Switch / LDO 2. Bypass to ground with a minimum 1uF
ceramic capacitor.
E5
E6
E7
VDD_LDO2
VDD_LDO1
VDD_LDO0
POWER
POWER
POWER
Input to Load Switch / LDO 1. Bypass to ground with a minimum 1uF
ceramic capacitor.
Input to Load Switch / LDO 0. Bypass to ground with a minimum 1uF
ceramic capacitor.
F1
F2
F3
SW_BST
VOUT_BST
FB_BST
POWER
POWER
AI
The boost switching node. Connect to the boost inductor.
Output of the boost converter. Bypass with a minimum of 10uF.
Boost output voltage feedback connection.
Load Switch or LDO2 output. Bypass to ground with a minimum 1uF
ceramic capacitor.
F5
F6
F7
VLDO2
VLDO1
VLDO0
POWER
POWER
POWER
Load Switch or LDO1 output. Bypass to ground with a minimum 1uF
ceramic capacitor.
Load Switch or LDO0 output. Bypass to ground with a minimum 1uF
ceramic capacitor.
Table 2: Pin Type Definition
Pin Type
DI
Description
Digital input
GND
DIO
Ground
Digital input/output
Digital output open drain
Power
DOD
POWER
AI
Analog input
Analog output
AO
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3
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specification are not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Table 3: Absolute Maximum Ratings
Parameter
TS
Description
Storage temperature
VDD_PWR
Conditions
Min
-65
Max
150
22
Unit
°C
VPWR
1V/ µsec max slew rate
-0.3
V
VBAT
VSYS
VBAT, VBAT_SNS
-0.3
-0.3
6
6
V
V
VDD_SYS, VDD_BUCK,
SW_BUCK, VDD_BST,
VDD_LDOx, VTEMP
VIO
VDDIO and all IO pins
(unless otherwise stated)
Note 1
-0.3
-0.3
6
V
V
VBST
SW_BST, VOUT_BST,
FB_BST
22
Note 1 VDDIO and IO voltages must be less than the higher of VBAT or VDD_PWR.
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Ultra-Low Quiescent Current PMIC
4
Recommended Operating Conditions
Recommended operating conditions are conditions for which the device is intended to be functional,
but parameter specifications may not be guaranteed. For guaranteed specifications and associated
test conditions, refer to the Electrical Characteristics tables.
Table 4: Recommended Operating Conditions
Parameter
Description
Conditions
Min
Typ
Max
Unit
TA
Operating Ambient
Temperature
-40
85
C
VDD_PWR
VDD_PWR voltage
Including OVP range
3.6
3.6
5
5
20
V
V
VDD_PWR operating
voltage
5.5
VBAT
Battery voltage
VDD_PWR supplied
VDD_PWR not supplied
Load switch mode
LDO mode
0
3.7
3.7
4.7
4.7
5.5
5.5
3.3
V
V
V
V
V
Battery voltage (act.bat)
VDD_LDO voltage
2.5
0.8
1.8
1.4
VDD_LDO
VDDIO
IO voltage
VDDIO < VDD_PWR or
1.8
VBAT, whichever is greater
VDD_BST
Boost input voltage
2.5
2.5
5.5
5.5
V
V
VDD_BUCK Buck input voltage
Note 1
Note 1 VDD_BUCK must be greater than Buck output voltage+600mV.
Table 5: Recommended External Components
Component values shown are typical values (not de-rated). For capacitors assume X5R type or better with a DC
voltage rating of 2x the maximum applied voltage. For inductors, the saturation current rating is equal or greater
than the current limit value. The Electrical Specifications are based on the typical values where applicable.
Parameter
C_VDD_SYS
C_VDD_PWR
C_VBAT
Description
Conditions
Min
3.3
1.0
1.0
Typ
4.7
4.7
2.2
10
Max
100
10
Unit
µF
µF
µF
µF
µF
µH
µF
µF
VDD_SYS capacitance
VDD_PWR capacitance
VBAT capacitance
Buck output capacitance
Buck input capacitance
Buck inductor
10
C_VO_BUCK
C_VDD_BUCK
L_BUCK
1.0
2.2
2.2
10
C_VO_BOOST
Boost output cap.
1MHz
4.7
1.0
VDD_BST connected to
VDD_SYS
1.0
C_VDD_BOOST
Boost input capacitance
VDD_BST powered by
independent supply
10
µF
L_BOOST
Boost inductor
4.7
2.2
1.0
µH
µF
µF
C_VO_LDO
C_VDD_LDO
LDO output capacitance
LDO input capacitance
1.0
2.2
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5
ESD Ratings
Parameter
Description
Conditions
Value
Unit
VESD
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001
±2000
V
Note 1
Charged device model (CDM), per ±500
ANSI/ESDA/JEDEC JS-002
Note 2
Note 1 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD
control process.
Note 2 JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD
control process.
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6
Electrical Characteristics
Electrical characteristics table limits are guaranteed by production testing, design, or correlation
using standard statistical quality control methods unless otherwise stated. Typical (Typ)
specifications are mean or average values 25 °C and are not guaranteed.
Unless otherwise noted, VBAT=3.7V, VDD_SYS=3.7V, VDD_PWR=5.0V, VDDIO=1.8V, TA=-40C to
85C.
6.1 Battery Charger
Table 6: Battery Charger
Parameter Description
Conditions
Min
Typ
Max
Unit
Electrical Performance
VDD_SYS_THR VDD_SYS DPPM voltage
VDD_SYS falling, above
VBAT_CHG
0.2
300
120
V
threshold
_DPPM
battery charger MOSFET on- Measured from VBAT to
resistance
RON_CHG_INT
400
160
mΩ
mV
VVDD_SYS
VDROP_BAT_T
O_VDD_SYS
VBAT > 3 V, IBAT discharge =
400 mA
VVBAT - VVDD_SYS
VDD_
SYS <
VBAT
Threshold to enter the
battery supplement mode
VBAT_SUP
VVBAT > VVBAT_UVLO
V
A
IBAT_DCHG_RN Discharge current limit
Selectable 0.2A / step
0.55
3.6
1.75
4.65
0.5
setting range
G
Operating in voltage
regulation, programmable
range in 10mV steps
VBAT_CHG
Charge voltage range
V
VBAT_CHG_AC
C
Charge voltage accuracy
0°C< TJ < 85°C
-0.5
%
ICHG
Fast charge current range
2
500
5
mA
%
ICHG_ACC
Fast charge current accuracy
-5
Termination current
programmable range
maximum over I2C.
Termination and pre-charge
current setting range
ITER_RNG
0.5
-10
50
10
mA
Termination charge current
accuracy
Peak current below
termination threshold
ITER_ACC
%
ms
V
tTER_DEGLITCH Termination deglitch time
Charge current falling
64
VTHR_PRE_TO Pre charge to fast charge
2.7
3.2
threshold voltage range
_FASTCHG
ICHG_PRE_ACC Pre-charge current accuracy VBAT > 2V
-10
10
%
VRCHG
Recharge threshold voltage
VBAT below VBAT_CHG
100
120
140
mV
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Parameter Description
Conditions
Min
Typ
Max
Unit
tRCHG_DEGLIT Recharge threshold deglitch
tFALL = 100 ns typ, VRCHG
falling
32
ms
time
CH
6.2 Battery Temperature Monitor
Table 7: Battery Temperature Monitor
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
% of VVDD_SYS,
VTEMP_SNS falling
VTEMP_HI
High temperature threshold
14.5
20.1
34.4
39.3
55
15
20.5
35
15.2
20.8
35.4
40.2
60
%
%
% of VVDD_SYS,
VTEMP_SNS falling
VTEMP_WARM Warm threshold
% of VVDD_SYS,
VTEMP_SNS rising
VTEMP_COOL
Cool threshold
%
% of VVDD_SYS,
VTEMP_SNS rising
VTEMP_LO
Low temperature threshold
39.8
%
VOFF_TEMP_S TEMP_SNS disable
NS
% of VVDD_SYSfor rising
VTEMP_SNS
%
threshold
tTEMP_SNS_DE
TEMP_SNS deglitch time
GLITCH
TEMP_SNS at any threshold
10
ms
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6.3 LDO / Load Switches
Table 8: LDO0/Loadswitch (LV)
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
Input voltage range for
LDSW
Load Switch mode VVDD_LDO
> VVLDO
VIN_LDSW_0
VIN_LDO_0
0.8
1.8
-3
5.5
5.5
3
V
V
Input voltage range for LDO
LDO mode, VVDD_LDO > VVLDO
VVDD_LDO > VVLDO + 0.2V
VOUT_ACC_LO
_0
DC output accuracy
Output range
%
Programmable range, 50mV
or 75mV steps
VOUT_LDO_0
VOUT_LINE_0
VOUT_LD_0
0.8
-0.8
-3
3.15
0.8
0
V
%
%
1.8V < VVDD_LDO < 5.5V
IOUT=500uA
DC line regulation
DC load regulation
0< IOUT < 50 mA, VVDD_LDO
=1.85V VVLDO =1.8V
2u to 50 mA, 100mA/usec,
VVDD_LDO >2.0V
VVLDO=1.8V
VOUT_TR2_LD_
0
Load transient
-120
-140
60
60
mV
mV
2u to 50 mA, 100mA/usec,
VVDD_LDO =1.85V
VVLDO=1.8V
VOUT_TR_LD_0 Load transient
RON_LDSW_ILI On resistance of LDSW
VVDD_LDO = 3.7V
0.7
0.11
32
Ω
Ω
mode with current limit
M_0
RON_LDSW_N On resistance of LDSW
VVDD_LDO = 3.7V
mode without current limit
O_ILIM_0
RDCHG_LDO_O MOSFET on-resistance for
ILOAD = -10 mA
Ω
LDO discharge
N_0
ILIM_OUT_LDO_ Output current limit for LDO
VLDO = 0.9 x VLDO(nom)
VVDD_LDO =1.85V VLDO = 1.8V
155
mA
mA
mA
mode
0
IOUT_LDO_LO_
0
Output current
50
VVDD_LDO > VVLDO + 0.2V
VVLDO = 1.8 V
IOUT_LDO_HI_0 Output current
150
IIN_LDO_ON_0 Quiescent current
LDO mode
0.75
μA
μA
IIN_LDO_OFF_0 OFF-state supply current
0.001
PSRR_vddldo
_0
Power supply rejection ratio
@10KHz, IOUT=75mA
43
20
dB
ms
tSTART_LDO0
LDO start-up delay time
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Table 9: LDO1/Loadswitch
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
Input voltage range for Load
Switch
Load Switch mode VVDD_LDO
> VVLDO
VIN_LDSW_1
VIN_LDO_1
0.8
1.8
-3
5.5
5.5
3
V
V
Input voltage range for LDO
LDO mode, VVDD_LDO > VVLDO
VVDD_LDO > VVLDO + 0.2V
VOUT_ACC_LO
_1
DC output accuracy
Output range
%
Programmable range, 50mV
or 75mV steps
VOUT_LDO_1
0.8
3.3
0.8
V
1.8V < VVDD_LDO < 5.5V
IOUT=500uA
VOUT_LINE_1
DC line regulation
-0.8
%
2uA < IOUT < 100 mA,
VVDD_LDO > VVOUT_LDO + 0.2V,
VVLDO=3.0V
VOUT_LD_1
DC load regulation
-3
0
%
2uA to 100 mA, 100mA/usec,
VVDD_LDO > VVLDO +
0.2V, VVLDO=3.0V
VOUT_TR_LD_1 Load transient
-120
60
mV
RON_LDSW_ILI On resistance of LDSW
VVDD_LDO = 3.7V
VVDD_LDO = 3.7V
ILOAD = -10 mA
1.5
0.27
32
Ω
Ω
mode with current limit
M_1
RON_LDSW_N On resistance of LDSW
mode without current limit
O_ILIM_1
RDCHG_LDO_O MOSFET on-resistance for
Ω
LDO discharge
N_1
ILIM_OUT_LDO_ Output current limit (LDO
VLDO = 0.9 x VLDO(nom)
155
mA
mA
MODE)
1
IOUT_LDO_HI1_
1
Output current
VVDD_LDO > VVLDO + 0.2V
LDO mode
150
IIN_LDO_ON_1 Quiescent current
0.8
μA
μA
IIN_LDO_OFF_1 OFF-state supply current
0.001
PSRR_vddldo
_1
Power supply rejection ratio
@10KHz, IOUT=75mA
40
20
dB
ms
tSTART_LDO1
LDO start-up delay time
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Table 10: LDO2/Loadswitch
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
Input voltage range for Load
Switch
Load Switch mode, VVDD_LDO
> VVLDO
VIN_LDSW_2
VIN_LDO_2
0.8
1.8
-3
5.5
5.5
3
V
V
Input voltage range for LDO
LDO mode, VVDD_LDO > VVLDO
VVDD_LDO > VVLDO + 0.2V
VOUT_ACC_LO
_2
DC output accuracy
Output range for LDO
DC line regulation
%
Programmable range, 50mV
or 75mV steps
VOUT_LDO_2
0.8
3.3
0.8
V
1.8V < VVDD_LDO < 5.5V
IOUT=500uA
VOUT_LINE_2
-0.8
%
2uA < IOUT < 100 mA,
VVDD_LDO > VVOUT_LDO + 0.2V,
VVLDO=3.0V
VOUT_LD_2
DC load regulation
-3
0
%
2uA to 100 mA, 100mA/usec,
VVDD_LDO > VVLDO +
0.2V, VVLDO=3.0V
VOUT_TR_LD_2 Load transient
-120
60
mV
RON_LDSW_ILI On resistance of LDSW
VVDD_LDO = 3.7V
VVDD_LDO = 3.7V
ILOAD = -10 mA
1.5
0.27
32
Ω
Ω
mode with current limit
M_2
RON_LDSW_N On resistance of LDSW
mode without current limit
O_ILIM_2
RDCHG_LDO_O MOSFET on-resistance for
Ω
LDO discharge
N_2
ILIM_OUT_LDO_ Output current limit (LDO
VLDO = 0.9 x VLDO(nom)
155
mA
mA
MODE)
2
IOUT_LDO_HI1_
2
Output current
VVDD_LDO > VVLDO + 0.2V
LDO mode
150
IIN_LDO_ON_2 Quiescent current
0.8
μA
μA
IIN_LDO_OFF_2 OFF-state supply current
0.001
PSRR_vddldo
_@
Power supply rejection ratio
@10KHz, IOUT=75mA
35
20
dB
ms
tSTART_LDO2
LDO start-up delay time
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6.4 Digital Inputs (MODE and WD)
Table 11: Digital Input Pins (MODE,WD)
Parameter Description
Conditions
Min
Typ
Max
Unit
External Electrical Conditions
WD minimum input pulse
width
tMIN_WD
25
μs
Electrical Performance
0.25*V
DDIO
VIN_LO
Input low threshold
V
0.75*V
DDIO
VIN_HI
Input high threshold
V
RPD_MODE
Internal pull-down resistance
MODE pin deglitch time
900
100
kΩ
μs
t_DEGLITCH_M
ODE
rising/falling
6.5 I2C Interface
Table 12: I2C Interface
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
fI2C_CLK
SCL frequency range
100
400
kHz
V
VDDI
O*0.25
VOUT_LO
Output low threshold level
Input low threshold level
SDA 5mA sink current
Input low threshold level for
SDA and SCL
VDDI
O*0.25
VIN_LO
V
Input high threshold level for
SDA and SCL
VDDI
O*0.75
VIN_HI
Input high threshold level
leakage current
V
ILKG_HILVL
SDA and SCL, high level
1
μA
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6.6 Input Currents
Table 13: Input Currents
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
0 °C < TJ < 60 °C, VVDD_PWR
0V or floating, Hi-Z mode,
Buck switching, no load
=
IBAT_HIZ_BUCK Battery discharge current in
0.8
1.6
1.5
μA
μA
Hiz mode, no LDO enable
_ON_LDO_OFF
0 °C < TJ < 60 °C, VVDD_PWR
= 0V, Hi-Z mode, Buck
switching, LDO_0 enabled,
No load
IBAT_HIZ_BUCK Battery discharge current in
Hiz mode, LDO_0 enable
_ON_LDO0_ON
0 °C < TJ < 85 °C, VVDD_PWR
= 0V, Active battery mode,
Buck switching, LDO_0 +
IBAT_ACT_LDO Battery discharge current in
2.5
1.1
μA
μA
Active battery mode
0_LDO1_ON
LDO_1 enabled, I2C enabled,
VBAT_UVLO < VBAT < 4.65 V
0 °C < TJ < 85 °C, VVDD_PWR
< VVDD_PWR_UVLO, Active
battery mode, Buck
IBAT_ACT_BUC Battery discharge current in
Active battery mode
switching, LDO disabled, I2C
enabled, MODE = low,
VBAT_UVLO < VBAT < 4.65 V
K_ON_LDO_OFF
Battery discharge current in
ship mode
0 °C < TJ < 85 °C, VVDD_PWR
= 0V, Ship mode
IBAT_SHIP
2
200
3
nA
mA
mA
VVDDPWR_UVLO < VVDD_PWR
<
VOVP and VVDD_PWR > VVBAT
VSLP
+
IIN_BUCK_ON
Supply Current for control
Supply Current for control
0.8
Buck switching,
IIN_CHG_READ
Y
0 °C < TJ < 85 °C, VVDD_PWR
= 5 V, Charge ready
1.5
6.7 Power-Path Management and Current Limit
Table 14: Power-Path Management and ILIM
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
Input current in USB
suspend mode
IUSBSUSPEND
2.5
mA
mV
mA
VDROP_IN_TO_
VDD_SYS
VVDD_PWR = 5 V, IIN = 300 mA,
includes ball resistance
VDD_PWR - VVDD_SYS
125
600
170
IDDPWR_LIM_M
AX
Programmable Range MAX,
50-mA steps
Input Current limit
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Ultra-Low Quiescent Current PMIC
Parameter Description
Conditions
Min
Typ
Max
Unit
IDDPWR_LIM_M
IN
Programmable Range MIN,
50-mA steps
Input Current limit
50
mA
IDDPWR_LIM_A
CC_RNG_LO
Current limit accuracy
Current limit accuracy
50 mA to 100 mA
100 mA to 600 mA
-12
-5
12
5
%
%
IDDPWR_LIM_A
CC_RNG_HI
At VDD_PWR,
programmable range, 100mV
steps
VDDPWR_IIN_D
WN
DPM threshold
4.2
-3
4.9
3
V
VDDPWR_IIN_D
WN_ACC
DPM threshold accuracy
%
6.8 Protection
Table 15: Protection
Parameter Description
Electrical Performance
VBAT_SHRT_T
Conditions
Min
Typ
Max
Unit
Battery voltage falling,
VDD_PWR=5V
Battery short circuit threshold
2
V
mV
mA
V
HR
VBAT_SHRT_H
YS
Hysteresis for VBAT_SHRT
100
ITER
Battery short circuit charge
current
IBAT_SHRT
VBAT_UVLO_T Battery under-voltage lockout Programmable range,
2.5
-3
3
3
threshold range
100mV steps VBAT falling
HR
VBAT_UVLO_A Default battery under-voltage
VBAT_UVLO=2.5V
%
lockout accuracy
CC
VBAT_UVLO_H Battery under-voltage lockout
200
5.55
100
32
mV
V
threshold hysteresis
YS
VDD_PWR over voltage
VDDPWR_OVP
VVDD_PWR rising
5.35
5.75
protection threshold voltage
VDDPWR_OVP_ Over voltage protection
mV
ms
hysteresis
HYS
tDEGLITCH_OV Over voltage protection
VVDD_PWR falling
recovery deglitch time
P
VVDD_PWR - VBAT ,
VDD_PWR falling
VSLP
Sleep entry threshold
Sleep-mode hysteresis
65
120
200
mV
mV
VSLP_HYS
VVDD_PWR rising
80
130
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Parameter Description
TSHDN Thermal shutdown
THYS
Conditions
Min
Typ
118
20
Max
Unit
°C
TJ
Thermal shutdown hysteresis TJ
°C
tDEGLITCH_TH_ Thermal shutdown deglitch
TJ rising
1
ms
mV
V
time
SHDN
VDDPWR_UVL VDD_PWR under-voltage
VVDD_PWR falling
VVDD_PWR rising
150
3.6
lockout threshold hysteresis
O_HYS
VDDPWR_UVL VDD_PWR under-voltage
3.4
3.8
lockout threshold
O_THR
6.9 Pushbutton Timer (RIN_N)
Table 16: Pushbutton Timer(RIN_N)
Parameter Description
Conditions
Min
Typ
Max
Unit
Electrical Performance
VRIN_N_LOLVL Low-level input voltage
0.3
V
RPU_RIN_N
Internal pull-up resistance
120
kΩ
6.10 Digital Outputs (SYS_FLT, PWR_FLT, and ROUT_N)
Table 17: Digital Output Pins (SYS_FLT, PWR_FLT, and ROUT_N)
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
0.25*V
DDIO
VOUT_LO
Low level output threshold
Sinking current = 5 mA
V
ILKG_TO_IN
tINTR
Leakage current into pin
Interrupt pulse width
Reset pulse duration
High impedance state
SYS_FLT
0
12
nA
μs
128
400
tRST_D
ROUT_N
ms
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6.11 Buck Regulator
Table 18: Buck
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
RON_PMOS
RON_NMOS
High-side on resistance
600
300
800
450
mΩ
mΩ
Low-side on resistance
Start-up delay time
From BUCK_EN =1 to
switching
tSTART
3
ms
ILIM_SW_PMOS SW current limit PMOS
VFB_BUCK=1.8V
600
270
mA
ns
tOFF_BUCK
fSW_BUCK
Off time
VFB_BUCK=1.8V
Switching frequency
Continuous conduction mode
3
MHz
ILIM_PMOS_SO PMOS switch current limit
300
mA
V
during softstart
FTSTART
Programmable range, 50 mV
steps (VOUT_FB_BUCK_HI > 1.9V,
VVDD_BUCK>2.7V)
VOUT_FB_BUC
K
Buck output voltage range
0.6
2.1
VOUT_FB_BUC
K_HI
HI programmable range, 50
mV steps, VOUT_RANGE_HI = 1
Buck output voltage range
1.3
0.6
2.1
1.3
V
V
VOUT_FB_BUC
K_LO
LO programmable range, 50
mV steps, VOUT_RANGE_HI = 0
Buck output voltage range
VVDD_BUCK = 5 V, PFM mode,
IOUT = 10 mA, VFB_BUCK = 1.8
V
VOUT_VBUCK_ Buck output voltage
-2.5
0
2.5
%
accuracy
OUT_ACC
VOUT = 1.8 V
VOUT_LD1_BU DC output voltage load
0.01
0.02
%/mA
%/mA
regulation
CK
100 mA < IOUT < 300 mA
VOUT = 0.9 V
VOUT_LD2_BU DC output voltage load
regulation
CK
100 mA < IOUT < 300 mA
VOUT_LINE_BU DC output voltage line
VOUT = 1.8 V IOUT = 100 mA
Vout=1.8V, no load
0.1
50
%/V
regulation
CK
tSTARTUP_BUC
Softstart time
K
μs
VOUT = 0.9 V
No load
tSTARTUP_L
Softstart time
25
μs
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6.12 Boost Regulator
Table 19: Boost
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
VVBAT=3.7 V, COUT=2.2 uF,
VBST_OUT=12 V
tSTARTUP
Startup time
2
5
1
ms
nA
V
VVDD_BST=4.65 V Boost
disabled
IQ_SHDN
Quiescent current
100
18
9
Output voltage range, 250
mV step size
VOUT_BST_HI
9
12
Output voltage range, 125
mV step size
VOUT_BST_LO
4.5
V
SCP threthhold for higher
Vout range
VSCP_HI
VOUT_BST=9V to 18V
VOUT_BST=4.5V to 9V
4
2.38
2
V
V
V
VBST_UVLO
VSCP_LO
Boost UVLO
SCP threthhold for lower
Vout range
Referenced to nominal
VOUT_BST setting
VOVP
OVP threshhold
OVP threshhold
120
100
%
%
Referenced to nominal
VOUT_BST setting
VOVP_RLS
VOUT_ACC
RON_SHDN
Boost output voltage
accuracy
VVDD_BST = 3.7 V, VBST_OUT
12 V ,IOUT=10mA
=
-2.5
2.5
%
True shutdown, RDSon
resistance
100
300
200
mΩ
RON_LS
ILIM_POS
Low side, RDSon resistance
Peak current limit
mΩ
A
Programmable range
Programmable range
0.9
-30
2.1
30
ILIM_POS_ACC Peak current limit accuracy
%
ILIM_SOFTSTAR
T
Softstart current limit
0.51
0.95
1.9
0.92
1.05
2.1
A
Typical value depends on
OTP setting. 1MHz
fSW_BST_1M
Switching frequency
Switching frequency
1
2
MHz
MHz
Typical value depends on
OTP setting. 2MHz
fSW_BST_2M
tON_BST
Minimum on time
Minimum off time
105
100
ns
ns
tOFF_BST
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Parameter Description
Conditions
Min
Typ
0.0015
0.2
Max
Unit
%/mA
%/V
VOUT = 12 V 1mA < Iload <
100mA
VOUT_LD
Boost load reg
Boost line reg
VOUT_LINE
VOUT = 12 V Iload=10mA
6.13 Battery Monitors (VBAT_DIV and IMON)
Table 20: Battery Monitors (VBAT_DIV and IMON)
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
AIMON_GAIN
IIMON
IMON current gain
1
mA/A
VBAT IQ current increase
with IMON enabled
0A discharge current
4
μA
Discharge current range
100mA to 1A
IMON_ACC_HI
IMON accuracy
-20
-40
1.4
20
40
%
%
V
Discharge current range
10mA to 100mA
IMON_ACC_LO IMON accuracy
IMON maximum
VIMON_MAX
2.5V <VVBAT< 4.7V Imon x
Rimon
recommended voltage
From VBAT_SNS to
GND_DIV
RBAT_DIV
Voltage divider resistance
Voltage
150
kΩ
V
2.5V < VVBAT < 4.65V 0°C <
Tj <85°C
VBAT* VBAT* VBAT*
0.585 0.6 0.615
VBAT_DIV1
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7
Thermal Characteristics
Table 21: Thermal Characteristics
Parameter Description
Conditions
Min
Typ
Max
Unit
Junction-to-ambient
RTH_JA_A
JEDEC 8-layer pcb, no
airflow
34
°C/W
thermal resistance
Junction-to-case (top)
RPSI_JC
0.5
10
79
°C/W
°C/W
°C/W
JT
thermal resistance
Junction-to-board thermal
resistance
RTH_JB
1mm from IC edge
Junction-to-ambient
RTH_JA_B
25mm x 25mm pcb, 8-layer,
no airflow
thermal resistance
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8
Typical Performance
Unless otherwise noted, VBAT = 3.6 V, T A =25 °C
Figure 3: Buck Efficiency, VOUT = 1.8 V
Figure 5: Buck Efficiency, VOUT = 0.9 V
Figure 6: Buck Regulation, VOUT = 1.8 V
Figure 4: Boost Efficiency, VOUT = 12 V,
VIN = VDD_BST
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Figure 9: Boost Efficiency, VOUT = 12 V,
VIN = VBAT
Figure 7: Buck Regulation, VOU = 0.9 V
Figure 10: Boost Efficiency, VOUT = 5 V,
VIN = VBAT
Figure 8: Boost Efficiency, VOUT = 5 V,
VIN = VDD_BST
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Figure 11: Boost Regulation, VOUT = 12 V
Figure 13: Boost Maximum Load Current
Capability
Figure 14: LDO_0 Dropout, VIN = 3.15 V,
VOUT Setting = 3.15 V
Figure 12: Boost Regulation, VOUT = 5 V
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Figure 15: LDO_1 and LDO_2 Dropout,
VIN = 3.3 V, VOUT Setting = 3.3 V
Figure 17: LDO_0 Regulation and Dropout,
VOUT = 3.15 V
Figure 16: LDO_0 Regulation and Dropout,
VOUT = 1.80 V
Figure 18: LDO_1 Regulation and Dropout,
VOUT = 3.30 V
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Figure 19: LDO_1 Regulation and Dropout,
VOUT = 1.80 V
Figure 21: LDO_2 Regulation and Dropout,
VOUT = 1.80 V
Figure 22: Typical Buck Startup,
VBAT = 3.6 V, VBUCK = 1.8 V and 0.9 V, 0 A
Figure 20: LDO2 Load Regulation,
VOUT = 3.30 V
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Figure 23: Typical Boost Startup,
VDD_BST = 3.6 V, VOUT = 5 V and 12 V, 0 A
Figure 25: VBAT IQ, Ship Mode
Figure 26: VDD_LDO IQ, no load
Figure 24: VBAT IQ, Buck Switching, no
load, Hi-Z mode
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Figure 27: Charger Efficiency, VDD_PWR = 5 V
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9
Functional Description
9.1 Overview
In a typical application, the DA9070 manages to two power inputs: a battery at VBAT and a USB
supply at VDD_PWR. The larger of these supplies feeds the unregulated system output voltage at
VDD_SYS. VDD_SYS in turn is used as the input supply to the linear charger, buck, boost, and
LDOs. Due to its extremely low IQ (<1uA), the buck can remain always on as the primary system
power rail without draining the battery excessively.
When USB power is present, VDD_SYS will be near 5V and the linear charger is active. When USB
power in not connected, VDD_SYS will track the battery voltage. Battery discharge current can be
monitored using the IMON pin. The DA9070 actively manages this power path, reducing charging
current and input current as necessary, and allowing VDD_SYS to draw current from both supplies
during peak loads.
The DA9070 includes multiple configurable protection features including battery and input over-
current. All settings can be controlled by I2C , but stand-alone operation is also possible with features
such as a pushbutton input timer, resistor programmable charge settings, and the MODE pin to
enable and disable charging.
As there are two input sources, the DA9070 has multiple regions of operation, illustrated below in
Figure 28.
VDD_PWR
20V
OVP
5.5V
ACTIVE POWER / CHARGING
SLEEP
VDD_PWR
UVLO (3.4V)
UVLO
ACTIVE BATTERY,
HiZ, or SHIP
POR
VBAT
4.65V
VBAT_UVLO
(2.0V-3.0V)
Figure 28: Regions of Operation
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9.2 Battery-Powered Operation
When the power source is unplugged (VDD_PWR < UVLO ), the DA9070 is battery-powered
provided that VBAT exceeds VBAT_UVLO (register 0x0E) In this condition, the device will be in one
of three modes: Ship mode, Active battery mode, or High Impedance mode (Hi-Z).
9.2.1
Ship Mode
Ship mode is an ultra low leakage standby state that minimizes battery depletion while the product
sits on the shelf. Typical battery current in ship mode is 5nA.
There are two methods to enter Ship mode:
1. By Register Write
a. VDD_PWR disconnected
b. MODE pin high
c. Enter Ship mode by setting EN_SHIPMODE bit high: 0x0D [0] = 1
d. The IC enters Ship mode immediately
(If VDD_PWR is plugged in, Ship mode entry is delayed until power is removed)
2. By Pushbutton Timer pin, RIN_N
a. VDD_PWR disconnected
b. MODE pin high
c. Enable RIN_N control of ship mode: 0x10 [1:0] = 0x01
d. Pull RIN_N low for longer than the reset period: RIN_N_PER_RST (0x10 [7:6])
e. The IC enters Ship mode when RIN_N is released (internally pulled up)
To exit Ship mode, apply VDD_PWR or toggle RIN_N low for longer than 50msec. Upon waking from
Ship mode, all pre-programmed OTP values are loaded.
9.2.2
Active Battery and High Impedance Modes
Under battery power there are two modes of operation, controlled by the MODE pin. A rising edge on
MODE puts the DA9070 in Active Battery mode. In this mode, all functions are active.
Conversely, a falling edge on MODE puts the DA9070 into Hi-Z mode, intended to be used during
system standby states with low power consumption. In this mode, the following communication
functions are placed in a high impedance mode to reduce leakage from the battery: I2C interface, the
SYS_FLT and PWR_FLT status outputs, and watchdog timer (WD).
All other functions and outputs remain active, with the exception of TSD.
Caution: The Thermal Shutdown function is not active in Hi-Z mode. Hi-Z mode should not be used in
high power dissipation or heavy load conditions.
Hi-Z mode can also be entered by setting the HZ_MODE bit to 1 (0x0D [1]); or by using RIN_N
pushbutton by setting 0x10 [1:0] to 2 and pulling RIN_N low for more than the RIN_N reset time
(0x10 [7:6]).
The DA9070 exits Hi-Z mode at a MODE pin rising edge or when VDD_PWR is applied. When
VDD_PWR is removed, the part will enter Active Battery mode regardless of the MODE pin state.
The behaviour of the MODE pin depends on whether VDD_PWR is connected, shown in Table 22.
The MODE pin is internally pulled low.
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Table 22: MODE Functionality
VDD_PWR
Disconnected
Connected
MODE = 0
MODE = 1
Hi-Z mode (edge triggered)
Active Battery mode
Charge disabled
Charge enabled if CE_N = 0
Charge disabled if CE_N = 1
9.2.3
Battery Protection
The DA9070 includes several types of battery protection. The battery is protected during discharge
by the IBAT_DCHG (over-current protection) and UVLO (over-discharge protection) functions. During
charging, the TEMP_SNS function protects against over-temperature, and highly accurate voltage
regulation and charging current prevent over-voltage and over-current conditions.
9.2.3.1
VBAT Over-Current Protection (OCP)
The battery discharge over-current protection threshold, IBAT_DCHG, is selectable from 0.55A to
1.75A at register 0x29 [4:2]. Over-current protection clamps the maximum battery current at the set
threshold and is available in all modes of operation. Battery current will begin to be limited
approximately 150mA below the protection clamp. When an over-current condition occurs during
charging, safety timers and charge termination are suspended.
In an over-current fault, a VBAT_OCP interrupt is generated at SYS_FLT and indicated by the event
bit 0x04:[2].
All battery current flows from VBAT to VDD_SYS. Therefore, the IBAT_DCHG threshold should be
set somewhat higher than the maximum expected system current from VDD_SYS. However, if the
threshold is set higher than the battery can support, battery voltage may drop below VBAT_UVLO
before the current is limited. When the IBAT_DCHG function clamps the battery current, VDD_SYS
will droop. This may cause secondary fault conditions such as VDD_SYS UVLO.
9.2.3.2
VBAT_UVLO and SHORT
The battery under voltage protection threshold can be set from 2.5V to 3.0V at register 0x0E. This
should be set at or above the battery’s minimum discharge voltage specification. VBAT_UVLO
protects the battery from over-discharge by disconnecting the discharge path when the battery
voltage falls below the UVLO threshold.
When a VBAT_UVLO occurs in battery powered modes (VDD_PWR not connected), the DA9070
outputs, including VDD_SYS, will shut down and all registers will be reset to their default OTP
values.
VBAT_UVLO will generate an interrupt at SYS_FLT and will be indicated by the event bit at 0x04[0].
With VDD_PWR connected, VBAT_UVLO is ignored, making pre-charge level charging available
down to 0V at VBAT. In this case, a separate fault condition applies: VBAT_SHORT. The
VBAT_SHORT threshold is typically 2.0V and is indicated by event bit 0x04[3].
9.2.3.3
Battery Temperature Sensing
The temperature sense function uses the battery’s NTC thermistor to monitor battery temperature. If
the battery is too cold or hot, the fast charge current or target voltage is reduced, or charging is
terminated. Table 23 summarizes what protective measures are taken in each temperature range.
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Table 23: Battery Thermal Protection Measures
Temperature Range
Voltage at TEMP_SNS
Charger Action
Interrupt name
TBAT < TLO
VTEMP_SNS > VTEMP_LO_THR
Charging terminated
TS COLD
VTEMP_LO_THR > VTEMP_SNS
VTEMP_COOL_THR
>
Charge current = ½ x ICHG
setting
TCOLD < TBAT < TCOOL
TCOOL < TBAT < TWARM
TWARM < TBAT < THI
THI < TBAT
TS COOL
VTEMP_COOL_THR > VTEMP_SNS
> VTEMP_WARM_THR
Normal charging
VTEMP_WARM_THR
>
Target voltage (VBAT_CHG
reduced by 140mV
)
TS WARM
TS HOT
TS OFF
VTEMP_SNS > VTEMP_HI_THR
VTEMP_SNS < VTEMP_HI_THR
VTEMP_SNS > VOFF_TEMP_SNS
Charging terminated
Temp sense disabled,
Optional Fault
Setting the Resistor Divider
The four temperature thresholds are fixed percentages of VTEMP as shown in the Electrical
Characteristics table. VTEMP is enabled in short pulses to allow the battery temperature to be
monitored without drawing unnecessary current through the resistor divider. VTEMP is derived from
the VDD_SYS voltage. The TEMP_SNS voltage is measured after a deglitch time of 10msec, which
precludes any need for filtering at TEMP_SNS. To avoid measurement error, no filter capacitance
larger than 10nF should be added to TEMP_SNS pin.
Temperature monitoring can be disabled at the TS_EN register 0x26[1:0], or by pulling TEMP_SNS
above the VOFF_TEMP_SNS threshold (TS_OFF). The TS_OFF state disables temperature sensing, and
can optionally be flagged as a fault condition by setting register 0x26:[2] to 1. When TEMP_SNS is
pulled high to enter TS_OFF, the off state is latched until TEMP_SNS is disabled.
Temp sense is disabled in Hi-Z mode.
Each temp sense threshold will generate an interrupt at SYS_FLT and has an event bit at register
0x04 or 0x05.
The battery NTC interfaces to the TEMP_SNS input through a resistive divider, see Figure 29.
VTEMP
VBAT
RHI
TEMP_SNS
NTC
RLO
Figure 29: Battery Temperature Sensing with NTC
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The resistor divider values (RHI and RLO) are selected as shown below so that the cold and hot
TEMP_SNS thresholds are reached at the corresponding NTC values.
Equation 1:
1
1
푅(퐶푂퐿퐷) × 푅(퐻푂푇) × ꢀ
−
ꢁ
0.398 0.15
1
푅(퐿푂)
=
1
푅(퐻푂푇) × ꢀ
− 1ꢁ − 푅(퐶푂퐿퐷) × ꢀ
− 1ꢁ
0.15
0.398
Equation 2:
1
ꢀ
− 1ꢁ
1
0.398
푅(퐻퐼)
=
ꢂ
1
+
ꢃ
푅(퐿푂) 푅(퐶푂퐿퐷)
Where
●
●
R(HOT) = the NTC resistance at the hot temperature
R(COLD) = the NTC resistance at the cold temperature
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The cool and warm thresholds are not independently programmable and are fixed once the cold and
hot values are determined. The cool and warm thresholds can be determined by the NTC value at
the threshold:
Equation 3:
푅(퐿푂) × 푅(퐻퐼) × 0.35
푅(퐶푂푂퐿)
=
푅(퐿푂) − 푅(
× 0.35 − 푅(
× 0.35
)
)
퐿푂
퐻퐼
Equation 4:
푅(퐿푂) × 푅(퐻퐼) × 0.205
푅(퐿푂) − 푅( × 0.205 − 푅(
푅(푊퐴ꢄ푀)
=
× 0.205
)
)
퐿푂
퐻퐼
Where
●
●
R(COOL) = the NTC resistance at the cool temperature
R(WARM) = the NTC resistance at the warm temperature
Temp Sense Modes of Operation
The DA9070 provides two modes of battery temperature sense control: auto-mode and host control
mode. In auto-mode, the DA9070 enables the VTEMP voltage every 2 second or every 50msec
depending on the VDD_PWR state. At the start of each cycle, the VTEMP voltage is activated for
10ms after which the TEMP_SNS voltage is checked. This timing is shown in Figure 30.
Because auto-mode does not rely on the host to operate, it is ideally suited to provide continuous
safety monitoring.
In battery powered operation, VTEMP is enabled for only 0.5% of the time which reduces the typical
current required for temperature sensing to less than 1uA.
While VDD_PWR is applied, the Temp Sense function is in auto-mode and host control of the
VTEMP period is not available. This is illustrated in the Active Power section of Figure 30.
If lower current consumption is needed, temperature sensing can be controlled by the host. In host-
controlled mode, an I2C command activates the same 10msec VTEMP and TEMPS_SNS cycle.
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ACTIVE BATTERY (discharging)
2sec
2sec
Auto-mode Period
VTEMP active
10ms
10ms
TEMP_SNS active
TEMP_SNS
update
TEMP_SNS
update
ACTIVE POWER (charging)
50ms
50ms
Auto-mode Period
VTEMP active
10ms
10ms
TEMP_SNS active
TEMP_SNS
update
TEMP_SNS
update
Host Controlled Mode
I2C Trigger
VTEMP active
10ms
10ms
10ms
TEMP_SNS active
TEMP_SNS
update
TEMP_SNS
update
TEMP_SNS
update
Figure 30: Battery Temperature Sense Timing
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9.3 Analog Battery Monitor Functions
The DA9070 incorporates two features to support accurate fuel gauging: IMON and VBAT_DIV.
These provide analog discharge current and battery voltage information scaled for compatibility with
typical ADC inputs.
Filter capacitors on IMON and VBAT_DIV should not be used, or should be minimized, in order to
minimize any time lag when using these outputs for fuel gauging.
IMON
The battery discharge current monitor (IMON) sources a current proportional to the battery discharge
current at a 1mA/A scale. An external resistor from IMON to GND should be selected to optimize the
dynamic range based on battery current range and maximum tolerance of both the DA9070 and ADC
inputs. To maintain accuracy, a maximum voltage of 1.4V is allowed at the IMON pin.
IMON can be enabled and disabled at register 0x2A. When enabled, the function draws an additional
4uA of quiescent current from VBAT.
VBAT_DIV
The VBAT_DIV function divides down the kelvin sensed battery voltage (from VBAT_SNS) and
provides a selectable output scaled at 60% or 30% of VBAT. The dedicated ground at GND_DIV
should be used as the reference point for the VBAT_DIV output.
This is ideal for driving the differential input of an external ADC in battery monitoring functions.
VBAT_DIV can be enabled and disabled with the VBAT_DIV_EN register at 0x0F[0]. When enabled,
the total resistance from VBAT_SNS to GND is 150k. To maintain accuracy, a high impedance
connection is recommended at VBAT_DIV. When disabled the VBAT_DIV resistor divider is
disconnected from VBAT to eliminate current drain.
Table 24: VBAT_DIV Ratios
VBAT_DIV_SEL, 0x0E:[4]
VBAT_DIV Ratio
0.6×VBAT
0
1
0.3×VBAT
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9.4 Battery Charging
9.4.1
Battery Charging Process
When USB power is connected (VDD_PWR > VUVLO_THR), the DA9070 is in one of four states as
listed in Table 25. Charging is enabled and disabled with the MODE pin and CE_N register at
0x20:[0]. This status is indicated by the STS_CHG register 0x02:[5:4].
Table 25: Charge Status
MODE pin
CE_N
ICHG
VBAT
Status
STS_CHG
Register
0x20 [0]
Either High
N/A
> ITERM
< ITERM
N/A
N/A
<= VBAT_CHG
>= VRCHG
N/A
Charge ready
Charge in-progress
Charge done
Fault
0x0
0x1
0x2
0x3
L
L
L
L
L
L
STS_CHG is a read-only register which shows immediate charge status. The register does not hold
status value and changes its value immediately when the charge status changes.
From the charge ready state, charging begins when the CE_N bit is low and the MODE input is
pulled low. There is approximately 2.5msec delay between enabling charging and charge starting.
Charging current operates in three regions based on battery voltage: pre-charge, fast charge (CC),
and constant voltage (CV). These regions are shown in the typical charging example of Figu re 31.
The charge status (CHG_STS) is also shown transitioning from the ‘charge ready’ to ‘charge in-
progress’ to ‘charge done’ states.
Figu re 31: Example 70 mAh Charge Cycle
(V_Pre-charge = 3.0 V, I_Pre-charge = 7 mA, I_Charge = 70 mA, V_Term = 4.2 V)
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9.4.2
Charge In-Progress
Assuming a depleted battery, the battery is initially charged at ICHG_PRE until VBAT reaches the pre-
charge threshold, at which point the charge current is increased to ICHG. The charger continues to
charge at constant current (CC) until VBAT approaches the target voltage programmed by VBREG,
0x24:[6:0]. The battery is then charged at near constant voltage (CV) and the charge current
gradually falls. Charging ends when the charge current falls below ITER (ITER current is the same as
ICHG_PRE). If the VDD_PWR remains plugged in, recharging starts when VBAT falls below the
recharge threshold, VBAT_CHG - 120mV typically.
Charging modes are shown in Table 26.
Table 26: Charging Modes
VBAT Voltage
Charge Current
IPRE_CHG
Charge mode
Pre-charge
Pre-charge timer
Running
Main timer
Running
< VPRECHARGE
> VPRECHARGE
< VBAT_CHG
= VBAT_CHG
= VBAT_CHG
ICHG
CC (fast charge)
Reset
Running
< ICHG
CV
Reset
Reset
Running
Reset
=
Termination
ITERM
From the charge ready state, the device enters charge in-progress state when all conditions below
are met.
●
●
●
●
●
VVDD_PWR > VBAT + VSLP (not in sleep mode)
VBAT< Recharge threshold
RMEAS sequence completed, if enabled
50ms TEMP_SNS delay, if enabled
MODE input is pulled low and CE_N register is set to 0
If these conditions are met, charging starts automatically at the appropriate level when VDD_PWR is
connected.
9.4.3
Pre-charge and Termination Current
In pre-charge mode, a constant low level charge current is supplied to the battery, up to 50mA.
Termination current is the charge current in CV mode at which charging is terminated. Both pre-
charge current and termination current are identical and cannot be controlled independently. The
current setting is selectable by the IPRETERM register at 0x23 within a range of 0.5mA to 50mA.
Pre-charge and termination currents can also be set by an external resistor connected to the
ITER_CHG pin.
Charge termination can be disabled by setting the termination enable bit at 0x21:[4] to 0. TS_WARM
and TS_COOL conditions can also optionally disable termination at 0x21:[6:5]. This may be useful in
conditions where the available charging current is reduced due to system load, or when charge
current is reduced due to fault conditions.
The pre-charge to fast charge threshold voltage is programmable between 2.7V and 3.2V with the
VBPRECHG register at 0x25: [2:0]. The threshold has 200mV of hysteresis. When VBAT rises above
the pre-charge threshold voltage, fast charging begins.
Pre-charging is indicated by an SYS_FLT interrupt and event bit at 0x05.
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9.4.4
Fast Charge Current
In fast charge mode, a constant charging current is supplied to the battery at up to 500mA. Fast
charge current is selectable by the ICHG registers, 0x22. This can also be set by an external resistor
connected to ILIM_CHG pin. Charge current is programmable from 5mA to 500mA with an accuracy
of +/-5% over the full range. Fast charge current settings down to 2mA are available with some OTP
variants.
When VBAT reaches VBAT_CHG the device ends CC fast charge operation and starts CV operation.
9.4.5
CV Voltage Regulation and Termination
CV charging mode begins when the battery voltage rises into the regulation range. The regulated
battery voltage, VBAT_CHG, can be set between 3.6V and 4.65V by the VBCHG register at 0x24.
Regulation accuracy is +/-0.5% in CV mode.
When the DA9070 enters CV mode, charge current begins gradually decreasing, while battery
voltage remains regulated at VBAT_CHG. When charge current drops to the termination current level,
charging is terminated and the charge status, STS_CHG, changes to charge done.
Charge done is indicated by an SYS_FLT interrupt and event bit at 0x05.
To ensure that the charging current is below the termination level, termination will not occur until the
peak current is below the threshold. In noisy conditions or at very low termination currents, the
average battery current at termination may be a few mA below the set threshold.
9.4.6
Charge Done and Recharge
To prevent rapid iterations of charging and discharging from the charge done state, there is 120mV
of hysteresis below the CV regulation level, VRCH. Charging will not restart until VBAT falls below this
threshold. In addition there is a 32msec deglitch time for noise immunity.
Recharging will start automatically, when VBAT falls below the VRCH threshold.
Recharging is indicated by an SYS_FLT interrupt and event bit at 0x05.
9.4.7
Charge Faults
The DA9070 identifies multiple conditions as charge faults, indicated by the STS_CHG status bit.
These conditions may reduce the charge current, reduce the target battery voltage, or take other
actions. All are indicated by an interrupt and event bit. When the charger is unable to provide the
programmed charge current to the battery, such as when VDD_PWR is in current limit, the
termination current is ignored and charging is allowed to continue until the safety timer expires. All of
the fault and event interrupts that affect charging are summarized in Table 27. VBAT_UVLO and
VBAT_SHORT are included in the table although they are not indicated as faults when VDD_PWR is
present. Normal pre-charging will continue in both cases.
Table 27: Charge Faults
Fault
Charging
Action
STS_CHG
Termination
Safety timer
VDD_PWR OVP
Suspend
VDD_PWR
open
Fault
-
Reset
VDD_PWR
UVLO
Suspend
Continue
VDD_PWR
open
Fault
Fault
-
Reset
x2
VDD_PWR
DPM
VDD_PWR
current limit
decreased
Disable
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Fault
Charging
Action
STS_CHG
Termination
Safety timer
VDD_PWR ILIM
Continue
VDD_PWR
Fault
Disable
x2
current limited
VBAT DPPM
VBAT OCP
Sleep mode
Continue
Suspend
Charge current
reduced
Fault
Fault
Disable
-
x2
VBAT current
limited
Suspend
Suspend
Suspend
Fault
Fault
-
-
Suspend
Suspend
Supplement
mode
Battery
discharging
TS COLD
TS HOT
Suspend
Suspend
Continue
Fault
Fault
-
Suspend
Suspend
x2
-
TS COOL
Charge current
reduced to ½
In-progress
Disable
TS WARM
Continue
Suspend
VBAT_CHG
reduced by
140mV
In-progress
Fault
Disable
-
x1
TS OFF (fault
option)
Reset
Safety timer
Over-temp.
Suspend
Suspend
Suspend
Fault
Fault
Fault
-
-
Reset
Reset
Reset
VDD_SYS
UVLO
Power-cycle
VBAT Short
Pre-charge
In-progress
x1
There are several option bits available to modify the fault behavior described above. Termination can
be enabled during TS_WARM and TS_COOL, a TS_HOT fault can trigger a power-cycle, and a
TS_OFF condition can trigger a fault or simply disable the battery Temp Sense feature.
9.4.8
Safety Timers
The safety timer starts counting as soon as a charge cycle begins, ensuring that the charge cycle is
terminated even if the battery fails to reach the termination condition. The duration of the timer,
tMAXCHG, is set by register 0x21:[1:0] between 30 minutes and 9 hours. If the safety timer expires
before charging is terminated, SYS_FLT toggles, and the CHG_TMR event bit is set to 1.
In pre-charge mode, the timer period is 10% of the safety timer setting. The pre-charge timer counts
during pre-charging and is reset at the transition to fast-charge. If the charger is still in pre-charge at
the end of the pre-charge timer period, the charge cycle is terminated. The main safety time is
running during both fast charge and pre-charge modes.
To reset the safety timer and resume charging after the timer has expired, toggle the MODE pin or
the CE_N bit, or remove and re-connect VDD_PWR.
Charge faults may cause the timer duration to be doubled, suspended, or reset as described in Table
27. The timer doubling function can be doubled using the TMR2x_EN bit at 0x21:[3].
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Table 28. Safety Timer Register Settings (0x21)
TMR
0x0
0x1
0x2
0x3
Pre-charge timer
3 min
Main timer
30 min
3 h
18 min
54 min
9 h
(Disable)
(Disable)
9.5
USB Powered Operation and Power Path Management
The DA9070 monitors battery voltage and current as well as VDD_PWR input voltage and current
during all modes of operation. At all levels of operation, the appropriate charge current is maintained
while protecting the battery, system connections, and the input supply from over-voltage and over-
current and other potential fault conditions.
The DA9070’s power path management features ensure smooth transitions from charging to reduced
charging to battery supplementing the load during load peaks.
9.5.1
Under-Voltage Lockout (VDD_PWR_UVLO)
The UVLO threshold for VDD_PWR is 3.6V (typical). Below this voltage, VDD_PWR will be
disconnected from the power path and the DA9070 will be in battery powered operation. VDD_PWR
UVLO will cause SYS_FLT to toggle and will set the VDD_PWR_UVLO event bit to 1.
The UVLO threshold has typically 150mV of hysteresis on the rising edge. When VDD_PWR rises
above this threshold, charging is re-enabled. UVLO recovery will also toggle the SYS_FLT interrupt
and will set the UVLO recovery event bit.
9.5.2
Sleep Mode
Sleep mode behavior is similar to VDD_PWR_UVLO, but the falling threshold is relative to VBAT.
When VDD_PWR falls within 65mV (typical) of VBAT, sleep mode is activated. In sleep mode,
VDD_PWR is disconnected from the power path, SYS_FLT toggles, and the SLP event bit is set to 1.
When VDD_PWR falls into the range of sleep mode, it will already be in DPPM mode
(VDD_PWR<VBAT_CHG), therefore charge current will already be reduced to zero.
9.5.3
VDD_PWR Current Limit (IDD_PWR_LIM)
The VDD_PWR current limit feature protects both the DA9070 and the USB supply from excessive
current. The current limit threshold is programmable from 50mA to 600mA in 50mA steps at register
0x27. When the input current reaches the set threshold, VDD_PWR current is clamped and an event
bit is set at register 0x03. If the load at VDD_SYS increases, the VDD_SYS voltage will drop
eventually triggering a VDD_SYS UVLO.
The DPM function, when enabled, will reduce the current limit threshold as USB input voltage is
reduced.
9.5.4
Input Voltage Dynamic Power Management (DPM)
If the charge current and system load exceed the current capability of the VDD_PWR input source,
the input voltage will drop. Dynamic power management (DPM) prevents the input from dropping
below the nominal USB range and into DPPM mode by scaling down the VDD_PWR current limit
(IDDPWR_LIM) until it matches current capability of the USB source.
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This feature becomes active when VDD_PWR falls below VDDPWR_IIN_DWN, which is programmable
between 4.2 V and 4.9 Vat 0x28:[2:0]. The DPM feature can be disabled by setting the
VDD_PWR_DPM_DIS bit to 1. However, when DPM is disabled, the USB power source may be
pulled down, triggering sleep mode or input UVLO.
The VDD_PWR_DPM event bit is set to 1 and the SYS_FLT pin toggles whenever the DA9070 is in
this current-limited mode. In charging mode, termination is ignored to allow the battery to be charged
with whatever current is still available.
9.5.5
Dynamic Power Path Mode (DPPM)
Dynamic Power Path Mode (DPPM) manages the situation in which the total charging and system
current exceeds the VDD_PWR current limit. When the input current is clamped, VVDD_SYS drops until
it reaches VDD_SYS_THR_DPPM (DPPM threshold). In DPPM operation, charging current is reduced as
needed to service the system current at VDD_SYS. DPPM is only active during charging, and will
toggle SYS_FLT and set an interrupt bit at register 0x04.
If VVDD_SYS drops further due to increasing load, the DA9070 eventually enters Battery supplement
mode.
9.5.6
Battery Supplement Mode
The DA9070 enters Battery Supplement mode when VDD_SYS falls below VBAT. Supplement mode
occurs in USB powered operation, regardless of whether the battery is charging or not. Similar to
DPPM mode, the total current at VDD_SYS exceeds the VDD_PWR current limit, causing VDD_SYS
to drop until it reaches the VBAT voltage. In this mode, the battery supplies current to VDD_SYS,
thus supplementing the input current to supply the system demands. In battery supplement mode,
the discharge current from the battery is limited by the over-discharge protection.
Supplement Mode toggles the SYS_FLT pin and sets an event bit at 0x05.
The device exits Supplement Mode when the system load is reduced and VDD_SYS rises above
VBAT.
9.5.7
Input Over-Voltage Protection (VDD_PWR_OVP)
The DA9070 protects itself (and downstream connections to VDD_SYS) against input over-voltage
conditions by disconnecting VDD_PWR from the power path. Over-voltage protection kicks in
immediately when VDD_PWR exceeds the OVP threshold. Over-voltage events are common at USB
plug-in due to the inductance of the long cable, where the transient overshoot may exceed 10V
depending on cable length, quality, and input capacitance. The VDD_PWR input is capable of
withstanding up to 20V and will remain in OVP until the voltage returns to nominal levels. During
OVP, VDD_PWR is disconnected from the power path and the DA9070 will be in normal battery
powered operation.
When an over-voltage occurs, the event bit is set to 1 and SYS-FLT toggles.
9.5.8
VDD_PWR Input Supply Impedance
The DA9070 charging path is typically supplied by a 5V USB source. USB cable resistance can
range from 100’s of milliohms to ohms. At higher charging currents, this parasitic input impedance
may cause VDD_PWR to drop from 5V into the DPM range.
High USB cable resistance can lead to oscillations in DPM or Sleep mode. As VDD_PWR drops, the
DA9070 attempts to reduce current demand, which in turn causes VDD_PWR and current draw to
increase again. Follow the guidelines in Figure 32 to ensure that the DA9070’s internal hysteresis will
be sufficient to overcome these effects. The worst case is at highest battery voltage, the VBAT_CHG
regulation point.
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It is recommended to always enable the DPM function, with the threshold set at least 0.4V above the
VBAT_CHG voltage. Referring to Figure 32, with a DPM setting of 4.5V and VBAT=4.2V, the system
has the potential to oscillate at any current greater than 75mA. Note that this would only occur if
VDD_PWR drops into the DPM or sleep region. For this example, a DPM setting of 4.6V or 4.7V is
recommended for currents above 75mA.
Figure 32: VDD_PWR DPM setting recommendations
(based on typical USB cable impedance)
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9.6 Power-Cycling
The power-cycle function disables all outputs (buck, boost, and LDOs) for a programmable time
period and then restarts. Power-cycle can be initiated by a fault condition, RIN_N pushbutton,
VDD_PWR insertion, or I2C command. The primary purpose of power-cycling is to clear a serious
fault condition such as IC over-temperature (OVT) or to reset the host.
9.6.1
Requested Power-Cycle
The power-cycle settings are configured at register 0x12. There are 3 methods to enter power-cycle:
by register write to PWR_CYC_FRC, by holding the RIN_N pushbutton low for the reset period, or by
inserting and removing VDD_PWR. The setting options are summarized in Table 29.
Table 29: Power Cycle Trigger Settings
PWR_CYC_EN
0x12 [0]
PWR_CYC_MODE
0x12 [1]
RIN_N RESET
wake-up timer
VDD_PWR
insertion / removal
PWR_CYC_FRC
0x12 [2]
0x0
0x1
0x1
(don’t care)
0x0
Disable
Disable
Enable
Disable
Enable
Disable
Disable
Enable
Enable
0x1
After any of these three host or user-initiated power-cycles, the Buck, Boost, and LDO outputs will be
disabled. When auto-restart occurs, only the Buck will restart. All register settings are preserved at
restart with the exception of the output enable registers. There is also a READ clear event bit at
0x02:[1] to indicate that a power-cycle has occurred.
Two timers apply to power-cycling: the wait timer and the period timer. The wait time allows the host
to take action before power is shut down and can be set between 0 seconds and 2 seconds. The
period timer controls how long the outputs are powered down before restart and can be set between
5 and 20 seconds. Both timers are programmable at register 0x12.
Figure 33 below shows the power-cycle timing using the RIN_N pushbutton. The RESET time is set
at register 0x10:[7:6]. The RIN_N pushbutton timer can be used for power-cycling only when
VDD_PWR is present.
tWAIT
tPERIOD
tRESET
tWAKE2
RIN_N
SYS_FLT
ROUT_N
tWAKE1
(don t care)
tINTR
tINTR
tINTR
tRST_D
Boost / LDOx
Buck
Figure 33: Power-Cycle by Pushbutton Timer
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Alternately, the VDD_PWR plug can be used to initiate a power-cycle as shown in Figure 34.
VDD_PWR must go low and high 3 times within 8 seconds. After the 8 second period, the power-
cycle will begin.
< 8 sec
tWAIT
tPERIOD
>150ms
>150ms
VDD_PWR (case 1)
UVLO
UVLO
VDD_PWR (case 2)
SYS_FLT
tINTR
ROUT_N
tRST_D
Boost / LDOx
Buck
Figure 34: Power-Cycle by VDD_PWR Insertion
The force power-cycle bit (PWR_CYC_FRC) follows the same power-cycle period and behaviour, but
does not impose any wait time; power-cycle shutdown occurs immediately.
9.6.2
Fault Triggered Power-Cycle
The DA9070 will also initiate a power-cycle in response to various fault conditions, listed in Table 30
and Table 31. Those not listed as “always on” will trigger a power-cycle only if that option is enabled.
Fault triggered power-cycles are intended to protect the system from a potentially damaging
condition. The behaviour is therefore somewhat different to a user-initiated power-cycle.
When a fault triggered power-cycle occurs, the wait time is skipped and all outputs will be shut-down
immediately. When the power-cycle period ends, the initial OTP register values are re-loaded at
restart, including any outputs that are enabled by default.
A fault triggered power-cycle will also disable VDD_SYS, thus creating a complete power system
restart (a host or user-initiated power-cycle does not disable VDD_SYS).
Table 30: Power-Cycle Faults
Power-cycle Fault
triggers
0x13 register bit
I2C Selectable
Register Reset
Battery Temp Sense HOT
Thermal Shutdown (OVT)
0
YES
YES
YES
YES
NA
NA
Always On
Always On
VBAT UVLO (in act bat
mode)
VDD_SYS UVLO
NA
Always On
YES
There are also three power-cycle faults associated with the Buck, listed in Table 31. Any of these
faults will cause an immediate power-cycle. Buck faults do not re-load the OTP register values, and
only the buck will restart after a Buck fault power-cycle.
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Table 31: BUCK Power Cycle Faults
Power-cycle Fault
triggers
0x13 register bit
I2C Selectable
Register Reset
BUCK OCP
4
YES
NO
NO
NO
BUCK OVP
BUCK UVP
NA
6
Always On
YES
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9.7 Standalone Mode
The DA9070 can operate without I2C communication using external resistors to program three
settings. Fast charge current, input current limit, and termination and pre-charge current can be set
by external resistors at the ITER_CHG, ILIM_PWR and ILIM_CHG pins, respectively.
This feature is enabled by the RMEAS_EN register at 0x20 [1]. Whenever VDD_PWR is plugged-in,
these three external resistors are evaluated and the control registers are set appropriately. If the pins
are connected to ground, the internal register values will be used.
If used, all three resistors must be installed. If any of the three pins is grounded, all three currents will
be determined by their respective register values.
The specification of RMEAS_EN register is described in Table 32.
Table 32: Enabling External Resistor Setting Mode
RMEAS_EN 0x20:[1]
Setting
External resistance []
0
1
1
(don’t care)
Register settings used
0
Register settings used
> 0
Calculated from external resistance
9.7.1
Termination and Pre-Charge Current Programming (ITER_CHG)
The pre-charge and termination currents are the same value and set with the same resistor. When
using the external resistor setting method, they can be set to 5%, 10%, 15%, or 20% of the fast
charge current.
Connect a resistor from the ITER_CHG pin to ground. Table 33 shows the recommended resistor
values to set the pre-charge and termination currents.
Table 33: ITER_CHG Recommended Resistor Values
% of ILIM_CHG (typ)
Resistance (k)
5
68
22
8.2
2.2
0
10
15
20
Register Setting at 0x23 is used
Once VDD_PWR is connected, the set pre-charge and termination values can be read at register
0x20:[5:4].
The pre-charge current cannot be set higher than 50mA, or lower than 0.5mA. Settings which are out
of range will result the minimum or maximum current setting. For example, with a 400mA fast charge
current, a 20% setting would result in 80mA, but the actual pre-charge current will be the maximum
value of 50mA.
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9.7.2
Input Current Limit Programming (ILIM_PWR)
VDD_PWR input current limit is programmed by a resistor connected from the ILIM_PWR pin to
ꢅꢆꢆꢆ
ground. The resistor value can be calculated as: 푅퐼퐿퐼푀_푃푊ꢄ(Ω) =
퐼퐿퐼푀(퐴)
Not all current limit register settings are available in resistor setting mode. The available current limit
settings and corresponding resistor values are shown in Table 34.
Table 34: ILIM_PWR Recommended Resistor Values
VDD_PWR ILIM (typ)
Resistance (k)
Register setting at 0x27 is used
0
600mA
500mA
400mA
300mA
200mA
150mA
100mA
50mA
1.6
2.0
2.7
3.6
5.1
6.8
10.0
20.0
9.7.3
Charge Current Programming (ILIM_CHG)
Fast charge current is programmed by a resistor connected from the ILIM_CHG pin to ground. The
ꢅꢆꢆꢆ
resistor value can be calculated as: 푅퐼퐿퐼푀_퐶퐻퐺(Ω) =
퐹푎푠푡퐶ℎ푎푟ꢇ푒(퐴)
Not all fast charge register settings are available. The available current limit settings and
corresponding resistor values are shown in Table 35.
Table 35: ILIM_CHG Recommended Resistor Values
Fast Charge Current (typ)
Resistance (kΩ)
Register setting at 0x22 is used
0
500mA
400mA
300mA
200mA
150mA
100mA
70mA
2.0
2.7
3.6
5.1
6.8
10.0
15.0
20.0
27.0
36.0
51.0
68.0
50mA
40mA
30mA
20mA
15mA
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Fast Charge Current (typ)
Resistance (kΩ)
100.0
10mA
7mA
5mA
150.0
200.0
9.8 Host and Pushbutton Communication
The DA9070 features multiple digital pins for host and user communication, as listed in Table 36 with
connections shown in Figure 35.
Table 36: Digital Pins for Host and Pushbutton Interface
Pin Name
Description
SCL / SDA
I2C Interface
Mode control input
MODE
RIN_N
Used to enter Hi-Z mode and control charging
(Edge triggered for Hi-Z control; Level triggered for charge control)
Pushbutton Interface
Used to wake up from ship mode and Hi-Z mode
Also used to generate a low-active reset pulse on ROUT_N
IRQ Interrupt output flag
SYS_FLT
PWR_FLT
Also functions as a charging status indicator
Power Input status flag
Can also be configured as a voltage shifted RIN_N output
ROUT_N
WD
Host Reset output which is controlled by RIN_N
Watchdog input
DA9070
SCL
Host
SDA
WD
MODE
ROUT_N
SYS_FLT
PWR_FLT
(always-on)
RIN_N
Figure 35: Digital Pin Connections
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9.8.1
Watchdog Input and Timer
A programmable watchdog timer, WD, is available to detect a stall in the host. The WD function is
enabled or disabled at register 0x14:[1:0]. Each time the host initiates I2C or toggles the watchdog
input, the timer resets. If no host activity is detected within the timeout period, the DA9070 toggles
the SYS_FLT flag and sets the WD event bit at 0x07 to 1. If the register reset option is enabled, the
outputs are disabled for a period of typically 20msec and then re-enabled to reset the host. The
watchdog is automatically re-activated and the pre-programmed OTP values are loaded (except for
RIN_N_RST_ROUT_EN and RIN_N_RST_REC at register 0x10:[3:0]).
The watchdog timeout period is programmable to 25 or 50 seconds via the 0x14 register.
Optionally, the WD function can also toggle the ROUT_N pin, also selectable at register 0x14.
The WD_EN register selects when the watchdog timer is available as described in Table 37.
Table 37: WD_EN Register 0x14 [1:0]
Register value
Charge mode
Disable
Active battery mode
Disable
Hi-Z mode
Disable
Disable
Disable
Enable
0x0
0x1
0x2
0x3
Enable
Disable
Enable
Enable
Enable
Enable
The WD_CLR_SEL register selects which activity the WD uses to clear the timer, described in Table
38.
Table 38: WD_CLR_SEL Register 0x14 [3:2]
Register value
Description
Only I2C clears the timer
Only WD pin clears the timer
Both I2C and WD pin clear the timer
Reserved
0x0
0x1
0x2
0x3
Figure 36 shows how to periodically feed the watchdog and what happens when the processor stalls.
VBAT_UVLO_THR
BAT
SYS
tWATCHDOG
I2C
Host stalls
tWATCHDOG
tWATCHDOG
tWATCHDOG
tWATCHDOG
tWATCHDOG
WD
tWATCHDOG
tWATCHDOG
tWATCHDOG
tWATCHDOG
tWATCHDOG
Figure 36: Watchdog Behaviour
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9.8.2
VDDIO
VDDIO is the I/O supply rail for the DA9070. I2C communication (SDA, SCL), MODE, WD, ROUT_N,
SYS_FLT, and PWR_FLT are all referenced to the VDDIO level.
VDDIO is an input pin, which can be supplied with any voltage between 1.4V and 3.3V as required to
interface with the host. However, the VDDIO voltage must not be higher than the VDD_PWR and
VBAT voltages. Therefore, it is recommended to use the Buck or LDO output to supply VDDIO. The
VDDIO pin should be bypassed with a 1uF capacitor placed close to the pin, and grounded to AGND.
9.8.3
Interrupt Events and Status Control (SYS_FLT, PWR_FLT)
The DA9070 has an interrupt interface for 35 individual events. Some of these events are
categorized as charge fault events. See 9.4.7 for more details about charge faults.
There is a READ-only event bit for each interrupt in the SYS_IMR registers 0x03 through 0x07. A
high state indicates that an event has occurred. The bit will be kept in a high state, even if the fault
condition is removed, until the bit is cleared. These are READ clear bits which can be READ once to
identify the event, and READ a second time to reset the bit to 0.
The DA9070 provides two open drain output flags to indicate system status and interrupts, SYS_FLT
and PWR_FLT. These should be pulled up to VDDIO with a 1 kΩ to 100 kΩ resistor. Both pins have
configuration options which can be selected at register 0x11.
The PWR_FLT output can be configured as an indicator of the VDD_PWR status, or as a level-
shifted RIN_N monitor. Both options are shown below in Figure 37 and Figure 38.
When used as a level shifted RIN_N monitor, there is a typical delay of 1.5msec between RIN_N and
PWR_FLT signals.
In the case of VDD_PWR status indicator, PWR_FLT goes low only when VDD_PWR is within a valid
range. In both cases a high state is high impedance.
RIN_N
PWR_FLT
Figure 37: PWR_FLT Configured as RIN_N Monitor, 0x11:[4]=1
VVDD_PWR_OVP
VDD_PWR
VVDD_PWR_UVLO
PWR_FLT
Figure 38: PWR_FLT Configured as VDD_PWR Status Indicator, 0x11:[4]=0
The SYS_FLT output indicates interrupt events with a 128 µs pulse, and can be also be configured to
indicate charging in progress. SYS_FLT is configured at 0x11:[0] as shown in Table 39.
Table 39: SYS_FLT Configuration, 0x11: [0]
Register Setting
Charge indicator
IRQ interrupt polarity
0
1
Disabled
Active-low
SYS_FLT low when charge in
progress
Active-low when charge is not in-
progress
Active-high when charge is in-
progress
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The SYS_FLT interrupt flag can be masked for each individual interrupt by setting its mask bit to 1.
Mask registers, SYS_IMR, are at registers 0x08 through 0x0C. Masking an interrupt will mask the
SYS_FLT flag but does not mask the event bit.
Once an interrupt has occurred, the SYS_FLT flag will not toggle a second time for the same
interrupt. The event bit must first be READ cleared before SYS_FLT will respond to that event again.
9.8.4
Pushbutton Reset Timer and Reset Output (RIN_N and ROUT_N)
The RIN_N input can be used to manually control the DA9070 even in ship mode, Hi-Z mode, or
when the host has stalled. The pin has three functions: enter/exit ship mode, enter Hi-Z mode, and
toggle the ROUT_N reset output. RIN_N is active in all modes of operation. The pin is internally
pulled high and can be pulled directly to ground with an external pushbutton to activate the timer.
When RIN_N is pulled low, a reset timer begins counting. There are three programmable RIN_N
timers; each associated with an event bit. Each time the RIN_N timer passes the programmable
count the SYS_FLT flag toggles, and a WAKE event bit is set. In this way, requests to the host can
be generated by pressing the button for different durations. The first two timers are WAKE1 and
WAKE2; the third timer is the RESET timer. If RIN_N is held low for the set RESET time, the DA9070
can be set to enter ship mode, enter Hi-Z, or initiate a power-cycle. The WAKE and RESET periods
are set as shown in Table 40.
Table 40: RIN_N Pushbutton wake-up timer control (0x10)
Timer Name
Timer control register
Programmable Period
WAKE1
RIN_N_PER_WAKE1
0x10 [4]
50 ms
500 ms
WAKE2
RESET
RIN_N_PER_WAKE2
0x10 [5]
1.0 s
1.5 s
RIN_N_PER_RST
0x10 [7:6]
4 s
8 s
10s
14s
The timer status registers, WAKE1, WAKE2, and RESET, are at 0x07. As with all other events, the
SYS_FLT flag can be masked. The RIN_N timing is described in Figure 39.
tRST
tWAKE2
tWAKE1
(don’t care)
RIN_N
tINTR
tINTR
tINTR
tRST_D
SYS_FLT
ROUT_N
RIN_N_WAKE1
RIN_N_WAKE2
RIN_N_RST
Figure 39: RIN_N Pushbutton Reset Timer Timing Diagram
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The RESET behavior is configurable with the options shown in Table 41.
Table 41: RIN_N Reset Timer Configuration
Register
Configuration Description
RIN_N_RST_REC
0x10 [1:0]
0: RESET event has no effect
1: Enter ship mode at RESET
2: Enter Hi-Z mode at RESET
PWR_CYC_MODE
0x12 [1]
0: Power-cycle triggered by VDD_PWR insertion / removal
1: Power-cycle triggered by RESET timer when VDD_PWR present
RIN_N_RST_ROUT_EN
0x10 [3:2]
0: Disable ROUT_N toggle at RESET
1: Enable ROUT_N toggle at RESET
2: Enable ROUT_N toggle at RESET only when VDD_PWR is present
The RIN_N timer can also be used to exit Ship mode. A WAKE1 event will trigger Ship mode exit,
with WAKE2 and RESET being ignored.
If ROUT_N is enabled, a RESET event will cause the ROUT_N output to toggle low for 400 msec
(typ). ROUT_N is an open-drain output that should be pulled-up to the logic rail with a 1 k to 100 k
resistor.
9.8.5
System Status Register
The System Status register (0x02) indicates the status of five system functions:
•
•
•
•
•
BUCK: High = enabled with no faults
BOOST: High = enabled with no faults
Charge Status: Ready, Charge in Progress, Charge Done, or Fault
MODE: Logic state of the MODE pin
Power-Cycle: High indicates that a power-cycle has occurred
Only the power-cycle bit shows previous events and is read-clear. The others are READ only,
reflecting the current status.
9.8.6
I2C Programming
The DA9070 includes an I2C compatible interface which allows READ/WRITE access to all registers.
The interface is disabled in some modes and is configurable as described in Table 42.
Table 42: I2C Interface Configuration
I2C_HIZ_EN
0x15 [0]
Ship mode
Hi-Z mode
Active battery mode
Charge mode
0
1
disabled
disabled
disabled
active
active
active
active
active
I2C communication uses the SDA and SCL are open drain I/O pins. These should be pulled up to
VDDIO with a 1k to 100k resistor. SCL is the serial clock generated by the host and SDA is the
serial address and data input/output.
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The DA9070 is compatible with the standard I2C protocol but only operates as a slave. The I2C bus
supports a frequency range of 400kHz (fast mode) to 100 kHz (slow mode). The transfer protocol is
the same whether operating in fast or slow mode.
The device supports 8-bit addressing only. The I2C slave ID is 7-bit and can be set at register 0x40
[6:0], with a range of 00 to 7F.
When active, the I2C bus is monitored at all times for a valid SLAVE address, and an
ACKNOWLEDGE (ACK) bit is generated if the SLAVE address is true.
This indicates to the master that the communication link has been established. The master then
generates SCL clock cycles to transmit or receive data. After receiving data, an ACK is generated
either by the DA9070 or the master. Basic communication is described below and in Figure 40.
●
●
●
A START condition is initiated by a high to low transition on the SDA line while the SCL is in the
high state
A STOP condition is indicated by a low to high transition on the SDA line while the SCL is in the
high state
An ACK is indicated by the receiver pulling the SDA line low during the following clock cycle
SDA
SCL
Data SDA must be stable
during high part of clock
Start(S ) is SDA falling while
SCL high
Stop (P ) is SDA rising while
SCL high
Data sampled on SCL
rising edge and driven on
SCL falling edge
SCL
Figure 40: I2C Start and Stop Conditions
Each data sequence is 9-bit, consisting of 8-bit data and 1-bit ACK. Data sequences can be repeated
indefinitely. At the end of the data transfer, the master generates a STOP condition.
The bus returns to IDLE mode if during a message a new START or STOP condition occurs. Data is
transmitted as MSB first for both READ and WRITE operations.
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9.9 Buck Regulator
The DA9070 includes a nano-ampere quiescent current buck regulator with adjustable output
voltage, up to 300mA load capability, and power saving mode for excellent efficiency at light load. It
also features Dynamic Voltage Scaling (DVS) capability and multiple protection features.
9.9.1
Buck Output Voltage Programmability
The DA9070 buck regulator output voltage is programmable in 50mV steps between 0.6V and 2.1V.
The output voltage is set by register BUCK_VOUT at 0x30 [4:0]. The voltage can be set within two
ranges based on the value of the VOUT_RANGE_HI register, 0x30 [6]. The output voltage can be
changed within one of the two range settings while the buck is enabled (0.6V-1.3V or 1.3V-2.1V).
The range setting, however, can only be changed while the buck is disabled.
If a command is received outside of the allowable range (that is above 1.3 V for
VOUT_RANGE_HI = 0 or below 1.3 V for VOUT_RANGE_HI = 1), digital will force the value of
BUCK_VOUT<3:0> to 01110 (1.3 V).
Although the output voltage can be set up to 2.1V, there is a headroom requirement of 600mV for
VDD_BUCK. Therefore if the output voltage is set to 2.0V or 2.1V, the VBAT UVLO must be set to
2.6V or 2.7V respectively to ensure proper operation.
9.9.2
Buck Enable and Soft Start Operation
DA9070 buck integrates a soft start circuit to minimize output voltage over-shoot and input voltage
droop during start-up. Writing 1 to BUCK_EN (0x30 : [7]) enables the buck and switching starts after
a typical delay of 3 ms. During soft-start, the cycle-by-cycle peak current limit is reduced to 300mA
(typ) to limit inrush current. Although the startup time is not controlled directly, a smooth startup can
be expected with timing variations due to input and output voltage conditions.
Due to the reduced current limit in startup, starting the buck regulator into a heavy load is not
recommended.
9.9.3
Power Saving Mode Operation
The DA9070 buck regulator features power saving mode that greatly reduces the quiescent current
in light load conditions. When the load decreases to a certain level, the buck regulator enters
discontinuous mode (DCM) and operates with Pulse Frequency Modulation (PFM). The low-side FET
will be turned off based on a zero-crossing comparator to prevent negative inductor current, which
can result in additional conduction loss. If both high and low-side FETs remain in the OFF state for a
certain delay time after the inductor current crosses zero, the buck will enter power saving mode. In
this mode, most of the internal circuitry is shut down to reduce quiescent current. The lighter the load,
the longer the duration power saving mode will be, thus achieve the lowest quiescent current and
improving light load efficiency. At no-load the buck regulator consumes only 900nA of quiescent
current typically.
At heavier loads, the buck operates in continuous conduction mode (CCM) with constant off-time.
The off timer imposes a minimum off time on the switching cycle, thereby placing a ceiling on the
switching frequency.
9.9.4
Dynamic Voltage Control
The DVC feature allows the buck output voltage to ramp up or down to a new target value in a
controlled manner. When a new voltage setting is applied, the register setting value will be
incremented or decremented by one bit every 4msec, which results in an output voltage slew rate of
50 mV/4ms. Since the buck output voltage can only be changed within the high or low range while
enabled, DVC also has this restriction. DVC can be enabled and disabled at register 0x50 [1:0].
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Because the buck works in DCM under light load, it cannot quickly discharge the output voltage
during DCM. When a voltage ramp down is commanded in DCM, the slew rate will depend on the
load. In CCM, the falling slew rate will be the same 50mV / 4msec as the rising slew rate.
Different DVC slew rates are available by OTP.
9.9.5
Over-Current Protection
The over-current Protection (OCP) monitors the peak current through high-side FET on a cycle-by-
cycle basis. When the sensed current exceeds the current limit threshold, the high-side FET will be
turned OFF immediately to limit the inductor current. The high-side FET will be turned on again after
the constant-off time expires. Current limit will trigger a BUCK_OCP event bit at 0x06, and SYS_FLT
will toggle.
In current limit conditions, the output voltage will drop, potentially causing an under-voltage fault.
Both over-current and under-voltage can be set to initiate a power-cycle, restarting the buck after a
programmable wait time. The power-cycle triggers can be configured at 0x13.
9.9.6
Output Under-Voltage Protection
When a buck output short or heavy loading occurs, inductor current will increase until the peak
reaches the cycle-by-cycle current limit. Because the output is shorted, the inductor current down
slope is very small during low-side FET on time. In this condition, the inductor current can potentially
increase with each cycle. To prevent the inductor current from running away in a short-circuit
condition, the buck output voltage is monitored. If an over-current condition happens and the buck
output drops 400 mV below the reference voltage, the BUCK_UVP event bit will be set at 0x06. UVP
can be set to trigger a power-cycle at register 0x13.
The under-voltage protection is not active during startup. Therefore, a short circuit during startup may
not trigger a fault event or a power-cycle.
9.9.7
Output Over-Voltage Protection
Over-voltage protection (OVP) protects the load from unexpected output overshoots. When the buck
output voltage is 200 mV greater than the target voltage, the high side FET is immediately turned off.
Simultaneously, the output discharge FET will be turned on to discharge the output capacitor. A
BUCK_OVP event bit will be set at 0x06:[1] and the SYS_FLT flag will toggle. The buck will remain
off with the output pulled-down until the fault is cleared. BUCK_OVP can also be set to initiate a
power-cycle.
9.9.8
Automatic Output voltage Discharge
To speed up the discharging of buck output capacitor and ensure a safe re-start, the buck regulator
provides automatic output voltage discharge when the buck is disabled or shutdown due to a fault.
Automatic output discharge when the buck is forced OFF by a fault is set at register 0x31:[4].
Automatic discharge when the buck is disabled is set at register 0x31:[5]. The output of the buck
regulator is discharged through the FB_BUCK pin with resistance of 33 (typical)..
9.9.9
External Component Selection
The choice of inductor and output capacitor is a trade-off between light load efficiency and load
transient response. In general the combination of a smaller L and larger COUT improves load
transient performance and reduces the voltage ripple at light loads. A larger L improves light load
efficiency by reducing the frequency of switching cycles and therefore switching losses.
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The inductor must have a saturation rating which exceeds the maximum value of the current limit
(ILIM_SW_PMOS). In order to optimize efficiency, decide the inductor value first and then select the
inductor with the lowest DCR possible given the PCB constraints.
Recommended component values are shown in Table 43
Table 43: External Buck Components
Component
Value
2.2 µH
10uF
L
COUT
9.10 Boost Regulator
The DA9070’s integrated boost is an asynchronous current mode control regulator. This architecture
provides excellent stability over a wide range of output voltage and operates in DCM at light loads for
excellent efficiency. The boost regulator also includes a true shutdown switch to disconnect the input
from the output when disabled.
The boost input voltage (VDD_BST) is uncommitted and can be powered by VDD_SYS or any
external supply between 2.5V and 5.5V. The output voltage can be set between 4.5V and 18V at
register 0x36.
Load current capability is determined by the peak current limit, which depends primarily on input and
output voltage conditions. With an output voltage of 12V, the typical load capability is 100mA. At 5V
output, the boost is capable of supporting 300mA. And up to 80mA at the maximum 18V output. At
light load, the boost enters DCM mode and will skip pulses as needed to maintain regulation. The
peak current limit threshold can be selected between 0.5A and 1.5A at register 0x38:[5:4].
The boost regulator operates at either 1MHz or 2MHz, selectable at 0x37:[0]. A 1MHz setting is
recommended for higher efficiency and higher load capability. 2MHz can be used to minimize the
inductor and output capacitor sizes but will have a more limited operation range. Typical component
values are shown Table 44. Always check capacitor voltage derating values. The values shown here
assume no more than 50% derating at the operating voltage.
Table 44: Recommended External Boost Components
Component
L
1MHz Value
4.7 µH
2MHz Value
2.2 µH
COUT, 5V
> 4.7 µF
> 10 µF
>3.3uF
> 3.3 µF
> 6.8 µF
>3.3uF
COUT, 12V
CIN (VDD_SYS)
CIN (VDD_BST)
>1uF
>1uF
9.10.1 Startup
When the boost is enabled at register 0x36, it begins the soft start cycle. To avoid inrush current and
potential output overshoot, the true shutdown switch is enabled and a pre-charge current limit is
imposed. This charges the output voltage to the same level as the input voltage in a controlled
manner. After a selectable pre-charge time (0x37:[5:4]), the output will begin ramping up to the target
voltage. During this second period of startup, the boost begins switching, but at a reduced peak
current limit. The lower startup current limit is selectable at 0x38:[7:6] and will be active for a period
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programmable at 0x37:[7:6]. The default soft start configuration will result in a smooth output voltage
ramp under almost any condition. When disabled, the true shutdown switch is open, allowing the
output to slowly discharge to 0V.
The boost should not be enabled before VDD_BST is applied, as this will result in improper startup.
If startup into a load is required, some derating is required below approximately 3.0V input to avoid
UVLO. Additional VDD_BST capacitance up to 47uF is recommended when starting into a load.
Figure 41 shows the typical maximum load capability at startup for battery voltage less than 3V.
Higher values can be achieved with larger input cap, or by supplying VDD_BST directly.
Figure 41: Maximum Boost Load at Startup vs VBAT
(VDD_BST cap = 1 µF and 22 µF)
9.10.2 Switch Node Anti-Ringing
An anti-ringing option is available and enabled by default at register 0x39:[4]. The anti-ringing
function works during the high side OFF state to eliminate SW node ringing in DCM mode. The
function creates a path across the inductor, between VDD_BST and SW_BST, to quickly bring
SW_BST to the input voltage level. Anti-ringing eliminates DCM noise which may cause system
interference while having a minimal impact on efficiency.
9.10.3 Protection
The boost regulator includes four types of protection, over-current, short-circuit, OVP, and UVLO.
When the peak inductor current rises to the current limit threshold, the switching cycle is immediately
terminated, reducing the duty cycle. If the load is maintained in current limit, the output voltage will
drop. When the voltage drops to the short circuit threshold, SCP, the boost will stop switching, the
true shutdown switch will be opened, and the boost will be disabled. The SCP threshold is 4V for the
output range of 9V to 18V, and 2V for the output range of 4.5V to 9V. SCP will trigger an event flag
and bit at 0x06.
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If the output voltage rises 120% above the set value, and OVP fault will occur. This triggers an event
flag and bit at 0x06. In OVP, the boost will stop switching but will not shutdown. Once the output
voltage falls back to the target voltage, normal switching will resume.
The boost regulator has an independent UVLO threshold of 2.4V typical. When the input voltage at
VDD_BST drops to this threshold, the boost will be disabled. Boost UVLO also has an event flag and
bit at 0x06. The boost will not automatically restart when VDD_BST rises above the UVLO threshold.
Rather the Boost EN bit must be toggled.
9.10.4 Low Output Voltage Settings
The boost output voltage can be set as low as 4.5V, which is below the maximum input voltage range
of operation. Therefore it is possible for the boost to be subjected to “buck” operating conditions.
Because the boost is not designed for this range, the output will not be well regulated, but will drift
upward towards Vin. The boost will continue to switch in pulse skipping mode which creates larger
than normal output ripple. Additionally, in these “buck” conditions, the SCP may not function
adequately as the output voltage is not controlled by switching.
9.11 LDO / Load Switches
Each of the three LDOs is configurable as either a load switch or an LDO and capable of delivering
150 mA to the load in either mode. All LDOs have uncommitted inputs which can be connected to
VDD_SYS, the buck output, or another suitable source. If using the buck output, confirm that the
buck provides sufficient headroom and current capability.
In LDO mode, LDO_0 can be programmed between 0.8 V and 3.15V in 25mV or 50mV steps.
LDO_1 and LDO_2 can be set between 0.8V and 3.3V in 50mV or 75mV steps. To ensure good
regulation and full load capability, 200mV of headroom is recommended at VDD_LDO, with load
capability decreasing with lower headroom. With sufficient headroom the LDOs are current limited at
a minimum of 215mA. LDO_0 is designed to operate with lower headroom.
To achieve the best performance from the LDOs, it is recommended to place the input bypass cap as
close as possible to the LDO input pins (VDD_LDO). A 1uF input capacitor is typically sufficient for
each LDO, provided that there is at least that much capacitance at the VDD_SYS or BUCK output.
Each LDO is enabled and output voltage set at registers 0x32 through 0x34. The LDOs can be
configured as load switches at register 0x36. There is an approximately 20ms delay between the I2C
enable command and LDO startup.
In load switch mode, there are two modes of operation: current limit enabled and full-on. Full-on
mode disables the load switch current limit, while providing a much lower on-resistance. In current
limit enabled operation, current limit is active with the same limit as the LDO mode limit.
Each load switch can operate over a wider range compared to LDO mode, with a minimum input
voltage of 0.8V. However, as with LDO mode, the load switch current capability is reduced at lower
input voltages. At the minimum input voltage, expect a maximum load-switch capability of 1mA.
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9.12 Thermal Protection
The DA9070 is protected from internal overheating by the over-temperature shutdown function.
When the junction temperature reaches TSHDN , the device initiates power-cycle and the safety timer
is reset.
When power-cycle ends, VDD_SYS will recover for several msec; if the junction temperature is still
above TSHDN, power-cycle will be initiated again. In this way, the DA9070 continually attempts to
restart with an active duty cycle of less than 1%, sufficient to allow the IC to cool down. When the
junction temperature has dropped below TSHUTDOWN – THYS, power-cycling will stop. When an over-
temperature fault occurs, SYS_FLT toggles and the OVT bit at 0x07 is set to 1.
To avoid tripping thermal shutdown, limit power dissipation to no more than:
118℃ − ꢉ
퐴
ꢈ퐷퐼푆푆
<
푅푇퐻_퐽퐴
Where TA is the ambient temperature, RTH_JA is the thermal resistance of the package and pcb.
Typical values for RTH_JA vary with pcb size, layer count, air-flow, and other factors. A typical value of
40 ºC/W is a good starting point. PDISS can be estimated as:
Equation 5:
ꢈ퐷퐼푆푆 = ꢈ퐵푈퐶퐾 + ꢈ퐿퐷푂ꢆ +ꢈ퐿퐷푂ꢅ + ꢈ퐿퐷푂ꢊ + ꢈ퐶퐻퐺 + ꢈ퐵푆푇
Where
●
●
●
●
●
●
PVLDO0 = (VVDD_LDO0 – VVLDO0) x ILDO0
PVLDO1 = (VVDD_LDO1 – VVLDO1) x ILDO1
PVLDO2 = (VVDD_LDO2 – VVLDO2) x ILDO2
PCHG = (VVDD_PWR – VBAT) x ICHG
PBUCK = VO_BUCK x IOUT_BUCK x (1/ - 1) – DCR x IOUT_BUCK
PBST = VO_BST x IOUT_BST x (1/ - 1) – DCR x IOUT_BST x VO_BST/VDD_BST
where is the efficiency of the buck or boost converter and DCR is the inductor’s DC resistance.
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
9.13 PCB Layout Guidelines
Following a few basic PCB design practices will ensure proper operation and optimal thermal
performance from the DA9070.
The first priority is to reduce and isolate high frequency switching noise so that it does not disturb
sensitive nodes. For the buck regulator, the primary sources of noise are at the input capacitor
ground and VDD_BUCK nodes. The input capacitor should be connected as close as possible to the
PGND_BUCK and VDD_BUCK pins. This reduces the parasitic inductance responsible for much of
the voltage spikes during switching. The current carrying traces (VDD_BUCK, PGND, VOUT) should
route directly to the pads of all capacitors, not through vias or separate traces. This applies to both
input and output capacitors and is good practice in general. Where possible these current carrying
traces should be wide or large copper areas to reduce impedance and improve thermal resistance.
Route these traces on the top layer only. VDD_SYS and VDD_BUCK can be connected close to or at
the pins to further reduce impedance.
These same guidelines apply somewhat differently to the boost, where VOUT_BST and PGND_BST
are the primary sources of noise. Therefore, the output caps should be placed close to the pins and
connected by thick traces on the top layer. On the boost input side, it is recommended to route the
inductor current path and VDD_BST input path separately, with the input cap placed close to the
VDD_BST pin. This provides some isolation from noise for VDD_BST.
The second largest noise sources are the SW nodes. Although the current here is not switching, the
fast voltage swings can introduce noise through capacitive coupling. To reduce this, use the smallest
area possible for the SW nodes, while keeping in mind the current handling requirements. Both
SW_BST and SW_BUCK should be routed on the second layer with multiple vias, which allows the
best routing for the buck input and boost output caps. As much as possible, surround the SW nodes
with GND copper to help shield the nearby FB traces.
All signal traces such as FB, SDA, and SCL should be routed away from the SW nodes, buck input
caps, boost output caps, and inductors. These sensitive traces can be shielded with GND copper or
routed on a lower layer with a ground plane providing shielding.
To create a good shield, one inner layer should be flooded with copper and connected as a common
ground to the GND pins of the IC (A1, D3, and F4) and external GND connections. Layer 2 is
recommended. The PGND_BUCK pin should connect directly to the buck input cap before
connecting to the ground plane. Similarly, the PGND_BST pin should connect directly to the boost
output cap before connecting to the ground plane. Multiple ground planes, for example a mid-layer
and bottom layer plane, are helpful to control high frequency noise and improve thermal
performance.
It is very important that the AGND node should not be used as a ground plane. Instead, all AGND
connections should connect to a small area or by star connection to the AGND pin. The AGND pin
should connect to the larger ground plane in a quiet location.
A good example of top and second layer routing is shown in Figure 42 and Figure 43. The buck input
cap is C21. C32 and C33 are the boost output caps. These three caps are placed close to the IC with
no vias between the pin and the caps. C23 is the buck output cap, connected on the top layer. L20
and L30 are the buck and boost inductors; their SW nodes are routed on layer 2 and connected by
multiple vias. C30 is the VDD_BST cap, placed close to the pin and connected by a different trace
than L30.
Layer-2 is a mostly filled GND plane, which provides shielding around the SW nodes routed on this
layer. The isolated AGND area is on the right side of Figure 43. AGND is connected to the GND area
at a single point on another layer, not shown here.
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
Figure 42: Example PCB Layout, Top Layer
Figure 43: Example PCB Layout, Layer-2
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
10 Registers
10.1 Register Map
10.1.1 System
System
Register
Addr 7
6
5
4
3
2
1
0
0x00
02
SYS_STS_0
STS_BOOST STS_BUCK
STS_CHG<1:0>
Reserved
Reserved
STS_PWR_CYC STS_MODE
0x00
03
ISR_VDD_SYS_ ISR_VDD_PWR_ILI ISR_VDD_PWR ISR_VDD_PWR_UVL ISR_VDD_PWR_ ISR_VDD_PWR
SYS_ISR_0
SYS_ISR_1
SYS_ISR_2
SYS_ISR_3
SYS_ISR_4
SYS_IMR_0
SYS_IMR_1
SYS_IMR_2
Reserved
Reserved
UVLO
M
_DPM
O_RCV
UVLO
_OVP
0x00
04
ISR_VBAT_SH
ORT
ISR_VBAT_DPP ISR_VBAT_UVL
ISR_TS_HOT ISR_TS_WARM
ISR_TS_COOL ISR_TS_COLD
ISR_VBAT_OCP
M
O
0x00
05
ISR_RECHG_STAR ISR_CHG_DON
Reserved
Reserved
ISR_TS_OFF
Reserved
ISR_CHG_TMR
ISR_PRECHG
ISR_BAT_SPPL ISR_SLP
ISR_BUCK_OC
T
E
0x00
06
ISR_BOOST_U
VLO
ISR_BOOST_S
CP
ISR_BOOST_OVP
ISR_BUCK_UVP
ISR_RIN_N_RST
ISR_BUCK_OVP
P
0x00 ISR_PWR_PL
07
ISR_MODE_RIS
E
ISR_RIN_N_WA ISR_RIN_N_WA
KE2 KE1
ISR_MODE_FALL
Reserved
ISR_WD
ISR_OVT
GGD
0x00
08
IMR_VDD_SYS_ IMR_VDD_PWR_ILI IMR_VDD_PWR IMR_VDD_PWR_UV IMR_VDD_PWR IMR_VDD_PWR
Reserved
UVLO
M
_DPM
LO_RCV
_UVLO
_OVP
0x00
09
IMR_VBAT_SH
ORT
IMR_VBAT_DPP IMR_VBAT_UV
IMR_TS_HOT IMR_TS_WARM
IMR_TS_COOL IMR_TS_COLD
IMR_VBAT_OCP
M
LO
IMR_BAT_SPPL IMR_SLP
IMR_BUCK_OC
0x00
0A
IMR_RECHG_STAR IMR_CHG_DON
Reserved
Reserved
IMR_TS_OFF
Reserved
IMR_CHG_TMR
IMR_PRECHG
T
E
0x00
0B
IMR_BOOST_U
VLO
IMR_BOOST_S
CP
SYS_IMR_3
IMR_BOOST_OVP
IMR_BUCK_UVP
IMR_BUCK_OVP
P
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Ultra-Low Quiescent Current PMIC
0x00 IMR_PWR_PL
0C GGD
IMR_MODE_RIS
E
IMR_RIN_N_WA IMR_RIN_N_W
SYS_IMR_4
SYS_SYS_0
SYS_BAT_0
SYS_BAT_1
IMR_MODE_FALL
IMR_WD
Reserved
IMR_OVT
Reserved
IMR_RIN_N_RST
Reserved 1
KE2
AKE1
0x00
0D
INIT_REGS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HZ_MODE
EN_SHIPMODE
0x00
0E
Reserved
Reserved
VBAT_DIV_RATIO Reserved
BUVLO<2:0>
Reserved
0x00
0F
IDISCHG_MON_
EN
TS_TRIG
Reserved
VBATDIV_EN
SYS_RIN_N_ 0x00
RIN_N_PER_W RIN_N_PER_WAKE
RIN_N_PER_RST<1:0>
RIN_N_RST_ROUT_EN<1:0>
RIN_N_RST_REC<1:0>
0
10
AKE2
1
SYS_STS_O 0x00
SYS_FLT_MOD
E
Reserved
Reserved
Reserved
PWR_FLT_MODE
Reserved
Reserved
Reserved 0
Reserved
Reserved
UT_0
11
SYS_PWR_C 0x00
PWR_CYC_MOD
E
PWR_CYC_WAIT_PER<1:0>
PWR_CYC_PER<1:0>
PWR_CYC_FRC
Reserved
PWR_CYC_EN
YC_0
12
SYS_PWR_C 0x00
BUCK_UVP_PWR_
CYC_EN
BUCK_OCP_PWR_
CYC_EN
BTS_PWR_CY
C_EN
Reserved
Reserved 0
Reserved 0
YC_1
13
0x00 WD_RST_REG
SYS_WD_0
WD_ROUT_EN
WD_TMR_PER<1:0>
WD_CLR_SEL<1:0>
WD_EN<1:0>
14
S_EN
0x00
15
I2C_RST_TMR_
EN
SYS_I2C_0
Reserved
Reserved
Reserved
Reserved
Reserved
I2C_RDCLR_DIS
I2C_HIZ_EN
Config
Register
Addr 7
6
5
4
3
2
1
0
SYS_CFG_I2 0x00
Reserved
I2C_SLAVE_ADDR<6:0>
C_0
40
10.1.2 Charger
Charger and Power-path
Register
Addr
7
6
5
4
3
2
1
0
CE_N
CHG_CHG_0
Reserved
IPRETERM_REXT<1:0>
ICHG_MAX<1:0>
RMEAS_EN
0x002 Reserve
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Ultra-Low Quiescent Current PMIC
0
d
0x002 Reserve TE_TS_COO
CHG_CHG_1
CHG_ICHG_0
TE_TS_WARM
TE
TMRX2_EN Reserved
TMR<1:0>
1
d
L
0x002 Reserve
ICHG<6:0>
2
d
CHG_IPRETERM_ 0x002 Reserve
IPRETERM<6:0>
VBCHG<6:0>
0
3
d
0x002 Reserve
CHG_VBREG_0
4
d
CHG_VBPRECHG 0x002 Reserve
VBPRECHG_COMP_D
IS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VBPRECHG<2:0>
_0
5
d
0x002 Reserve
TS_DISCHG_MODE_S
EL
TS_WARM_E TS_OFF_MOD
N
CHG_BAT_TS_0
Reserved 0
Reserved
TS_EN_DISCHG
TS_EN_CHG
6
d
E
0x002 Reserve
CHG_VDD_PWR_0
CHG_VDD_PWR_1
CHG_IDISCHG_0
Reserved
ILIM<3:0>
7
d
0x002 Reserve
VDD_PWR_OVP_DIS VDD_PWR_DPM_DIS ILIM_EN
VDD_PWR_DPM<2:0>
IDISCHG_OCP_HIZ_E IDISCHG_OCP_E
8
d
0x002 Reserve
Reserved
IDISCHG_OCP<2:0>
9
d
N
N
10.1.3 Buck, Boost, and LDO Control
Vout User Registers
Register
Addr
7
6
5
4
3
2
1
0
VOUT_BUCK
0x0030 BUCK_EN
VOUT_RANGE_HI Reserved
Reserved
BUCK_VOUT<4:0>
VOUT_BUCK_CFG 0x0031 Reserved
BUCK_PD_CFG2 Reserved 0
Reserved
Reserved
SEL_ILIM_DLT<1:0>
VOUT_LS_LDO0
VOUT_LS_LDO1
VOUT_LS_LDO2
0x0032 EN_LS_LDO_0 Reserved
0x0033 EN_LS_LDO_1 Reserved
0x0034 EN_LS_LDO_2 Reserved
LS_LDO_0<5:0>
LS_LDO_1<5:0>
LS_LDO_2<5:0>
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Ultra-Low Quiescent Current PMIC
VOUT_LS_LDO_CFG 0x0035 Reserved
SEL_FULLON_2 SEL_FULLON_1 SEL_FULLON_0Reserved
BOOST_VOUT<6:0>
SEL_LDSW_2 SEL_LDSW_1 SEL_LDSW_0
VOUT_BOOST
0x0036 BOOST_EN
VOUT_BOOST_CFG0 0x0037 TSS_SEL<1:0>
TPCHG_SEL<1:0>
BST_CFG_OC<1:0>
Reserved
Reserved
Reserved
BST_CFG_FREQ
Reserved 0
VOUT_BOOST_CFG1 0x0038 BST_CFG_OCS<1:0>
Reserved 0
Reserved 1
Reserved 1
VOUT_BOOST_CFG2 0x0039 Reserved 0
Reserved 1
Reserved 1
BST_CFG_ANTI BST_CFG_PCHGLMT<3:0>
Vout Opt Registers
Register
Addr
7
6
5
4
3
2
1
0
0
VOUT_BUCK_OPT0 0x0050 Reserved 0
Reserved 0
Reserved 0
Reserved 1
Reserved 1
Reserved 0
DVC_STEP<1:0>
Vout Test Registers
Register
Addr
7
6
5
4
3
2
1
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Ultra-Low Quiescent Current PMIC
10.2 Register Definitions
10.2.1 System
Table 45: Register SYS_STS_0
Address
0x0002
Register Name
POR Value
0x00
Status
SYS_STS_0
7
6
5
4
3
2
1
0
STS_BOOST
Field Name
STS_BOOST
STS_BUCK
STS_BUCK
STS_CHG<1:0>
Description
Reserved
Reserved
STS_PWR_CYC
STS_MODE
Bits
[7]
POR
0x0
Boost no fault status
Buck power-good status
Charge status
[6]
0x0
Value
Description
0x0 (POR) Charge ready
STS_CHG
[5:4]
0x0
0x1
0x2
0x3
Charge in progress
Charge done
Fault
STS_PWR_CYC
STS_MODE
[1]
[0]
0x0
0x0
Power cycle status register. Cleared after being read
MODE pin status
Table 46: Register SYS_ISR_0
Address
Register Name
POR Value
0x00
IRQ status
0x0003
SYS_ISR_0
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Ultra-Low Quiescent Current PMIC
7
6
5
4
3
2
1
0
Reserved
Field Name
Reserved
ISR_VDD_SYS_UVLO ISR_VDD_PWR_ILIM ISR_VDD_PWR_DPM ISR_VDD_PWR_UVLO_RCVISR_VDD_PWR_UVLOISR_VDD_PWR_OVP
Bits
[5]
POR Description
ISR_VDD_SYS_UVLO
ISR_VDD_PWR_ILIM
ISR_VDD_PWR_DPM
0x0
0x0
0x0
0x0
0x0
0x0
VDD_SYS UVLO IRQ status
[4]
VDD_PWR ILIM IRQ status
VDD_PWR DPM IRQ status
VDD_PWR UVLO recovery IRQ status
VDD_PWR UVLO IRQ status
VDD_PWR OVP IRQ status
[3]
ISR_VDD_PWR_UVLO_RCV [2]
ISR_VDD_PWR_UVLO
ISR_VDD_PWR_OVP
[1]
[0]
Table 47: Register SYS_ISR_1
Address
Register Name
SYS_ISR_1
6
POR Value
0x00
IRQ status
0x0004
7
5
4
3
2
1
0
ISR_TS_HOT
Field Name
ISR_TS_WARM
ISR_TS_COOL
ISR_TS_COLD
ISR_VBAT_SHORT ISR_VBAT_OCP
ISR_VBAT_DPPM ISR_VBAT_UVLO
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
POR Description
ISR_TS_HOT
ISR_TS_WARM
ISR_TS_COOL
ISR_TS_COLD
ISR_VBAT_SHORT
ISR_VBAT_OCP
ISR_VBAT_DPPM
ISR_VBAT_UVLO
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Battery temperature sensor IRQ status.TS_HOT
Battery temperature sensor IRQ status.TS_WARM
Battery temperature sensor IRQ status.TS_COOL
Battery temperature sensor IRQ status.TS_COLD
VBAT short IRQ status
VBAT OCP IRQ status
VBAT DPPM IRQ status
VBAT UVLO IRQ status
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DA9070
Ultra-Low Quiescent Current PMIC
Table 48: Register SYS_ISR_2
Address
0x0005
Register Name
POR Value
0x00
IRQ status
SYS_ISR_2
7
6
5
4
3
2
1
0
Reserved
Field Name
ISR_TS_OFF
ISR_CHG_TMR
ISR_TS_OFF
ISR_CHG_TMR
Description
ISR_RECHG_START ISR_CHG_DONE
ISR_PRECHG
ISR_BAT_SPPL
ISR_SLP
Bits
[6]
POR
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Battery temperature sensor IRQ status.TS_OFF
Charge safety timer IRQ status
Recharge started IRQ status
Charge done IRQ status
[5]
ISR_RECHG_START
ISR_CHG_DONE
ISR_PRECHG
ISR_BAT_SPPL
ISR_SLP
[4]
[3]
[2]
[1]
[0]
Pre-charge IRQ status
Battery supplement mode IRQ status
Sleep mode IRQ status
Table 49: Register SYS_ISR_3
Address
Register Name
POR Value
IRQ status
0x0006
SYS_ISR_3
0x00
7
6
5
4
3
2
1
0
Reserved
Reserved
ISR_BOOST_UVLO ISR_BOOST_OVP ISR_BOOST_SCP ISR_BUCK_UVP
ISR_BUCK_OVP
ISR_BUCK_OCP
Field Name
ISR_BOOST_UVLO
ISR_BOOST_OVP
ISR_BOOST_SCP
ISR_BUCK_UVP
Bits
[5]
POR
0x0
0x0
0x0
0x0
Description
Boost UVP IRQ status
Boost OVP IRQ status
Boost OCP IRQ status
Buck UVP IRQ status
[4]
[3]
[2]
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ISR_BUCK_OVP
ISR_BUCK_OCP
[1]
[0]
0x0
0x0
Buck OVP IRQ status
Buck OCP IRQ status
Table 50: Register SYS_ISR_4
Address
0x0007
7
Register Name
SYS_ISR_4
6
POR Value
IRQ status
0x00
5
4
3
2
1
0
ISR_PWR_PLGGD ISR_MODE_FALL ISR_MODE_RISE
ISR_WD
ISR_OVT
ISR_RIN_N_RST
ISR_RIN_N_WAKE2 ISR_RIN_N_WAKE1
Field Name
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
POR
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
ISR_PWR_PLGGD
ISR_MODE_FALL
ISR_MODE_RISE
ISR_WD
VDD_PWR insertion/removeal power cycle IRQ status
MODE pin falling edge IRQ status
MODE pin rising edge IRQ status
Watchdog timer IRQ status
ISR_OVT
Overtemperature IRQ status
ISR_RIN_N_RST
ISR_RIN_N_WAKE2
ISR_RIN_N_WAKE1
RIN_N RESET timer IRQ status
RIN_N WAKE2 timer IRQ status
RIN_N WAKE1 timer IRQ status
Table 51: Register SYS_IMR_0
Address
0x0008
7
Register Name
SYS_IMR_0
5
POR Value
0x3F
IRQ mask
6
4
3
2
1
0
Reserved
Reserved
IMR_VDD_SYS_UVLOIMR_VDD_PWR_ILIM IMR_VDD_PWR_DPMIMR_VDD_PWR_UVLO_RCVIMR_VDD_PWR_UVLOIMR_VDD_PWR_OVP
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Ultra-Low Quiescent Current PMIC
Field Name
Bits
[5]
POR Description
IMR_VDD_SYS_UVLO
IMR_VDD_PWR_ILIM
IMR_VDD_PWR_DPM
0x1
0x1
0x1
0x1
0x1
0x1
VDD_SYS UVLO IRQ mask
[4]
VDD_PWR ILIM IRQ mask
[3]
VDD_PWR DPM IRQ mask
VDD_PWR UVLO recovery IRQ mask
VDD_PWR UVLO IRQ mask
VDD_PWR OVP IRQ mask
IMR_VDD_PWR_UVLO_RCV [2]
IMR_VDD_PWR_UVLO
IMR_VDD_PWR_OVP
[1]
[0]
Table 52: Register SYS_IMR_1
Address
Register Name
SYS_IMR_1
6
POR Value
0xFF
IRQ mask
0x0009
7
5
4
3
2
1
0
IMR_TS_HOT
Field Name
IMR_TS_WARM
IMR_TS_COOL
IMR_TS_COLD
IMR_VBAT_SHORT IMR_VBAT_OCP
IMR_VBAT_DPPM IMR_VBAT_UVLO
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
POR Description
IMR_TS_HOT
IMR_TS_WARM
IMR_TS_COOL
IMR_TS_COLD
IMR_VBAT_SHORT
IMR_VBAT_OCP
IMR_VBAT_DPPM
IMR_VBAT_UVLO
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
Battery temperature sensor IRQ mask.TS_HOT
Battery temperature sensor IRQ mask.TS_WARM
Battery temperature sensor IRQ mask.TS_COOL
Battery temperature sensor IRQ mask.TS_COLD
VBAT short IRQ mask
VBAT OCP IRQ mask
VBAT DPPM IRQ mask
VBAT UVLO IRQ mask
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Ultra-Low Quiescent Current PMIC
Table 53: Register SYS_IMR_2
Address
Register Name
POR Value
0x7F
IRQ mask
0x000A
SYS_IMR_2
7
6
5
4
3
2
1
0
Reserved
Field Name
IMR_TS_OFF
IMR_CHG_TMR
IMR_TS_OFF
IMR_CHG_TMR
Description
IMR_RECHG_STARTIMR_CHG_DONE
IMR_PRECHG
IMR_BAT_SPPL
IMR_SLP
Bits
[6]
POR
0x1
0x1
0x1
0x1
0x1
0x1
0x1
Battery temperature sensor IRQ mask.TS_OFF
Charge safety timer IRQ mask
Recharge started IRQ mask
[5]
IMR_RECHG_START
IMR_CHG_DONE
IMR_PRECHG
IMR_BAT_SPPL
IMR_SLP
[4]
[3]
[2]
[1]
[0]
Charge done IRQ mask
Pre-charge started IRQ mask
Battery supplement mode IRQ mask
Sleep mode IRQ mask
Table 54: Register SYS_IMR_3
Address
Register Name
POR Value
IRQ mask
0x000B
SYS_IMR_3
0x3F
7
6
5
4
3
2
1
0
Reserved
Reserved
IMR_BOOST_UVLO IMR_BOOST_OVP IMR_BOOST_SCP IMR_BUCK_UVP
IMR_BUCK_OVP
IMR_BUCK_OCP
Field Name
IMR_BOOST_UVLO
IMR_BOOST_OVP
IMR_BOOST_SCP
IMR_BUCK_UVP
Bits
[5]
POR
0x1
0x1
0x1
0x1
Description
Boost UVP IRQ mask
Boost OVP IRQ mask
Boost OCP IRQ mask
Buck UVP IRQ mask
[4]
[3]
[2]
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DA9070
Ultra-Low Quiescent Current PMIC
IMR_BUCK_OVP
IMR_BUCK_OCP
[1]
[0]
0x1
0x1
Buck OVP IRQ mask
Buck OCP IRQ mask
Table 55: Register SYS_IMR_4
Address
0x000C
7
Register Name
SYS_IMR_4
6
POR Value
IRQ mask
0xFF
5
4
3
2
1
0
IMR_PWR_PLGGD IMR_MODE_FALL IMR_MODE_RISE IMR_WD
IMR_OVT
IMR_RIN_N_RST
IMR_RIN_N_WAKE2 IMR_RIN_N_WAKE1
Field Name
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
POR
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
Description
IMR_PWR_PLGGD
IMR_MODE_FALL
IMR_MODE_RISE
IMR_WD
VDD_PWR insertion/removeal power cycle IRQ mask
MODE pin falling edge IRQ mask
MODE pin rising edge IRQ mask
Watchdog timer IRQ mask
IMR_OVT
Overtemperature IRQ mask
IMR_RIN_N_RST
IMR_RIN_N_WAKE2
IMR_RIN_N_WAKE1
RIN_N RESET timer IRQ mask
RIN_N WAKE2 timer IRQ mask
RIN_N WAKE1 timer IRQ mask
Table 56: Register SYS_SYS_0
Address
0x000D
7
Register Name
SYS_SYS_0
6
POR Value
System configuration
0x04
5
4
3
2
1
0
INIT_REGS
Reserved
Reserved
Reserved
Reserved
Reserved 1
HZ_MODE
EN_SHIPMODE
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DA9070
Ultra-Low Quiescent Current PMIC
Field Name
INIT_REGS
HZ_MODE
Bits
[7]
POR
0x0
0x0
0x0
Description
Initialize register trigger
[1]
Hi-Z mode entry control. Automatically cleared when HZ mode exit
Shipmode entry control
EN_SHIPMODE
[0]
Table 57: Register SYS_BAT_0
Address
0x000E
7
Register Name
SYS_BAT_0
6
POR Value
System configuration
0x06
5
4
3
2
1
0
Reserved
Field Name
Reserved
Bits
Reserved
VBAT_DIV_RATIO Reserved
BUVLO<2:0>
POR
Description
VBATDIV divider ratio setting
Value Description
0x0 (POR) 60 %
0x1 30 %
VBAT_DIV_RATIO
[4]
0x0
Battery UVLO threshold
Value
0x0
0x1
0x2
0x3
0x4
0x5
Description
Reserved
2.5V
2.6V
BUVLO
[2:0]
0x6
2.7V
2.8V
2.9V
0x6 (POR) 3.0V
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DA9070
Ultra-Low Quiescent Current PMIC
0x7
Reserved
Table 58: Register SYS_BAT_1
Address
Register Name
POR Value
0x00
System configuration
0x000F
SYS_BAT_1
7
6
5
4
3
2
1
0
Reserved
Field Name
TS_TRIG
IDISCHG_MON_EN
VBATDIV_EN
Reserved
Bits
[4]
Reserved
TS_TRIG
Reserved
Reserved
IDISCHG_MON_EN VBATDIV_EN
POR
0x0
0x0
0x0
Description
Trigger register for one-shot battery temp sense enable
Enable battery discharge current monitor
Battery voltage devider enable
[1]
[0]
Table 59: Register SYS_RIN_N_0
Address
0x0010
7
Register Name
SYS_RIN_N_0
6
POR Value
RIN_N
0x66
5
4
3
2
1
0
RIN_N_PER_RST<1:0>
RIN_N_PER_WAKE2 RIN_N_PER_WAKE1RIN_N_RST_ROUT_EN<1:0>
RIN_N_RST_REC<1:0>
Field Name
Bits
POR
Description
RIN_N RESET timer period
Value
Description
0x0
4s
RIN_N_PER_RST
[7:6]
0x1
0x1 (POR) 8s
0x2
0x3
10s
14s
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DA9070
Ultra-Low Quiescent Current PMIC
RIN_N WAKE2 timer period
Value
Description
RIN_N_PER_WAKE2
RIN_N_PER_WAKE1
[5]
[4]
0x1
0x0
0x0
1.0s
0x1 (POR) 1.5s
RIN_N WAKE1 timer period
Value
0x0 (POR) 50ms
0x1 500ms
Description
ROUT_N pulse output enable for RESET wake-up
Value
Description
0x0
Disable
RIN_N_RST_ROUT_EN [3:2]
0x1
0x1 (POR) Enable
0x2
0x3
Enable only when VDD_PWR is present
Reserved
Reset timer Hi-Z / ship mode transition control
Value
0x0
Description
Reset timer is not used for both
Enter ship mode after RIN_N reset timer hit
RIN_N_RST_REC
[1:0]
0x2
0x1
0x2 (POR) Enter Hi-Z mode after RIN_N reset timer hit
0x3 Reserved
Table 60: Register SYS_STS_OUT_0
Address
Register Name
POR Value
Status inidicator
0x0011
SYS_STS_OUT_0 0x01
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DA9070
Ultra-Low Quiescent Current PMIC
7
6
5
4
3
2
1
0
Reserved
Field Name
Reserved
Reserved
Description
PWR_FLT_MODE Reserved
Reserved
Reserved
SYS_FLT_MODE
Bits
POR
PWR_FLT mode select
Value Description
0x0 (POR) Power good indicator
PWR_FLT_MODE
SYS_FLT_MODE
[4]
[0]
0x0
0x1
Voltage shifted RIN_N output
SYS_FLT mode select
Value
Description
IRQ I/F enabled and charge status indicator disabled
0x1
0x0
0x1 (POR) IRQ I/F enabled and charge status indicator enabled
Table 61: Register SYS_PWR_CYC_0
Address
0x0012
7
Register Name
POR Value
Power cycle
SYS_PWR_CYC_0 0x91
6
5
4
3
2
1
0
PWR_CYC_WAIT_PER<1:0>
PWR_CYC_PER<1:0>
Description
Reserved
PWR_CYC_FRC
PWR_CYC_MODE PWR_CYC_EN
Field Name
Bits
POR
Power cycle wait period setting
Value
0x0
Description
0s
PWR_CYC_WAIT_PER
[7:6]
0x2
0x1
0.5s
0x2 (POR) 1.0s
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DA9070
Ultra-Low Quiescent Current PMIC
0x3
2.0s
Power cycle period setting
Value
Description
0x0
5s
PWR_CYC_PER
[5:4]
0x1
0x1 (POR) 10s
0x2
0x3
15s
20s
PWR_CYC_FRC
PWR_CYC_MODE
PWR_CYC_EN
[2]
[1]
[0]
0x0
0x0
0x1
Write 1 to force power-cycling
Power cycle trigger select
Value
Description
0x0 (POR) VDD_PWR insertion/removal
0x1
RESET wake-up timer when VDD_PWR present
Power cycle enable
Table 62: Register SYS_PWR_CYC_1
Address
0x0013
7
Register Name
POR Value
Power cycle
SYS_PWR_CYC_1 0x00
6
5
4
3
2
1
0
BUCK_UVP_PWR
_CYC_EN
BUCK_OCP_PWR_CYC
_EN
BTS_PWR_CYC
_EN
Reserved
Reserved 0
Reserved 0
Reserved
Reserved 0
Field Name
Bits POR Description
BUCK_UVP_PWR_CYC_EN
BUCK_OCP_PWR_CYC_EN
[6]
[4]
0x0
0x0
Power cycle enable triggerd by Buck UVP
Power cycle enable triggerd by Buck OCP
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
BTS_PWR_CYC_EN
[0]
0x0
Power cycle enable triggerd by TS_HOT
Table 63: Register SYS_WD_0
Address
0x0014
7
Register Name
SYS_WD_0
6
POR Value
Watchdog timer
0x10
5
4
3
2
1
0
WD_RST_REGS_EN WD_ROUT_EN
WD_TMR_PER<1:0>
WD_CLR_SEL<1:0>
WD_EN<1:0>
Field Name
Bits
[7]
POR
0x0
Description
WD_RST_REGS_EN
WD_ROUT_EN
Register reset on watchdog timeout enable
Reset output on watchdog timeout enable
Watchdog timer timeout period
[6]
0x0
Value
Description
0x0
25s
WD_TMR_PER
[5:4]
0x1
0x1 (POR) 50s
0x2
0x3
Reserved
Reserved
Watchdog timer clear condition
Value Description
0x0 (POR) Only I2C clears the timer
WD_CLR_SEL
[3:2]
[1:0]
0x0
0x0
0x1
0x2
0x3
Only WD pin clears the timer
Both I2C and WD pin clear the timer
Reserved
Watchdog timer enable
Value Description
WD_EN
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DA9070
Ultra-Low Quiescent Current PMIC
0x0 (POR) Disable
0x1
0x2
0x3
Enable only when VDD_PWR present
Disable in Hi-Z mode
Always enable
Table 64: Register SYS_I2C_0
Address
Register Name
POR Value
I2C
0x0015
SYS_I2C_0
0x00
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
I2C_RDCLR_DIS
I2C_RST_TMR_EN I2C_HIZ_EN
Field Name
Bits
[2]
POR
0x0
0x0
0x0
Description
I2C_RDCLR_DIS
I2C_RST_TMR_EN
I2C_HIZ_EN
I2C read clear disable for ISR registers and STS_PWR_CYC register
I2C reset timer enable
[1]
[0]
I2C enable in Hi-Z mode
10.2.2 Config
Table 65: Register SYS_CFG_I2C_0
Address
0x0040
Register Name
POR Value
I2C
SYS_CFG_I2C_0 0x68
7
6
5
4
3
2
1
0
Reserved
Field Name
I2C_SLAVE_ADDR
I2C_SLAVE_ADDR<6:0>
Bits
POR
Description
[6:0]
0x68
I2C slave addr
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DA9070
Ultra-Low Quiescent Current PMIC
10.2.3 Charger
10.2.3.1
Charger and Power-Path
Table 66: Register CHG_CHG_0
Address
0x0020
7
Register Name
CHG_CHG_0
6
POR Value
Charge
0x01
5
4
3
2
1
0
Reserved
Field Name
Reserved
Bits
IPRETERM_REXT<1:0>
ICHG_MAX<1:0>
RMEAS_EN
CE_N
POR
Description
Charge termination/pre-charge current range by RITER_CHG. Read-only.
Value Description
0x0 (POR) 5% of ICHG
IPRETERM_REXT
[5:4]
0x0
0x1
0x2
0x3
10% of ICHG
15% of ICHG
20% of ICHG
Maximum charge current limit.
Value Description
0x0 (POR) No limit
ICHG_MAX
[3:2]
0x0
0x1
0x2
0x3
20mA
70mA
200mA
RMEAS_EN
CE_N
[1]
[0]
0x0
0x1
External resistance programming enable. Write-locked when CE_N is 0.
Charge enable
Value
Description
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DA9070
Ultra-Low Quiescent Current PMIC
0x0
Enable charging
0x1 (POR) Disable charging
Table 67: Register CHG_CHG_1
Address
0x0021
Register Name
POR Value
Charge
CHG_CHG_1
0x19
7
6
5
4
3
2
1
0
Reserved
Field Name
TE_TS_COOL
TE_TS_WARM
TE
TE_TS_COOL
TE_TS_WARM
Description
TE
TMRX2_EN
Reserved
TMR<1:0>
Bits
[6]
POR
0x0
0x0
0x1
0x1
Termination enable during TS COOL. Write-locked when CE_N is 0.
Termination enable during TS WARM. Write-locked when CE_N is 0.
Charge current termination enable. Write-locked when CE_N is 0.
Safety timer half rate enable. Write-locked when CE_N is 0.
Safety timer period. Write-locked when CE_N is 0.
[5]
[4]
TMRX2_EN
[3]
Value
Description
0x0
30m
TMR
[1:0]
0x1
0x1 (POR) 3h
0x2
0x3
9h
Timer disabled
Table 68: Register CHG_ICHG_0
Address
Register Name
POR Value
Charge current
0x0022
CHG_ICHG_0
0x41
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DA9070
Ultra-Low Quiescent Current PMIC
7
6
5
4
3
2
1
0
Reserved
Field Name
ICHG<6:0>
Bits
POR
Description
Charge current (mA)
2.0-4.8 mA settings are available when SEL_ICHG_LOW=1.
Value
0x0
Description
5 (2)
6 (2.4)
7 (2.8)
8 (3.2)
9 (3.6)
10 (4)
11 (4.4)
12 (4.8)
13
0x1
0x2
0x3
0x4
0x5
0x6
ICHG
[6:0]
0x41
0x7
0x8
0x9
14
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
15
16
17
18
19
20
21
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DA9070
Ultra-Low Quiescent Current PMIC
0x11
22
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x3F
0x40
23
24
25
26
27
28
29
30
31
32
33
34
35
Reserved
Reserved
40
0x41 (POR) 50
0x42
0x43
0x44
0x45
0x46
60
70
80
90
100
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
0x47
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
0x5E
340
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x7F
350
360
370
380
390
400
410
420
430
440
450
460
470
480
490
500
Reserved
Reserved
Table 69: Register CHG_IPRETERM_0
Address
Register Name
POR Value
Precharge / termination current
0x0023
CHG_IPRETERM_0 0x04
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DA9070
Ultra-Low Quiescent Current PMIC
7
6
5
4
3
2
1
0
Reserved
IPRETERM<6:0>
Field Name
Bits
POR
Description
Precharge / termination current
Value
0x0
Description
0.5
1
0x1
0x2
1.5
2
0x3
0x4 (POR) 2.5
0x5
3
0x6
3.5
0x7
4
IPRETERM
[6:0]
0x4
0x8
4.5
0x9
5
0x0A
0x3F
0x40
0x41
0x42
0x43
0x44
Reserved
Reserved
6
7
8
9
10
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
0x45
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
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DA9070
Ultra-Low Quiescent Current PMIC
0x5C
34
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x7F
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Reserved
Reserved
Table 70: Register CHG_VBREG_0
Address
Register Name
POR Value
Battery regulation voltage
0x0024
CHG_VBREG_0
0x3C
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DA9070
Ultra-Low Quiescent Current PMIC
7
6
5
4
3
2
1
0
Reserved
VBCHG<6:0>
Field Name
Bits
POR
Description
Battery regulation voltage
Value
0x0
Description
3.6
0x1
3.61
3.62
3.63
3.64
3.65
3.66
3.67
3.68
3.69
3.7
0x2
0x3
0x4
0x5
0x6
0x7
VBCHG
[6:0]
0x3C
0x8
0x9
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
3.71
3.72
3.73
3.74
3.75
3.76
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
0x11
3.77
3.78
3.79
3.8
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
3.81
3.82
3.83
3.84
3.85
3.86
3.87
3.88
3.89
3.9
3.91
3.92
3.93
3.94
3.95
3.96
3.97
3.98
3.99
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
0x28
4
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
4.01
4.02
4.03
4.04
4.05
4.06
4.07
4.08
4.09
4.1
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
0x3C (POR) 4.2
0x3D
0x3E
4.21
4.22
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DA9070
Ultra-Low Quiescent Current PMIC
0x3F
4.23
4.24
4.25
4.26
4.27
4.28
4.29
4.3
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
4.31
4.32
4.33
4.34
4.35
4.36
4.37
4.38
4.39
4.4
4.41
4.42
4.43
4.44
4.45
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
0x56
4.46
4.47
4.48
4.49
4.5
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x7F
4.51
4.52
4.53
4.54
4.55
4.56
4.57
4.58
4.59
4.6
4.61
4.62
4.63
4.64
4.65
Reserved
Reserved
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DA9070
Ultra-Low Quiescent Current PMIC
Table 71: Register CHG_VBPRECHG_0
Address
Register Name
POR Value
Battery precharge voltage
0x0025
CHG_VBPRECHG_0 0x06
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
VBPRECHG_COMP_DIS Reserved
VBPRECHG<2:0>
Field Name
Bits
POR
Description
Precharge comparator disable. Charger operates in pre-charge mode when VBAT short detected. Write-locked when CE_N is 0.
Value Description
0x0 (POR) Precharge threshold is as specified by VBPRECHG
0x1 Charger will ignore precharge threshold
VBPRECHG_COMP_DIS [4]
0x0
Battery precharge voltage (V)
Value
0x0
0x1
0x2
0x3
0x4
0x5
Description
Reserved
2.7
2.8
2.9
3
VBPRECHG
[2:0]
0x6
3.1
0x6 (POR) 3.2
0x7 Reserved
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DA9070
Ultra-Low Quiescent Current PMIC
Table 72: Register CHG_BAT_TS_0
Address
Register Name
POR Value
Battery temperature sense
0x0026
CHG_BAT_TS_0
0x01
7
6
5
4
3
2
1
0
Reserved
Reserved
TS_DISCHG_MODE_SEL Reserved 0
TS_WARM_EN
TS_OFF_MODE
TS_EN_DISCHG
TS_EN_CHG
Field Name
Bits
POR
Description
Temp sense mode selection during discharging
Value Description
0x0 (POR) Periodic sampling mode with 2s period
0x1 Host triggered sampling mode
TS_DISCHG_MODE_SEL [5]
0x0
0x0
0x0
TS_WARM_EN
TS_OFF_MODE
[3]
[2]
TS WARM function enable. Write-locked when CE_N is 0, or when TS_EN is not 0.
TS OFF mode control. Write-locked when CE_N is 0, or when TS_EN is not 0.
Value
0x0 (POR) Battery TS feature is disabled when TS_OFF
0x1 Charger falut condition when TS_OFF
Description
TS_EN_DISCHG
TS_EN_CHG
[1]
[0]
0x0
0x1
Battery temperature sense enable during discharging
Battery temperature sense enable during charging
Table 73: Register CHG_VDD_PWR_0
Address
Register Name
POR Value
VDD_PWR
0x0027
CHG_VDD_PWR_0 0x02
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DA9070
Ultra-Low Quiescent Current PMIC
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
ILIM<3:0>
Field Name
Bits
POR
Description
Input current limit (mA)
Value
0x0
Description
2.5
50
0x1
0x2 (POR) 100
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
150
200
250
300
ILIM
[3:0]
0x2
350
400
450
500
550
600
Reserved
Reserved
Reserved
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DA9070
Ultra-Low Quiescent Current PMIC
Table 74: Register CHG_VDD_PWR_1
Address
Register Name
POR Value
VDD_PWR
0x0028
CHG_VDD_PWR_1 0x0C
7
6
5
4
3
2
1
0
Reserved
Reserved
VDD_PWR_OVP_DISVDD_PWR_DPM_DISILIM_EN
VDD_PWR_DPM<2:0>
Field Name
Bits
POR
0x0
0x0
0x1
Description
VDD_PWR_OVP_DIS
VDD_PWR_DPM_DIS
ILIM_EN
[5]
[4]
[3]
VDD_PWR OVP disable
VDD_PWR DPM disable
Input current limit enable
VDD_PWR DPM threshold voltage (V)
Value
0x0
Description
4.2
4.3
4.4
4.5
0x1
0x2
VDD_PWR_DPM
[2:0]
0x4
0x3
0x4 (POR) 4.6
0x5
0x6
0x7
4.7
4.8
4.9
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DA9070
Ultra-Low Quiescent Current PMIC
Table 75: Register CHG_IDISCHG_0
Address
Register Name
POR Value
Battery discharge current limit
0x0029
CHG_IDISCHG_0 0x0D
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
IDISCHG_OCP<2:0>
IDISCHG_OCP_HIZ_EN IDISCHG_OCP_EN
Field Name
Bits
POR
Description
Battery discharge over-current protection setting (A)
Value
0x0
Description
0.55
0x1
0.75
0x2
0.95
IDISCHG_OCP
[4:2]
0x3
0x3 (POR) 1.15
0x4
0x5
0x6
0x7
1.35
1.55
1.75
Reserved
IDISCHG_OCP_HIZ_EN [1]
0x0
0x1
Battery discharge over-current protection enable, even during HiZ
Battery discharge over-current protection enable
IDISCHG_OCP_EN
[0]
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
10.2.4 Buck, Boost, and LDO Control
10.2.4.1
VOUT User Registers
Table 76: Register VOUT_BUCK
Address
Register Name
POR Value
Buck eneble & vout control
0x0030
VOUT_BUCK
0x5C
7
6
5
4
3
2
1
0
BUCK_EN
VOUT_RANGE_HI Reserved
BUCK_VOUT<4:0>
Field Name
Bits
POR
Description
BUCK_EN
[7]
0x0
BUCK enable
Buck output range control.
This register can be written when buck is disabled or when BUCK_EN is being written to 0.
Value
Description
VOUT_RANGE_HI
[6]
0x1
0x0
0.60 V <= VBUCK <= 1.30 V
0x1 (POR) 1.30 V <= VBUCK <= 2.10 V
Buck output voltage setting (0.6 V to 2.1 V in 50 mV steps).
0.60 V to 1.30 V can be set when VOUT_RANGE_HI=0 and 1.3 V to 2.1 V can be set when VOUT_RANGE_HI=1.
Value
0x00
0x01
0x02
0x03
Description
0.60 V
BUCK_VOUT
[4:0]
0x1C
0.65 V
0.70 V
0.75 V
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DA9070
Ultra-Low Quiescent Current PMIC
0x04
0.80 V
0.85 V
0.90 V
0.95 V
1.00 V
1.05 V
1.10 V
1.15 V
1.20 V
1.25 V
1.30 V
1.35 V
1.40 V
1.45 V
1.50 V
1.55 V
1.60 V
1.65 V
1.70 V
1.75 V
1.80 V
1.85 V
1.90 V
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
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DA9070
Ultra-Low Quiescent Current PMIC
0x1B
1.95 V
0x1C (POR) 2.00 V
0x1D
0x1E
0x1F
2.05 V
2.10 V
Reserved
Table 77: Register VOUT_BUCK_CFG
Address
Register Name
POR Value
Buck config
0x0031
VOUT_BUCK_CFG 0x00
7
6
5
4
3
2
1
0
Reserved
Reserved
BUCK_PD_CFG2
Reserved 0
Reserved
Reserved
SEL_ILIM_DLT<1:0>
Field Name
Bits
POR
Description
Output discharge enable at buck disable
Value Description
0x0 (POR) Enable
0x1 Disable
BUCK_PD_CFG2
[5]
0x0
Buck peak current limit setting
Value Description
0x0 (POR) Default -50mA
SEL_ILIM_DLT
[1:0]
0x0
0x1
0x2
0x3
Default current limit
Default +50mA
Default +100mA
Datasheet
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DA9070
Ultra-Low Quiescent Current PMIC
Table 78: Register VOUT_LS_LDO0
Address
Register Name
POR Value
LS_LDO_0 control
0x0032
VOUT_LS_LDO0
0x24
7
6
5
4
3
2
1
0
EN_LS_LDO_0
Reserved
LS_LDO_0<5:0>
Field Name
Bits
POR
Description
EN_LS_LDO_0
[7]
0x0
LS_LDO_0 enable. LDO becomes active 20ms after LDO0 gets enabled.
LDO0 voltage setting, can't be written when LS_LDO0 is enabled.
0.8 V to 1.6 V in 25 mV steps and 1.6 V to 3.15 V in 50 mV steps.
Value
0x0
Description
0.8
0x1
0.825
0.85
0x2
0x3
0.875
0.9
0x4
LS_LDO_0
[5:0]
0x24
0x5
0.925
0.95
0x6
0x7
0.975
1
0x8
0x9
1.025
1.05
0x0A
0x0B
1.075
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DA9070
Ultra-Low Quiescent Current PMIC
0x0C
1.1
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
1.125
1.15
1.175
1.2
1.225
1.25
1.275
1.3
1.325
1.35
1.375
1.4
1.425
1.45
1.475
1.5
1.525
1.55
1.575
1.6
1.65
1.7
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Ultra-Low Quiescent Current PMIC
0x23
0x24 (POR) 1.8
1.85
1.75
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
1.9
1.95
2
2.05
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.45
2.5
2.55
2.6
2.65
2.7
2.75
2.8
2.85
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DA9070
Ultra-Low Quiescent Current PMIC
0x3A
2.9
0x3B
0x3C
0x3D
0x3E
0x3F
2.95
3
3.05
3.1
3.15
Table 79: Register VOUT_LS_LDO1
Address
Register Name
POR Value
LS_LDO_1 control
0x0033
VOUT_LS_LDO1
0x28
7
6
5
4
3
2
1
0
EN_LS_LDO_1
Reserved
LS_LDO_1<5:0>
Field Name
Bits
POR
Description
EN_LS_LDO_1
[7]
0x0
LS_LDO_1 enable. LDO becomes active 20ms after LS_LDO_1 gets enabled.
LDO1 voltage setting, can't be written when LS_LDO1 is enabled.
0.8 V to 2.4 V in 50 mV steps and 2.4 V to 3.3 V in 75 mV steps.
Value
0x0
Description
0.8
0.85
0.9
0.95
1
LS_LDO_1
[5:0]
0x28
0x1
0x2
0x3
0x4
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DA9070
Ultra-Low Quiescent Current PMIC
0x5
0x6
0x7
0x8
0x9
1.05
1.1
1.15
1.2
1.25
1.3
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
1.35
1.4
1.45
1.5
1.55
1.6
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2
2.05
2.1
2.15
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Ultra-Low Quiescent Current PMIC
0x1C
2.2
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
2.25
2.3
2.35
2.4
2.475
2.55
2.625
2.7
2.775
2.85
2.925
0x28 (POR) 3
0x29
0x2A
0x2B
0x2C
0x2D
0x3F
3.075
3.15
3.225
3.3
Reserved
Reserved
Table 80: Register VOUT_LS_LDO2
Address
Register Name
POR Value
LS_LDO_2 control
0x0034
VOUT_LS_LDO2
0x14
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DA9070
Ultra-Low Quiescent Current PMIC
7
6
5
4
3
2
1
0
EN_LS_LDO_2
Reserved
LS_LDO_2<5:0>
Field Name
Bits
POR
Description
EN_LS_LDO_2
[7]
0x0
LS_LDO_2 enable. LDO becomes active 20ms after LS_LDO_2 gets enabled.
LDO2 voltage setting, can't be written when LS_LDO2 is enabled.
0.8 V to 2.4 V in 50 mV steps and 2.4 V to 3.3 V in 75 mV steps.
Value
0x0
Description
0.8
0x1
0.85
0.9
0x2
0x3
0.95
1
0x4
0x5
1.05
1.1
0x6
LS_LDO_2
[5:0]
0x14
0x7
1.15
1.2
0x8
0x9
1.25
1.3
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
1.35
1.4
1.45
1.5
1.55
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DA9070
Ultra-Low Quiescent Current PMIC
0x10
1.6
0x11
0x12
0x13
1.65
1.7
1.75
0x14 (POR) 1.8
1.85
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
1.9
1.95
2
2.05
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.475
2.55
2.625
2.7
2.775
2.85
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Ultra-Low Quiescent Current PMIC
0x27
2.925
3
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x3F
3.075
3.15
3.225
3.3
Reserved
Reserved
Table 81: Register VOUT_LS_LDO_CFG
Address
Register Name
POR Value
LS_LDO_CFG
0x0035
VOUT_LS_LDO_CFG0x00
7
6
5
4
3
2
1
0
Reserved
SEL_FULLON_2
SEL_FULLON_1
SEL_FULLON_0
Reserved
SEL_LDSW_2
SEL_LDSW_1
SEL_LDSW_0
Field Name
Bits
POR
Description
LS_LDO2 current limit enable, can't be written when LS_LDO2 is enabled.
Value Description
0x0 (POR) Enable
0x1 Disable
SEL_FULLON_2
[6]
0x0
0x0
LS_LDO1 current limit enable, can't be written when LS_LDO1 is enabled.
Value Description
0x0 (POR) Enable
SEL_FULLON_1
[5]
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Ultra-Low Quiescent Current PMIC
0x1
Disable
LS_LDO0 current limit enable, can't be written when LS_LDO0 is enabled.
Value Description
0x0 (POR) Enable
0x1 Disable
SEL_FULLON_0
SEL_LDSW_2
SEL_LDSW_1
SEL_LDSW_0
[4]
[2]
[1]
[0]
0x0
0x0
0x0
0x0
LS_LDO2 function select, can't be written when LS_LDO2 is enabled.
Value Description
0x0 (POR) LDO
0x1
LDSW
LS_LDO1 function select, can't be written when LS_LDO1 is enabled.
Value
Description
0x0 (POR) LDO
0x1
LDSW
LS_LDO0 function select, can't be written when LS_LDO0 is enabled.
Value
Description
0x0 (POR) LDO
0x1
LDSW
Table 82: Register VOUT_BOOST
Address
Register Name
POR Value
BOOST control
0x0036
VOUT_BOOST
0x27
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DA9070
Ultra-Low Quiescent Current PMIC
7
6
5
4
3
2
1
0
BOOST_EN
BOOST_VOUT<6:0>
Field Name
Bits
POR
Description
BOOST_EN
[7]
0x0
Boost enable
Boost voltage setting, can be written when boost is disabled or being disabled by the same write access.
4.5 V to 9 V in 125 mV steps and 9 V to 18 V in 250 mV steps.
Writing 0x1A or lower becomes writing 0x1B.
Value
0x0
Description
Reserved
Reserved
9
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
9.25
9.5
9.75
BOOST_VOUT
[6:0]
0x27
10
10.25
10.5
10.75
11
11.25
11.5
11.75
0x27 (POR) 12
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Ultra-Low Quiescent Current PMIC
0x28
12.25
12.5
12.75
13
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
13.25
13.5
13.75
14
14.25
14.5
14.75
15
15.25
15.5
15.75
16
16.25
16.5
16.75
17
17.25
17.5
17.75
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Ultra-Low Quiescent Current PMIC
0x3F
18
0x40
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
Reserved
Reserved
4.5
4.625
4.75
4.875
5
5.125
5.25
5.375
5.5
5.625
5.75
5.875
6
6.125
6.25
6.375
6.5
6.625
6.75
6.875
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DA9070
Ultra-Low Quiescent Current PMIC
0x6F
7
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
7.125
7.25
7.375
7.5
7.625
7.75
7.875
8
8.125
8.25
8.375
8.5
8.625
8.75
8.875
9
Table 83: Register VOUT_BOOST_CFG0
Address
Register Name
POR Value
BOOST config0
0x0037
VOUT_BOOST_CFG0 0x00
7
6
5
4
3
2
1
0
TSS_SEL<1:0>
TPCHG_SEL<1:0>
Reserved
Reserved
Reserved
BST_CFG_FREQ
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Ultra-Low Quiescent Current PMIC
Field Name
Bits
POR
Description
BOOST Tss select, can't be written when boost is enabled.
Value
Description
0x0 (POR) 3 ms
TSS_SEL
[7:6]
0x0
0x1
0x2
0x3
6 ms
9 ms
12 ms
BOOST Tpchg select, can't be written when boost is enabled.
Value Description
0x0 (POR) 2 ms
TPCHG_SEL
[5:4]
0x0
0x1
0x2
0x3
4 ms
8 ms
16 ms
Switching frequency select, can't be written when boost is enabled.
Value Description
0x0 (POR) 1 MHz
0x1 2 MHz
BST_CFG_FREQ
[0]
0x0
Table 84: Register VOUT_BOOST_CFG1
Address
Register Name
POR Value
BOOST config1
0x0038
VOUT_BOOST_CFG1 0xA6
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Ultra-Low Quiescent Current PMIC
7
6
5
4
3
2
1
0
BST_CFG_OCS<1:0>
BST_CFG_OC<1:0>
Reserved 0
Reserved 1
Reserved 1
Reserved 0
Field Name
Bits
POR
Description
Over current protection during soft start, can't be written when boost is enabled.
Value
0x0
Description
510 mA
BST_CFG_OCS
[7:6]
0x2
0x1
650 mA
0x2 (POR) 780 mA
0x3 920 mA
Over current protection at normal operation, can't be written when boost is enabled.
Value
0x0
Description
0.9 A
BST_CFG_OC
[5:4]
0x2
0x1
1.3 A
0x2 (POR) 1.7 A
0x3 2.1 A
Table 85: Register VOUT_BOOST_CFG2
Address
Register Name
POR Value
BOOST config2
0x0039
VOUT_BOOST_CFG2 0x70
7
6
5
4
3
2
1
0
Reserved 0
Reserved 1
Reserved 1
BST_CFG_ANTI
BST_CFG_PCHGLMT<3:0>
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Ultra-Low Quiescent Current PMIC
Field Name
Bits
POR
Description
BST_CFG_ANTI
[4]
0x1
Anti ringing enable, can't be written when boost is enabled.
Pre-charge current limit, can't be written when boost is enabled.
Value
Description
0x0 (POR) x1
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
x2
x3
x4
x5
x6
x7
BST_CFG_PCHGLMT
[3:0]
0x0
x8
x9
x10
x11
x12
x13
x14
x15
x16
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Ultra-Low Quiescent Current PMIC
10.2.4.2
VOUT Opt Registers
Table 86: Register VOUT_BUCK_OPT0
Address
0x0050
Register Name
POR Value
BUCK_OPT0
VOUT_BUCK_OPT0 0x1B
7
6
5
4
3
2
1
0
Reserved 0
Field Name
Reserved 0
Reserved 0
Description
Reserved 1
Reserved 1
Reserved 0
DVC_STEP<1:0>
Bits
POR
DVC step control; 00: No DVC, 01: 50mV/0.5ms, 10: 50mV/1ms, 11: 50mV/2ms
Value
0x0
Description
No DVC
DVC_STEP
[1:0]
0x3
0x1
50mV/1ms
50mV/2ms
0x2
0x3 (POR) 50mV/4ms
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11 Package Information
11.1 Package Outlines
Figure 44: WLCSP-42 Package Outline Drawing
11.2 Moisture Sensitivity Level
The Moisture Sensitivity Level (MSL) is an indicator for the maximum allowable time period (floor
lifetime) in which a moisture sensitive plastic device, once removed from the dry bag, can be
exposed to an environment with a maximum temperature of 30 °C and a maximum relative humidity
of 60 % RH before the solder reflow process. The MSL classification is defined in Table 87.
The device package is qualified for MSL 1.
Table 87: MSL Classification
MSL Level
Floor Lifetime
Conditions
MSL 1
Unlimited
30 °C / 85 % RH
11.3 Soldering Information
Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can
be downloaded from http://www.jedec.org.
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12 Ordering Information
The ordering number consists of the part number followed by a suffix indicating the OTP variant (xx),
package type, and packing method. For details and availability, please consult Dialog
Semiconductor’s customer support portal or your local sales representative.
Table 88: Ordering Information
Part Number
DA9070-xxV32
DA9070-xxV36
Package
WLCSP
WLCSP
Size (mm)
2.97 x 2.66
2.97 x 2.66
Shipment Form
T&R
Pack Quantity
2000
90
Waffle
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Status Definitions
Revision
Datasheet Status
Product Status
Definition
1.<n>
Target
Development
This datasheet contains the design specifications for product development.
Specifications may be changed in any manner without notice.
2.<n>
3.<n>
Preliminary
Final
Qualification
Production
This datasheet contains the specifications and preliminary characterisation
data for products in pre-production. Specifications may be changed at any
time without notice in order to improve the design.
This datasheet contains the final specifications for products in volume
production. The specifications may be changed at any time in order to
improve the design, manufacturing and supply. Relevant changes will be
communicated via Customer Product Notifications.
4.<n>
Obsolete
Archived
This datasheet contains the specifications for discontinued products. The
information is provided for reference only.
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