DA9230-08VZ2 [DIALOG]

Ultra-Low Quiescent Current Buck;


型号：	DA9230-08VZ2
厂家：	Dialog Semiconductor
描述：	Ultra-Low Quiescent Current Buck
文件：	总47页 (文件大小：1844K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DA9230

Ultra-Low Quiescent Current Buck

General Description

DA9230 is an ultra-low quiescent current, high efficiency buck regulator in a compact I²C

configurable WLCSP package targeting battery powered applications needing highly efficient power

supplies.

The battery life of these devices is significantly improved due to the low quiescent current delivered

by DA9230 during operation and shutdown.

The buck regulator extends high light load efficiency down to 10 uA further extending battery life.

Dynamic Voltage Control in the Buck regulator facilitates optimization across the system power

modes enabling further improvement in System efficiency and battery life.

DA9230 provides multiple protection features and comes with the ability to monitor the events and

indicators in the GPO pin.

Suitable for space constrained applications, the DA9230 comes in a 1.65 mm x 1.25 mm, 12-pin

WLCSP package.

Key Features

■

300 mA buck regulator

■

I²C interface for device configuration and

control

□

750 nA total input current (buck enabled

no load)

■

Protection features and System Monitors

Up to 81% efficiency at 1.8 V output,

10 µA load currents

Small 1.65 mm x 1.25 mm, 12-pin WLCSP

package

Input voltage 2.5 V to 5.5 V(Minimum

2.75 V for start up)

□

Output voltage 0.6 V to 1.9 V

Dynamic Voltage Control (DVC)

Applications

■

Wearables – wrist wear, hearables

Smart devices - thermostats and door locks

Smoke detectors

■

Portable medical devices

Remote sensors

High efficiency, low power applications

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

1 of 47

DA9230

Ultra-Low Quiescent Current Buck

Contents

General Description ............................................................................................................................ 1

Key Features ........................................................................................................................................ 1

Applications ......................................................................................................................................... 1

Contents ............................................................................................................................................... 1

Figures.................................................................................................................................................. 3

Tables ................................................................................................................................................... 4

Terms and Definitions................................................................................................................... 6

Block and Application Diagrams ................................................................................................. 7

Pinout ............................................................................................................................................. 8

Absolute Maximum Ratings ....................................................................................................... 10

Recommended Operating Conditions....................................................................................... 11

ESD Ratings................................................................................................................................. 12

Electrical Characteristics ........................................................................................................... 13

Thermal Characteristics ............................................................................................................. 16

Typical Operating Characteristics............................................................................................. 17

9.1 Buck No Load Quiescent Current vs Temperature, Device is Switching............................ 17

9.2 RDSon vs Temperature ...................................................................................................... 17

9.3 Efficiency vs Load Current .................................................................................................. 18

9.4 Switching Frequency vs Load Current................................................................................ 19

9.5 Buck V_OUTRipple vs Load Current...................................................................................... 20

9.6 Buck V_OUTvs Load Current .................................................................................................. 21

9.7 Typical Mode Operation...................................................................................................... 22

9.8 Buck Load Transient Response.......................................................................................... 23

9.9 Buck Dynamic Voltage Control ........................................................................................... 25

9.10 Device Enable and Start up ................................................................................................ 26

10 Feature Descriptions................................................................................................................... 27

10.1 Chip Enable and Disable Through IC_EN .......................................................................... 27

10.2 VDD Under-Voltage Lockout............................................................................................... 27

10.3 Over-Temperature Protection ............................................................................................. 27

10.4 Buck Regulator.................................................................................................................... 27

10.4.1 Buck Output Voltage Programability.................................................................... 27

10.4.2 Start-up Operation ............................................................................................... 28

10.4.3 Power Saving Mode Operation............................................................................ 28

10.4.4 Dynamic Voltage Control..................................................................................... 29

10.4.5 Cycle-by-cycle Over-Current Protection.............................................................. 29

10.4.6 Output Over-Voltage Protection .......................................................................... 29

10.4.7 Output Under-Voltage Protection ........................................................................ 29

10.4.8 Automatic Output voltage Discharge................................................................... 29

10.4.9 Event Flag and Fault Control............................................................................... 30

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

2 of 47

DA9230

Ultra-Low Quiescent Current Buck

10.5 I²C Programing.................................................................................................................... 31

10.5.1 Interface Description............................................................................................ 31

10.5.2 Details of the I²C Protocol.................................................................................... 31

10.6 GPO Pin Function Programing ........................................................................................... 32

10.6.1 Power Good Indicator.......................................................................................... 32

10.6.2 Event Indicator..................................................................................................... 32

10.6.3 Reset Pulse Generation....................................................................................... 32

10.6.4 Always Pull-Down or Hi-Z.................................................................................... 32

11 Register Overview ....................................................................................................................... 33

11.1 Register Map....................................................................................................................... 33

11.1.1 Buck Control ........................................................................................................ 33

11.1.2 System Module.................................................................................................... 34

11.2 Register Definitions............................................................................................................. 34

11.2.1 Buck Control ........................................................................................................ 34

11.2.1.1

11.2.1.2

Event/Status/Mask Registers .......................................................... 34

User Registers................................................................................. 36

11.2.2 System Module.................................................................................................... 41

11.2.2.1

11.2.2.2

System Reset Registers .................................................................. 41

System ID Registers........................................................................ 42

12 Package Information................................................................................................................... 44

12.1 Package Outlines................................................................................................................ 44

12.2 Moisture Sensitivity Level.................................................................................................... 45

12.3 Soldering Information.......................................................................................................... 45

13 Ordering Information .................................................................................................................. 46

Contacting Dialog Semiconductor .................................................................................................. 47

Figures

Figure 1: Block Diagram........................................................................................................................ 7

Figure 2: DA9230 Application Diagram................................................................................................. 7

Figure 3: Pinout Diagram (Top View) .................................................................................................... 8

Figure 4: Buck V_OUT= 1.8 V ................................................................................................................ 17

Figure 5: Buck V_OUT= 0.9 V ................................................................................................................ 17

Figure 6: High-Side FET...................................................................................................................... 17

Figure 7: Low-Side FET....................................................................................................................... 17

Figure 8: Buck V_OUT= 1.9 V ................................................................................................................ 18

Figure 9: Buck V_OUT= 1.8 V ................................................................................................................ 18

Figure 10: Buck V_OUT= 1.2 V .............................................................................................................. 18

Figure 11: Buck V_OUT= 0.9 V .............................................................................................................. 18

Figure 12: Buck V_OUT= 0.6 V .............................................................................................................. 18

Figure 13: Buck V_OUT= 1.9 V .............................................................................................................. 19

Figure 14: Buck V_OUT= 0.9 V .............................................................................................................. 19

Figure 15: Buck V_OUT= 1.2 V .............................................................................................................. 19

Figure 16: Buck V_OUT= 0.6 V .............................................................................................................. 19

Figure 17: Buck V_OUT= 1.9 V .............................................................................................................. 20

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

3 of 47

DA9230

Ultra-Low Quiescent Current Buck

Figure 18: Buck V_OUT= 1.3 V .............................................................................................................. 20

Figure 19: Buck V_OUT= 0.9 V .............................................................................................................. 20

Figure 20: Buck V_OUT= 0.6 V .............................................................................................................. 20

Figure 21: Buck V_OUT= 1.9 V .............................................................................................................. 21

Figure 22: Buck V_OUT= 1.2 V .............................................................................................................. 21

Figure 23: Buck V_OUT= 0.9 V .............................................................................................................. 21

Figure 24: Buck V_OUT= 0.6 V .............................................................................................................. 21

Figure 25: Buck V_IN= 3.6 V, Buck V_OUT= 1.8 V, Buck I_LOAD= 1 mA................................................... 22

Figure 26: Buck V_IN= 3.6 V, Buck V_OUT= 1.8 V, Buck I_LOAD= 10 mA................................................. 22

Figure 27: Buck VIN = 3.6 V, Buck VOUT = 1.8 V, Buck I_LOAD= 100 mA........................................... 22

Figure 28: Buck V_IN= 3.6 V, Buck V_OUT= 1.8 V, Buck I_LOAD= 300 mA............................................... 22

Figure 29: Buck I_LOAD= 10 mA to 300 mA to 10 mA (0.3 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 1.8 V 23

Figure 30: Buck I_LOAD= 100 mA to 300 mA to 100 mA (0.2 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 1.8 V

............................................................................................................................................................. 23

Figure 31: Buck I_LOAD= 10 mA to 300 mA to 10 mA (0.3 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 1.2 V23

Figure 32: Buck I_LOAD= 100 mA to 300 mA to 100 mA (0.2 A/ µs); Buck V_IN= 3.6 V, Buck

V_OUT= 1.2 V......................................................................................................................................... 23

Figure 33: Buck I_LOAD= 10 mA to 300 mA to 10 mA (0.3 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 0.9 V23

Figure 34: Buck I_LOAD= 100 mA to 300 mA to 100 mA (0.2 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 0.9 V

............................................................................................................................................................. 23

Figure 35: Buck I_LOAD= 10 mA to 300 mA to 10 mA (0.3 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 0.6 V24

Figure 36: Buck I_LOAD= 100 mA to 300 mA to 100mA (0.2 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 0.6 V

............................................................................................................................................................. 24

Figure 37: Buck V_OUT0.6 V to 1.2 V; Buck V_IN= 3.6 V, Buck I_LOAD= 300 mA..................................... 25

Figure 38: Buck V_OUT1.2 V to 0.6 V; Buck V_IN= 3.6 V, Buck I_LOAD= 300 mA..................................... 25

Figure 39: Buck V_OUT1.3 V to 1.9 V; Buck V_IN= 3.6 V, Buck I_LOAD= 300 mA..................................... 25

Figure 40: Buck V_OUT1.9 V to 1.3 V; Buck V_IN= 3.6 V, Buck I_LOAD= 300 mA..................................... 25

Figure 41: Device Enable: Buck V_IN= 3.6 V, Buck V_OUT1.8 V, Buck I_LOAD= 300 mA......................... 26

Figure 42: V_OUTramp-up after Enabled (Zoom-in of Figure 41).......................................................... 26

Figure 43: I²C Serial Interface Pins ..................................................................................................... 31

Figure 44: I²C Start and Stop Conditions ............................................................................................ 31

Figure 45: Package Outline Drawing................................................................................................... 44

Tables

Table 1: Pin Description ........................................................................................................................ 8

Table 2: Pin Type Definition .................................................................................................................. 9

Table 3: Absolute Maximum Ratings................................................................................................... 10

Table 4: Recommended Operating Conditions ................................................................................... 11

Table 5: Input Current.......................................................................................................................... 13

Table 6: Buck Output........................................................................................................................... 13

Table 7: GPO - Electrical performance ............................................................................................... 14

Table 8: Analog Core - Electrical performance ................................................................................... 14

Table 9: I2C interface .......................................................................................................................... 15

Table 10: Thermal Characteristics ...................................................................................................... 16

Table 11: Buck Output Voltage Settings ............................................................................................. 27

Table 12: GPO as Power Good Indicator............................................................................................ 32

Table 13: Event/Status/Mask and User Registers .............................................................................. 33

Table 14: System Reset Registers...................................................................................................... 34

Table 15: Register EVENT .................................................................................................................. 34

Table 16: Register STATUS................................................................................................................ 35

Table 17: Register MASK.................................................................................................................... 36

Table 18: Register GPO ...................................................................................................................... 36

Table 19: Register BUCK .................................................................................................................... 37

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

4 of 47

DA9230

Ultra-Low Quiescent Current Buck

Table 20: Register BUCK_CFG .......................................................................................................... 39

Table 21: Register FAUL_CTL ............................................................................................................ 40

Table 22: Register PIN_MONITOR..................................................................................................... 41

Table 23: Register SYS_RST_EVENT................................................................................................ 41

Table 24: Register SYS_SRST ........................................................................................................... 41

Table 25: Register SYS_DEVICE_ID................................................................................................. 42

Table 26: Register SYS_VARIANT_ID............................................................................................... 42

Table 27: Register SYS_CONFIG_ID ................................................................................................ 43

Table 28: MSL Classification............................................................................................................... 45

Table 29: Ordering Information ........................................................................................................... 46

Table 30: OTP List............................................................................................................................... 46

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

5 of 47

DA9230

Ultra-Low Quiescent Current Buck

Terms and Definitions

CDM

Charged Device Model

Direct Current

DCM

FET

Discontinuous Conduction Mode

Field Effect Transistor

NMOS

OTP

N-channel Metal-Oxide-Semiconductor

One-Time Programable (memory)

Power Management IC

PMIC

PMOS

R/W

P-channel Metal-Oxide-Semiconductor

Read/Write

SCL

Serial CLock SDA

T&R

Tape and Reel

UVLO

WLCSP

Under-Voltage LockOut

Wafer-Level Chip-Scale Package

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

6 of 47

DA9230

Ultra-Low Quiescent Current Buck

2 Block and Application Diagrams

VDD_SYS

VDD

Buck Control

Const

T_OFF

Comp

IC_EN

Logic

Drivers

Peak

Current

VDAC

PGND

SDA

SCL

I2C

Interface

VBUCK_SNS

Fault Handling

VBUCK Over-

Voltage

UVLO

VBUCK Over-

Current

Over-

Temperature

GPO

Control

VBUCK

Under-Voltage

GPO

DA9230

GND

Figure 1: Block Diagram

Buck V_IN: 2.5 to 5.5 V

(Minimum 2.75V for start up)

4.7 µF

1 µF

VDD

VDD_SYS

Buck V_OUT

2.2 µH

MCU/

System I/O

10 µF

PGND

DA9230

SDA

SCL

GPO

VBUCK_SNS

HOST

IC_EN

GND

Figure 2: DA9230 Application Diagram

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

7 of 47

DA9230

Ultra-Low Quiescent Current Buck

Pinout

VDD_SYS

PGND

ESD

SDA

SCL

GPO

VBUCK_SNS

ESD

GND

ESD

IC_EN

VDD

Figure 3: Pinout Diagram (Top View)

Table 1: Pin Description

Pin #

Pin Name

Type

(See Table 2)

Drive Reset

(mA) State

Description

VDD_SYS

Buck V_IN

AIO

DIO

Buck switch node

Buck ground

PGND

SDA

I²C serial data

General purpose output

Buck V_OUT/feedback voltage

I²C serial clock

No connection

Analog ground

Chip enable

GPO

VBUCK_SNS

SCL

GND

IC_EN

No connection

Analog V_IN

VDD

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

8 of 47

DA9230

Ultra-Low Quiescent Current Buck

Table 2: Pin Type Definition

Pin Type

Description

Pin Type

Description

Digital Input

Analog Input

Digital Output

Analog Output

DIO

Digital Input/Output

Digital Input/Output open Drain

Fixed pull-up resistor

Fixed pull-down resistor

AIO

Analog Input/Output

Back drive Protection

Switchable pull-up resistor

Switchable pull-down resistor

DIOD

SPU

SPD

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

9 of 47

DA9230

Ultra-Low Quiescent Current Buck

Absolute Maximum Ratings

Table 3: Absolute Maximum Ratings

Symbol

T_STG

Description

Conditions

Min

-40

Max

125

Unit

°C

Storage temperature

T_J

Operating junction

temperature

°C

VDD

Analog V_INpin

Power V_INpin

Tied to VDD_SYS

Tied to VDD

-0.3

VDD_SYS

I/O pins

Maximum voltage

I/O pin voltage ≤ VDD

Stresses beyond those listed under Absolute maximum ratings may cause permanent damage to the device.

These are stress ratings only, so functional operation of the device at these or any other conditions beyond

those indicated in the operational sections of the specification are not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

10 of 47

DA9230

Ultra-Low Quiescent Current Buck

Recommended Operating Conditions

Table 4: Recommended Operating Conditions

Parameter Description

VDD Analog V_IN

Conditions

Min

Typ

Max

Unit

Tied to VDD_SYS

2.5

5.5

Note 1

VDD_SYS Power V_IN

Tied to VDD

2.5

5.5

Note 1

I_{OUT_BUCK}

Buck load Current

Output current from SW pin,

continuous DC current

300

Note 1 Requires minimum 2.75V for start-up. Once started, input voltage can go down to 2.5V.

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

11 of 47

DA9230

Ultra-Low Quiescent Current Buck

ESD Ratings

Parameter

Description

Conditions

Value

Unit

V_ESD

Electrostatic discharge

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001

± 2000

Note 1

Charged device model (CDM), per

JEDEC specification JESD22-

C101

± 500

Note 2

Note 1 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD

control process.

Note 2 JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD

control process.

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

12 of 47

DA9230

Ultra-Low Quiescent Current Buck

Electrical Characteristics

VDD = VDD_SYS = 3.6 V, T_J= -40C to 85C. Typical values are at T_J= 25°C (unless otherwise

noted).

Table 5: Input Current

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Electrical performance

-40 °C < T_J< 85 °C

Buck enabled and regulating,

no load

2.5 V ≤ V_{VDD_SYS}≤ 5.5 V

V_BUCK= 1.8 V

I_{Q_BUCK_ON}Buck no load quiescent

0.75

3.5

μA

current

_NO_LD

Table 6: Buck Output

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Electrical performance

On resistance of PMOS

pass device

V_{VDD_SYS}= 3.6 V

I_OUT= 50 mA

R_{ON_PMOS}

R_{ON_NMOS}

R_{SYS_DHCG}

600

300

800

450

mΩ

On resistance of NMOS

pass device

V_{VDD_SYS}= 3.6 V

I_OUT= 50 mA

MOSFET on-resistance for V_{VDD_SYS}= 3.6 V

buck discharge

I_OUT= -10 mA into VOUT pin

V_{VDD_SYS}= 3.6 V

V_BUCK= 1.8 V

I_OUT= 0 A from BUCK_EN =

1 to switching start

t_START

Buck start-up time

I_{LIM_SW_PM}

V_{VDD_SYS}= 3.6 V

V_BUCK= 1.8 V

SW current limit PMOS

600

270

Off time in continuous

conduction mode

t_OFF

V_BUCK= 1.8 V

Switching frequency in

continuous conduction

mode

f_SW

MHz

Maximum DC output

current

I_{OUT_MAX}

300

0.6

I_{LIM_PMOS_}PMOS switch current limit

Current limit is reduced

during softstart

350

during softstart

SOFTSTART

V_{OUT_VBUC}

K_SNS

Programable range, 50 mV

steps

Buck output voltage range

1.9

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

13 of 47

DA9230

Ultra-Low Quiescent Current Buck

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HI programable range, 50 mV

steps

V_{OUT_RANGE_HI}= 1

V_{OUT_VBUC}

K_SNS_HI

Buck output voltage range

1.3

1.9

LO programable range,

50 mV steps

V_{OUT_RANGE_HI}= 0

V_{OUT_VBUC}

K_SNS_LO

Buck output voltage range

0.6

1.3

2.5

V_{VDD_SYS}= 5 V

PFM mode

I_OUT= 10 mA

V_{OUT_RANGE_HI}= 1

V_BUCK= 1.8 V

V_{OUT_VBUC}Buck output voltage

K_ACC

-2.5

accuracy

V_{OUT_PWM}DC output voltage load

V_BUCK= 1.8 V

Load range

0.01

0.1

%/mA

%/V

regulation in CCM mode

_LD2

V_BUCK= 1.8 V

I_OUT= 200 mA

V_DDrange

V_{OUT_PWM}DC output voltage line

regulation in CCM mode

_LINE2

Table 7: GPO - Electrical performance

Symbol

R_PD

Parameter

Conditions

Min

Typ

Max

Unit

GPO pull-down resistance

GPO Output high voltage

GPO Output low voltage

V_{VDD_SYS}= 3.6 V

V_PULLUP= 1.8 V

V_OH

1.4

V_OL

0.4

Table 8: Analog Core - Electrical performance

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Thermal shut-down

hysteresis

T_{SHDN_HYS}

°C

Thermal shut-down

threshold

T_{SHDN_THR}

125

°C

Under-voltage lockout

threshold

V_{TH_UVLO}

Input voltage falling

Input voltage rising.

Input voltage rising

2.4

2.5

V_{TH_UVLO_}Under-voltage lockout

2.75

threshold rising.

RISE

Under-voltage lockout

V_{HYS_UVLO}

200

hysteresis

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

14 of 47

DA9230

Ultra-Low Quiescent Current Buck

Table 9: I2C interface

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Electrical performance

I²C bus specification

standard and fast mode

frequency support

f_{I2C_CLK}

100

1.4

400

kHz

Input high threshold level

for SDA and SCL

V_{IN_HI_THR}

Input low threshold level for

SDA and SCL

V_{IN_LO_THR}

0.4

V_{OUT_LO_T}Output low threshold level

for SDA

High-level leakage current

I_{LKG_HILVL}

V_PU= V_VDD

SDA and SCL

μA

for SDA and SCL.

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

15 of 47

DA9230

Ultra-Low Quiescent Current Buck

Thermal Characteristics

Table 10: Thermal Characteristics

Parameter

Description

Conditions

Typ

Unit

R_{TH_JA}

Junction-to-ambient thermal

resistance

JEDEC 6-layer pcb, no airflow

73.2

°C/W

Ψ_JT

Junction-to-top characterization

parameter

JEDEC 6-layer pcb, no airflow

6.66

34.8

°C/W

R_{TH_JB}

Junction-to-board thermal

resistance

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

16 of 47

DA9230

Ultra-Low Quiescent Current Buck

Typical Operating Characteristics

Test Circuit of Figure 2, Buck V_IN= VDD_SYS = VDD, L=2.2 µH (170 mΩ), T_A= 25°C, unless

specified otherwise.

9.1 Buck No Load Quiescent Current vs Temperature, Device is Switching

Figure 4: Buck V_OUT= 1.8 V

Figure 5: Buck V_OUT= 0.9 V

9.2 RDSon vs Temperature

Figure 6: High-Side FET

Figure 7: Low-Side FET

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

17 of 47

DA9230

Ultra-Low Quiescent Current Buck

9.3 Efficiency vs Load Current

Figure 9: Buck V_OUT= 1.8 V

Figure 8: Buck V_OUT= 1.9 V

Figure 10: Buck V_OUT= 1.2 V

Figure 11: Buck V_OUT= 0.9 V

Figure 12: Buck V_OUT= 0.6 V

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

18 of 47

DA9230

Ultra-Low Quiescent Current Buck

9.4 Switching Frequency vs Load Current

Figure 13: Buck V_OUT= 1.9 V

Figure 15: Buck V_OUT= 1.2 V

Figure 14: Buck V_OUT= 0.9 V

Figure 16: Buck V_OUT= 0.6 V

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

19 of 47

DA9230

Ultra-Low Quiescent Current Buck

9.5 Buck V_OUTRipple vs Load Current

Figure 17: Buck V_OUT= 1.9 V

Figure 18: Buck V_OUT= 1.3 V

Figure 19: Buck V_OUT= 0.9 V

Figure 20: Buck V_OUT= 0.6 V

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

20 of 47

DA9230

Ultra-Low Quiescent Current Buck

9.6 Buck V_OUTvs Load Current

Figure 21: Buck V_OUT= 1.9 V

Figure 22: Buck V_OUT= 1.2 V

Figure 23: Buck V_OUT= 0.9 V

Figure 24: Buck V_OUT= 0.6 V

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

21 of 47

DA9230

Ultra-Low Quiescent Current Buck

9.7 Typical Mode Operation

Buck Vout

20mV/div

Buck Vout

20mV/div

2V/div

300mA/div

100µs/div

5µs/div

Figure 25: Buck V_IN= 3.6 V, Buck V_OUT= 1.8 V,

Buck I_LOAD= 1 mA

Figure 26: Buck V_IN= 3.6 V, Buck V_OUT= 1.8 V,

Buck I_LOAD= 10 mA

Buck Vout

20mV/div

Buck Vout

20mV/div

2V/div

300mA/div

500ns/div

Figure 27: Buck VIN = 3.6 V, Buck VOUT = 1.8 V,

Buck I_LOAD= 100 mA

Figure 28: Buck V_IN= 3.6 V, Buck V_OUT= 1.8 V,

Buck I_LOAD= 300 mA

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

22 of 47

DA9230

Ultra-Low Quiescent Current Buck

9.8 Buck Load Transient Response

Buck Vout

50mV/div

Buck Vout

50mV/div

ILoad

300mA/div

ILoad

300mA/div

200mA/div

10µs/div

Figure 29: Buck I_LOAD= 10 mA to 300 mA to 10 mA

(0.3 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 1.8 V

Figure 30: Buck I_LOAD= 100 mA to 300 mA to 100 mA

(0.2 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 1.8 V

Buck Vout

50mV/div

Buck Vout

50mV/div

ILoad

300mA/div

200mA/div

10µs/div

Figure 31: Buck I_LOAD= 10 mA to 300 mA to 10 mA

(0.3 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 1.2 V

Figure 32: Buck I_LOAD= 100 mA to 300 mA to 100 mA

(0.2 A/ µs); Buck V_IN= 3.6 V, Buck V_OUT= 1.2 V

Buck Vout

50mV/div

ILoad

300mA/div

200mA/div

10µs/div

Figure 33: Buck I_LOAD= 10 mA to 300 mA to 10 mA

(0.3 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 0.9 V

Figure 34: Buck I_LOAD= 100 mA to 300 mA to 100 mA

(0.2 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 0.9 V

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

23 of 47

DA9230

Ultra-Low Quiescent Current Buck

Buck Vout

50mV/div

Buck Vout

50mV/div

ILoad

300mA/div

200mA/div

10µs/div

Figure 35: Buck I_LOAD= 10 mA to 300 mA to 10 mA

(0.3 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 0.6 V

Figure 36: Buck I_LOAD= 100 mA to 300 mA to 100mA

(0.2 A/µs); Buck V_IN= 3.6 V, Buck V_OUT= 0.6 V

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

24 of 47

DA9230

Ultra-Low Quiescent Current Buck

9.9 Buck Dynamic Voltage Control

SDA

2V/div

SDA

2V/div

Buck Vout

200mV/div

Buck Vout

200mV/div

2V/div

5ms/div

Figure 37: Buck V_OUT0.6 V to 1.2 V;

Buck V_IN= 3.6 V, Buck I_LOAD= 300 mA

Figure 38: Buck V_OUT1.2 V to 0.6 V;

Buck V_IN= 3.6 V, Buck I_LOAD= 300 mA

SDA

2V/div

SDA

2V/div

Buck Vout

400mV/div

Buck Vout

400mV/div

2V/div

5ms/div

Figure 39: Buck V_OUT1.3 V to 1.9 V;

Buck V_IN= 3.6 V, Buck I_LOAD= 300 mA

Figure 40: Buck V_OUT1.9 V to 1.3 V;

Buck V_IN= 3.6 V, Buck I_LOAD= 300 mA

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

25 of 47

DA9230

Ultra-Low Quiescent Current Buck

9.10 Device Enable and Start up

IC_EN

2V/div

IC_EN

2V/div

Buck Vout

1V/div

Buck Vout

1V/div

300mA/div

5ms/div

10µs/div

Figure 41: Device Enable:

Buck V_IN= 3.6 V, Buck V_OUT1.8 V,

Buck I_LOAD= 300 mA

Figure 42: V_OUTramp-up after Enabled

(Zoom-in of Figure 41)

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

26 of 47

DA9230

Ultra-Low Quiescent Current Buck

10 Feature Descriptions

10.1 Chip Enable and Disable Through IC_EN

DA9230 features a dedicated IC_EN pin to enable and disable the chip. When IC_EN = high, the

device is turned on. IC_EN voltage should not exceed VDD_SYS voltage on the device. When

EN = low, the device is shut down completely, including I²C communications.

10.2 VDD Under-Voltage Lockout

DA9230 features an under-voltage lockout (UVLO) on VDD. When VDD falls below UVLO falling

threshold, buck is disabled, see Section 10.4.9 for fault behaviour and control, A VIN_UV_Event will

be flagged if it is not masked. When VDD rises above the UVLO rising threshold, the device will be

alive. VDD should be always tied to VDD_SYS on the PCB board so both VDD and VDD_SYS will

share the same UVLO protection.

10.3 Over-Temperature Protection

DA9230 also features an on-Chip over-temperature protection (TSD). The die junction temperature is

monitored when buck is in continuous current Mode. When the junction temperature is higher than

the thermal shutdown threshold, buck is disabled to prevent the device being damaged by over-

heating, see Section 10.4.9 for fault behavior and control. An OT_Event will be flagged if it is not

masked.

10.4 Buck Regulator

DA9230 includes a nano-ampere standby buck regulator with an adjustable output voltage, Dynamic

Voltage Scaling capability and a maximum load current of 300 mA. It also has power saving mode

operation and different protection features.

10.4.1 Buck Output Voltage Programability

The DA9230 buck regulator can be set to two different ranges based on the value of

VOUT_RANGE_HI. The value of BUCK_VOUT<4:0> is locked to a certain range based on the value

of VOUT_RANGE_HI, and VOUT_RANGE_HI can only be changed while the buck is disabled. The

buck can be set to the output voltages shown in Table 11. If a command is received outside of the

allowable range (that is above 1.3 V for VOUT_RANGE_HI = 0 or below 1.3 V for

VOUT_RANGE_HI = 1), digital will force the value of BUCK_VOUT<3:0> to 01110 (1.3 V).

Table 11: Buck Output Voltage Settings

VOUT_RANGE_HI

BUCK_VOUT<4:0>

00000

Buck Output Voltage (V)

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

00001

00010

00011

00100

00101

00110

00111

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

27 of 47

DA9230

Ultra-Low Quiescent Current Buck

VOUT_RANGE_HI

BUCK_VOUT<4:0>

Buck Output Voltage (V)

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

0 or 1

10.4.2 Start-up Operation

DA9230 buck integrates a start-up circuit to minimize output voltage over-shoot and input voltage

drop during start-up. When writing 1 to BUCK_EN (Bit 7 of Reg0x05), the buck is enabled and starts

switching after a typical delay time of 3 ms. During start-up, the cycle-by-cycle current limit is reduced

to limit inrush current.

10.4.3 Power Saving Mode Operation

DA9230 buck regulator features power saving mode that greatly reduces the quiescent current when

device has very light load condition. When load decreases, buck regulator enters discontinuous

mode and operates with Pulse Frequency Modulation (PFM). The low-side FET will be turned off

based on a zero-crossing comparator to prevent negative inductor current flowing through the FET

which can result in additional conduction loss. If both FETs remain in the OFF state for a certain

delay time after inductor current crosses zero, the device will enter power saving mode. In power

saving mode, DA9230 shuts down most of the internal circuitry to save current consumption. The

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

28 of 47

DA9230

Ultra-Low Quiescent Current Buck

lighter the load, the longer the duration of power saving mode will be, to achieve the lowest quiescent

current and improve light load efficiency.

10.4.4 Dynamic Voltage Control

DA9230 buck regulator has dynamic voltage control (DVC) feature which allows the buck output

voltage to track the internal reference voltage when it changes at a rate of 50 mV/2 ms. Since the

buck output voltage can only be changed within an allowable range while still keeping the buck

enabled, DVC also follows the same behaviour. The DVC is done via I²C, whereby the buck output

voltage setting is stepped in 50 mV steps within either the low range or high range. Each voltage step

lasts for 2 ms.

10.4.5 Cycle-by-cycle Over-Current Protection

For the Over-current Protection (OCP) in DA9230, the peak current through high-side FET is

monitored cycle-by-cycle. When the sensed current exceeds the pre-set current limit, the high-side

FET will be turned OFF immediately to limit the inductor current. The high-side FET will be turned on

again after the constant-off time expires. If the OC condition persists for 64 µs, buck will be forced off

and buck output will be pull-down until the fault clears, see Section 10.4.9 for fault behavior and

control and Section 10.4.8 for output voltage discharge and control. An OC_BUCK_Event will be

flagged if it is not masked.

10.4.6 Output Over-Voltage Protection

DA9230 features an output over-voltage protection (OVP) to protect the load from damage. When

both IC_EN and BUCK_EN are high and the buck output voltage is 200 mV greater than the internal

reference voltage, the high side FET is immediately OFF, see Section 10.4.9 for fault behavior and

control. Then the internal buck output discharge FET will be turned on to discharge buck output

capacitor, see Section 10.4.8 for output voltage discharge and control. An OV_BUCK_Event will be

flagged if it is not masked. Buck will remain off and buck output will be pull-down until the fault is

cleared.

10.4.7 Output Under-Voltage Protection

When buck output short happens, inductor current will increase until the peak reaches the cycle-by-

cycle current limit. Then the high-side FET turns OFF and low-side FET turns on. Since buck output

is shorted, inductor current slope is very small during low-side FET on time. The inductor current

could gradually go higher and higher. To effectively prevent the inductor current running away at V_OUT

short condition, buck V_OUTis also monitored. If over-current condition happens and buck V_OUTdrops

400 mV below the reference voltage, the buck regulator will be shut off immediately and an

UV_BUCK_Event will be flagged if it is not masked, see Section 10.4.9 for fault behavior and control.

10.4.8 Automatic Output voltage Discharge

To speed up the discharging of buck output capacitor and ensure a safer start-up next time, the buck

regulator provides automatic output voltage discharge when IC_EN is pulled low or buck shutdown

caused by any fault. Automatic output discharge when buck is forced OFF by fault needs to set

BUCK_EN = 0 needs to set register bit BUCK_PD_CFG2 = 0. The output of the buck regulator is

discharged through VBUCK_SNS pin and an internal buck output discharge FET with typical 33 Ω

resistance.

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

29 of 47

DA9230

Ultra-Low Quiescent Current Buck

10.4.9 Event Flag and Fault Control

DA9230 has the flexibility for customers to control the behavior of buck when there is a fault

condition. There are five register bits (UVLO_FRC_DIS, TSD_FRC_DIS, OV_DIS_BUCK,

OC_BUCK_EVENT, SC_DIS_BUCK) controlling whether the buck will be disabled when the

corresponding fault condition happens. In addition, users can choose whether to mask or unmask the

event flag when the fault condition happens.

When there is a VDD Under-voltage condition, buck will be forced OFF if UVLO_FRC_DIS = 1. Buck

will remain alive if UVLO_FRC_DIS = 0. During the VDD Under-voltage condition, the event register

bit VIN_UV_EVENT = 1 if the corresponding mask register bit M_VIN_UV is set to 0 otherwise

VIN_UV_EVENT = 0.

When there is an Over-Temperature fault inside the device, buck will be forced OFF if

TSD_FRC_DIS = 1. If TSD_FRC_DIS = 0, buck will remain alive. During the over-temperature

condition, the event register bit OT_EVENT = 1.

When there is an over-voltage fault at buck output, buck will be forced OFF if OV_DIS_BUCK = 1.

Buck will continue switching if OV_DIS_BUCK = 0. During the fault, OV_BUCK_EVENT is set to 1 if

M_OV_BUCK_EVENT = 0 otherwise OV_BUCK_EVENT = 0.

When the over-current condition in buck persists for 64 µs and M_OC_BUCK_EVENT is set to 0,

OC_BUCK_EVENT will be set to 1. If OC_DIS_BUCK = 1, BUCK is forced disabled. If

OC_DIS_BUCK = 0, buck will continue switching during the over-current condition.

When there is a buck Output under-voltage condition and M_UV_BUCK_EVENT = 0,

UV_BUCK_EVENT is set to 1. If both buck output under-voltage and over-current condition exist and

SC_DIS_BUCK = 1, buck will be forced OFF. If SC_DIS_BUCK = 0, buck will continue switching

without shutting down by the under-voltage protection.

DA9230 also has a fault recovery mechanism that can be customized through the 3-bits

RCVRY_NUM. This value determines the fault recovery trial number for buck and is counted down

by every fault that triggers buck OFF. When RCVRY_NUM reaches 0, recovery trial is ended and

buck will remain OFF even if the buck enable signals are toggled HI. If RCVRY_NUM is set to 0x7,

there will be no count down on the recovery trial number and recovery trail will not be ended. Before

RCVRY_NUM reaches 0, buck will be recovered automatically if the fault condition disappears.

Event flags are not automatically cleared when the fault conditions disappear. They have to be

cleared by changing the values in register EVENT through I²C.

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

30 of 47

DA9230

Ultra-Low Quiescent Current Buck

10.5 I²C Programing

10.5.1 Interface Description

DA9230 includes an I²C compatible interface based on the following signals:

●

SCL: standard 400 kHz I²C bus serial clock generated by the Host processor

SDA: standard 400 kHz I²C bus serial address/data input output

SDA and SCL are open drain I/O terminals. The standard frequency of the I²C bus is 400 kHz in fast

mode or 100 kHz in slow mode.

SCL

Serial Interface

I2C

SDA

Figure 43: I²C Serial Interface Pins

The I²C bus is used to control most functions and change register values depending on the

application requirements. In active battery, the I²C circuitry is powered from the battery. The interface

maintains a proper operation as long as VDD_SYS is valid.

The device is compatible with the standard I²C protocol but only operates as a slave. The transfer

protocol is the same whether operating in fast or slow mode.

10.5.2 Details of the I²C Protocol

The device supports 7-bit addressing only, the address is 0x2F. The 8-bit shifted address is 0x5E.

A timer runs during I²C transitions. If the timer expires while SDA is held low, all additional

commands are ignored and the I²C state machine is reset. The timer is reset with a START condition

and stopped with a STOP condition.

The I²C bus is monitored at all times for a valid SLAVE address, and an acknowledge bit is

generated if the SLAVE address was true.

●

A START condition is initiated by a high to low transition on the SDA line while the SCL is in the

high state.

A STOP condition is indicated by a low to high transition on the SDA line while the SCL is in the

high state.

An ACKNOWLEDGE is indicated by the receiver pulling the SDA line low during the following

clock cycle.

SDA

SCL

Data SDA must be stable

during high part of clock

Start(S ) is SDA falling while

SCL high

Stop (P ) is SDA rising while

SCL high

Data sampled on SCL

rising edge and driven on

SCL falling edge

SCL

Figure 44: I²C Start and Stop Conditions

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

31 of 47

DA9230

Ultra-Low Quiescent Current Buck

When the address is matching the following event sequence happens:

1. The device generates an ACKNOWLEDGE to indicate to the master that the communication link

has been established

2. The master generates SCL clock cycles to transmit or receive data

3. After receiving data, an ACKNOWLEDGE is generated either by the device or the master

(whichever is transmitting the data)

A data sequence is 9-bit, consisting of 8-bit data and 1-bit ACKNOWLEDGE. It can be repeated

as long as necessary.

4. The master generates a STOP condition to end the data transfer

The bus returns to IDLE-mode if during a message a new START or STOP condition occurs. Data is

transmitted MSB first for both R/W operations.

10.6 GPO Pin Function Programing

DA9230 has a General purpose output (GPO) pin which can be programed to have multiple

functions.

10.6.1 Power Good Indicator

When GPO pin is configured to the VDD power good indicator, it is an open drain output and can be

configured to either active high or active low. When GPO status is Hi-Z, an external pull-up is

required for GPO to be high.

Table 12: GPO as Power Good Indicator

GPO Configuration

V_IN> V_{IN_UVLO}

GPO Status

Active High

Yes

Hi-Z

Active Low

Yes

10.6.2 Event Indicator

GPO pin can also be configured as the event indicator in open drain output. Whenever there is an

event or multiple events (VIN_UV_EVNT or OT_EVENT or OV_BUCK_EVENT or

OC_BUCK_EVENT or UV_BUCK_EVENT) happen, GPO will be pulled down Low. This can be used

as an interrupt to host CPU to inform events happened. When there is no event, GPO will remain in

Hi-Z status and an external pull-up is required for GPO to be high.

10.6.3 Reset Pulse Generation

GPO pin can be configured to generate a reset pulse signal when buck starts. The reset signal can

be used by host CPU or other device that are connected to buck output. When GPO is Low, it

indicates a reset pulse period; when GPO is in Hi-Z status (An external pull-up is required for GPO to

be high), it indicates a non-reset period.

There is also a timing control to negate the reset pulse signal. The GPO reset pulse width can be

adjusted between 8 and 112 ms measured from written 1 to BUCK_EN register bit.

10.6.4 Always Pull-Down or Hi-Z

When GPO pin is not used, it can be configured to either always Hi-Z or pull-down to Low.

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

32 of 47

DA9230

Ultra-Low Quiescent Current Buck

11 Register Overview

11.1 Register Map

11.1.1 Buck Control

Table 13: Event/Status/Mask and User Registers

User Registers

Addr

EVENT

0x0000 OT_EVENT

0x0002 OT_STAT

VIN_UV_EVENT Reserved

OC_BUCK_EVENT

OV_BUCK_EVENT

UV_BUCK_EVENT

ReservedReserved

BUCK_EN_STA

STATUS

VIN_UV_STAT

M_VIN_UV

Reserved

OC_BUCK_STAT

OV_BUCK_STAT

UV_BUCK_STAT

Reserved

M_OC_BUCK_EVEN M_OV_BUCK_EVEN M_UV_BUCK_EVEN

MASK

GPO

0x0003 Reserved

ReservedReserved

0x0004 GPO_RST_CTRL<3:0>

VOUT_RANGE_H

GPO_CTRL<3:0>

BUCK

0x0005 BUCK_EN

Reserved

BUCK_VOUT<4:0>

BUCK_PD_CFG1

BUCK_PD_CFG

BUCK_CFG 0x0006 Reserved

Reserved

SEL_BUCK_ILIM<1:0>

SC_DIS_BUC

FAULT_CTL 0x0008

PIN_MONTO

OC_DIS_BUCK

Reserved

OV_DIS_BUCK TSD_FRC_DIS

UVLO_FRC_DIS

Reserved

RCVRY_NUM<2:0>

Reserved

0x000AReserved

Reserved

ReservedGPO_OUT_MON

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

33 of 47

DA9230

Ultra-Low Quiescent Current Buck

11.1.2 System Module

Table 14: System Reset Registers

User Registers

SYS_RST_EVENT 0x0001 Reserved

SYS_SRST 0x0009 Reserved

Addr

Reserved

SRST<3:0>

Reserved

RESET_EVENT

SYS_DEVICE_ID 0x0080 DEV_ID<7:0>

SYS_VARIANT_ID 0x0081 MRC<3:0>

VRC<3:0>

SYS_CONFIG_ID 0x0082 CONFIG_REV<7:0>

11.2 Register Definitions

11.2.1 Buck Control

11.2.1.1

Event/Status/Mask Registers

Table 15: Register EVENT

Address

0x0000

POR Value

0x00

Event flag

EVENT

OT_EVENT

Field Name

VIN_UV_EVENT

Reserved

OC_BUCK_EVENT OV_BUCK_EVENT UV_BUCK_EVENT Reserved

POR Description

Reserved

Bits

Type

Over Temperature fault event flag. When Over temperature condition is detected, this bit is set to 1.

When I2C writes '1' to this bit, the event flag is cleared.

OT_EVENT

[7]

evnt

0x0

Under Voltage on VDD event flag. When Under Voltage (UVLO) condition is detected, this bit is set to

1. When I2C writes '1' to this bit, the event flag is cleared.

VIN_UV_EVENT

[6]

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

34 of 47

DA9230

Ultra-Low Quiescent Current Buck

Field Name

Bits

Type

POR

Description

Over Current on BUCK OUT event flag. When the buck Over Current condition is detected (when

BUCK_EN==1 && M_OC_BUCK==0), this bit is set to 1. When I2C writes '1' to this bit, the event flag

is cleared.

OC_BUCK_EVENT

[4]

evnt

0x0

Over Voltage on BUCK OUT event flag. When the buck Over Voltage condition is detected (when

BUCK_EN==1 && M_OV_BUCK==0), this bit is set to 1. When I2C writes '1' to this bit, the event flag

is cleared.

OV_BUCK_EVENT

UV_BUCK_EVENT

[3]

[2]

evnt

0x0

Under voltage on BUCK OUT event flag. When the under voltage condition (i.e. short circuit) is

detected on the buck (when BUCK_EN==1 && M_UV_BUCK==0), this bit is set to 1. When I2C

writes '1' to this bit, this event flag is cleared.

Table 16: Register STATUS

Address

POR Value

0x00

Status

0x0002

STATUS

OT_STAT

VIN_UV_STAT

Reserved

Type

OC_BUCK_STAT

OV_BUCK_STAT

UV_BUCK_STAT

Reserved

BUCK_EN_STAT

Field Name

OT_STAT

Bits

[7]

POR

0x0

Description

Indicate present Over Temp status.

virtual

VIN_UV_STAT

OC_BUCK_STAT

OV_BUCK_STAT

UV_BUCK_STAT

[6]

Indicate present V_INunder-voltage status.

[4]

Indicate present BUCK VOUT over current status.

Indicate present BUCK VOUT over voltage status.

Indicate present BUCK VOUT under voltage status.

[3]

[2]

Indicate present Buck Enable status.

1:Buck enabled

BUCK_EN_STAT

[0]

virtual

0x0

0:Buck disabled

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

35 of 47

DA9230

Ultra-Low Quiescent Current Buck

Table 17: Register MASK

Address

0x0003

MASK

POR Value

Mask

0x7C

Reserved

Field Name

M_VIN_UV

Reserved

M_OC_BUCK_EVENTM_OV_BUCK_EVENT M_UV_BUCK_EVENTReserved

Type POR Description

Reserved

Bits

[6]

cfg OTP 0x1

Mask to set VIN_UV_EVNT. VIN_UV_STAT is updated regardless of this mask.

Masks to set OC_BUCK_EVENT. OC_BUCK_STAT is updated regardless of this mask.

Masks to set OV_BUCK_EVENT. OV_BUCK_STAT is updated regardless of this mask.

Masks to set UV_BUCK_EVENT. UV_BUCK_STAT is updated regardless of this mask.

M_OC_BUCK_EVENT

M_OV_BUCK_EVENT

M_UV_BUCK_EVENT

[4]

[3]

[2]

11.2.1.2

User Registers

Table 18: Register GPO

Address

0x0004

POR Value

GPO control

GPO

0x00

GPO_RST_CTRL<3:0>

GPO_CTRL<3:0>

Field Name

Bits

Type

POR

Description

Reset pulse signal nagate timing control

Value

Description

GPO_RST_CTRL

[7:4]

cfg OTP 0x0

0x0

8ms after BUCK_EN = 1, GPO reset pulse is negated.

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

36 of 47

DA9230

Ultra-Low Quiescent Current Buck

Field Name

Bits

Type

POR

Description

0x1

0x2

0x3

0x4

0x5

0x6

0x7

16ms after BUCK_EN = 1, GPO reset pulse is negated.

32ms after BUCK_EN = 1, GPO reset pulse is negated.

48ms after BUCK_EN = 1, GPO reset pulse is negated.

64ms after BUCK_EN = 1, GPO reset pulse is negated.

80ms after BUCK_EN = 1, GPO reset pulse is negated.

96ms after BUCK_EN = 1, GPO reset pulse is negated.

112ms after BUCK_EN = 1, GPO reset pulse is negated.

GPO Control

Value

0x1

Description

Reset Pulse generation output

PowerGood indicator, Active Low

PowerGood indicator, Active High

Event indicator

0x2

GPO_CTRL

[3:0]

cfg OTP 0x0

0x3

0x4

0x8

Force GPO output low

Force GPO output hi-z

0x9

Table 19: Register BUCK

Address

0x0005

POR Value

Buck enable & vout control

BUCK

0x58

BUCK_EN

VOUT_RANGE_HI Reserved

BUCK_VOUT<4:0>

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

37 of 47

DA9230

Ultra-Low Quiescent Current Buck

Field Name

Bits

Type

POR

Description

BUCK_EN

[7]

cfg OTP 0x0

BUCK enable

Range selection for buck. This can only be changed while BUCK_EN = 0

Value

0x0

Description

VOUT_RANGE_HI

[6]

cfg OTP 0x1

0.60 V <= VBUCK <= 1.30 V

1.30 V <= VBUCK <= 1.90 V

0x1

Buck output voltage

Description

Value

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0.60 V

0.65 V

0.70 V

0.75 V

0.80 V

0.85 V

0.90 V

0.95 V

1.00 V

1.05 V

1.10 V

1.15 V

1.20 V

1.25 V

1.30 V

datablk

OTP

BUCK_VOUT

[4:0]

0x18

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

38 of 47

DA9230

Ultra-Low Quiescent Current Buck

Field Name

Bits

Type

POR

Description

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

1.35 V

1.40 V

1.45 V

1.50 V

1.55 V

1.60 V

1.65 V

1.70 V

1.75 V

1.80 V

1.85 V

1.90 V

Table 20: Register BUCK_CFG

Address

0x0006

BUCK_CFG

POR Value

Buck config

0x00

Reserved

BUCK_PD_CFG2

BUCK_PD_CFG1

Reserved

SEL_BUCK_ILIM<1:0>

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

39 of 47

DA9230

Ultra-Low Quiescent Current Buck

Field Name

Bits

[5]

Type

POR

Description

BUCK_PD_CFG2

BUCK_PD_CFG1

cfg OTP 0x0

0: If BUCK_EN = 0, BUCK_PD_EN = 1 1: If BUCK_EN = 0, BUCK_PD_EN = 0

0: When BUCK is forced off by faults, BUCK_PD_EN = 1 1: When BUCK is forced off by faults, BUCK_PD_EN = 0

Buck peak current limit setting

[4]

Value

0x0

Description

Default current limit

Default +50mA

Default +100mA

Default +150mA

SEL_BUCK_ILIM

[1:0]

cfg OTP 0x0

0x1

0x2

0x3

Table 21: Register FAUL_CTL

Address

POR Value

Fault & Recovery control

0x0008

FAULT_CTL

0x1F

SC_DIS_BUCK

Field Name

SC_DIS_BUCK

OC_DIS_BUCK

OV_DIS_BUCK

OC_DIS_BUCK

OV_DIS_BUCK

TSD_FRC_DIS

UVLO_FRC_DIS

RCVRY_NUM<2:0>

Bits

[7]

Type

POR

Description

cfg OTP 0x0

1: Force disable BUCK during SHORT CIRCUIT condition oc_buck=1 & uv_buck=1

1: Force disable BUCK during oc_buck=1 for over 64 cycles

1: Force disable BUCK during ov_buck=1

[6]

cfg OTP 0x0

[5]

1: Force disable BUCK

during Over Temp

TSD_FRC_DIS

[4]

cfg OTP 0x1

1: Force disable BUCK

during UVLO

UVLO_FRC_DIS

RCVRY_NUM

[3]

data

0x7

BUCK recovery trial fault number. This is counted down by every fault forcing BUCK off. If RCVRY_NUM becomes 0,

Recovery trial is ended. If RCVRY_NUM is set 0x7, this is not counted down and recovery trail is not ended.

[2:0]

OTP

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

40 of 47

DA9230

Ultra-Low Quiescent Current Buck

Table 22: Register PIN_MONITOR

Address

0x000A

PIN_MONTOR

POR Value

0x00

PIN MONITOR

Reserved

Field Name

GPO_OUT_MON

Reserved

GPO_OUT_MON

Bits

Type

POR

Description

[0]

virtual 0x0

Indicate current GPO output

11.2.2 System Module

11.2.2.1

System Reset Registers

Table 23: Register SYS_RST_EVENT

Address

0x0001

POR Value

Reset Event flag

SYS_RST_EVENT 0x01

Reserved

Field Name

RESET_EVENT

Reserved

Bits

Reserved

RESET_EVENT

Type

POR

Description

RESET event flag. After Reset, this bit is set. When I2C write '1' to this bit, this event flag is cleared.

[0]

evnt

0x1

Table 24: Register SYS_SRST

Address

0x0009

SYS_SRST

POR Value

0x00

Soft Reset

Reserved

SRST<3:0>

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

41 of 47

DA9230

Ultra-Low Quiescent Current Buck

Field Name

Bits

Type

POR

Description

SRST

[3:0]

cfg

0x0

Initiate Soft Reset by writing 0x5.

11.2.2.2

System ID Registers

Table 25: Register SYS_DEVICE_ID

Address

0x0080

POR Value

DEVICE_ID

SYS_DEVICE_ID 0x00

DEV_ID<7:0>

Field Name

DEV_ID

Bits

Type

POR

Description

Device ID; hard-coded or metal-programmed

[7:0]

virtual 0x0

Table 26: Register SYS_VARIANT_ID

Address

0x0081

POR Value

VARIANT_ID

SYS_VARIANT_ID 0x00

MRC<3:0>

Field Name

MRC

VRC<3:0>

Bits

Type

POR

Description

[7:4]

virtual 0x0

Mask Revision Code; mask design changes increment reset value.

Chip Variant Code; e.g. package variants.

trim

0x0

OTP

VRC

[3:0]

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

42 of 47

DA9230

Ultra-Low Quiescent Current Buck

Table 27: Register SYS_CONFIG_ID

Address

0x0082

POR Value

0x00

CONFIG_ID

SYS_CONFIG_ID

CONFIG_REV<7:0>

Field Name

Bits

Type

POR

Description

OTP settings revision

trim

OTP

CONFIG_REV

[7:0]

0x0

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

43 of 47

DA9230

Ultra-Low Quiescent Current Buck

12 Package Information

12.1 Package Outlines

Figure 45: Package Outline Drawing

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

44 of 47

DA9230

Ultra-Low Quiescent Current Buck

12.2 Moisture Sensitivity Level

The Moisture Sensitivity Level (MSL) is an indicator for the maximum allowable time period (floor

lifetime) in which a moisture sensitive plastic device, once removed from the dry bag, can be

exposed to an environment with a maximum temperature of 30 °C and a maximum relative humidity

of 60% RH before the solder reflow process. The MSL classification is defined in Table 28.

The device package is qualified for MSL 1.

Table 28: MSL Classification

MSL level

Floor Lifetime

MSL 1

unlimited at 30 °C/85% RH

12.3 Soldering Information

Refer to the JEDEC standard J-STD-020 for relevant soldering information. This document can be

downloaded from http://www.jedec.org.

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

45 of 47

DA9230

Ultra-Low Quiescent Current Buck

13 Ordering Information

The ordering number consists of the part number followed by a suffix indicating the packing method.

For details and availability or other custom OTP parts, please consult Dialog Semiconductor’s

customer portal or your local sales representative.

Table 29: Ordering Information

Part number

Package

Size (mm)

Shipment Form

Pack Quantity

DA9230 -xxxx

WLCSP-12

1.25 x 1.65

T&R

4500

Table 30: OTP List

Order code

Description

Buck V_OUT

DA9230-07VZ2

DA9230-08VZ2

DA9230-09VZ2

DA9230-0AVZ2

DA9230-61VZ2

DA9230-62VZ2

OTP with buck voltage preconfigured

0.6 V

0.8 V

1.2 V

1.8 V

1.9 V

1.1 V

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

46 of 47

DA9230

Ultra-Low Quiescent Current Buck

Status Definitions

Revision

Datasheet Status

Product Status

Definition

1.<n>

Target

Development

This datasheet contains the design specifications for product development.

Specifications may be changed in any manner without notice.

2.<n>

3.<n>

Preliminary

Final

Qualification

Production

This datasheet contains the specifications and preliminary characterization

data for products in pre-production. Specifications may be changed at any

time without notice in order to improve the design.

This datasheet contains the final specifications for products in volume

production. The specifications may be changed at any time in order to

improve the design, manufacturing and supply. Relevant changes will be

communicated via Customer Product Notifications.

4.<n>

Obsolete

Archived

This datasheet contains the specifications for discontinued products. The

information is provided for reference only.

Disclaimer

Unless otherwise agreed in writing, the Dialog Semiconductor products (and any associated software) referred to in this document are not

designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications

where failure or malfunction of a Dialog Semiconductor product (or associated software) can reasonably be expected to result in personal injury,

death or severe property or environmental damage. Dialog Semiconductor and its suppliers accept no liability for inclusion and/or use of Dialog

Semiconductor products (and any associated software) in such equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or

warranties, express or implied, as to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no

responsibility whatsoever for the content in this document if provided by any information source outside of Dialog Semiconductor.

Dialog Semiconductor reserves the right to change without notice the information published in this document, including, without limitation, the

specification and the design of the related semiconductor products, software and applications. Notwithstanding the foregoing, for any automotive

grade version of the device, Dialog Semiconductor reserves the right to change the information published in this document, including, without

limitation, the specification and the design of the related semiconductor products, software and applications, in accordance with its standard

automotive change notification process.

Applications, software, and semiconductor products described in this document are for illustrative purposes only. Dialog Semiconductor makes

no representation or warranty that such applications, software and semiconductor products will be suitable for the specified use without further

testing or modification. Unless otherwise agreed in writing, such testing or modification is the sole responsibility of the customer and Dialog

Semiconductor excludes all liability in this respect.

Nothing in this document may be construed as a license for customer to use the Dialog Semiconductor products, software and applications

referred to in this document. Such license must be separately sought by customer with Dialog Semiconductor.

All use of Dialog Semiconductor products, software and applications referred to in this document is subject to Dialog Semiconductor’s Standard

Terms and Conditions of Sale, available on the company website (www.dialog-semiconductor.com) unless otherwise stated.

Dialog, Dialog Semiconductor and the Dialog logo are trademarks of Dialog Semiconductor Plc or its subsidiaries. All other product or service

names and marks are the property of their respective owners.

RoHS Compliance

Dialog Semiconductor’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European

Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our

suppliers are available on request.

Contacting Dialog Semiconductor

United Kingdom (Headquarters)

Dialog Semiconductor (UK) LTD

Phone: +44 1793 757700

North America

Hong Kong

China (Shenzhen)

Dialog Semiconductor Inc.

Phone: +1 408 845 8500

Dialog Semiconductor Hong Kong

Phone: +852 2607 4271

Dialog Semiconductor China

Phone: +86 755 2981 3669

Germany

Japan

Korea

China (Shanghai)

Dialog Semiconductor GmbH

Phone: +49 7021 805-0

Dialog Semiconductor K. K.

Phone: +81 3 5769 5100

Dialog Semiconductor Korea

Phone: +82 2 3469 8200

Dialog Semiconductor China

Phone: +86 21 5424 9058

The Netherlands

Taiwan

Dialog Semiconductor B.V.

Phone: +31 73 640 8822

Dialog Semiconductor Taiwan

Phone: +886 281 786 222

Email:

Web site:

enquiry@diasemi.com

www.dialog-semiconductor.com

Datasheet

Revision 3.0

27-Feb-2020

CFR0011-120-00

47 of 47

DA9230-08VZ2 [DIALOG]

相关型号：

DA9230-09VZ2

DA9230-0AVZ2

DA9230-61VZ2

DA9230-62VZ2

DA9232

DA9232-81VZ2

DA9232-82VZ2

DA9318L

DA9318L-05UF2

DA9318M

DA9318M-06UF2

DA945-B-B-B