SLG46517M [DIALOG]
GreenPAK Programmable Mixed-Signal Matrix with ASM and Dual 44 mΩ/2 A P-FET;
| 型号： | SLG46517M |
| 厂家： | 
Dialog Semiconductor |
| 描述： | GreenPAK Programmable Mixed-Signal Matrix with ASM and Dual 44 mΩ/2 A P-FET |
| 文件： | 总190页 (文件大小：1862K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
General Description
The SLG46517 provides a small, low power component for commonly used Mixed-Signal functions. The user creates their
circuit design by programming the one time programmable (OTP) Non-Volatile Memory (NVM) to configure the interconnect
logic, the IO Pins, and the macrocells of the SLG46517. This highly versatile device allows a wide variety of Mixed-Signal
functions to be designed within a very small, low power single integrated circuit.
Configurable 25 kHz/2 MHz
25 MHz RC Oscillator
Key Features
Four Analog Comparators
Voltage Reference
Seventeen Combination Function Macrocells
Crystal Oscillator
Power-On Reset
Eight Byte RAM + OTP User Memory
Three Selectable DFF/LATCH or 2-bit LUTs
One Selectable Continuous DFF/LATCH or 3-bit LUT
Four Selectable DFF/LATCH or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
One Selectable Programmable Pattern Generator or
2-bit LUT
RAM Memory Space that is Readable and Writable via
I2C
User Defined Initial Values Transferred from OTP
P-FET Power Switch
Power Switch IDS: 2 A
VIN: 1.71 V to 5.5 V
Low RDSON
44 mΩ @ 5.5 V
58 mΩ @ 3.3 V
110 mΩ @ 1.71 V
Five 8-bit Delays/Counters or 3-bit LUTs
Two 16-bit Delays/Counters or 4-bit LUTs
Asynchronous State Machine
Eight States
Flexible Input Logic from State Transitions
Read Back Protection (Read Lock)
Power Supply
Serial Communications
I2C Protocol Interface
1.8 V (±5%) to 5 V (±10%) Supply
Pipe Delay – 16 Stage/3 Output (Part of Combination
Function Macrocell)
Operating Temperature Range: -40 °C to 85 °C
RoHS Compliant/Halogen-Free
Available Package
Programmable Delay
Additional Logic Functions – 2 Deglitch Filters with Edge
Detectors
28-pin MSTQFN: 2 mm x 3 mm x 0.55 mm, 0.4 mm pitch
Two Oscillators
Applications
Personal Computers and Servers
PC Peripherals
Consumer Electronics
Data Communications Equipment
Handheld and Portable Electronics
Power Management Switches
Power Sequencing with Complex Analog Control
Power Plane Component Size Reduction Project
LED Driver
Haptic Motor Driver
Datasheet
22-Jul-2021
Revision 3.6
1 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Contents
General Description.................................................................................................................................................................1
Key Features.............................................................................................................................................................................1
Applications..............................................................................................................................................................................1
1 Block Diagram ......................................................................................................................................................................9
2 Pinout ..................................................................................................................................................................................10
2.1 Pin Configuration - MSTQFN- 28L .......................................................................................................................10
3 Characteristics ...................................................................................................................................................................15
3.1 Absolute Maximum Ratings .................................................................................................................................15
3.2 Electrostatic Discharge Ratings ...........................................................................................................................15
3.3 Recommended Operating Conditions .................................................................................................................16
3.4 Electrical Characteristics ......................................................................................................................................16
3.5 Timing Characteristics ..........................................................................................................................................20
3.6 OSC Characteristics .............................................................................................................................................22
3.7 ACMP Characteristics ..........................................................................................................................................26
3.8 Power Switch EC (Each P-FET) ..........................................................................................................................30
4 User Programmability ........................................................................................................................................................32
5 IO Pins .................................................................................................................................................................................33
5.1 Input Modes .........................................................................................................................................................33
5.2 Output Modes .......................................................................................................................................................33
5.3 Pull-Up/Down Resistors .......................................................................................................................................34
5.4 IO Register Settings .............................................................................................................................................34
5.5 GPI Structure .......................................................................................................................................................41
5.6 Matrix OE IO Structure .........................................................................................................................................42
5.7 IO Structure ..........................................................................................................................................................45
6 Connection Matrix ..............................................................................................................................................................47
6.1 Matrix Input Table ...............................................................................................................................................48
6.2 Matrix Output Table ..............................................................................................................................................50
6.3 Connection Matrix Virtual Inputs ..........................................................................................................................53
6.4 Connection Matrix Virtual Outputs .......................................................................................................................53
7 Combination Function Macrocells ....................................................................................................................................54
7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................54
7.2 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................58
7.3 3-Bit LUT or Pipe Delay Macrocell .......................................................................................................................66
7.4 3-Bit LUT or 8-Bit Counter/Delay Macrocells .......................................................................................................68
7.5 4-Bit LUT or 16-Bit Counter/Delay Macrocells .....................................................................................................76
7.6 CNT/DLY/FSM Timing Diagrams .........................................................................................................................81
7.7 2-bit LUT or Programmable Pattern Generator ....................................................................................................88
7.8 Wake and Sleep Controller ..................................................................................................................................89
8 Analog Comparators ..........................................................................................................................................................93
8.1 ACMP0 Block Diagram and Register Settings .....................................................................................................96
8.2 ACMP1 Block Diagram and Register Settings .....................................................................................................98
8.3 ACMP2 Block Diagram and Register Settings ...................................................................................................100
8.4 ACMP3 Block Diagram and Register Settings ...................................................................................................102
9 Pipe Delay .........................................................................................................................................................................104
10 Programmable Delay/Edge Detector ............................................................................................................................104
10.1 Programmable Delay Timing Diagram - Edge Detector Output .......................................................................104
11 Additional Logic Function. Deglitch Filter ...................................................................................................................106
11.1 Deglitch Filter/Edge Detector ...........................................................................................................................106
12 Voltage Reference ..........................................................................................................................................................107
12.1 Voltage Reference Overview ...........................................................................................................................107
12.2 Vref Selection Table ........................................................................................................................................107
12.3 Vref Block Diagram ........................................................................................................................................108
12.4 Vref Load Regulation .......................................................................................................................................109
13 Clocking ..........................................................................................................................................................................111
13.1 OSC General Description .................................................................................................................................111
Datasheet
22-Jul-2021
Revision 3.6
2 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
13.2 25 kHz/2 MHz and 25 MHz RC Oscillators ......................................................................................................111
13.3 Oscillators Power-On Delay .............................................................................................................................113
13.4 Oscillators Accuracy .........................................................................................................................................115
14 Crystal Oscillator ...........................................................................................................................................................117
15 Power-On Reset ..............................................................................................................................................................118
15.1 General Operation ............................................................................................................................................118
15.2 POR Sequence ................................................................................................................................................119
15.3 Macrocells Output States During POR Sequence ...........................................................................................119
16 Asynchronous State Machine Macrocell .....................................................................................................................122
16.1 ASM Macrocell Overview .................................................................................................................................122
16.2 ASM Inputs .......................................................................................................................................................123
16.3 ASM Outputs ....................................................................................................................................................125
16.4 Basic ASM Timing ............................................................................................................................................127
16.5 Asynchronous State Machines vs. Synchronous State Machines ...................................................................127
16.6 ASM Power Considerations .............................................................................................................................127
16.7 ASM Logical vs. Physical Design .....................................................................................................................128
16.8 ASM Special Case Timing Considerations ......................................................................................................128
17 I2C Serial Communications Macrocell .........................................................................................................................132
17.1 I2C Serial Communications Macrocell Overview ..............................................................................................132
17.2 I2C Serial Communications Device Addressing ...............................................................................................132
17.3 I2C Serial General Timing ................................................................................................................................133
17.4 I2C Serial Communications Commands ...........................................................................................................133
17.5 I2C Serial Command Register Protection .........................................................................................................136
17.6 I2C Additional options .......................................................................................................................................140
18 External Clocking ...........................................................................................................................................................142
18.1 Crystal Mode ....................................................................................................................................................142
18.2 IO17 or IO15 Source for 25 kHz/2 MHz Clock .................................................................................................142
18.3 IO14 Source for 25 MHz Clock ........................................................................................................................142
19 Dual, 2A P-FET Power Switches ...................................................................................................................................143
19.1 Power Switches Overview ................................................................................................................................143
19.2 Driving the P-FET Switch .................................................................................................................................144
19.3 Power Dissipation ............................................................................................................................................146
19.4 Power Switch Typical Performance .................................................................................................................147
20 Register Definitions .......................................................................................................................................................152
20.1 Register Map ....................................................................................................................................................152
21 Package Top Marking Definitions .................................................................................................................................183
21.1 MSTQFN 28L 2 mm x 3 mm 0.4P Package .....................................................................................................183
22 Package Information ......................................................................................................................................................184
22.1 Package outlines FOR MSTQFN 28L 2 mm x 3 mm 0.4P Package ................................................................184
22.2 MSTQFN Handling ...........................................................................................................................................185
22.3 Soldering Information .......................................................................................................................................185
23 Ordering Information .....................................................................................................................................................185
23.1 Tape and Reel Specifications ..........................................................................................................................185
23.2 Carrier Tape Drawing and Dimensions ............................................................................................................185
24 Layout Guidelines ..........................................................................................................................................................186
24.1 MSTQFN 28L 2 mm x 3 mm 0.4P Package .....................................................................................................186
Glossary................................................................................................................................................................................187
Revision History...................................................................................................................................................................189
Datasheet
22-Jul-2021
Revision 3.6
3 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Figures
Figure 1: Block Diagram.............................................................................................................................................................9
Figure 2: Steps to Create a Custom GreenPAK Device...........................................................................................................32
Figure 3: IO0 GPI Structure Diagram.......................................................................................................................................41
Figure 4: Matrix OE IO Structure Diagram...............................................................................................................................42
Figure 5: Matrix OE IO Structure Diagram...............................................................................................................................43
Figure 6: Matrix OE IO 4X Drive Structure Diagram ................................................................................................................44
Figure 7: IO Structure Diagram................................................................................................................................................45
Figure 8: IO 4X Drive Structure Diagram .................................................................................................................................46
Figure 9: Connection Matrix.....................................................................................................................................................47
Figure 10: Connection Matrix Example....................................................................................................................................47
Figure 11: 2-bit LUT0 or DFF0.................................................................................................................................................54
Figure 12: 2-bit LUT1 or DFF1.................................................................................................................................................55
Figure 13: 2-bit LUT2 or DFF2.................................................................................................................................................55
Figure 14: DFF Polarity Operations..........................................................................................................................................58
Figure 15: 3-bit LUT0 or DFF3 with RST/SET..........................................................................................................................59
Figure 16: 3-bit LUT1 or DFF4 with RST/SET..........................................................................................................................59
Figure 17: 3-bit LUT2 or DFF5 with RST/SET..........................................................................................................................60
Figure 18: 3-bit LUT3 or DFF6 with RST/SET..........................................................................................................................60
Figure 19: 3-bit LUT4 or DFF7 with RST/SET..........................................................................................................................61
Figure 20: DFF Polarity Operations with nReset......................................................................................................................65
Figure 21: DFF Polarity Operations with nSet..........................................................................................................................66
Figure 22: 3-bit LUT10 or Pipe Delay.......................................................................................................................................67
Figure 23: 3-bit LUT5 or CNT/DLY2.........................................................................................................................................69
Figure 24: 3-bit LUT6 or CNT/DLY3.........................................................................................................................................69
Figure 25: 3-bit LUT7 or CNT/DLY4.........................................................................................................................................70
Figure 26: 3-bit LUT8 or CNT/DLY5.........................................................................................................................................71
Figure 27: 3-bit LUT9 or CNT/DLY6.........................................................................................................................................71
Figure 28: 4-bit LUT0 or CNT/DLY0.........................................................................................................................................77
Figure 29: 4-bit LUT1 or CNT/DLY1.........................................................................................................................................78
Figure 30: Delay Mode Timing Diagram...................................................................................................................................81
Figure 31: Counter Mode Timing Diagram...............................................................................................................................81
Figure 32: One-Shot Function Timing Diagram........................................................................................................................82
Figure 33: Frequency Detection Mode Timing Diagram...........................................................................................................84
Figure 34: Edge Detection Mode Timing Diagram...................................................................................................................85
Figure 35: Delay Mode Timing Diagram...................................................................................................................................86
Figure 36: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3.....86
Figure 37: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3 .........87
Figure 38: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3.....87
Figure 39: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3 .........88
Figure 40: 2-bit LUT2 or PGen.................................................................................................................................................89
Figure 41: PGen Timing Diagram.............................................................................................................................................89
Figure 42: Wake/Sleep Controller............................................................................................................................................90
Figure 43: Wake/Sleep Timing Diagram ..................................................................................................................................90
Figure 44: Maximum Power-On Delay vs. VDD, BG = Auto-delay. ..........................................................................................93
Figure 45: Max. Power-On Delay vs. VDD, BG = 550 µs.........................................................................................................94
Figure 46: Max. Power-On Delay vs. VDD, BG = 100 µs..........................................................................................................94
Figure 47: Typical Buffer Input Voltage Offset vs. Voltage Reference.....................................................................................95
Figure 48: Typical Input Threshold Variation (Including Vref Variation, ACMP Offset) vs. Voltage Reference........................95
Figure 49: ACMP0 Block Diagram ...........................................................................................................................................96
Figure 50: ACMP1 Block Diagram ...........................................................................................................................................98
Figure 51: ACMP2 Block Diagram .........................................................................................................................................100
Figure 52: ACMP3 Block Diagram .........................................................................................................................................102
Figure 53: Programmable Delay ............................................................................................................................................104
Figure 54: Edge Detector Output ...........................................................................................................................................104
Figure 55: Deglitch Filter/Edge Detector................................................................................................................................106
Datasheet
22-Jul-2021
Revision 3.6
4 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Figure 56: Voltage Reference Block Diagram........................................................................................................................108
Figure 57: Typical Load Regulation, Vref = 600 mV, T = -40 °C to +85 °C, Buffer - Enable..................................................109
Figure 58: Typical Load Regulation, Vref = 1000 mV, T = -40 °C to +85 °C, Buffer - Enable................................................109
Figure 59: Typical Load Regulation, Vref = 1200 mV, T = -40 °C to +85 °C, Buffer - Enable................................................110
Figure 60: 25 kHz/2 MHz RC OSC Block Diagram ................................................................................................................112
Figure 61: 25 MHz RC OSC Block Diagram ..........................................................................................................................112
Figure 62: Oscillator Startup Diagram....................................................................................................................................113
Figure 63: Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 2 MHz .......................................................113
Figure 64: Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 25 kHz.......................................................114
Figure 65: Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC1 = 25 MHz .....................................................114
Figure 66: Oscillator Frequency vs. Temperature, OSC0 = 2 MHz........................................................................................115
Figure 67: Oscillator Frequency vs. Temperature, OSC0 = 25 kHz.......................................................................................115
Figure 68: Oscillator Frequency vs. Temperature, OSC1 = 25 MHz.....................................................................................116
Figure 69: Crystal OSC Block Diagram..................................................................................................................................117
Figure 70: External Crystal Connection..................................................................................................................................117
Figure 71: POR Sequence.....................................................................................................................................................119
Figure 72: Internal Macrocell States during POR Sequence..................................................................................................120
Figure 73: Power-Down..........................................................................................................................................................121
Figure 74: Asynchronous State Machine State Transitions ...................................................................................................122
Figure 75: Asynchronous State Machine ...............................................................................................................................123
Figure 76: Asynchronous State Machine Inputs.....................................................................................................................124
Figure 77: Maximum 3 State Transitions into Given State.....................................................................................................124
Figure 78: Maximum 7 State Transitions out of a Given State...............................................................................................125
Figure 79: Connection Matrix Output RAM ............................................................................................................................126
Figure 80: State Transition.....................................................................................................................................................127
Figure 81: State Transition Timing.........................................................................................................................................127
Figure 82: State Transition.....................................................................................................................................................128
Figure 83: State Transition Timing and Power Consumption.................................................................................................128
Figure 84: State Transition.....................................................................................................................................................128
Figure 85: State Transition Pulse Input Timing......................................................................................................................129
Figure 86: State Transition - Competing Inputs......................................................................................................................129
Figure 87: State Transition Timing - Competing Inputs Indeterminate...................................................................................129
Figure 88: State Transition Timing - Competing Inputs Determinable ...................................................................................130
Figure 89: State Transition - Sequential.................................................................................................................................130
Figure 90: State Transition - Sequential Timing.....................................................................................................................130
Figure 91: State Transition - Closed Cycling..........................................................................................................................131
Figure 92: State Transition - Closed Cycling Timing..............................................................................................................131
Figure 93: Basic Command Structure....................................................................................................................................132
Figure 94: I2C General Timing Characteristics ......................................................................................................................133
Figure 95: Byte Write Command, R/W = 0.............................................................................................................................133
Figure 96: Sequential Write Command..................................................................................................................................134
Figure 97: Current Address Read Command, R/W = 1..........................................................................................................134
Figure 98: Random Read Command .....................................................................................................................................135
Figure 99: Sequential Read Command..................................................................................................................................135
Figure 100: Register Bank Map..............................................................................................................................................136
Figure 101: Reset Command Timing .....................................................................................................................................140
Figure 102: Dual P-FET Power Switch...................................................................................................................................143
Figure 103: Typical Circuit Topology for Internal (Left) and External (Right) Drive Modes....................................................144
Figure 104: Definitions for Rise, Fall and Switching Delay Times..........................................................................................144
Figure 105: Test Circuit for Typical Switching Waveforms.....................................................................................................145
Figure 106: Typical Switching Waveforms (Internal Drive, Resistive Load, RL = 100 W, VDD = VIN = 5.5 V).......................145
Figure 107: Typical Switching Waveforms (Internal Drive, Resistive Load, RL = 100 W, VDD = VIN = 1.71 V).....................145
Figure 108: Power Dissipation Derating Curve......................................................................................................................147
Figure 109: Typical Output Characteristics............................................................................................................................147
Figure 110: Drain-Source On-Resistance vs. Drain Current..................................................................................................147
Figure 111: Typical Drain-Source On-Resistance vs. Ambient Temperature ........................................................................148
Figure 112: Gate-Source On-Resistance Gate-Source Voltage ............................................................................................148
Datasheet
22-Jul-2021
Revision 3.6
5 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Figure 113: Drain Current vs. Gate-Source Voltage ..............................................................................................................148
Figure 114: Typical Forward Transconductance....................................................................................................................148
Figure 115: Typical Drain-Source Diode Forward Voltage.....................................................................................................149
Figure 116: Gate Threshold Voltage vs Ambient Temperature..............................................................................................149
Figure 117: Zero Gate Voltage Drain Current........................................................................................................................149
Figure 118: Gate-Body Leakage vs. Ambient Temperature...................................................................................................149
Figure 119: Typical Switching Time (Internal Gate Drive) at VDS = 1.71 V............................................................................150
Figure 120: Typical Switching Time (Internal Gate Drive) at VDS = 5.5 V..............................................................................150
Figure 121: Typical Gate Input Waveform, Internal Gate Drive Source (Switching Time Test) .............................................150
Figure 122: Typical Gate Charge vs. Gate-Source Voltage...................................................................................................150
Figure 123: Typical Capacitance vs. Drain-Source Voltage...................................................................................................151
Datasheet
22-Jul-2021
Revision 3.6
6 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Tables
Table 1: Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2: Pin Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4: Electrostatic Discharge Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6: EC at VDD = 1.8 V ±5%, T = -40 °C to +85 °C, Unless Otherwise Noted . . . . . . . . . . . . . . . . . . . . . . 16
Table 7: EC at VDD = 3.3 V ±10%, T = -40 °C to +85 °C, Unless Otherwise Noted . . . . . . . . . . . . . . . . . . . . . 17
Table 8: EC at VDD = 5 V ±10%, T = -40 °C to +85 °C, Unless Otherwise Noted . . . . . . . . . . . . . . . . . . . . . . 18
Table 9: I2C Pins Timing Characteristics T = -40 °C to +85 °C, Unless Otherwise Noted . . . . . . . . . . . . . . . . . . 19
Table 10: Asynchronous State Machine Specifications at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11: Typical Current Estimated for Each Macrocell at T = -40 °C to +85 °C . . . . . . . . . . . . . . . . . . . . . . 20
Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13: Typical Propagations Delays and Pulse Widths at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14: Typical Deglitch Filter Pulse Width Performance at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15: Typical Counter/Delay Offset Measurements at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 16: 25 kHz RC OSC0 Frequency Limits VDD = 2.3 V to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17: 25 kHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value) . . . . . . . . . . . . . . . . . 23
Table 18: 2 MHz RC OSC0 Frequency Limits VDD = 2.3 V to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 19: 2 MHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value) . . . . . . . . . . . . . . . . . 23
Table 20: 25 MHz RC OSC1 Frequency Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 21: 25 MHz RC OSC1 Frequency Error (Error Calculated Relative to Nominal Value) . . . . . . . . . . . . . . . . 24
Table 22: OSC Power-On Delay, T = 25 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 23: OSC Power-On Delay, T = 25 °C, Fast Start-Up Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 24: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V, Unless Otherwise Noted . . . . . . . . . . 26
Table 25: Power Switch EC, TA = -40 °C to +85 °C (Typ Values at TA = +25 °C), VDD = 5.5 V, Unless Otherwise Noted . . 30
Table 26: IO0 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 27: IO1 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 28: IO2 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 29: IO3 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 30: IO4 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 31: IO5 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 32: IO6 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 33: IO7 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 34: IO8 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 35: IO9 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 36: IO10 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 37: IO11 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 38: IO12 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 39: IO13 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 40: IO14 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 41: IO15 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 42: Matrix Input Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 43: Matrix Output Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 44: Connection Matrix Virtual Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 45: 2-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 46: 2-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 47: 2-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 48: 2-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 49: DFF0 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 50: DFF1 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 51: DFF2 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 52: 3-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 53: 3-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 54: 3-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 55: 3-bit LUT3 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 56: 3-bit LUT4 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 57: 3-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 58: DFF3 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 59: DFF4 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 60: DFF5 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 61: DFF6 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Datasheet
22-Jul-2021
Revision 3.6
7 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 62: DFF7 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 63: 3-bit LUT10 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 64: Pipe Delay Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 65: 3-bit LUT5 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 66: 3-bit LUT6 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 67: 3-bit LUT7 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 68: 3-bit LUT8 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 69: 3-bit LUT9 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 70: 3-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 71: CNT/DLY2 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 72: CNT/DLY3 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 73: CNT/DLY4 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 74: CNT/DLY5 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 75: CNT/DLY6 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 76: 4-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 77: 4-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 78: 4-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 79: CNT/DLY0 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 80: CNT/DLY1 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 81: DLY/CNTx One-Shot/Freq. Detect Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 82: WS Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 83: Gain Divider Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 84: Gain Divider Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 85: Built-In Hysteresis Tolerance at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 86: ACMP0 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 87: ACMP1 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 88: ACMP2 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 89: ACMP3 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 90: Programmable Delay Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 91: Deglitch Filter Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 92: Vref Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 93: External Components Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 94: ASM Editor - Connection Matrix Output RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 95: Read/Write Protection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 96: RAM Array Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 97: Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Datasheet
22-Jul-2021
Revision 3.6
8 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
1
Block Diagram
IO9
IO6
IO8
IO5
IO12
IO7
Additional Logic Functions
Combination Function Macrocells
IO4
IO3
GND
Filter_0
with
Filter_1
with
Edge
ACMP0
2-bit
2-bit
LUT2_1
or DFF1
2-bit
LUT2_2
or DFF2
Edge
Detect
LUT2_0
or DFF0
Detect
2bit
LUT2_3
or PGen
3-bit
LUT3_0
or DFF3
3-bit
LUT3_1
or DFF4
IO10
Programmable
Delay
POR
ACMP1
3-bit
LUT3_2
or DFF5
3-bit
LUT3_3
or DFF6
3-bit
IO2
IO0
LUT3_4
or DFF7
Vref
ASM
8 States
IO11
3-bit
LUT3_6 or
CNT/DLY3
3-bit
LUT3_5 or
CNT/DLY2
3-bit
LUT3_7 or
CNT/DLY4
ACMP2
I2C Serial
Communication
25 MHz
RC Oscillator
3-bit
LUT3_9 or
CNT/DLY6
3-bit
LUT3_8 or
CNT/DLY5
4-bit
LUT4_0 or
CNT/DLY0
IO13
25 kHz/2 MHz
Oscillator
8 Byte RAM +
OTP Memory
V
DD
3-bit
LUT3_10 or
Pipe Delay
4-bit
LUT4_1 or
CNT/DLY1
ACMP3
IO15
Crystal
Oscillator
IO1
P-Channel
MOSFET0
P-Channel
MOSFET1
IO14
PWR_SW
_ON0
PWR_SW
_ON1
VIN1
AGND
VIN0
VOUT0
VOUT1
Figure 1: Block Diagram
Datasheet
22-Jul-2021
Revision 3.6
9 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
2
Pinout
2.1 PIN CONFIGURATION - MSTQFN- 28L
Pin # Signal Name Pin Functions
20 19 18
1
2
3
4
5
6
7
17
16
15
GND
IO10
IO4
IO3
IO2
1
GND
IO10
IO11
GND
2
GPIO10/ACMP2+/ACMP3+
GPIO11/ACMP2-/ACMP3-
GPIO13/XTAL0
21
22
23
24
28
27
26
25
3
IO11
4
IO13
IO15
VIN0
VOUT0
NC
14 IO0
13 VDD
IO13
5
GPIO15/EXT_CLK1
Power Switch 0 VIN
Power Switch 0 VOUT
Not Connected
6
IO15
7
VIN1
12
VIN0
8
11 VOUT1
VOUT0
9
NC
Not Connected
8
9
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AGND
VOUT1
VIN1
Power Switch Ground
Power Switch 1 VOUT
Power Switch 1 VIN
MSTQFN-28
(Top View)
V
V
DD
DD
8
NC
NC
22
IO12
IO14
PWR_SW_ON0
PWR_SW_ON1
IO1
NC
IO6
IO0
IO2
IO3
IO4
IO5
IO7
IO8
IO9
IO12
IO14
GPIO0
9
23
GPIO2
10
AGND
24
25
26
27
28
GPIO3
18
IO5
IO7
IO8
IO9
GPIO4/ACMP0+
GPIO5/ACMP0-
GPIO7/SDA
19
20
21
GPIO8/ACMP1+
GPIO/ACMP0-/ACMP1-/ACMP2-/ACMP3-
GPIO12/ACMP3+
GPIO14/XTAL1/EXT_CLK0
PWR_SW_ON0 Power Switch ON0
PWR_SW_ON1 Power Switch ON1
IO1
NC
IO6
GPIO1
Not Connected
GPIO6/SCL
Table 1: Functional Pin Description
MSTQFN
28L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
1
GND
GND
Ground
--
--
Digital Input without Schmitt
Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
IO10
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
2
IO10
Low Voltage Digital Input
--
Analog Comparator 2
Positive Input
ACMP2+
ACMP3+
Analog
--
Analog Comparator 3
Positive Input
Analog
--
Datasheet
22-Jul-2021
Revision 3.6
10 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 1: Functional Pin Description(Continued)
MSTQFN
28L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
Digital Input without Schmitt
Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
IO11
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
3
IO11
Low Voltage Digital Input
--
Analog Comparator 2
Negative Input
ACMP2-
ACMP3-
Analog
--
Analog Comparator 3
Negative Input
Analog
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
IO13
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
4
IO13
Low Voltage Digital Input
--
External Crystal
Connection 0
XTAL0
--
Analog
Digital Input without Schmitt
Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
IO15
Low Voltage
Digital Input
--
Analog
--
5
IO15
Voltage Reference 1
Output
Vref
--
Digital Input without
Schmitt Trigger
External Clock
Connection 1
EXT_CLK1
Digital Input
with Schmitt Trigger
--
--
Low Voltage Digital Input
--
Input and source termi-
nal of Power Switch 0.
Bypass the VIN0 pin to
GND with a 1 µF
6
7
VIN0
VIN0
--
(or larger), low-ESR ca-
pacitor.
Output and drain termi-
nal of Power Switch 0.
VOUT0
VOUT0
--
8
9
NC
NC
NC
NC
No Connection
No Connection
--
--
--
--
Power switch ground
connection.
10
11
AGND
AGND
Connect this pin to sys-
tem analog or power
ground plane.
--
--
--
Output and drain termi-
nal of Power Switch 1
VOUT1
VOUT1
Datasheet
22-Jul-2021
Revision 3.6
11 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 1: Functional Pin Description(Continued)
MSTQFN
28L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
Input and source termi-
nal of Power Switch 1.
Bypass the VIN1 pin to
GND with a 1 µF
12
13
14
VIN1
VDD
IO0
VIN1
VDD
IO0
--
(or larger), low-ESR ca-
pacitor.
Power Supply
--
--
--
Digital Input without
Schmitt Trigger
General Purpose Input
Digital Input
with Schmitt Trigger
--
Low Voltage Digital Input
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
15
16
IO2
IO3
IO2
IO3
IO4
General Purpose IO
Open-Drain PMOS
(1x) (2x)
Low Voltage Digital Input
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
Low Voltage Digital Input
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
General Purpose IO
17
18
IO4
Open-Drain PMOS
(1x) (2x)
Low Voltage Digital Input
Analog
Analog Comparator 0
Positive Input
ACMP0+
IO5
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
IO5
Low Voltage Digital Input
--
Analog Comparator 0
Negative Input
ACMP0-
IO7
Analog
--
Digital Input without
Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
General Purpose IO
I2C Serial Data
Digital Input
with Schmitt Trigger
--
Low Voltage Digital Input
--
19
IO7
Digital Input without
Schmitt Trigger
Open-Drain NMOS
SDA
Digital Input
with Schmitt Trigger
Open-Drain NMOS
Open-Drain NMOS
Low Voltage Digital Input
Datasheet
22-Jul-2021
Revision 3.6
12 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 1: Functional Pin Description(Continued)
MSTQFN
28L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x) (4x)
IO8
20
IO8
Open-Drain PMOS
(1x) (2x)
Low Voltage Digital Input
Analog
Analog Comparator 1
Positive Input
ACMP1+
IO9
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x) (4x)
21
IO9
Low Voltage Digital Input
--
Analog Comparator
Negative Input
EXT_Vref
Analog
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
IO14
General Purpose IO
Open-Drain PMOS
(1x) (2x)
Low Voltage Digital Input
Analog
23
IO14
External Crystal
Connection 1
XTAL1
--
--
Digital Input without
Schmitt Trigger
External Clock
Connection 0
EXT_CLK0
Digital Input
with Schmitt Trigger
--
--
--
Low Voltage Digital Input
ON0turnsPowerSwitch
0 ON
24
25
PWR_SW_ON0 PWR_SW_ON0
PWR_SW_ON1 PWR_SW_ON1
P-FET gate with 200 Ω resistor
ON1turnsPowerSwitch
1 ON
P-FET gate with 200 Ω resistor
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
26
27
IO1
NC
IO1
NC
IO6
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
Low Voltage Digital Input
--
--
--
No connection
Digital Input without
Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
General Purpose IO
Digital Input
with Schmitt Trigger
--
Low Voltage Digital Input
--
28
IO6
Digital Input without
Schmitt Trigger
Open-Drain NMOS
SCL
I2C Serial Clock
Digital Input
with Schmitt Trigger
Open-Drain NMOS
Open-Drain NMOS
Low Voltage Digital Input
Datasheet
22-Jul-2021
Revision 3.6
13 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 1: Functional Pin Description(Continued)
MSTQFN
28L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
Note 1 General Purpose IO's with OE can be used to implement bidirectional signals under user control via Connection Matrix
to OE signal in IO structure.
Table 2: Pin Type Definitions
Pin Type
GND
Description
Ground
AGND
IO
P-FET Power Switch Ground
Input/Output
VIN
P-FET Power Switch Input
P-FET Power Switch Output
No Connection
VOUT
NC
VDD
Power Supply
PWR_SW_ON
Power Switch ON
Datasheet
22-Jul-2021
Revision 3.6
14 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
3
Characteristics
3.1 ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability.
Table 3: Absolute Maximum Ratings
Parameter
Supply voltage on VDD relative to GND
DC Input voltage
Condition
Min
Max
7
Unit
V
-0.5
GND - 0.5
VDD + 0.5
45
V
TJ = 85 °C
TJ = 110 °C
TJ = 85 °C
TJ = 110 °C
Push-Pull 1x
Push-Pull 2x
OD 1x
--
--
mA
mA
mA
mA
Maximum Average or DC Current Through
VDD Pin (Per chip side) (Note 1)
22
--
86
Maximum Average or DC Current Through
GND Pin (Per chip side) (Note 1)
--
41
--
11
--
16
Maximum Average or DC Current
(Through pin)
--
11
mA
OD 2x
--
21
OD 4x
--
43
Current at Input Pin
Input Leakage Current (Absolute Value)
Storage Temperature Range
Junction Temperature
Moisture Sensitivity Level
VIN
-1.0
--
1.0
mA
nA
°C
1000
150
150
-65
--
°C
1
P-FET
0.3
--
VDD
99
V
ΘJA
Thermal Resistance (Note 2)
°C/W
Maximum Power Dissipation,
TA = +25 °C
PD
--
1.25
W
TJ,MAX
Maximum Junction Temperature
Total, TJ < 150 °C
150
2
°C
A
P-FET Power Switch IDSCONT
--
--
For no more than 1 ms with 1% duty
cycle
P-FET Power Switch IDSPK
2.5
A
Note 1 The GreenPAK’s power rails are divided in two sides. IOs 0, 1, 2, 3, 4, 5, 6, 7, and 8 are connected to one side, IOs 9,
10, 11, 12, 13, 14, and 15 to another.
Note 2 Mounted on 27.4 mm x 30.1 mm PCB (1.6 mm thick, 1 oz copper, FR-4 material).
3.2 ELECTROSTATIC DISCHARGE RATINGS
Table 4: Electrostatic Discharge Ratings
Parameter
Min
2000
1300
Max
--
Unit
V
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
--
V
Datasheet
22-Jul-2021
Revision 3.6
15 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
3.3 RECOMMENDED OPERATING CONDITIONS
Table 5: Recommended Operating Conditions
Parameter
Condition
Min
1.8
Max
5
Unit
V
Supply Voltage (VDD
)
Operating Temperature
Programming Voltage
-40
85
°C
V
7.25
7.75
Maximal Voltage Applied to any PIN in High
Impedance State
--
VDD
V
Capacitor Value at VDD
0.1
0
--
μF
Analog Input Common Mode Range
Allowable Input Voltage atAnalog Pins
VDD
V
3.4 ELECTRICAL CHARACTERISTICS
Table 6: EC at VDD = 1.8 V ±5%, T = -40 °C to +85 °C, Unless Otherwise Noted
Parameter Description
Condition
Min
1.71
1.06
1.28
0.94
0
Typ
1.80
--
Max
1.89
VDD
VDD
VDD
0.76
0.49
0.52
Unit
VDD
Supply Voltage
V
V
V
V
V
V
V
Logic Input
VIH
HIGH-Level Input Voltage
Logic Input with Schmitt Trigger
Low-Level Logic Input
Logic Input
--
--
--
VIL
LOW-Level Input Voltage
Logic Input with Schmitt Trigger
Low-Level Logic Input
0
--
0
--
Schmitt Trigger Hysteresis
Voltage
VHYS
Logic Input with Schmitt Trigger
0.10
0.41
0.66
V
Push-Pull, IOH = 100 μA, 1x Driver
PMOS OD, IOH = 100 μA, 1x Driver
Push-Pull, IOH = 100 μA, 2x Driver
PMOS OD, IOH = 100 μA, 2x Driver
Push-Pull, IOL= 100 μA, 1x Driver
Push-Pull, IOL = 100 μA, 2x Driver
Open-Drain, IOL = 100 μA, 1x Driver
Open-Drain, IOL = 100 μA, 2x Driver
1.69
1.69
1.70
1.70
--
1.79
1.79
1.79
1.79
--
--
V
V
V
V
V
V
V
V
VOH
VOL
IOH
HIGH-Level Output Voltage
--
--
0.009
0.004
0.006
0.003
0.013
0.006
0.009
0.004
--
--
LOW-Level Output Voltage
--
Open-Drain NMOS 4x,
IOL = 100 μA
--
0.001
0.002
V
Push-Pull, VOH = VDD - 0.2, 1x Driver
PMOS OD, VOH = VDD - 0.2, 1x Driver
Push-Pull, VOH = VDD - 0.2, 2x Driver
PMOS OD, VOH = VDD - 0.2, 2x Driver
Push-Pull, VOL = 0.15 V, 1x Driver
Push-Pull, VOL = 0.15 V, 2x Driver
Open-Drain, VOL = 0.15 V, 1x Driver
Open-Drain, VOL = 0.15 V, 2x Driver
1.07
1.07
2.22
2.22
0.92
1.83
1.38
2.75
1.70
1.70
3.41
3.41
1.69
3.38
2.53
5.07
--
--
--
--
--
--
--
--
mA
mA
mA
mA
mA
mA
mA
mA
HIGH-Level Output Pulse
Current (Note 1)
LOW-Level Output Pulse
Current (Note 1)
IOL
Open-Drain NMOS 4x,
VOL = 0.15 V
7.21
0.63
9.00
1.36
--
mA
ms
TSU
Startup Time
From VDD rising past PONTHR
1.87
Datasheet
22-Jul-2021
Revision 3.6
16 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 6: EC at VDD = 1.8 V ±5%, T = -40 °C to +85 °C, Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
PONTHR Power-On Threshold
VDD Level Required to Start Up the Chip
1.41
1.54
1.66
V
VDD Level Required to Switch Off the
Chip
POFFTHR Power-Off Threshold
1.00
1.15
1.31
V
1 M Pull-up
859.8
86.47
10.82
873.9
88.89
9.65
1097.1 1358.9
110.13 136.18
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
RPUP
Pull-up Resistance
100 k Pull-up
10 k Pull-up
12.86
15.36
1 M Pull-down
100 k Pull-down
10 k Pull-down
1097.0 1359.0
110.53 136.55
RPDWN
Pull-down Resistance
12.75
15.76
Note 1 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
Note 2 The GreenPAK’s power rails are divided in two sides. IOs 0, 1, 2, 3, 4, 5, 6, 7 and 8 are connected to one side, IOs 9,
10, 11, 12, 13, 14 to 15 another.
Table 7: EC at VDD = 3.3 V ±10%, T = -40 °C to +85 °C, Unless Otherwise Noted
Parameter Description
Condition
Min
3.0
1.81
2.14
1.06
0
Typ
3.3
--
Max
3.6
Unit
V
VDD
Supply Voltage
Logic Input
VDD
VDD
VDD
1.31
0.97
0.67
V
VIH
HIGH-Level Input Voltage
Logic Input with Schmitt Trigger
Low-Level Logic Input
Logic Input
--
V
--
V
--
V
VIL
LOW-Level Input Voltage
Logic Input with Schmitt Trigger
Low-Level Logic Input
0
--
V
0
--
V
Schmitt Trigger Hysteresis
Voltage
VHYS
Logic Input with Schmitt Trigger
0.29
0.62
0.94
V
Push-Pull, IOH = 3 mA, 1x Driver
PMOS OD, IOH = 3 mA, 1x Driver
Push-Pull, IOH = 3 mA, 2x Driver
PMOS OD, IOH = 3 mA, 2x Driver
Push-Pull, IOL= 3 mA, 1x Driver
Push-Pull, IOL = 3 mA, 2x Driver
Open-Drain, IOL = 3 mA, 1x Driver
Open-Drain, IOL = 3 mA, 2x Driver
2.70
2.70
2.85
2.86
--
3.12
3.12
3.21
3.21
0.13
0.06
0.08
0.04
--
--
V
V
V
V
V
V
V
V
VOH
VOL
IOH
HIGH-Level Output Voltage
--
--
0.23
0.11
0.15
0.08
--
--
LOW-Level Output Voltage
--
Open-Drain NMOS 4x,
IOL = 3 mA
--
0.02
0.04
V
Push-Pull, VOH = 2.4 V, 1x Driver
PMOS OD, VOH = 2.4 V, 1x Driver
Push-Pull, VOH = 2.4 V, 2x Driver
PMOS OD, VOH = 2.4 V, 2x Driver
6.05
6.05
12.08
12.08
24.16
24.16
--
--
--
--
mA
mA
mA
mA
HIGH-Level Output Pulse
Current (Note 1)
11.54
11.52
Datasheet
22-Jul-2021
Revision 3.6
17 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 7: EC at VDD = 3.3 V ±10%, T = -40 °C to +85 °C, Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
4.88
9.75
7.31
14.54
Typ
8.24
Max
--
Unit
mA
mA
mA
mA
Push-Pull, VOL = 0.4 V, 1x Driver
Push-Pull, VOL = 0.4 V, 2x Driver
Open-Drain, VOL = 0.4 V, 1x Driver
Open-Drain, VOL = 0.4 V, 2x Driver
16.49
12.37
24.74
--
LOW-Level Output Pulse
--
IOL
Current (Note 1)
--
Open-Drain NMOS 4x,
VOL = 0.4 V
31.32
41.06
--
mA
TSU
Startup Time
From VDD rising past PONTHR
0.61
1.41
1.24
1.54
1.65
1.66
ms
V
PONTHR Power-On Threshold
POFFTHR Power-Off Threshold
VDD Level Required to Start Up the Chip
V
DD Level Required to Switch Off the
1.00
1.15
1.31
V
Chip
1 M Pull-up
100 k Pull-up
10 k Pull-up
1 M Pull-down
100 k Pull-down
10 k Pull-down
873.2
85.17
9.61
1094.7 1364.3
109.30 135.52
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
RPUP
Pull-up Resistance
11.86
14.73
862.5
87.95
8.66
1096.3 1357.4
109.76 136.06
RPDWN
Pull-down Resistance
11.81
15.05
Note 1 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
Note 2 The GreenPAK’s power rails are divided in two sides. IOs 0, 1, 2, 3, 4, 5, 6, 7 and 8 are connected to one side, IOs 9,
10, 11, 12, 13, 14 to 15 another.
Table 8: EC at VDD = 5 V ±10%, T = -40 °C to +85 °C, Unless Otherwise Noted
Parameter Description
Condition
Min
4.5
2.68
3.34
1.15
0
Typ
5.0
--
Max
5.5
Unit
V
VDD
Supply Voltage
Logic Input
VDD
VDD
VDD
1.96
1.41
0.77
V
VIH
HIGH-Level Input Voltage
Logic Input with Schmitt Trigger
Low-Level Logic Input
Logic Input
--
V
--
V
--
V
VIL
LOW-Level Input Voltage
Logic Input with Schmitt Trigger
Low-Level Logic Input
0
--
V
0
--
V
Schmitt Trigger Hysteresis
Voltage
VHYS
Logic Input with Schmitt Trigger
0.44
0.90
1.38
V
Push-Pull, IOH = 5 mA, 1x Driver
PMOS OD, IOH = 5 mA, 1x Driver
Push-Pull, IOH = 5 mA, 2x Driver
PMOS OD, IOH = 5 mA, 2x Driver
Push-Pull, IOL= 5 mA, 1x Driver
Push-Pull, IOL = 5 mA, 2x Driver
Open-Drain, IOL = 5 mA, 1x Driver
Open-Drain, IOL = 5 mA, 2x Driver
4.15
4.16
4.32
4.33
--
4.76
4.76
4.89
4.89
0.19
0.09
0.12
0.07
--
--
--
--
V
V
V
V
V
V
V
V
VOH
HIGH-Level Output Voltage
0.24
--
0.12
0.16
0.08
--
VOL
LOW-Level Output Voltage
--
Open-Drain NMOS 4x,
IOL = 5 mA
--
0.03
0.05
V
Datasheet
22-Jul-2021
Revision 3.6
18 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 8: EC at VDD = 5 V ±10%, T = -40 °C to +85 °C, Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
--
Unit
mA
mA
mA
mA
mA
mA
mA
mA
Push-Pull, VOH = 2.4 V, 1x Driver
PMOS OD, VOH = 2.4 V, 1x Driver
Push-Pull, VOH = 2.4 V, 2x Driver
PMOS OD, VOH = 2.4 V, 2x Driver
Push-Pull, VOL = 0.4 V, 1x Driver
Push-Pull, VOL = 0.4 V, 2x Driver
Open-Drain, VOL = 0.4 V, 1x Driver
Open-Drain, VOL = 0.4 V, 2x Driver
22.08
22.08
41.76
41.69
7.22
34.04
34.04
68.08
68.08
11.58
23.16
17.38
34.76
--
HIGH-Level Output Pulse
Current (Note 1)
IOH
--
--
--
13.83
10.82
17.34
--
LOW-Level Output Pulse
Current (Note 1)
--
IOL
--
Open-Drain NMOS 4x,
VOL = 0.4 V
41.06
55.18
--
mA
TSU
Startup Time
From VDD rising past PONTHR
0.60
1.41
1.23
1.54
1.61
1.66
ms
V
PONTHR
Power-On Threshold
VDD Level Required to Start Up the Chip
V
Chip
DD Level Required to Switch Off the
POFFTHR Power-Off Threshold
1.00
1.15
1.31
V
1 M Pull-up
100 k Pull-up
10 k Pull-up
1 M Pull-down
100 k Pull-down
10 k Pull-down
864.6
84.32
8.74
1093.4 1348.1
108.97 135.24
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
RPUP
Pull-up Resistance
11.37
14.52
873.3
87.57
7.95
1096.1 1370.5
109.48 135.89
RPDWN
Pull-down Resistance
11.33
14.78
Note 1 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
Note 2 The GreenPAK’s power rails are divided in two sides. IOs 0, 1, 2, 3, 4, 5, 6, 7 and 8 are connected to one side, IOs 9,
10, 11, 12, 13, 14 to 15 another.
Table 9: I2C Pins Timing Characteristics T = -40 °C to +85 °C, Unless Otherwise Noted
Parameter Description
Condition
Min
--
Typ
--
Max
400
--
Unit
kHz
ns
FSCL
tLOW
tHIGH
Clock Frequency, SCL
VDD = 1.71 to 5.5 V
VDD = 1.71 to 5.5 V
VDD = 1.71 to 5.5 V
Clock Pulse Width Low
Clock Pulse Width High
1300
600
--
--
--
--
ns
V
DD = 1.8 V ± 5%
--
95
Input Filter Spike Suppression
(SCL, SDA)
tI
VDD = 3.3 V ± 10%
VDD = 5.0 V ± 10%
VDD = 1.71 to 5.5 V
--
--
95
ns
--
--
111
900
tAA
Clock Low to Data Out Valid
--
--
ns
ns
Bus Free Time between Stop
and Start
tBUF
V
DD = 1.71 to 5.5 V
1300
--
--
tHD_STA
tSU_STA
tHD_DAT
tSU_DAT
tR
Start Hold Time
Start Set-up Time
Data Hold Time
Data Set-up Time
Inputs Rise Time
Inputs Fall Time
Stop Set-up Time
VDD = 1.71 to 5.5 V
VDD = 1.71 to 5.5 V
VDD = 1.71 to 5.5 V
VDD = 1.71 to 5.5 V
VDD = 1.71 to 5.5 V
VDD = 1.71 to 5.5 V
VDD = 1.71 to 5.5 V
600
600
0
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
--
100
--
--
300
300
--
tF
--
tSU_STO
600
Datasheet
22-Jul-2021
Revision 3.6
19 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 9: I2C Pins Timing Characteristics T = -40 °C to +85 °C, Unless Otherwise Noted(Continued)
Parameter Description
tDH Data Out Hold Time
Condition
Min
Typ
Max
Unit
VDD = 1.71 to 5.5 V
50
--
--
ns
Table 10: Asynchronous State Machine Specifications at T = 25 °C
Parameter Description Note
Min
225
95
67
--
Typ
Max
275
118
77
165
70
46
--
Unit
V
DD = 1.8 V ± 5%
--
Asynchronous State Machine
Output Delay Time
tst_out_delay
VDD = 3.3 V ± 10%
VDD = 5.0 V ± 10%
ns
--
--
V
DD = 1.8 V ± 5%
Asynchronous State Machine
Output Transition Time
tst_out
VDD = 3.3 V ± 10%
VDD = 5.0 V ± 10%
--
ns
ns
ns
--
--
--
--
--
--
--
--
V
DD = 1.8 V ± 5%
29
14
9.2
--
Asynchronous State Machine
Input Pulse Acceptance Time
tst_pulse
VDD = 3.3 V ± 10%
VDD = 5.0 V ± 10%
--
--
V
DD = 1.8 V ± 5%
29
14
10
Asynchronous State Machine
Input Compete Time
tst_comp
VDD = 3.3 V ± 10%
VDD = 5.0 V ± 10%
--
--
Table 11: Typical Current Estimated for Each Macrocell at T = -40 °C to +85 °C
Parameter
Description Note
Chip Quiescent
VDD = 1.8 V VDD = 3.3 V VDD = 5.0 V
Unit
0.45
41.48
25.68
7.16
0.75
64.00
32.41
7.94
1.12
94.89
43.22
9.25
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
OSC 2 MHz, pre-divider = 1
OSC 2 MHz, pre-divider = 8
OSC 25 kHz, pre-divider = 1
OSC 25 kHz, pre-divider = 8
OSC 25 MHz, pre-divider = 1
OSC 25 MHz, pre-divider = 1, Force On
OSC 25 MHz, pre-divider = 8
ACMP (each)
6.97
7.60
8.68
87.25
87.25
78.01
54.96
75.06
49.70
71.93
238.27
238.27
212.45
52.64
72.74
47.32
71.27
428.66
428.67
390.17
60.81
81.25
55.60
79.62
IDD
Current
ACMP with buffer (each)
Vref
Vref with buffer
3.5 TIMING CHARACTERISTICS
Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C
VDD = 1.8 V
VDD = 3.3V
VDD = 5.0V
Parameter Description Note
Unit
Rising Falling Rising Falling Rising Falling
tpd
tpd
tpd
Delay
Delay
Delay
Digital Input to PP 1x
45
44
46
50
19
19
19
21
14
14
14
15
ns
ns
ns
Digital Input with Schmitt Trigger
to PP 1x
49
21
15
Low Voltage Digital input to PP 1x
447
195
134
Datasheet
22-Jul-2021
Revision 3.6
20 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C(Continued)
VDD = 1.8 V
VDD = 3.3V
VDD = 5.0V
Parameter Description Note
Unit
Rising Falling Rising Falling Rising Falling
tpd
tpd
Delay
Delay
Digital input to PMOS output
Digital input to NMOS output
44
-
-
19
-
-
14
-
-
ns
ns
81
30
20
Output enable from pin, OE Hi-Z
to 1
tpd
tpd
Delay
Delay
48
-
-
20
-
-
15
-
-
ns
ns
Output enable from pin, OE Hi-Z
to 0
46
20
14
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
LUT2bit(LATCH)
LATCH(LUT2bit)
LUT3bit(LATCH)
LATCH+nRESET(LUT3bit)
LATCH
34
30
33
34
14
14
13
13
10
10
9
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
38
37
18
15
13
10
12
10
9
45
42
21
17
15
33
35
14
14
11
LUT4bit
28
33
14
13
10
LUT2bit
31
31
14
13
10
9
LUT3bit
35
33
15
13
11
10
20
9
CNT/DLY Logic
DFF
62
68
27
29
19
32
28
14
12
11
P_DLY1C
367
667
968
1265
213
1600
356
656
956
1252
210
1900
165
303
440
576
84
160
297
434
570
83
123
225
327
428
55
119
221
322
423
55
1800
P_DLY2C
P_DLY3C
P_DLY4C
Filter
ACMP (5mV overdrive)
1500
1800
1600
Pulse
Width
IO with 1x Push-Pull (min transmit-
ted)
tw
tw
20
20
20
55
20
55
20
35
20
35
ns
ns
Pulse
Width
filter (min transmitted)
150
150
Table 13: Typical Propagations Delays and Pulse Widths at T = 25 °C
Parameter Description Note
VDD = 1.8 V VDD = 3.3V VDD = 5.0V
Unit
Pulse Width,
tw
tw
tw
tw
mode: (any)edge detect, edge detect output
mode: (any)edge detect, edge detect output
mode: (any)edge detect, edge detect output
mode: (any)edge detect, edge detect output
296
597
135
272
410
546
101
203
305
407
ns
ns
ns
ns
1 cell
Pulse Width,
2 cell
Pulse Width,
3 cell
898
Pulse Width,
4 cell
1195
time1
time1
time1
time1
time2
time2
Delay, 1 cell mode: (any)edge detect, edge detect output
Delay, 2 cell mode: (any)edge detect, edge detect output
Delay, 3 cell mode: (any)edge detect, edge detect output
Delay, 4 cell mode: (any)edge detect, edge detect output
Delay, 1 cell mode: both edge delay, edge detect output
Delay, 2 cell mode: both edge delay, edge detect output
55
55
24
24
18
18
ns
ns
ns
ns
ns
ns
55
24
18
55
24
18
367
667
165
300
106
193
Datasheet
22-Jul-2021
Revision 3.6
21 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 13: Typical Propagations Delays and Pulse Widths at T = 25 °C(Continued)
Parameter Description Note
VDD = 1.8 V VDD = 3.3V VDD = 5.0V
Unit
ns
time2
time2
Delay, 3 cell mode: both edge delay, edge detect output
Delay, 4 cell mode: both edge delay, edge detect output
968
440
575
279
365
1265
ns
Table 14: Typical Deglitch Filter Pulse Width Performance at T = 25 °C
Parameter
VDD = 2.5 V VDD = 3.3V VDD = 5.0V
Unit
Filtered Pulse Width for Filter 0
Filtered Pulse Width for Filter 1
< 114
<75
< 47
<30
< 30
<19
ns
ns
Table 15: Typical Counter/Delay Offset Measurements at T = 25 °C
RC OSC
Description
RC OSC Power VDD = 1.8 V VDD = 3.3V VDD = 5.0V
Unit
Freq
25 kHz
25 kHz
2 MHz
2 MHz
25 MHz
25 kHz
2 MHz
25 kHz
2 MHz
25 MHz
Offset (start time)
auto
auto
auto
auto
auto
auto
auto
forced
forced
--
1.6
2.1
1.6
2.1
1.6
2.1
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
Offset (start time), fast start
Offset (start time)
0.4
0.2
0.2
Offset (start time), fast start
Offset (start time)
0.7
0.5
0.4
0.01
19
0.05
14
0.04
12
Frequency settling time
Frequency settling time
Variable (CLK period)
Variable (CLK period)
Variable (CLK period)
14
14
14
0-40
0-0.5
0-0.04
0-40
0-0.5
0-0.04
0-40
0-0.5
0-0.04
25 kHz/
2 MHz
Tpd (non-delayed edge)
either
35
14
10
ns
3.6 OSC CHARACTERISTICS
Table 16: 25 kHz RC OSC0 Frequency Limits VDD = 2.3 V to 5.5 V
Temperature Range
0 °C to +85 °C
Power Supply Range
(VDD), V
+25 °C
Minimum
-40 °C to +85 °C
Maximum
Value, kHz
Minimum
Maximum
Minimum
Maximum
Value, kHz
Value, kHz
Value, kHz
Value, kHz
Value, kHz
1.8 V ±5%
3.3 V ±10%
5 V ±10%
23.792
26.288
25.526
25.939
25.559
26.670
23.275
27.089
21.728
29.173
27.002
27.181
27.038
29.545
24.473
23.357
26.028
23.357
24.316
23.309
26.177
23.309
2.5 V to 4.5 V
1.71 V to 5.5 V
24.438
23.336
26.051
23.336
23.354
22.828
27.483
21.301
Datasheet
22-Jul-2021
Revision 3.6
22 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 17: 25 kHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
Error (% at
Minimum)
-4.83%
-2.11%
0 °C to +85 °C
-40 °C to +85 °C
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Minimum)
-6.90%
-6.57%
-6.76%
-6.66%
-8.69%
Minimum)
-13.09%
-6.57%
1.8 V ±5%
3.3 V ±10%
5 V ±10%
5.15%
2.10%
3.76%
2.24%
6.68%
8.36%
4.11%
4.71%
4.21%
9.93%
16.69%
8.01%
8.72%
8.15%
18.18%
-2.73%
-2.25%
-6.58%
-6.76%
2.5 V to 4.5 V
1.71 V to 5.5 V
-6.66%
-14.80%
Table 18: 2 MHz RC OSC0 Frequency Limits VDD = 2.3 V to 5.5 V
Temperature Range
0 °C to +85 °C
Power Supply Range
(VDD), V
+25 °C
-40 °C to +85 °C
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
1.8 V ±5%
3.3 V ±10%
5 V ±10%
1.915
2.062
2.070
2.233
2.124
2.274
1.832
2.103
2.132
2.270
2.171
2.305
1.810
1.813
1.767
1.784
1.629
2.144
2.145
2.270
2.171
2.305
1.937
1.858
1.894
1.853
2.5 V to 4.5 V
1.71 V to 5.5 V
1.907
1.836
1.760
1.706
Table 19: 2 MHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
Error (% at
0 °C to +85 °C
-40 °C to +85 °C
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Error (% at
Minimum)
Error (% at
Maximum)
Minimum)
Minimum)
1.8 V ±5%
3.3 V ±10%
5 V ±10%
-4.26%
3.12%
3.49%
11.66%
6.18%
13.72%
-8.38%
5.17%
6.58%
13.50%
8.57%
15.23%
-9.50%
-9.33%
7.20%
7.24%
13.50%
8.57%
15.23%
-3.14%
-7.10%
-5.31%
-7.37%
-11.67%
-10.81%
-18.57%
2.5 V to 4.5 V
1.71 V to 5.5 V
-4.65%
-8.22%
-12.01%
-14.69%
Table 20: 25 MHz RC OSC1 Frequency Limits
Temperature Range
0 °C to +85 °C
Power Supply Range
(VDD), V
+25 °C
-40 °C to +85 °C
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
2.5 V ±10%
22.316
27.220
21.771
27.572
21.771
27.912
Datasheet
22-Jul-2021
Revision 3.6
23 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 20: 25 MHz RC OSC1 Frequency Limits(Continued)
Temperature Range
0 °C to +85 °C
Power Supply Range
(VDD), V
+25 °C
-40 °C to +85 °C
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
3.3 V ±10%
5 V ±10%
23.430
26.220
26.651
26.220
26.220
22.389
26.679
27.305
26.679
26.679
22.389
27.014
27.486
27.014
27.014
23.289
22.500
22.500
2.5 V to 4.5 V
1.71 V to 5.5 V
23.383
20.725
20.725
12.643
12.203
11.317
Table 21: 25 MHz RC OSC1 Frequency Error (Error Calculated Relative to Nominal Value)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
Error (% at
0 °C to +85 °C
-40 °C to +85 °C
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Error (% at
Minimum)
Error (% at
Maximum)
Minimum)
Minimum)
2.5 V ±10%
-10.73%
8.88%
-12.92%
10.29%
-12.92%
11.65%
3.3 V ±10%
5 V ±10%
-6.28%
-6.84%
4.88%
6.61%
4.88%
4.88%
-10.44%
-10.00%
-17.10%
-51.19%
6.72%
9.22%
6.72%
6.72%
-10.44%
-10.00%
-17.10%
-54.73%
8.06%
9.95%
8.06%
8.06%
2.5 V to 4.5 V
1.71 V to 5.5 V
-14.47%
-49.43%
Note: 25 MHz RC OSC1 performance is not guaranteed at VDD < 2.5 V.
Datasheet
22-Jul-2021
Revision 3.6
24 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
3.6.1 OSC Power-On Delay
Note: DLY/CNT Counter Data = 100, RC OSC Power Setting: "Auto Power-On", RC OSC Clock to Matrix Input: "Enable".
Table 22: OSC Power-On Delay, T = 25 °C
RC OSC0 2 MHz
RC OSC0 25 kHz
RC OSC1
Power Supply
Range
Typical
Maximum
Value, ns
Typical
Maximum
Value, µs
Typical
Maximum
Value, ns
(VDD) V
Value, ns
372.7
349.2
330.3
277.2
262.0
250.2
236.6
226.7
219.0
207.4
202.8
196.3
190.8
Value, µs
0.40
0.38
0.35
0.29
0.28
0.26
0.25
0.23
0.22
0.37
1.63
1.67
1.69
Value, ns
71.2
65.0
59.7
43.0
39.6
36.7
33.2
30.4
28.2
25.8
25.0
24.3
23.7
1.71
1.80
1.89
2.30
2.50
2.70
3.00
3.30
3.60
4.20
4.50
5.00
5.50
407.3
379.5
358.0
298.1
281.9
269.8
256.7
247.4
239.9
229.2
224.5
218.7
213.3
0.57
0.41
0.41
0.31
0.30
0.30
0.44
0.47
0.46
0.50
1.92
2.05
1.99
87.3
78.7
71.3
54.0
48.1
43.5
39.8
36.8
34.3
30.6
29.2
27.5
26.8
Table 23: OSC Power-On Delay, T = 25 °C, Fast Start-Up Time Mode
RC OSC0 2 MHz
RC OSC1 25 kHz
Power Supply
Range
Typical
Value, ns
Maximum
Value, ns
Typical
Maximum
(VDD) V
Value, µs
Value, µs
1.71
1.80
1.89
2.30
2.50
2.70
3.00
3.30
3.60
4.20
4.50
5.00
5.50
327.9
309.9
295.5
254.9
243.1
234.1
223.7
215.7
209.4
199.5
195.5
189.8
184.9
360.0
338.3
323.1
278.1
266.1
257.1
246.8
239.1
232.9
223.4
219.8
214.6
209.8
0.68
0.76
0.64
0.64
0.61
0.70
0.53
21.93
21.88
21.94
21.90
21.77
21.74
21.78
21.69
21.71
21.75
3.23
16.68
19.25
19.22
19.21
19.17
19.15
19.12
19.05
Datasheet
22-Jul-2021
Revision 3.6
25 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
3.7 ACMP CHARACTERISTICS
Table 24: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V, Unless Otherwise Noted
Parameter Description
Note
Conditions
Min
0
Typ
--
Max
VDD
1.2
Unit
V
Positive Input
Negative Input
Positive Input
Negative Input
Positive Input
Negative Input
VDD = 1.8 V ± 5%
0
--
V
0
--
VDD
1.2
V
ACMP Input Voltage
VACMP
VDD = 3.3 V ± 10%
Range
0
--
V
0
--
VDD
1.2
V
VDD = 5.0 V ± 10%
T = 25 °C
0
--
V
Low Bandwidth -
Enable, Vhys = 0 mV,
Gain = 1,
-9.1
--
8.4
mV
Vref = 50 mV to
1200 mV,
VDD = 1.71 V to 5.5 V
T = -40 °C to 85 °C
T = 25 °C
-10.9
-7.5
--
--
--
10.9
7.2
mV
mV
mV
ACMP Input Offset
Voltage
Voffset
Low Bandwidth -
Disable, Vhys = 0 mV,
Gain =1,
Vref = 50 mV to
1200 mV,
T = -40 °C to 85 °C
-10.7
10.5
VDD = 1.71 V to 5.5 V
BG = 550 μs,
T = 25 °C
VDD = 1.71 V to 5.5 V
--
--
--
--
--
--
--
--
609.7
675.0
132.4
149.4
609.5
674.6
131.6
149.2
862.2
1028.8
176.2
213.5
862.0
1027.5
176.0
213.3
µS
µS
µS
µS
µS
µS
µS
µS
ACMP Power-On
delay, Minimal
required wake time for
the "Wake and Sleep
function",
Regulator and Charge
Pump set to automatic
ON/OFF
BG = 550 μs,
T = -40 °C to 85 °C
VDD = 1.71 V to 5.5 V
BG = 100 μs,
T = 25 °C
DD = 2.7 V to 5.5 V
V
BG = 100 μs,
T = -40 °C to 85 °C
DD = 2.7 V to 5.5 V
V
tstart
ACMP Start Time
BG = 550 μs,
T = 25 °C
VDD = 3V to 5.5 V
ACMP Power-On
delay, Minimal
required wake time for
the "Wake and Sleep
function",
Regulator and Charge
Pump always OFF
BG = 550 μs,
T = -40 °C to 85°C
DD = 3 V to 5.5 V
V
BG = 100 μs,
T = 25 °C
DD = 3 V to 5.5 V
V
BG = 100 μs,
T = -40 °C to 85°C
VDD = 3 V to 5.5 V
Datasheet
22-Jul-2021
Revision 3.6
26 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 24: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V, Unless Otherwise Noted(Continued)
Parameter Description
Note
Conditions
Min
Typ
Max
Unit
LB - Enabled,
T = 25 °C
7.32
--
35.5
mV
VHYS = 25 mV
VIL = Vin - VHYS/2
VIH = Vin + VHYS/2
LB - Disabled,
T = 25 °C
10.0
42.9
--
--
--
--
--
38.5
57.8
mV
mV
mV
mV
mV
LB - Enabled,
T = 25 °C
VHYS = 50 mV
VIL = Vin - VHYS
VIH = VHYS
LB - Disabled,
T = 25 °C
44.2
54.3
LB - Enabled,
T = 25 °C
192.7
193.3
208.7
204.8
V
HYS = 200 mV
VIL = Vin - VHYS
VIH = VHYS
VHYS
Built-in Hysteresis
LB - Disabled,
T = 25 °C
VHYS = 25 mV
VIL = Vin - VHYS/2
VIH = Vin + VHYS/2
LB - Enabled
LB - Disabled
LB - Enabled
LB - Disabled
LB - Enabled
LB - Disabled
0.0
0.0
--
--
--
--
--
--
58.0
52.9
mV
mV
mV
mV
mV
mV
VHYS = 50 mV
VIL = Vin - VHYS
VIH = VHYS
22.5
29.2
157.1
160.2
86.9
76.5
VHYS = 200 mV
VIL = Vin - VHYS
VIH = VHYS
251.6
245.3
Gain = 1x
--
--
--
--
100.0
1.0
--
--
--
--
ΜΩ
ΜΩ
ΜΩ
ΜΩ
Gain = 0.5x
Gain = 0.33x
Gain = 0.25x
Rsin
Series Input Resistance
0.8
1.0
Low Bandwidth -
Enable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 50 mV
Low to High,
T = (-40…+85)°C
--
--
--
--
--
--
--
--
--
--
35.99
39.36
1.85
216.56
208.81
3.04
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 50 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
2.17
4.10
Low Bandwidth -
Enable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 50 mV
Low to High,
T = (-40…+85)°C
25.22
28.31
1.55
129.31
145.47
2.63
Propagation Delay,
Response Time
PROP
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 50 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
1.93
3.83
Low Bandwidth -
Enable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 250 mV
Low to High,
T = (-40…+85)°C
36.46
39.79
216.78
216.05
High to Low,
T = (-40…+85)°C
Datasheet
22-Jul-2021
Revision 3.6
27 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 24: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V, Unless Otherwise Noted(Continued)
Parameter Description
Note
Conditions
Min
Typ
Max
Unit
Low Bandwidth -
Disable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 250 mV
Low to High,
T = (-40…+85)°C
--
2.04
3.37
µs
High to Low,
T = (-40…+85)°C
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
2.21
25.81
28.65
1.74
4.12
132.94
142.43
2.93
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Low Bandwidth -
Enable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 250 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 250 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
1.97
3.96
Low Bandwidth -
Enable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 600 mV
Low to High,
T = (-40…+85)°C
37.36
40.67
2.23
222.82
219.61
4.02
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 600 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
2.23
4.33
Low Bandwidth -
Enable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 600 mV
Low to High,
T = (-40…+85)°C
26.41
29.32
1.92
135.47
149.01
3.53
Propagation Delay,
Response Time
PROP
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 600 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
2.00
4.25
Low Bandwidth -
Enable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 850 mV
Low to High,
T = (-40…+85)°C
38.36
41.67
2.26
232.64
232.78
4.20
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 850 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
2.25
4.60
Low Bandwidth -
Enable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 850 mV
Low to High,
T = (-40…+85)°C
27.08
29.89
1.91
137.02
146.92
3.57
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 850 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
1.98
4.34
Datasheet
22-Jul-2021
Revision 3.6
28 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 24: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V, Unless Otherwise Noted(Continued)
Parameter Description
Note
Conditions
Min
Typ
Max
Unit
Low Bandwidth -
Enable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 1200 mV
Low to High,
T = (-40…+85)°C
--
103.93 1853.68
101.06 1656.70
µs
High to Low,
T = (-40…+85)°C
--
--
--
--
--
--
--
µs
µs
µs
µs
µs
µs
µs
Low Bandwidth -
Disable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 1200 mV
Low to High,
T = (-40…+85)°C
68.29
63.06
30.62
33.54
5.00
1753.33
1568.55
167.56
181.40
32.61
High to Low,
T = (-40…+85)°C
Propagation Delay,
Response Time
PROP
Low Bandwidth -
Enable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 1200 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 1200 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
5.24
33.88
G = 1, VDD = 1.71 V
G = 1, VDD = 3.3 V
--
1
1
--
--
--
G = 1, VDD = 5.5 V
--
1
--
G = 0.5, VDD = 1.71 V
G = 0.5, VDD = 3.3 V
G = 0.5, VDD = 5.5 V
G = 0.33, VDD = 1.71V
G = 0.33, VDD = 3.3 V
G = 0.33, VDD = 5.5 V
G = 0.25, VDD = 1.71V
G = 0.25, VDD = 3.3 V
G = 0.25, VDD = 5.5 V
-1.00%
-0.96%
-1.04%
-1.75%
-1.95%
-2.03%
-1.91%
-1.98%
-2.12%
--
--
--
--
--
--
--
--
--
0.93%
0.82%
0.90%
2.10%
1.69%
1.77%
2.13%
1.80%
1.90%
Gain error (including
threshold and internal
Vref error),
Vref = 50 mV to
1200 mV
G
T = -40 °C to +85 °C
Datasheet
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 24: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V, Unless Otherwise Noted(Continued)
Parameter Description
Note
Conditions
T = 25 °C
Min
Typ
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
Unit
-0.58%
-1.01%
-0.59%
-1.06%
-0.64%
-1.16%
-0.57%
-1.14%
-0.59%
-1.04%
-0.67%
-1.15%
-0.64%
-1.11%
-0.63%
-1.10%
-0.72%
-1.15%
0.56%
0.70%
0.58%
0.72%
0.60%
0.74%
0.58%
0.76%
0.58%
0.73%
0.64%
0.73%
0.64%
0.75%
0.63%
0.78%
0.70%
0.80%
VDD = 1.8 V ± 5%
T = 25 °C
T = 25 °C
T = 25 °C
T = 25 °C
T = 25 °C
T = 25 °C
T = 25 °C
T = 25 °C
Internal Vref error,
Vref = 1200 mV
VDD = 3.3 V ± 10%
VDD = 5.0 V ± 10%
VDD = 1.8 V ± 5%
VDD = 3.3 V ± 10%
VDD = 5.0 V ± 10%
VDD = 1.8 V ± 5%
VDD = 3.3 V ± 10%
VDD = 5.0 V ± 10%
Internal Vref error,
Vref = 1000 mV
Vref
Internal Vref error,
Vref = 500 mV
3.8 POWER SWITCH EC (EACH P-FET)
Table 25: Power Switch EC, TA = -40 °C to +85 °C (Typ Values at TA = +25 °C), VDD = 5.5 V, Unless Otherwise Noted
Parameter Description
Conditions
Min
Typ
Max
Unit
TA = +25 °C, VGS = -5.5 V, ID = -100
mA (Note 1)
--
44
50
TA = +25 °C, VGS = -3.3 V, ID = -100
mA (Note 1)
--
--
--
--
58
110
51
65
119
58
TA = +25 °C, VGS = -1.71 V, ID =
-100 mA (Note 1)
Static Drain-to-Source On-Resis-
tance
RDS(ON)
mΩ
TA = +85 °C, VGS = -5.5 V, ID = -100
mA (Note 1)
TA = +85 °C, VGS = -3.3 V, ID = -100
mA (Note 1)
69
77
TA = +85 °C, VGS = -1.71 V, ID =
-100 mA (Note 1)
--
-0.48
--
129
-0.61
--
138
-0.72
0.4
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = -1 mA
V
TA = +25 °C, VDS = -4.0 V, VGS = 0
V (Note 2)
TA = +25 °C, VDS = -5.5 V, VGS = 0
V
IDSS
Zero Gate Voltage Drain Current
--
--
--
--
1.0
3.4
µA
TA = +85 °C, VDS = -5.5 V, VGS = 0
V
TA = +25 °C, VGS = ±5.5 V
TA = +85 °C, VGS = ±5.5 V
--
--
±5
±100
IGSS
Gate-Body Leakage
nA
±400
±2000
Datasheet
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 25: Power Switch EC, TA = -40 °C to +85 °C (Typ Values at TA = +25 °C), VDD = 5.5 V, Unless Otherwise Noted
Parameter Description
Conditions
Min
Typ
Max
Unit
VDS = -5.5 V, VGS = -1.8 V, ID = -2
A (Note 1)
Gm
Forward Transconductance
4.5
5.4
--
S
Dynamic
RG
Internal Gate Resistance
Input Capacitance
--
--
--
--
--
--
--
200
207
122
57
--
--
Ω
Ciss
TA = +25 °C
VDS = -5.5 V
VGS = 0 V
ƒ = 1.0 MHz (Note 3)
Coss
Crss
Qg
Output Capacitance
--
pF
Reverse Transfer Capacitance
Total Gate Charge
--
TA = +25 °C
1.45
0.24
0.24
1.55
--
VDS = -5.5 V
VGS = -5.5 V
ID = -2 A (Note 1)
Qgs
Gate-to-Source Charge
Gate-to-Drain Charge
nC
Qgd
--
TA = +25 °C, VDS = -5.5 V, VGS = 0
to -5.5 V, ID = -1 A, Internal Drive
ton
toff
Turn-On Time
--
--
63
--
--
ns
ns
TA = +25 °C, VDS = -5.5 V, VGS = 0
to -5.5 V, ID = -1 A, Internal Drive
Turn-Off Delay Time
287
Drain-Source Body Diode Characteristics
Maximum Continuous
Drain-Source Diode Forward Cur-
rent
TA = +25 °C, single channel opera-
tion
IS
--
--
-2
A
V
VDSF
Diode Forward Voltage
VGS = 0 V, IS = 100 mA (Note 1)
0.63
0.75
0.87
Note 1 Pulse test: ƒ = 100 Hz, Duty cycle < 2%.
Note 2 Measured to be less than 0.4 μA during production test.
Note 3 RG influence has been excluded.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
4
User Programmability
The SLG46517 is a user programmable device with one time programmable (OTP) memory elements that are able to configure
the connection matrix and macrocells. A programming development kit allows the user the ability to create initial devices. Once
the design is finalized, the programming code (.gpx file) is forwarded to Dialog Semiconductor to integrate into a production
process.
Product
Definition
E-mail Product Idea, Definition, Drawing or
Customer creates their own design in
Schematic to
GreenPAK Designer
CMBUGreenPAK@diasemi.com
Dialog Semiconductor Applications
Program Engineering Samples with
Engineer will review design specifications
GreenPAK Programmer
with customer
Samples, Design and Characterization
Report send to customer
Customer verifies GreenPAK in system
design
GreenPAK Design
GreenPAK Design
approved
approved
E-mail .gpx to
CMBUGreenPAK@diasemi.com
Customers verifies GreenPAK design
GreenPAK Design
Approved in system test
Custom GreenPAK part enters production
Figure 2: Steps to Create a Custom GreenPAK Device
Datasheet
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
5
IO Pins
The SLG46517 has a total of 18 multi-function IO pins which can function as either a user defined Input or Output, as well as
serving as a special function (such as voltage reference output), or serving as a signal for programming of the on-chip Non Volatile
Memory (NVM).
Refer to Section 2 for normal and programming modepin definitions.
Normal Mode pin definitions are as follows:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
VDD: VDD power supply
IO0: general purpose input
IO1: general purpose input or output with OE
IO2: general purpose input or output
IO3: general purpose input or output with OE
IO4: general purpose input or output or analog comparator 0(+)
IO5: general purpose input or output with OE or analog comparator 0(-)
IO6: general purpose input or OD output I2C SCL
IO7: general purpose input or OD output I2C SDA
IO8: general purpose input or output with OE, or analog comparator 1(+)
GND: ground
IO9: general purpose input or output, or analog comparator 1(-)
IO10: general purpose input or output with OE, or analog comparator 2(+)
IO11: general purpose input or output with OE, or analog comparator 2(-)
IO12: general purpose input or output, or analog comparator 3(+)
IO13: general purpose input or output with OE
IO14: general purpose input or output
IO15: general purpose input or output with OE and Vref output (Vref)
VIN0: Power Switch 0 VIN
VOUT0: Power Switch 0 VOUT
AGND: Power Switch Ground
VOUT1: Power Switch 1 VOUT
VIN1: Power Switch 1 VIN
ON0: Power Switch 0 ON
ON1: Power Switch 1 ON
Programming Mode pin definitions are as follows:
•
•
•
•
•
•
VDD: VDD power supply
IO0: VPP programming voltage
IO6: Programming SCL
IO7: Programming SDA
GND: ground
IO13: programming mode control
Of the 18 user defined IO pins on the SLG46517, all but one of the pins (IO0) can serve as both digital input and digital output.
IO0 can only serve as a digital input pin.
5.1 INPUT MODES
Each IO pin can be configured as a digital input pin with/without buffered Schmitt Trigger, or can also be configured as a low
voltage digital input. IOs 4, 5, 8, 9, 10, 11, and 12 can also be configured to serve as analog inputs to the on-chip comparators.
IOs 15 and 16 can also be configured as analog reference voltage inputs.
5.2 OUTPUT MODES
IOs 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, and 17 can all be configured as digital output pins.
Datasheet
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
5.3 PULL-UP/DOWN RESISTORS
All IO pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors
are 10 kΩ, 100 kΩ, and 1 MΩ. In the case of IO0, the resistors are fixed to a Pull-down configuration. In the case of all other IO
pins, the internal resistors can be configured as either Pull-up or Pull-downs.
5.4 IO REGISTER SETTINGS
Table 26: IO0 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO0 Pull-down
Resistor Value
Selection
[1028:1029]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO0 Mode Control
[1030:1031]
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
Table 27: IO1 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO1 Pull-up/down
Resistor Selection
[1033]
0: Pull-down Resistor
1: Pull-up Resistor
IO1 Pull-up/down
Resistor Value
Selection
[1035:1034]
[1037:1036]
[1039:1038]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO1 Mode Control
(sig_IO1_oe = 0)
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
IO1 Mode Control
(sig_IO1_oe = 1)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
Table 28: IO2 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO2 Driver Strength
Selection
[1041]
0: 1x
1: 2x
IO2 Pull-up/down
Resistor Selection
[1042]
0: Pull-down Resistor
1: Pull-up Resistor
IO2 Pull-up/down
Resistor Value
Selection
[1044:1043]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
Datasheet
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 28: IO2 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
IO2 Mode Control
[1047:1045]
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Reserved
Table 29: IO3 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO3 Pull-up/down
Resistor Selection
[1049]
0: Pull-down Resistor
1: Pull-up Resistor
IO3 Pull-up/down
Resistor Value
Selection
[1051:1050]
[1053:1052]
[1055:1054]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO3 Mode Control
(sig_IO3_oe = 0)
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
IO3 Mode Control
(sig_IO3_oe = 1)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
Table 30: IO4 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO4 Driver Strength
Selection
[1057]
0: 1x
1: 2x
IO4 Pull-up/down
Resistor Selection
[1058]
0: Pull-down Resistor
1: Pull-up Resistor
IO4 Pull-up/down
Resistor Value
Selection
[1060:1059]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO4 Mode Control
[1063:1061]
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input & Open-Drain
Datasheet
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CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 31: IO5 Register Settings
Register Bit
Signal Function
Address
Register Definition
IO5 Pull-up/down
Resistor Selection
[1065]
0: Pull-down Resistor
1: Pull-up Resistor
IO5 Pull-up/down
Resistor Value
Selection
[1067:1066]
[1069:1068]
[1071:1070]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO5 Mode Control
(sig_IO5_oe = 0)
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
IO5 Mode Control
(sig_IO5_oe = 1)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
Table 32: IO6 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO6 Driver Strength
Selection
[1073]
0: 1x
1: 2x
Select SCL& Virtual
Input 0 or IO6
[1074]
0: SCL & Virtual Input 0
1: IO6
IO6 Pull-down
Resistor Value
Selection
[1076:1075]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO6 Mode Control
[1079:1077]
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Reserved
101: Open-Drain NMOS
110: Reserved
111: Reserved
Table 33: IO7 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO7 (or SDA) Driver
Strength Selection
[1081]
0: 1x
1: 2x
SelectSDA&Virtual
Input 1 or IO7
[1082]
0: SDA & Virtual Input 1
1: IO7
IO7 Pull-down
Resistor Value
Selection
[1084:1083]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
Datasheet
22-Jul-2021
Revision 3.6
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 33: IO7 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
IO7 (or SDA) Mode
Control
[1087:1085]
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Reserved
101: Open-Drain NMOS
110: Reserved
111: Reserved
Table 34: IO8 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO8 4x Drive (4x,
NMOS Open-Drain)
Selection
[1088]
0: 4x Drive Off
1: 4x Drive On (if [884:882] = ‘101’)
(IO8 OE = 1 and PIN Mode is OD NMOS 1x)
IO8 Pull-up/down
Resistor Selection
[1089]
0: Pull-down Resistor
1: Pull-up Resistor
IO8 Pull-up/down
Resistor Value
Selection
[1091:1090]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO8 Mode Control
(sig_IO8_oe = 0)
[1093:1092]
[1095:1094]
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
IO8 Mode Control
(sig_IO8_oe = 1)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
Table 35: IO9 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO9 4x Drive (4x,
NMOS Open-Drain)
Selection
[1096]
0: 4x Drive Off
1: 4x Drive On (if [892:890] = ‘101’)
(IO9 OE = 1 and PIN Mode is OD NMOS 1x)
IO9 Driver Strength
Selection
[1097]
[1098]
0: 1x
1: 2x
IO9 Pull-up/down
Resistor Selection
0: Pull-down Resistor
1: Pull-up Resistor
IO9 Pull-up/down
Resistor Value
Selection
[1100:1099]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
Datasheet
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Revision 3.6
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 35: IO9 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
IO9 Mode Control
[1103:1101]
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input & Open-Drain
Table 36: IO10 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO10 Pull-up/down
Resistor Selection
[1105]
0: Pull-down Resistor
1: Pull-up Resistor
IO10 Pull-up/down
Resistor Value
Selection
[1107:1106]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO10 Mode Control
(sig_IO10_oe = 0)
[1109:1108]
[1111:1110]
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
IO10 Mode Control
(sig_IO10_oe = 1)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
Table 37: IO11 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO11 Pull-up/down
Resistor Selection
[1113]
0: Pull-down Resistor
1: Pull-up Resistor
IO11 Pull-up/down
Resistor Value
Selection
[1115:1114]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO11 Mode Control
(sig_IO11_oe = 0)
[1117:1116]
[1119:1118]
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
IO11 Mode Control
(sig_IO11_oe = 1)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
Datasheet
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Revision 3.6
38 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 38: IO12 Register Settings
Register Bit
Signal Function
Address
Register Definition
IO12 Driver
Strength Selection
[1121]
0: 1x
1: 2x
IO12 Pull-up/down
Resistor Selection
[1122]
0: Pull-down Resistor
1: Pull-up Resistor
IO12 Pull-up/down
Resistor Value
Selection
[1124:1123]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO12 Mode Control
[1127:1125]
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input & Open-Drain
Table 39: IO13 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO13 Pull-up/down
Resistor Selection
[1129]
0: Pull-down Resistor
1: Pull-up Resistor
IO13 Pull-up/down
Resistor Value
Selection
[1131:1130]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO13 Mode Control
(sig_IO13_oe = 1)
[1135:1134]
[1133:1132]
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO13 Mode Control
(sig_IO13_oe = 0)
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
Table 40: IO14 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO14 Driver
Strength Selection
[1137]
0: 1x
1: 2x
IO14 Pull-up/down
Resistor Selection
[1138]
0: Pull-down Resistor
1: Pull-up Resistor
IO14 Pull-up/down
Resistor Value
Selection
[1140:1139]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
Datasheet
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 40: IO14 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
IO14 Mode Control
[1143:1141]
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Reserved
Table 41: IO15 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO15 Pull-up/down
Resistor Selection
[1145]
0: Pull-down Resistor
1: Pull-up Resistor
IO15 Pull-up/down
Resistor Value
Selection
[1147:1146]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO15 Mode Control
(sig_io15_oe = 0)
[1149:1148]
[1151:1150]
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
IO15 Mode Control
(sig_io15_oe = 1)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
5.5 GPI STRUCTURE
5.5.1 GPI Structure (for IO0)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1, OE=0
01: Digital In with Schmitt Trigger, smt_en = 1, OE = 0
10: Low Voltage Digital In mode, lv_en = 1, OE = 0
11: Reserved
WOSMT_EN
SMT_EN
OE
OE
Schmitt
Trigger Input
Digital IN
Note 1: OE cannot be selected by user
Note 2: OE is Matrix output, Digital In is Matrix input
Low Voltage
Input
LV_EN
OE
Floating
PAD
s0
s1
s2
s3
900 kΩ
90 kΩ
10 kΩ
Res_sel [1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Figure 3: IO0 GPI Structure Diagram
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
5.6 MATRIX OE IO STRUCTURE
5.6.1 Matrix OE IO Structure (for IOs 1, 3, 5, 10, 11, 13, 15)
Non-Schmitt
Trigger Input
Input Mode [1:0]
WOSMT_EN
SMT_EN
00: Digital In without Schmitt Trigger, wosmt_en=1
01: Digital In with Schmitt Trigger, smt_en=1
10: Low Voltage Digital In mode, lv_en = 1
11: Analog IO mode
OE
OE
Schmitt
Trigger Input
Output Mode [1:0]
Digital IN
00: 1x push-pull mode, pp1x_en=1
01: 2x push-pull mode, pp2x_en=1, pp1x_en=1
10: 1x NMOS open drain mode, od1x_en=1
11: 2x NMOS open drain mode, od2x_en=1, od1x_en=1
Low Voltage
Input
Note 1: Digital Out and OE are Matrix output, Digital In is Matrix input
Note 2: Can be varied over PVT, for reference only
LV_EN
OE
Analog IO
(For IOs 5, 10, 11, 15 only)
Floating
s0
s1
s2
s3
VDD
172 Ω
(Note 2)
s1
s0
900 kΩ
Res_sel
90 kΩ
10 kΩ
VDD
[1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
Digital OUT
OE
Digital OUT
OE
OD1x_EN
PP1x_EN
VDD
PAD
VDD
Digital OUT
OE
Digital OUT
OE
PP2x_EN
OD2x_EN
Figure 4: Matrix OE IO Structure Diagram
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
5.6.2 Matrix OE IO Structure (for IOs 6 and 7)
Non-Schmitt
Trigger Input
IO6, IO7 Mode [2:0]
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Reserved
101: Open Drain NMOS
110: Reserved
111: Reserved
WOSMT_EN
SMT_EN
OE
OE
Schmitt
Trigger Input
Digital IN
Note: Digital Out and OE are Matrix output, Digital In is Matrix input
Low Voltage
Input
LV_EN
OE
Digital OUT
OE
OD1x_EN
Floating
PAD
s0
s1
s2
s3
900 kΩ
90 kΩ
10 kΩ
Res_sel [1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Figure 5: Matrix OE IO Structure Diagram
Datasheet
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
5.6.3 Matrix OE 4x Drive Structure (for IO8)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en=1
01: Digital In with Schmitt Trigger, smt_en=1
10: Low Voltage Digital In mode, lv_en = 1
11: analog IO mode
Output Mode [1:0]
00: 1x push-pull mode, pp1x_en=1
01: 2x push-pull mode, pp2x_en=1, pp1x_en=1
10: 1x NMOS open drain mode, od1x_en=1, odn_en=1
11: 2x NMOS open drain mode, od2x_en=1, od1x_en=1, odn_en=1
WOSMT_EN
SMT_EN
OE
OE
Schmitt
Trigger Input
Digital IN
Low Voltage
Input
Note 1: Digital Out and OE are Matrix output, Digital In is Matrix input
Note 2: Can be varied over PVT, for reference only
LV_EN
OE
Analog IO
Floating
s0
s1
s2
s3
VDD
172 Ω
(Note 2)
s1
s0
900 kΩ
Res_sel
90 kΩ
10 kΩ
VDD
[1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
Digital OUT
OE
Digital OUT
OE
OD1x_EN
4x_EN
PP1x_EN
ODn_EN
VDD
Digital OUT
OE
OD2x_EN
4x_EN
PAD
VDD
ODn_EN
2x
2x
Digital OUT
OE
Digital OUT
OE
4x_EN
ODn_EN
PP2x_EN
Digital OUT
OE
4x_EN
ODn_EN
Figure 6: Matrix OE IO 4X Drive Structure Diagram
Datasheet
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
5.7 IO STRUCTURE
5.7.1 IO Structure (for IOs 2, 4, 12, 14)
Non-Schmitt
Trigger Input
Mode [2:0]
000: Digital In without Schmitt Trigger, wosmt_en=1, OE = 0
001: Digital In with Schmitt Trigger, smt_en=1, OE = 0
010: Low Voltage Digital In mode, lv_en = 1, OE = 0
011: analog IO mode
WOSMT_EN
SMT_EN
OE
OE
Schmitt
Trigger Input
100: push-pull mode, pp_en=1, OE = 1
101: NMOS open drain mode, odn_en=1, OE = 1
110: PMOS open drain mode, odp_en=1, OE = 1
111: analog IO and NMOS open-drain mode, odn_en=1 and AIO_en=1
Digital IN
Note 1: OE cannot be selected by user and is controlled by register
Note 2: Can be varied over PVT, for reference only
Low Voltage
Input
LV_EN
OE
Analog IO
(For IOs 4, 12 only)
Floating
s0
s1
s2
s3
s1
s0
172 Ω
(Note 2)
900 kΩ
Res_sel
90 kΩ
10 kΩ
[1:0]
VDD
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
ODp_EN
Digital OUT
OE
Digital OUT
OE
ODn_EN
2x_EN
PP_EN
VDD
PAD
VDD
ODp_EN
Digital OUT
OE
Digital OUT
OE
2x_EN
2x_EN
PP_EN
ODn_EN
Figure 7: IO Structure Diagram
Datasheet
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
5.7.2 4x Drive Structure (for IO9)
Non-Schmitt
Trigger Input
Mode [2:0]
000: Digital In without Schmitt Trigger, wosmt_en=1, OE = 0
001: Digital In with Schmitt Trigger, smt_en=1, OE = 0
010: Low Voltage Digital In mode, lv_en = 1, OE = 0
011: analog IO mode
WOSMT_EN
SMT_EN
OE
OE
Schmitt
Trigger Input
100: push-pull mode, pp_en=1, OE = 1
Digital IN
101: NMOS open drain mode, odn_en=1, OE = 1
110: PMOS open drain mode, odp_en=1, OE = 1
111: analog IO and NMOS open-drain mode, odn_en=1 and AIO_en=1
Low Voltage
Input
Note 1: OE cannot be selected by user
Note 2: Digital Out and OE are Matrix output, Digital In is Matrix input
Note 3: Can be varied over PVT, for reference only
LV_EN
OE
Analog IO
Floating
s0
s1
s2
s3
VDD
172 Ω
(Note 3)
s1
s0
900 kΩ
Res_sel
90 kΩ
10 kΩ
[1:0]
Pull-up_EN
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
VDD
Digital OUT
OE
Digital OUT
OE
OD1x_EN
4x_EN
PP1x_EN
ODn_EN
Digital OUT
OE
VDD
OD2x_EN
4x_EN
ODn_EN
PAD
VDD
Digital OUT
OE
Digital OUT
OE
4x_EN
PP2x_EN
ODn_EN
Digital OUT
OE
4x_EN
ODn_EN
Figure 8: IO 4X Drive Structure Diagram
Datasheet
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
6
Connection Matrix
The Connection Matrix in the SLG46517 is used to create the internal routing for internal functional macrocells of the device once
it is programmed. The registers are programmed from the one-time NVM cell during Test Mode Operation. The output of each
functional macrocell within the SLG46517 has a specific digital bit code assigned to it that is either set to active “High” or inactive
“Low”, based on the design that is created. Once the 2048 register bits within the SLG46517 are programmed a fully custom
circuit will be created.
The Connection Matrix has 64 inputs and 110 outputs. Each of the 64 inputs to the Connection Matrix is hard-wired to the digital
output of a particular source macrocell, including IO pins, LUTs, analog comparators, other digital resources, such as VDD and
GND. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines.
For a complete list of the SLG46517’s register table, see Section 20.
Matrix Input Signal
N
Functions
Ground
0
1
2
3
IO0 Digital In
IO1 Digital In
IO2 Digital In
Resetb_core
VDD
62
63
Matrix Inputs
0
1
2
109
N
Registers
[5:0]
[13:8]
[21:16]
[877:872]
Matrix OUT: PD of
either Temp out or
XTAL Osc
Matrix OUT:
ASM-state0-EN0
Matrix OUT:
ASM-state0-EN1
Matrix OUT:
ASM-state0-EN2
Function
Matrix Outputs
Figure 9: Connection Matrix
Function
Connection Matrix
IO10
IO9
LUT
IO9
IO11
IO10
LUT
IO11
Figure 10: Connection Matrix Example
Datasheet
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CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
6.1 MATRIX INPUT TABLE
Table 42: Matrix Input Table
Matrix Decode
Matrix Input
Matrix Input Signal Function
Number
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GND
IO0 Digital Input
2
IO1 Digital Input
3
IO2 Digital Input
4
IO3 Digital Input
5
IO4 Digital Input
6
IO5 Digital Input
7
IO8 Digital Input
8
LUT2_0/DFF0 Output
LUT2_1/DFF1 Output
LUT2_2/DFF2 Output
LUT2_3/PGen Output
LUT3_0/DFF3 Output
LUT3_1/DFF4 Output
LUT3_2/DFF5 Output
LUT3_3/DFF6 Output
LUT3_4/DFF7 Output
LUT3_5/CNT_DLY2(8bit) Output
LUT3_6/CNT_DLY3(8bit) Output
LUT3_7/CNT_DLY4(8bit) Output
LUT3_8/CNT_DLY5(8bit) Output
LUT3_9/CNT_DLY6(8bit) Output
LUT4_0/CNT_DLY0(16bit) Output
LUT4_1/CNT_DLY1(16bit) Output
LUT3_10/Pipe Delay (1st stage) Output
Pipe Delay Output0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Pipe Delay Output1
Internal OSC Pre-Divided by 1/2/4/8 Output and Post-Divided by 1/
2/3/4/8/12/24/64 Output (25kHz/2MHz)
27
28
Internal OSC Pre-Divided by 1/2/4/8 Output and Post-Divided by 1/
2/3/4/8/12/24/64 Output (25kHz/2MHz)
0
1
1
1
0
0
29
30
31
32
33
34
35
36
Internal OSC Pre-Divided by 1/2/4/8 Output (25MHz)
Filter0/Edge Detect0 Output
Filter1/Edge Detect1 Output
IO6 Digital or I2C_virtual_0 Input
IO7 Digital or I2C_virtual_1 Input
I2C_virtual_2 Input
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
I2C_virtual_3 Input
I2C_virtual_4 Input
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 42: Matrix Input Table(Continued)
Matrix Decode
Matrix Input
Matrix Input Signal Function
Number
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
I2C_virtual_5 Input
I2C_virtual_6 Input
I2C_virtual_7 Input
ASM-stateX-dout0
ASM-stateX-dout1
ASM-stateX-dout2
ASM-stateX-dout3
ASM-stateX-dout4
ASM-stateX-dout5
ASM-stateX-dout6
ASM-stateX-dout7
IO9 Digital Input
IO10 Digital Input
IO11 Digital Input
IO12 Digital Input
IO13 Digital Input
IO14 Digital Input
IO15 Digital Input
Power Switch ON0, Digital Input
Power Switch ON1, Digital Input
ACMP_0 Output
ACMP_1 Output
ACMP_2 Output
ACMP_3 Output
Programmable Delay with Edge Detector Output
nRST_core (POR) as matrix input
VDD
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
6.2 MATRIX OUTPUT TABLE
Table 43: Matrix Output Table
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
7:0
Matrix OUT: ASM-state0-EN0
0
15:8
Matrix OUT: ASM-state0-EN1
1
23:16
Matrix OUT: ASM-state0-EN2
2
31:24
Matrix OUT: ASM-state1-EN0
3
39:32
Matrix OUT: ASM-state1-EN1
4
47:40
Matrix OUT: ASM-state1-EN2
5
55:48
Matrix OUT: ASM-state2-EN0
6
63:56
Matrix OUT: ASM-state2-EN1
7
71:64
Matrix OUT: ASM-state2-EN2
8
79:72
Matrix OUT: ASM-state3-EN0
9
87:80
Matrix OUT: ASM-state3-EN1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
95:88
Matrix OUT: ASM-state3-EN2
103:96
111:104
119:112
127:120
135:128
143:136
151:144
159:152
167:160
175:168
183:176
191:184
199:192
207:200
215:208
223:216
231:224
239:232
247:240
255:248
263:256
271:264
279:272
287:280
295:288
303:296
Matrix OUT: ASM-state4-EN0
Matrix OUT: ASM-state4-EN1
Matrix OUT: ASM-state4-EN2
Matrix OUT: ASM-state5-EN0
Matrix OUT: ASM-state5-EN1
Matrix OUT: ASM-state5-EN2
Matrix OUT: ASM-state6-EN0
Matrix OUT: ASM-state6-EN1
Matrix OUT: ASM-state6-EN2
Matrix OUT: ASM-state7-EN0
Matrix OUT: ASM-state7-EN1
Matrix OUT: ASM-state7-EN2
Matrix OUT: ASM-state-nRST
Matrix OUT: IO1 Digital Output Source
Matrix OUT: IO1 Output Enable
Matrix OUT: IO2 Digital Output Source
Matrix OUT: IO3 Digital Output Source
Matrix OUT: IO3 Output Enable
Matrix OUT: IO4 Digital Output Source
Matrix OUT: IO5 Digital Output Source
Matrix OUT: IO5 Output Enable
Matrix OUT: IO6 Digital Output Source (SCL with VI/Input & NMOS Open-Drain)
Matrix OUT: IO7 Digital Output Source (SDA with VI/Input & NMOS Open-Drain)
Matrix OUT: IO8 Digital Output Source
Matrix OUT: IO8 Output Enable
Matrix OUT: IO9 Digital Output Source
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 43: Matrix Output Table(Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
311:304
319:312
327:320
335:328
343:336
351:344
359:352
367:360
375:368
383:376
391:384
399:392
407:400
415:408
423:416
431:424
439:432
447:440
455:448
463:456
471:464
479:472
487:480
495:488
503:496
511:504
519:512
527:520
535:528
543:536
551:544
559:552
567:560
575:568
583:576
591:584
599:592
607:600
615:608
Matrix OUT: IO10 Digital Output Source
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
Matrix OUT: IO10 Output Enable
Matrix OUT: IO11 Digital Output Source
Matrix OUT: IO11 Output Enable
Matrix OUT: IO12 Digital Output Source
Matrix OUT: IO13 Digital Output Source
Matrix OUT: IO13 Output Enable
Matrix OUT: IO14 Digital Output Source
Matrix OUT: IO15 Digital Output Source
Matrix OUT: IO15 Output Enable
Matrix OUT: Power Switch ON0, Digital Output Source
Matrix OUT: Reserved
Matrix OUT: Power Switch ON1, Digital Output Source
Matrix OUT: ACMP0 PWR UP
Matrix OUT: ACMP1 PWR UP
Matrix OUT: ACMP2 PWR UP
Matrix OUT: ACMP3 PWR UP
Matrix OUT: Input of Filter_0 with fixed time edge detector
Matrix OUT: Input of Filter_1 with fixed time edge detector
Matrix OUT: Input of Programmable Delay & Edge Detector
Matrix OUT: OSC 25kHz/2MHz PDB (Power-Down)
Matrix OUT: OSC 25MHz PDB (Power-Down)
Matrix OUT: IN0 of LUT2_0 or Clock Input of DFF0
Matrix OUT: IN1 of LUT2_0 or Data Input of DFF0
Matrix OUT: IN0 of LUT2_1 or Clock Input of DFF1
Matrix OUT: IN1 of LUT2_1 or Data Input of DFF1
Matrix OUT: IN0 of LUT2_2 or Clock Input of DFF2
Matrix OUT: IN1 of LUT2_2 or Data Input of DFF2
Matrix OUT: IN0 of LUT2_3 or Clock Input of PGen
Matrix OUT: IN1 of LUT2_3 or nRST of PGen
Matrix OUT: IN0 of LUT3_0 or Clock Input of DFF3
Matrix OUT: IN1 of LUT3_0 or Data Input of DFF3
Matrix OUT: IN2 of LUT3_0 or nRST (nSET) of DFF3
Matrix OUT: IN0 of LUT3_1 or Clock Input of DFF4
Matrix OUT: IN1 of LUT3_1 or Data Input of DFF4
Matrix OUT: IN2 of LUT3_1 or nRST (nSET) of DFF4
Matrix OUT: IN0 of LUT3_2 or Clock Input of DFF5
Matrix OUT: IN1 of LUT3_2 or Data Input of DFF5
Matrix OUT: IN2 of LUT3_2 or nRST (nSET) of DFF5
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 43: Matrix Output Table(Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
623:616
631:624
639:632
647:640
655:648
663:656
671:664
679:672
687:680
695:688
703:696
711:704
719:712
727:720
735:728
743:736
751:744
759:752
767:760
775:768
783:776
791:784
799:792
807:800
815:808
823:816
831:824
839:832
847:840
855:848
863:856
871:864
Matrix OUT: IN0 of LUT3_3 or Clock Input of DFF6
77
78
Matrix OUT: IN1 of LUT3_3 or Data Input of DFF6
Matrix OUT: IN2 of LUT3_3 or nRST (nSET) of DFF6
Matrix OUT: IN0 of LUT3_4 or Clock Input of DFF7
79
80
Matrix OUT: IN1 of LUT3_4 or Data Input of DFF7
81
Matrix OUT: IN2 of LUT3_4 or nRST (nSET) of DFF7
Matrix OUT: IN0 of LUT3_5 or Delay2 Input (or Counter2 RST Input)
Matrix OUT: IN1 of LUT3_5 or External Clock Input of Delay2 (or Counter2)
Matrix OUT: IN2 of LUT3_5
82
83
84
85
Matrix OUT: IN0 of LUT3_6 or Delay3 Input (or Counter3 RST Input)
Matrix OUT: IN1 of LUT3_6 or External Clock Input of Delay3 (or Counter3)
Matrix OUT: IN2 of LUT3_6
86
87
88
Matrix OUT: IN0 of LUT3_7 or Delay4 Input (or Counter4 RST Input)
Matrix OUT: IN1 of LUT3_7 or External Clock Input of Delay4 (or Counter4)
Matrix OUT: IN2 of LUT3_7
89
90
91
Matrix OUT: IN0 of LUT3_8 or Delay5 Input (or Counter5 RST Input)
Matrix OUT: IN1 of LUT3_8 or External Clock Input of Delay5 (or Counter5)
Matrix OUT: IN2 of LUT3_8
92
93
94
Matrix OUT: IN0 of LUT3_9 or Delay6 Input (or Counter6 RST Input)
Matrix OUT: IN1 of LUT3_9 or External Clock Input of Delay6 (or Counter6)
Matrix OUT: IN2 of LUT3_9
95
96
97
Matrix OUT: IN0 of LUT3_10 or Input of Pipe Delay
98
Matrix OUT: IN1 of LUT3_10 or nRST of Pipe Delay
Matrix OUT: IN2 of LUT3_10 or Clock of Pipe Delay
Matrix OUT: IN0 of LUT4_0 or Delay0 Input (or Counter0 RST/SET Input)
Matrix OUT: IN1 of LUT4_0 or External Clock Input of Delay0 (or Counter0)
Matrix OUT: IN2 of LUT4_0 or UP Input of FSM0
99
100
101
102
103
104
105
106
107
108
Matrix OUT: IN3 of LUT4_0 or KEEP Input of FSM0
Matrix OUT: IN0 of LUT4_1 or Delay1 Input (or Counter1 RST/SET Input)
Matrix OUT: IN1 of LUT4_1 or External Clock Input of Delay1 (or Counter1)
Matrix OUT: IN2 of LUT4_1 or UP Input of FSM1
Matrix OUT: IN3 of LUT4_1 or KEEP Input of FSM1
Matrix OUT: crystal oscillator by
register [1268]
879:872
109
Note 1 For each Address, the two most significant bits are unused.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
6.3 CONNECTION MATRIX VIRTUAL INPUTS
As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macrocells on the device. Eight
of the Connection Matrix inputs have the special characteristic that the state of these signal lines comes from a corresponding
data bit written as a register value via I2C. This gives the user the ability to write data via the serial channel, and have this
information translated into signals that can be driven into the Connection Matrix and from the Connection Matrix to the digital
inputs of other macrocells on the device. The I2C address for reading and writing these register values is at byte 0244.
Six of the eight Connection Matrix Virtual Inputs are dedicated to this virtual input function. An I2C write command to these register
bits will set the signal values going into the Connection Matrix to the desired state. A read command to these register bits will read
either the original data values coming from the NVM memory bits (that were loaded during the initial device startup), or the values
from a previous write command (if that has happened).
Two of the eight Connection Matrix Virtual Inputs are shared with Pin digital inputs,(IO6 Digital or I2C_virtual_0 Input) and (IO7
Digital or I2C_virtual_1 Input). If the virtual input mode is selected, an I2C write command to these register bits will set the signal
values going into the Connection Matrix to the desired state. Two register bits select whether the Connection Matrix input comes
from the pin input or from the virtual register:
register [1074] Select SCL & Virtual Input 0 or IO6
register [1082] Select SDA & Virtual Input 1 or IO7
See Table 44 for Connection Matrix Virtual Inputs.
Table 44: Connection Matrix Virtual Inputs
Matrix Input
Register Bit
Addresses (d)
Matrix Input Signal Function
Number
32
I2C_virtual_0 Input
I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
I2C_virtual_5 Input
I2C_virtual_6 Input
I2C_virtual_7 Input
[1952]
[1953]
[1954]
[1955]
[1956]
[1957]
[1958]
[1959]
33
34
35
36
37
38
39
6.4 CONNECTION MATRIX VIRTUAL OUTPUTS
The digital outputs of the various macrocells are routed to the Connection Matrix to enable interconnections to the inputs of other
macrocells in the device. At the same time, it is possible to read the state of each of the macrocell outputs as a register value via
I2C. This option, called Connection Matrix Virtual Outputs, allows the user to remotely read the values of each macrocell output.
The I2C addresses for reading these register values are at bytes 0240 to 0247. Write commands to these same register values
will be ignored (with the exception of the Virtual Input register bits at byte 0244).
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7
Combination Function Macrocells
The SLG46517 has seventeen combination function macrocells that can serve more than one logic or timing function. In each
case, they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that
can be implemented in these macrocells.
Three macrocells that can serve as either 2-bit LUTs or as D Flip-Flops
Five macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input
One macrocell that can serve as either 3-bit LUT or as Pipe Delay
One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGen)
Five macrocells that can serve as either 3-bit LUTs or as 8-Bit Counter/Delays
Two macrocells that can serve as either 4-bit LUTs or as 16-Bit Counter/Delays
Inputs/Outputs for the 17 combination function macrocells are configured from the connection matrix with specific logic functions
being defined by the state of NVM bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined
function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
7.1 2-BIT LUT OR D FLIP-FLOP MACROCELLS
There are three macrocells that can serve as either 2-bit LUTs or as D Flip-Flops. When used to implement LUT functions, the
2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the
connection matrix. When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data
(D) and clock (CLK) inputs for the Flip-Flop, with the output going back to the connection matrix.
The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:
DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change
LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK
is High).
register [1207] DFF or Latch Select
IN1
register [1206] Output Select (Q or nQ)
S0
From Connection Matrix Output [61]
register [1205] DFF Initial Polarity Select
OUT
2-bit LUT0
0: 2-bit LUT0 IN1
1: DFF0 Data
S1
IN0
LUT Truth
Table
To Connection Matrix
Input [8]
S0
S1
4-bits NVM
registers [1207:1204]
0: 2-bit LUT0 OUT
1: DFF0 OUT
DFF
Registers
D
S0
S1
From Connection Matrix Output [60]
Q/nQ
DFF0
0: 2-bit LUT0 IN0
1: DFF0 CLK
CLK
1-bit NVM
register [1191]
Figure 11: 2-bit LUT0 or DFF0
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
register [1203] DFF or Latch Select
register [1202] Output Select (Q or nQ)
register [1201] DFF Initial Polarity Select
IN1
S0
From Connection Matrix Output [63]
OUT
2-bit LUT1
0: 2-bit LUT1 IN1
1: DFF1 Data
S1
IN0
LUT Truth
Table
To Connection Matrix
S0
Input [9]
4-bits NVM
registers [1203:1200]
0: 2-bit LUT1 OUT
1: DFF1 OUT
S1
DFF
Registers
D
S0
S1
From Connection Matrix Output [62]
Q/nQ
DFF1
0: 2-bit LUT1 IN0
1: DFF1 CLK
CLK
1-bit NVM
register [1190]
Figure 12: 2-bit LUT1 or DFF1
register [1215] DFF or Latch Select
register [1214] Output Select (Q or nQ)
register [1213] DFF Initial Polarity Select
IN1
S0
S1
From Connection Matrix Output [65]
OUT
2-bit LUT2
0: 2-bit LUT2 IN1
1: DFF2 Data
IN0
LUT Truth
Table
To Connection Matrix
S0
Input [10]
4-bits NVM
registers [1215:1212]
0: 2-bit LUT2 OUT
1: DFF2 OUT
S1
DFF
Registers
D
S0
S1
From Connection Matrix Output [64]
Q/nQ
DFF2
0: 2-bit LUT2 IN0
1: DFF2 CLK
CLK
1-bit NVM
register [1189]
Figure 13: 2-bit LUT2 or DFF2
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUTs
Table 45: 2-bit LUT0 Truth Table
Table 47: 2-bit LUT2 Truth Table
IN1
0
IN0
0
OUT
IN1
0
IN0
0
OUT
register [1204]
register [1205]
register [1206]
register [1207]
LSB
register [1212]
register [1213]
register [1214]
register [1215]
LSB
0
1
0
1
1
0
1
0
1
1
MSB
1
1
MSB
Table 46: 2-bit LUT1 Truth Table
IN1
0
IN0
0
OUT
register [1200]
register [1201]
register [1202]
register [1203]
LSB
0
1
1
0
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-Bit LUT0 is defined by registers [1207:1204]
2-Bit LUT1 is defined by registers [1203:1200]
2-Bit LUT2 is defined by registers [1215:1212]
Table 48 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the 2-bit LUT logic cells.
Table 48: 2-bit LUT Standard Digital Functions
Function
AND-2
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-2
OR-2
NOR-2
XOR-2
XNOR-2
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7.1.2 2-Bit LUT or D Flip-Flop Macrocells Used as D Flip-Flop Register Settings
Table 49: DFF0 Register Settings
Register Bit
Address
Signal Function
Register Definition
LUT2_0 or DFF0
Select
[1191]
0: LUT2_0
1: DFF0
DFF0 Initial Polarity
Select
[1205]
[1206]
[1207]
0: Low
1: High
DFF0 Output Select
0: Q output
1: nQ output
DFF0 or LATCH
Select
0: DFF function
1: LATCH function
Table 50: DFF1 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT2_1 or DFF1
Select
[1190]
0: LUT2_1
1: DFF1
DFF1 Initial Polarity
Select
[1201]
[1202]
[1203]
0: Low
1: High
DFF1 Output Select
0: Q output
1: nQ output
Select or LATCH
select
0: DFF function
1: LATCH function
Table 51: DFF2 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT2_2 or DFF2
Select
[1189]
0: LUT2_2
1: DFF2
DFF2 Initial Polarity
Select
[1213]
[1214]
[1215]
0: Low
1: High
DFF2 Output Select
0: Q output
1: nQ output
DFF2 or LATCH
Select
0: DFF function
1: LATCH function
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7.1.3 Initial Polarity Operations
VDD
Data
Clock
POR
Initial Polarity: High
Q
Initial Polarity: Low
Q
Figure 14: DFF Polarity Operations
7.2 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELLS
There are five macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset inputs. When used to implement
LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce a single output, which goes
back into the connection matrix. When used to implement D Flip-Flop function, the three input signals from the connection matrix
go to the data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output going back to the
connection matrix.
DFF3 has a user selectable option to allow the macrocell output to either come from the Q/nQ output of one D Flip-Flop, or two
D Flip-Flops in series, with the first D Flip-Flop triggering on the rising clock edge, and the second D Flip-Flop triggering on the
falling clock edge.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
register [1223] DFF or Latch Select
register [1222] Output Select (Q or nQ)
register [1221] DFF nRST or nSET Select
register [1220] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [70]
S0
IN1
OUT
3-bit LUT0
0: 3-bit LUT0 IN2
1: DFF3 nRST/nSET
S1
IN0
LUT Truth
Table
From Connection
Matrix Output [69]
To Connection Matrix
S0
S1
Input [12]
S0
8-bits NVM
0: 3-bit LUT0 IN1
1: DFF3 D
registers [1223:1216]
register [1471]
0: 3-bit LUT0 OUT
1: DFF3 OUT
S1
DFF3
nRST/nSET
From Connection
S0
S1
D
Q/nQ
Matrix Output [68]
Q
D
D
Q
0: 3-bit LUT0 IN0
1: DFF3 CLK
CLK
register [1222]
register [1471] Selects output from one or two
1-bit NVM
register [1187]
Figure 15: 3-bit LUT0 or DFF3 with RST/SET
register [1231] DFF or Latch Select
IN2
From Connection
Matrix Output [73]
S0
S1
register [1230] Output Select (Q or nQ)
register [1229] DFF nRST or nSET Select
register [1228] DFF Initial Polarity Select
IN1
IN0
OUT
3-bit LUT1
0: 3-bit LUT1 IN2
1: DFF4 nRST/nSET
LUT Truth
Table
From Connection
To Connection Matrix
Matrix Output [72]
S0
S1
Input [13]
S0
8-bits NVM
registers [1231:1224]
0: 3-bit LUT1 IN1
1: DFF4 D
0: 3-bit LUT1 OUT
S1
1: DFF4 OUT
DFF
Registers
D
From Connection
Matrix Output [71]
S0
S1
nRST/nSET
CLK
DFF4
Q/nQ
0: 3-bit LUT1 IN0
1: DFF4 CLK
1-bit NVM
register [1186]
Figure 16: 3-bit LUT1 or DFF4 with RST/SET
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
register [1239] DFF or Latch Select
IN2
From Connection
S0
register [1238] Output Select (Q or nQ)
register [1237] DFF nRST or nSET Select
register [1236] DFF Initial Polarity Select
Matrix Output [76]
IN1
OUT
3-bit LUT2
0: 3-bit LUT2 IN2
1: DFF5 nRST/nSET
S1
IN0
LUT Truth
Table
From Connection
To Connection Matrix
S0
S1
Matrix Output [75]
S0
S1
Input [14]
8-bits NVM
registers [1239:1232]
0: 3-bit LUT2 IN1
1: DFF5 D
0: 3-bit LUT2 OUT
1: DFF5 OUT
DFF
Registers
D
From Connection
Matrix Output [74]
S0
S1
nRST/nSET
CLK
DFF5
Q/nQ
0: 3-bit LUT2 IN0
1: DFF5 CLK
1-bit NVM
register [1185]
Figure 17: 3-bit LUT2 or DFF5 with RST/SET
register [1247] DFF or Latch Select
IN2
From Connection
Matrix Output [79]
S0
S1
register [1246] Output Select (Q or nQ)
register [1245] DFF nRST or nSET Select
register [1244] DFF Initial Polarity Select
IN1
IN0
OUT
3-bit LUT3
0: 3-bit LUT3 IN2
1: DFF6 nRST/nSET
LUT Truth
Table
From Connection
To Connection Matrix
Matrix Output [78]
S0
S1
Input [15]
S0
8-bits NVM
registers [1247:1240]
0: 3-bit LUT3 IN1
1: DFF6 D
0: 3-bit LUT3 OUT
S1
1: DFF6 OUT
DFF
Registers
D
From Connection
Matrix Output [77]
S0
S1
nRST/nSET
CLK
DFF6
Q/nQ
0: 3-bit LUT3 IN0
1: DFF6 CLK
1-bit NVM
register [1184]
Figure 18: 3-bit LUT3 or DFF6 with RST/SET
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
register [1255] DFF or Latch Select
IN2
From Connection
S0
register [1254] Output Select (Q or nQ)
register [1253] DFF nRST or nSET Select
register [1252] DFF Initial Polarity Select
Matrix Output [82]
IN1
OUT
3-bit LUT4
0: 3-bit LUT4 IN2
1: DFF7 nRST/nSET
S1
IN0
LUT Truth
Table
From Connection
To Connection Matrix
S0
S1
Matrix Output [81]
S0
S1
Input [16]
8-bits NVM
registers [1255:1248]
0: 3-bit LUT4 IN1
1: DFF7 D
0: 3-bit LUT4 OUT
1: DFF7 OUT
DFF
Registers
D
From Connection
Matrix Output [80]
S0
S1
nRST/nSET
CLK
DFF7
Q/nQ
0: 3-bit LUT4 IN0
1: DFF7 CLK
1-bit NVM
register [1199]
Figure 19: 3-bit LUT4 or DFF7 with RST/SET
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7.2.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs
Table 52: 3-bit LUT0 Truth Table
Table 55: 3-bit LUT3 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1216]
register [1217]
register [1218]
register [1219]
register [1220]
register [1221]
register [1222]
register [1223]
LSB
register [1240]
register [1241]
register [1242]
register [1243]
register [1244]
register [1245]
register [1246]
register [1247]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 53: 3-bit LUT1 Truth Table
Table 56: 3-bit LUT4 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1224]
register [1225]
register [1226]
register [1227]
register [1228]
register [1229]
register [1230]
register [1231]
register [1248]
register [1249]
register [1250]
register [1251]
register [1252]
register [1253]
register [1254]
register [1255]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
Table 54: 3-bit LUT2 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [1232]
register [1233]
register [1234]
register [1235]
register [1236]
register [1237]
register [1238]
register [1239]
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT0 is defined by registers [1223:1216]
3-Bit LUT1 is defined by registers [1231:1224]
3-Bit LUT2 is defined by registers [1239:1232]
3-Bit LUT3 is defined by registers [1247:1240]
3-Bit LUT5 is defined by registers [1255:1248]
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GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 57 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the six 3-bit LUT logic cells.
Table 57: 3-bit LUT Standard Digital Functions
Function
AND-3
MSB
LSB
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-3
OR-3
NOR-3
XOR-3
XNOR-3
7.2.2 3-Bit LUT or D Flip-Flop Macrocells Used as D Flip-Flop Register Settings
Table 58: DFF3 Register Settings
Register Bit
Address
Signal Function
Register Definition
LUT3_0 or DFF3
Select
[1187]
0: LUT3_0
1: DFF3
DFF3 Initial Polarity
Select
[1220]
[1221]
[1222]
[1223]
0: Low
1: High
DFF3 nRST/nSET
Select
1: nSET from matrix out
0: nRST from matrix out
DFF3 Output Select
0: Q output
1: nQ output
DFF3 or LATCH
Select
0: DFF function
1: LATCH function
Table 59: DFF4 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_1 or DFF4
Select
[1186]
0: LUT3_1
1: DFF4
DFF4 Initial Polarity
Select
[1128]
[1129]
[1130]
[1131]
0: Low
1: High
DFF4 nRST/nSET
Select
1: nSET from matrix out
0: nRST from matrix out
DFF4 Output Select
0: Q output
1: nQ output
DFF4 or LATCH
Select
0: DFF function
1: LATCH function
Table 60: DFF5 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_2 or DFF5
Select
[1185]
0: LUT3_2
1: DFF5
DFF5 Initial Polarity
Select
[1236]
0: Low
1: High
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GreenPAK Programmable Mixed-Signal Matrix
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Table 60: DFF5 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
DFF5 nRST/nSET
Select
[1237]
1: nSET from matrix out
0: nRST from matrix out
DFF5 Output Select
[1238]
[1239]
0: Q output
1: nQ output
DFF5 or LATCH
Select
0: DFF function
1: LATCH function
Table 61: DFF6 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_3 or DFF6
Select
[1184]
0: LUT3_3
1: DFF6
DFF6 Initial Polarity
Select
[1244]
[1245]
[1246]
[1247]
0: Low
1: High
DFF6 nRST/nSET
Select
1: nSET from matrix out
0: nRST from matrix out
DFF6 Output Select
0: Q output
1: nQ output
DFF6 or LATCH
Select
0: DFF function
1: LATCH function
Table 62: DFF7 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_4 or DFF7
Select
[1199]
0: LUT3_4
1: DFF7
DFF7 Initial Polarity
Select
[1252]
[1253]
[1254]
[1255]
0: Low
1: High
DFF7 nRST/nSET
Select
1: nSET from matrix out
0: nRST from matrix out
DFF7 Output Select
0: Q output
1: nQ output
DFF7 or LATCH
Select
0: DFF function
1: LATCH function
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GreenPAK Programmable Mixed-Signal Matrix
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7.2.3 Initial Polarity Operations
VDD
Data
Clock
POR
Initial Polarity: High
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Initial Polarity: Low
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Figure 20: DFF Polarity Operations with nReset
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VDD
Data
Clock
POR
Initial Polarity: High
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Initial Polarity: Low
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Figure 21: DFF Polarity Operations with nSet
7.3 3-BIT LUT OR PIPE DELAY MACROCELL
There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay.
When used to implement LUT functions, the 3-bit LUT take in three input signals from the connection matrix and produces a single
output, which goes back into the connection matrix.
When used as a Pipe Delay, there are three inputs signals from the matrix: Input (IN), Clock (CLK), and Reset (nRST). The Pipe
Delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF
cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell. The first delay option (OUT2) is fixed at
the output of the first Flip-Flop stage. The other two outputs (OUT0 and OUT1) provide user selectable options for 1 to 16 stages
of delay. There are delay output points for each set of the OUT0 and OUT1 outputs to a 16-input mux that is controlled by registers
[1259:1256] for OUT0 and registers [1263:1260] for OUT1. The 16-input mux is used to select the amount of delay.
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GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
The overall time of the delay is based on the clock used in the SLG46517 design. Each DFF cell has a time delay of the inverse
of the clock time (either external clock or the RC Oscillator within the SLG46517). The sum of the number of DFF cells used will
be the total time delay of the Pipe Delay logic cell.
Note: CLK is rising edge triggered.
registers [1263:1256]
LUT Truth
Table
From Connection
Matrix Output [98]
IN0
IN1
From Connection
Matrix Output [99]
OUT
3-bit LUT10
From Connection
Matrix Output [100]
IN2
registers [1263:1260]
register [1271]
S0
S1
OUT1
To Connection
Matrix Input[26]
From Connection
Matrix Output [98]
IN
nRST
From Connection
Matrix Output [99]
16 Flip-Flops
CLK
From Connection
Matrix Output [100]
OUT0
To Connection
Matrix Input [25]
S0
S1
1 Pipe OUT
registers [1259:1256]
To Connection
Matrix Input [24]
register [1270]
Figure 22: 3-bit LUT10 or Pipe Delay
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7.3.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUTs
Table 63: 3-bit LUT10 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [1256]
register [1257]
register [1258]
register [1259]
register [1260]
register [1261]
register [1262]
register [1263]
LSB
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT10 is defined by registers [1263:1256]
7.3.2 3-Bit LUT or Pipe Delay Macrocells Used as Pipe Delay Register Settings
Table 64: Pipe Delay Register Settings
Register Bit
Address
Signal Function
Register Definition
LUT3_10 or Pipe
Delay Output Select
[1270]
0: LUT3_10
1: 1 Pipe Delay Output
OUT0 select
OUT1 select
[1259:1256]
[1263:1260]
[1271]
Pipe delay OUT1
Polarity Select Bit
0: Non-inverted
1: Inverted
7.4 3-BIT LUT OR 8-BIT COUNTER/DELAY MACROCELLS
There are five macrocells that can serve as either 3-bit LUTs or as Counter/Delays. When used to implement LUT function, the
3-bit LUT takes in three input signals from the connection matrix and produces a single output, which goes back into the
connection matrix. When used to implement 8-Bit Counter/Delay function, two of the three input signals from the connection matrix
go to the external clock (EXT_CLK) and reset (DLY_IN/CNT Reset) for the counter/delay, with the output going back to the
connection matrix.
These macrocells can also operate in a one-shot mode, which will generate an output pulse of user-defined width.
These macrocells can also operate in a frequency detection or edge detection mode.
For timing diagrams refer to Section 7.6
Note Counters initialize with counter data after POR.
Two of the five macrocells can have their active count value read via I2C (CNT4 and CNT6). See Section 17.6.1 for further details.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7.4.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams
From Connection
Matrix Output [85]
IN2
3-bit LUT5
IN1
IN0
From Connection
Matrix Output [84]
S0
S1
OUT
0: 3-bit LUT5 IN1
1: CNT/DLY2 CLK
LUT Truth
Table
To Connection
S0
S1
Matrix Input [17]
8-bits NVM
registers [1543:1536]
0: 3-bit LUT5 OUT
1: CNT/DLY2 OUT
CNT
Data
CLK
From Connection
Matrix Output [83]
S0
S1
OUT
CNT/DLY2
0: 3-bit LUT5 IN0
1: CNT/DLY2 RST
DLY_IN/CNT Reset
1-bit NVM
register [1198]
Figure 23: 3-bit LUT5 or CNT/DLY2
From Connection
Matrix Output [88]
IN2
3-bit LUT6
IN1
From Connection
Matrix Output [87]
S0
S1
OUT
0: 3-bit LUT6 IN1
1: CNT/DLY3 CLK
IN0
LUT Truth
Table
To Connection
S0
S1
Matrix Input [18]
8-bits NVM
registers [1551:1544]
0: 3-bit LUT6 OUT
1: CNT/DLY3 OUT
CNT
Data
CLK
From Connection
Matrix Output [86]
S0
S1
OUT
CNT/DLY3
DLY_IN/CNT Reset
0: 3-bit LUT6 IN0
1: CNT/DLY3 RST
1-bit NVM
register [1197]
Figure 24: 3-bit LUT6 or CNT/DLY3
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
From Connection
Matrix Output [91]
IN2
3-bit LUT7
IN1
IN0
From Connection
Matrix Output [90]
S0
S1
OUT
0: 3-bit LUT7 IN1
1: CNT/DLY4 CLK
LUT Truth
Table
To Connection
S0
S1
Matrix Input [19]
8-bits NVM
registers [1559:1552]
0: 3-bit LUT7 OUT
1: CNT/DLY4 OUT
CNT
Data
CLK
From Connection
Matrix Output [89]
S0
S1
OUT
CNT/DLY4
DLY_IN/CNT Reset
0: 3-bit LUT7 IN0
1: CNT/DLY4 RST
1-bit NVM
register [1196]
Figure 25: 3-bit LUT7 or CNT/DLY4
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
From Connection
Matrix Output [94]
IN2
3-bit LUT8
IN1
IN0
From Connection
Matrix Output [93]
S0
S1
OUT
0: 3-bit LUT8 IN1
1: CNT/DLY5 CLK
LUT Truth
Table
To Connection
S0
S1
Matrix Input [20]
8-bits NVM
registers [1567:1560]
0: 3-bit LUT8 OUT
1: CNT/DLY5 OUT
CNT
Data
CLK
From Connection
Matrix Output [92]
S0
S1
OUT
CNT/DLY5
DLY_IN/CNT Reset
0: 3-bit LUT8 IN0
1: CNT/DLY5 RST
1-bit NVM
register [1195]
Figure 26: 3-bit LUT8 or CNT/DLY5
From Connection
Matrix Output [97]
IN2
3-bit LUT9
IN1
From Connection
Matrix Output [96]
S0
S1
OUT
0: 3-bit LUT9 IN1
1: CNT/DLY6 CLK
IN0
LUT Truth
Table
To Connection
S0
S1
Matrix Input [21]
8-bits NVM
registers [1575:1568]
0: 3-bit LUT9 OUT
1: CNT/DLY6 OUT
CNT
Data
CLK
From Connection
Matrix Output [95]
S0
S1
OUT
CNT/DLY6
DLY_IN/CNT Reset
0: 3-bit LUT9 IN0
1: CNT/DLY6 RST
1-bit NVM
register [1194]
Figure 27: 3-bit LUT9 or CNT/DLY6
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7.4.2 3-Bit LUT or Counter/Delay Macrocells Used as 3-Bit LUTs
Table 65: 3-bit LUT5 Truth Table
Table 68: 3-bit LUT8 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1536]
register [1537]
register [1538]
register [1539]
register [1540]
register [1541]
register [1542]
register [1543]
LSB
register [1560]
register [1561]
register [1562]
register [1563]
register [1564]
register [1565]
register [1566]
register [1567]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 66: 3-bit LUT6 Truth Table
Table 69: 3-bit LUT9 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1544]
register [1545]
register [1546]
register [1547]
register [1548]
register [1549]
register [1550]
register [1551]
register [1568]
register [1569]
register [1570]
register [1571]
register [1572]
register [1573]
register [1574]
register [1575]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
Table 67: 3-bit LUT7 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [1552]
register [1553]
register [1554]
register [1555]
register [1556]
register [1557]
register [1558]
register [1559]
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT5 is defined by registers [1543:1536]
3-Bit LUT6 is defined by registers [1551:1544]
3-Bit LUT7 is defined by registers [1559:1552]
3-Bit LUT8 is defined by registers [1567:1560]
3-Bit LUT9 is defined by registers [1575:1568]
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 70 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the six 3-bit LUT logic cells.
Table 70: 3-bit LUT Standard Digital Functions
Function
AND-3
MSB
LSB
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-3
OR-3
NOR-3
XOR-3
XNOR-3
7.4.3 3-Bit LUT or 8-Bit Counter/Delay Macrocells Used as 8-Bit Counter/Delay Register Settings
Table 71: CNT/DLY2 Register Settings
Register Bit
Address
Signal Function
Register Definition
LUT3_5 or
Counter2 Select
[1198]
0: LUT3_5
1: Counter2
Delay2 Mode Select
or asynchronous
Counter Reset
[1273:1272]
[1276:1274]
00: on both falling and rising edges (for Delay & Counter Reset)
01: on falling edge only (for Delay & Counter Reset)
10: on rising edge only (for Delay & Counter Reset)
11: no Delay on either falling or rising edges/counter high level reset
Counter/Delay2
Clock Source Select
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: 25MHz OSC clock
110: External Clock
111: Counter1 Overflow
Counter/Delay2
Output Selection for
Counter mode
[1277]
0: Default Output
1: Edge Detector Output
Counter/Delay2
Mode Selection
[1279:1278]
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/Delay2
Control Data
[1543:1536]
1 - 255
Table 72: CNT/DLY3 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_6 or
[1197]
0: LUT3_6
Counter3 Select
1: Counter3
Delay3 Mode Select
or asynchronous
Counter Reset
[1281:1280]
00: on both falling and rising edges (for Delay & Counter Reset)
01: on falling edge only (for Delay & Counter Reset)
10: on rising edge only (for Delay & Counter Reset)
11: no Delay on either falling or rising edges/counter high level reset
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GreenPAK Programmable Mixed-Signal Matrix
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Table 72: CNT/DLY3 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
Counter/Delay3
Clock Source Select
[1284:1282]
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: 25MHz OSC clock
110: External Clock
111: Counter2 Overflow
Counter/Delay3
Output Selection for
Counter mode
[1285]
0: Default Output
1: Edge Detector Output
Counter/Delay2
Mode Selection
[1287:1286]
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/Delay3
Control Data
[1551:1544]
1 - 255
Table 73: CNT/DLY4 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_7 or
Counter4 Select
[1196]
0: LUT3_7
1: Counter4
Delay4 Mode Select
or asynchronous
Counter Reset
[1289:1288]
[1292:1290]
00: on both falling and rising edges (for Delay & Counter Reset)
01: on falling edge only (for Delay & Counter Reset)
10: on rising edge only (for Delay & Counter Reset)
11: no Delay on either falling or rising edges/counter high level reset
Counter/Delay4
Clock Source Select
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: 25MHz OSC clock
110: External Clock
111: Counter3 Overflow
Counter/Delay4
Output Selection for
Counter mode
[1293]
0: Default Output
1: Edge Detector Output
Counter/Delay4
Mode Selection
[1295:1294]
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/Delay4
Control Data
[1559:1552]
1 - 255
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 74: CNT/DLY5 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_8 or
Counter5 Select
[1195]
0: LUT3_8
1: Counter5
Delay5 Mode Select
or asynchronous
Counter Reset
[1297:1296]
[1300:1298]
00: on both falling and rising edges (for Delay & Counter Reset)
01: on falling edge only (for Delay & Counter Reset)
10: on rising edge only (for Delay & Counter Reset)
11: no Delay on either falling or rising edges/counter high level reset
Counter/Delay5
Clock Source Select
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: 25 MHz OSC clock
110: External Clock
111: Counter4 Overflow
Counter/Delay5
Output Selection for
Counter mode
[1301]
0: Default Output
1: Edge Detector Output
Counter/Delay5
Mode Selection
[1303:1302]
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/Delay5
Control Data
[1567:1560]
1 - 255
Table 75: CNT/DLY6 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_9 or
Counter5 Select
[1194]
0: LUT3_9
1: Counter6
Delay6 Mode Select
or asynchronous
Counter Reset
[1305:1304]
[1308:1306]
00: on both falling and rising edges (for Delay & Counter Reset)
01: on falling edge only (for Delay & Counter Reset)
10: on rising edge only (for Delay & Counter Reset)
11: no Delay on either falling or rising edges/counter high level reset
Counter/Delay6
Clock Source Select
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: 25 MHz OSC clock
110: External Clock
111: Counter5 Overflow
Counter/Delay6
Output Selection for
Counter mode
[1309]
0: Default Output
1: Edge Detector Output
Counter/Delay6
Mode Selection
[1311:1310]
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 75: CNT/DLY6 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
Counter/Delay6
Control Data
[1575:1568]
1 - 255
7.5 4-BIT LUT OR 16-BIT COUNTER/DELAY MACROCELLS
There are two macrocells that can serve as either 4-bit LUTs or as 16-bit Counter/Delays. When used to implement LUT function,
the 4-bit LUT takes in four input signals from the Connection Matrix and produces a single output, which goes back into the
Connection Matrix. When used to implement 16-Bit Counter/Delay function, four input signals from the connection matrix go to
the external clock (EXT_CLK) and Reset (DLY_IN/CNT Reset), Keep and Up for the counter/delay, with the output going back to
the connection matrix.
These two macrocells have an optional Finite State Machine (FSM) function. There are two matrix inputs for Up and Keep to
support FSM functionality. Any counter within Green PAK is counting down by default. In FSM mode (CNT/DLY0 and CNT/DLY1)
it is possible to reverse counting by applying High level to Up input. Also, there is a possibility to pause counting by applying High
level to Keep input, after the level goes Low, the counter will proceed counting.These macrocells can also operate in a one-shot
mode, which will generate an output pulse of user-defined width.
These macrocells can also operate in a frequency detection.
Delay time and Output Period can be calculated using the following formulas:
Delay time: [(Counter data + 2)/CLK input frequency – Offset*];
Output Period: [(Counter data + 1)/CLK input frequency – Offset*].
One Shot pulse width can be calculated using formula:
Pulse width = [(Counter Data + 2)/CLK input frequency – Offset*];
*Offset is the asynchronous time offset between the input signal and the first clock pulse.
Note Counters initialize with counter data after POR
For timing diagrams refer to Section 7.6.
Both of these macrocells can have their active count value read via I2C. See Section 17.6.1 for further details.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7.5.1 4-Bit LUT or 16-Bit CNT/DLY Block Diagram
From Connection
Matrix Output [104]
S0
0: 4-bit LUT0 IN3
1: FSM KEEP
S1
IN3
From Connection
S0
S1
Matrix Output [103]
0: 4-bit LUT0 IN2
1: FSM UP
IN2
IN1
4-bit LUT0
From Connection
Matrix Output [102]
S0
S1
OUT
0: 4-bit LUT0 IN1
1: CNT/DLY0 CLK
IN0
LUT Truth
Table
To Connection
Matrix Input [22]
16-bits NVM
registers [1591:1576]
0: 4-bit LUT0 OUT
1: CNT/DLY0 OUT
CNT
Data
CLK
From Connection
S0
S1
Matrix Output [101]
OUT
CNT/DLY0
0: 4-bit LUT0 IN0
1: CNT/DLY0 RST
DLY_IN/CNT Reset
KEEP
FSM
UP
1-bit NVM
register [1193]
Figure 28: 4-bit LUT0 or CNT/DLY0
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
From Connection
Matrix Output [108]
S0
0: 4-bit LUT1 IN3
1: FSM KEEP
S1
IN3
From Connection
S0
S1
Matrix Output [107]
0: 4-bit LUT1 IN2
1: FSM UP
IN2
IN1
4-bit LUT1
From Connection
Matrix Output [106]
S0
S1
OUT
0: 4-bit LUT1 IN1
1: CNT/DLY1 CLK
IN0
LUT Truth
Table
To Connection
S0
S1
Matrix Input [23]
16-bits NVM
registers [1607:1592]
0: 4-bit LUT1 OUT
1: CNT/DLY1 OUT
CNT
Data
CLK
From Connection
S0
S1
Matrix Output [105]
OUT
CNT/DLY1
0: 4-bit LUT1 IN0
1: CNT/DLY1 RST
DLY_IN/CNT Reset
KEEP
FSM
UP
1-bit NVM
register [1192]
Figure 29: 4-bit LUT1 or CNT/DLY1
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7.5.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs
Table 76: 4-bit LUT0 Truth Table
Table 77: 4-bit LUT1 Truth Table
IN3
0
IN2
0
IN1
0
IN0
0
OUT
IN3
0
IN2
0
IN1
0
IN0
0
OUT
register [1576] LSB
register [1577]
register [1578]
register [1579]
register [1580]
register [1581]
register [1582]
register [1583]
register [1584]
register [1585]
register [1586]
register [1587]
register [1588]
register [1589]
register [1590]
register [1591] MSB
register [1592] LSB
register [1593]
register [1594]
register [1595]
register [1596]
register [1597]
register [1598]
register [1599]
register [1600]
register [1601]
register [1602]
register [1603]
register [1604]
register [1605]
register [1606]
register [1607] MSB
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
Each macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:
4-Bit LUT0 is defined by registers [1591:1576]
4-Bit LUT1 is defined by registers [1607:1592]
Table 78: 4-bit LUT Standard Digital Functions
Function
AND-4
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-4
OR-4
NOR-4
XOR-4
XNOR-4
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7.5.3 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 16-Bit Counter/Delay Register Setting
Table 79: CNT/DLY0 Register Settings
Register Bit
Address
Signal Function
Register Definition
LUT4_0 or
Counter0 Select
[1193]
0: LUT4_0
1: Counter0
Delay0 Mode Select
or asynchronous
Counter Reset
[1313:1312]
[1316:1314]
00: on both falling and rising edges (for delay & Counter Reset)
01: on falling edge only (for delay & Counter Reset)
10: on rising edge only (for delay & Counter Reset)
11: no delay on either falling or rising edges/counter high level reset
Counter/delay0
Clock Source Select
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: 25 MHz OSC clock
110: External Clock
111: Counter6 Overflow
CNT0/FSM0's Q are
Set to data or Reset
to 0s Selection
[1317]
0: Reset to 0s
1: Set to control data (Registers [1583:1576, 1591:1584])
Counter/delay0
Mode Selection
[1319:1318]
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/delay0
Control Data
[1591:1576]
1 - 65535 (Delay Time = [Counter Control Data + 1]/Freq)
Table 80: CNT/DLY1 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT4_1 or
Counter1 Select
[1192]
0: LUT4_1
1: Counter1
Delay1 Mode Select
or asynchronous
Counter Reset
[1321:1320]
[1324:1322]
00: on both falling and rising edges (for delay & Counter Reset)
01: on falling edge only (for delay & Counter Reset)
10: on rising edge only (for delay & Counter Reset)
11: no delay on either falling or rising edges/counter high level reset
Counter/delay1
Clock Source Select
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: 25MHz OSC clock
110: External Clock
111: Counter0 Overflow
CNT0/FSM0's Q are
Set to data or Reset
to 0s Selection
[1325]
0: Reset to 0s
1: Set to counter data (Registers [1599:1592, 1607:1600])
Counter/delay1
Mode Selection
[1327:1326]
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/delay1
Control Data
[1607:1592]
1 - 65535 (Delay Time = [Counter Control Data + 1]/Freq)
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7.6 CNT/DLY/FSM TIMING DIAGRAMS
7.6.1 Delay Mode (Edge Select: Both, Counter Data: 3) CNT/DLY2 to CNT/DLY6
Delay In
Asynchronous delay variable
Asynchronous delay variable
RC osc: force Power-On
(always running)
Delay Output
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
Delay In
offset
offset
RC osc: auto Power-On
(powers up from delay in)
Delay Output
delay = offset + period x (counter data + 1)
See offset in table 3
delay = offset + period x (counter data + 1)
See offset in table 3
Figure 30: Delay Mode Timing Diagram
7.6.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY2 to CNT/DLY6
RESET_IN
CLK
Counter OUT
4 CLK period pulse
Count start in 0 CLK after reset
Figure 31: Counter Mode Timing Diagram
7.6.3 One-Shot Mode CNT/DLY0 to CNT/DLY6
This macrocell will generate a pulse whenever a selected edge is detected on its input. Register bits set the edge selection. The
pulse width determines by counter data and clock selection properties. The output pulse polarity (non-inverted or inverted) is
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
selected by register bit. See Figure 81. Any incoming edges will be ignored during the pulse width generation. The following
diagram shows one-shot function for non-inverted output.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
Delay time
One-Shot Function
Rising Edge Detection
t
One-Shot Function
Falling Edge Detection
t
One-Shot Function
Both Edge Detection
t
Figure 32: One-Shot Function Timing Diagram
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 81: DLY/CNTx One-Shot/Freq. Detect Output Polarity
I2C Interface
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
Select the Polarity of DLY/CNT6's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
[1329]
Valid
Valid
Select the Polarity of DLY/CNT5's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
[1330]
[1331]
[1332]
[1333]
[1334]
[1335]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Select the Polarity of DLY/CNT4's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT3's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
A6
Select the Polarity of DLY/CNT2's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT1's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT0's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
This macrocell generates a high level pulse with a set width (defined by counter data) when detecting the respective edge. It does
not restart while pulse is high.
7.6.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6
Rising Edge: The output goes high if the time between two successive edges is less than the delay. The output goes low if the
second rising edge has not come after the last rising edge in specified time.
Falling Edge: The output goes high if the time between two falling edges is less than the set time. The output goes low if the
second falling edge has not come after the last falling edge in specified time.
Both Edge: The output goes high if the time between the rising and falling edges is less than the set time, which is equivalent to
the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not come.
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GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Delay time
Frequency Detector Function
Rising Edge Detection
Frequency Detector Function
Falling Edge Detection
t
t
Frequency Detector Function
Both Edge Detection
Figure 33: Frequency Detection Mode Timing Diagram
7.6.5 Edge Detection Mode CNT/DLY2 to CNT/DLY6
The macrocell generates high level short pulse when detecting the respective edge. See Table 13.
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GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Edge Detector Function
Rising Edge Detection
Edge Detector Function
Falling Edge Detection
t
t
Edge Detector Function
Both Edge Detection
Figure 34: Edge Detection Mode Timing Diagram
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
7.6.6 Delay Mode CNT/DLY0 to CNT/DLY6
The macrocell shifts the respective edge to a set time and restarts by appropriate edge. It works as a filter if the input signal is
shorter than the delay time.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
Delay time
Delay Function
Rising Edge Detection
t
Delay Function
Falling Edge Detection
t
Delay Function
Both Edge Detection
t
Figure 35: Delay Mode Timing Diagram
7.6.7 CNT/FSM Mode CNT/DLY0, CNT/DLY1
RESET IN
KEEP
COUNT END
CLK
3
2
1
0
3
2
1
0
3
2
1
3
2
1
0
0
Q
Note: Q = current counter value
Figure 36: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
SET IN
KEEP
COUNT END
CLK
2
1
0
3
2
1
0
3
3
2
1
2
1
0
3
3
Q
Note: Q = current counter value
Figure 37: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3
RESETI N
KEEP
COUNT END
CLK
65535
65533 65534
4
5
5
6
7
8
9
3
3
4
5
1
2
3
4
0
Q
Note: Q = current counter value
Figure 38: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
SET IN
KEEP
COUNT END
CLK
65533 65534 65535
8
9
10 11 12
3
4
5
3
4
5
4
5
6
7
3
Q
Note: Q = current counter value
Figure 39: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3
7.7 2-BIT LUT OR PROGRAMMABLE PATTERN GENERATOR
The SLG46517 has one combination function macrocell that can serve as a logic or timing function. This macrocell can serve as
a Look Up Table (LUT), or Programmable Pattern Generator (PGen).
When used to implement LUT functions, the 2-bit LUT takes in four input signals from the connection matrix and produce a single
output, which goes back into the connection matrix. When used as a LUT to implement combinatorial logic functions, the outputs
of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND,
OR, NOR, XOR, XNOR). The user can also define the combinatorial relationship between inputs and outputs to be any selectable
function.
When operating as a Programmable Pattern Generator, the output of the macrocell with clock out a sequence of two to sixteen
bits that are user selectable in their bit values, and user selectable in the number of bits (up to sixteen) that are output before the
pattern repeats. See Figure 40.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
From Connection Matrix Output [66]
From Connection Matrix Output [67]
In0
In1
OUT
2-bit LUT3
LUT Truth
Table
To Connection Matrix Input [11]
S0
S1
registers [1623:1608]
0: 2-bit LUT3 OUT
1: PGen OUT
Pattern
Data
nRST
CLK
PGen
OUT
PGen
size
register [1188]
registers [1211:1208]
Figure 40: 2-bit LUT2 or PGen
V
DD
t
t
nRST
CLK
OUT
1
2
6
8
16 17
0
3
4
5
7
9
11
10
14 15
12 13
t
t
D7
D6
D5
D10
D8
D4
D3
D2
D1
D15
D9
D0
D0
D15
D14
D13
D12
D11
D0
Figure 41: PGen Timing Diagram
7.8 WAKE AND SLEEP CONTROLLER
The SLG46517 has a Wake and Sleep (WS) function for all ACMPs. The macrocell CNT/DLY0 can be reconfigured for this
purpose registers [1319:1318] = 11 and registers [1495] = 1. The WS serves for power saving, it allows to switch on and off
selected ACMPs on selected bit of 16-bit counter.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
WS Controller
OSC
CNT0 out
CNT
CNT_end
WS out
000:/1
001:/4
010:/12
011:/24
100:/64
To Connection Matrix Input [22]
Power Control
CK
register [1489]
CK_OSC
WS_PD
From Connection
Matrix Output[58]
WS time selection
From Connection
Matrix Output [54:51]
WS_PD
4
4
ACMPs_pdb
Analog
Control
Block
bg/regulator pdb
registers [1316:1314]
WS out
WS clock freq.
selection
registers [1591:1576]
WS ratio control data
registers [1493:1490]
ACMP WS enable
register [1494]
WS out state for OSC off
WS_PD to W&S out state selection block
4
ACMPs_pdb
ACMP0..3 OUT
4
4
Latches
+
-
WS out
Note: WS_PD is High at WS OSC (25 kHz/2 MHz OSC) power-down
To Connection
Matrix Input
[60:57]
Figure 42: Wake/Sleep Controller
ACMP_PD is High
through the Connection
Matrix
CNT_out (to CM)
1 us
ACMP output is latched,
and BG/Analog is powered off
WS_out
(internal signal)
BG/Analog_Good
(internal signal)
BG/Analog ON Start
Sleep Mode
Normal ACMP
Operation
Sleep Mode (maintains latched ACMP output
BG/Analog
stabilization time*
Note: * Refer to Electrical Spec (ACMP Start Time)
Figure 43: Wake/Sleep Timing Diagram
To use any ACMP under WS controller the following settings must be done:
ACMP Power Up Input from matrix = 1 (for each ACMP separately);
CNT/DLY0 must be set to Wake and Sleep Controller function (for all ACMPs);
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Register WS => enable (for each ACMP separately);
CNT/DLY0 set/reset input = 0 (for all ACMPs);
In case of using OSC1 (25 MHz), OSC0 must be set to Force Power-On.
As the OSC any oscillator with any pre-divider can be used. The user can select a period of time while the ACMPs are sleeping
in a range of 1 - 65535 clock cycles. Before they are sent to sleep their outputs are latched, so the ACMPs remain their state
(High or Low) while sleeping.
WS controller has the following settings:
Wake and Sleep Output State (High/Low)
If OSC is powered off (Power-Down option is selected; power-down input = 1) and Wake and Sleep Output State = High, the
ACMP is continuously on.
If OSC is powered off (Power-Down option is selected; power-down input = 1) and Wake and Sleep Output State = Low, the
ACMP is continuously off.
Both cases WS function is turned off.
Counter Data (Range: 1 - 65535)
User can select wake and sleep ratio of the ACMP; counter data = sleep time, one clock = wake time.
Q mode - defines the state of WS counter data when Set/Reset signal appears
Reset - when active signal appears, the WS counter will reset to zero and High level signal on its output will turn the ACMPs
on. When Reset signal goes out, the WS counter will go Low and turn the ACMPs off until the counter counts up to the end
Set - when active signal appears, the WS counter will stop and Low level signal on its output will turn the ACMPs off. When
Set signal goes out, the WS counter will go on counting and High level signal will turn the ACMPs on while counter is counting
up to the end.
Edge Select defines the edge for Q mode
High level Set/Reset - switches mode Set/Reset when level is High
Note: Q mode operates only in case of "High Level Set/Reset”.
Wake time selection - time required for wake signal to turn the ACMPs on
Normal Wake Time - when WS signal is High, it takes a BG time (100/550 µs) to turn the ACMPs on. They will stay on until
WS signal is Low again. Wake time is one clock period. It should be longer than BG turn on time and minimal required
comparing time of the ACMP.
Short Wake Time - when WS signal is High, it takes a BG time (100/550 µs) to turn the ACMPs on. They will stay on for 1 µs
and turn off regardless of WS signal. The WS signal width does not matter.
Keep - pauses counting while Keep = 1
Up - reverses counting
If Up = 1, CNT is counting up from user selected value to 65535.
If Up = 0, CNT is counting down from user selected value to 1.
Table 82: WS Register Settings
Register Bit
Address
Signal Function
Register Definition
Counter/delay0
Clock Source Select
[1316:1314]
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: 25 MHz OSC clock
110: External Clock
111: Counter6 Overflow
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 82: WS Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
WS time selection
[1489]
0: Short Wake Time
1: Normal Wake Time
ACMP0 Wake & Sleep
function Enable
[1490]
[1491]
[1492]
[1493]
[1494]
0: Disable
1: Enable
ACMP1 Wake & Sleep
function Enable
0: Disable
1: Enable
ACMP2 Wake & Sleep
function Enable
0: Disable
1: Enable
ACMP3 Wake & Sleep
function Enable
0: Disable
1: Enable
Wake Sleep Output State
When WS Oscillator
is Power-down own if DLY/
CNT0 Mode Selection
is "11"
0: Low
1: High
Wake Sleep Ratio Control
Mode Selection if
[1495]
0: Default Mode
1: Wake Sleep Ratio Control Mode
DLY/CNT0 Mode Selection
is "11"
DLY/CNT0
[1591:1576]
1 - 65535
(16bits, [15:0] =
[1591:1576]) Control Data
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8
Analog Comparators
There are four Analog Comparator (ACMP) macrocells in the SLG46517. In order for the ACMP cells to be used in a GreenPAK
design, the power up signals (ACMPx PWR UP) need to be active. By connecting to signals coming from the Connection Matrix,
it is possible to have each ACMP be always on, always off, or power cycled based on a digital signal coming from the Connection
Matrix. Also, all ACMPs have Wake and Sleep function (WS), see Section 7.8. When ACMP is powered down, output is low.
PWR UP = 1 => ACMP is powered up.
PWR UP = 0 => ACMP is powered down.
During ACMP power up, its output will remain low, and then becomes valid 1.03 ms (max) after ACMP power up signal goes high,
see Figure 45. If VDD is greater or equal to 2.7 V, it is possible to decrease turn-on time by setting the BG ok delay to 100 µs, see
Figure 46. The ACMP cells have an input "Low bandwidth" signal selection, which can be used to save power and reduce noise
impact when lower bandwidth signals are being compared. To ensure proper chip startup operation, it is recommended to enable
the ACMPs with the POR signal, and not the VDD signal.
Note: Regulator and Charge Pump set to automatic ON/OFF.
240
220
200
180
160
-40⁰C
+25⁰C
140
+85⁰C
120
VDD (V)
Figure 44: Maximum Power-On Delay vs. VDD, BG = Auto-delay.
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220
210
200
190
180
170
160
150
140
130
120
1100
1050
1000
950
900
850
800
750
-40⁰C
+25⁰C
+85⁰C
-40⁰C
+25⁰C
+85⁰C
700
650
600
VDD (V)
VDD (V)
Figure 45: Max. Power-On Delay vs. VDD, BG = 550 µs
Figure 46: Max. Power-On Delay vs. VDD, BG = 100 µs
Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources. There is also a selectable
gain stage (1x, 0.5x, 0.33x, 0.25x) before connection to the analog comparator. The Gain divider is unbuffered and consists of
250 KΩ (typ) resistors, see Table 83. For gain divider accuracy refer to Table 84. IN- voltage range: 0 - 1.2 V. Can use Vref selection
VDD/4 and VDD/3 to maintain this input range.
Input bias current < 1 nA (typ).
Table 83: Gain Divider Input Resistance
Gain
x1
x0.5
x0.33
x0.25
1 MΩ
Input Resistance
100 MΩ
1 MΩ
0.75 MΩ
Table 84: Gain Divider Accuracy
Gain
x0.5
±0.51%
x0.33
x0.25
±0.25%
Accuracy
±0.34%
Each cell also has a hysteresis selection, to offer hysteresis of (0, 25, 50, 200) mV. The 50 mV and 200 mV hysteresis options
can be used with internal voltage reference only, while 25 mV hysteresis option can be used with both internal and external voltage
reference. The 50 mV and 200 mV hysteresis options are one way hysteresis. It means that the actual thresholds will be Vref
(high threshold) and Vref - hysteresis (low threshold). The ACMP output will retain its previous value, if the input voltage is within
threshold window (between Vref and Vref - hysteresis). Please note: for the 25 mV hysteresis option threshold levels will be Vref +
hysteresis/2 (high threshold) and Vref – hysteresis/2 (low threshold).
Note: Any ACMP powered on enables the BandGap internal circuit as well. An analog voltage will appear on Vref even when the
Force BandGap option is set as Disabled.
For high input impedance when using the gain divider (x0.25, x0.33, x0.5), it is possible to use the input buffer. However, this will
add some offset, see Figure 47 to Figure 48. It is not recommended to use ACMP buffer when VDD < 2.5 V.
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GreenPAK Programmable Mixed-Signal Matrix
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40
30
20
10
Upper Limit @ VDD≥2.7V
Lower Limit @ VDD≥2.7V
VOLTAGE REFERENCE (mV)
600
0
-10
-20
-30
-40
50
250
850
1200
Note: Buffer Bandwidth = 1 kHz, Vhys = 0 mV, Gain = 1, T = -40 °C to +85 °C
Figure 47: Typical Buffer Input Voltage Offset vs. Voltage Reference
20%
15%
10%
5%
Upper Limit
Lower Limit
0%
50
150
250
350
450
550
650
750
850
950
1050
1150
-5%
-10%
-15%
-20%
-25%
VOLTAGE REFERENCE (mV)
Note: LMB Mode - Disable, Vhys = 0 mV, T = -40 °C to +85 °C
Figure 48: Typical Input Threshold Variation (Including Vref Variation, ACMP Offset) vs. Voltage Reference
Note: When VDD < 1.8 V voltage reference should not exceed 1100 mV.
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Table 85: Built-In Hysteresis Tolerance at T = 25 °C
VDD= 1.7 V to 1.8 V
Vref =
VDD = 1.89 V to 5.5 V
Vhys (mV)
50 mV to
500)mV
Vref = 550 V to Vref = 1050 V to
1000 mV 1200 mV
Vref =
Vref = 550 V to Vref = 1050 V to
50 V to 500 mV
1000 mV
1200 mV
min
max
32.2
min
max
32.3
min
max
32.5
min
8.5
max
32.3
min
max
32.3
min
max
34.0
25
50
8.6
44.8
192.8
8.6
43.9
194.0
7.0
42.7
192.7
8.5
43.6
193.0
7.8
43.1
190.8
56.5
56.7
56.4
44.2
192.0
56.8
57.3
56.0
200
207.9
208.0
205.4
208.6
209.5
207.7
8.1 ACMP0 BLOCK DIAGRAM AND REGISTER SETTINGS
to ACMP1, ACMP2, AC-
register [1631]
MP3’s MUX input
registers [1175:1174]
LBW
Selection
Hysteresis
Selection
External V
DD
2.7 V ~ 5.5 V
registers [1630:1629]
110
100
0X1
BG_ok
L/S
IO4: ACMP0(+)
External V 1.71 V ~ 5.5 V
Selectable
Gain
+
To Connection
Matrix Input[57]
0
1
DD
Vref
-
PWR UP
Latch
*IO4_aio_en; register [1173]; register [1172]
*IO4_aio_en:
if registers [1062:1061]=’11’ then 1,
otherwise: 0
register [1490]
ACMP0 Wake & Sleep function Enable
IO9: Ext_Vref
IO5: ACMP0(-)
IO9: Ext_Vref/2
IO5: ACMP0(-)/2
11010
11011
11100
11101
From Connection
Matrix Output [51]
11001-
00000
Internal
Vref
registers [1628:1624]
Figure 49: ACMP0 Block Diagram
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GreenPAK Programmable Mixed-Signal Matrix
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Table 86: ACMP0 Register Settings
Register Bit
Signal Function
Address
Register Definition
ACMP0 Positive
Input Source Select
[1172]
0: IO4
1: VDD
ACMP0 Analog
Buffer Enable
[1173]
0: Disable analog buffer
1: Enable analog buffer
ACMP0 Hysteresis
Enable
[1175:1174]
00: Disabled (0 mV)
01: Enabled (25 mV)
10: Enabled (50 mV)
11: Enabled (200 mV)
(01: for both external & internal Vref; 10 & 11: for only internal Vref; External Vref will
not have 50 mV & 200 mV hysteresis.)
ACMP0 Wake &
Sleep function
Enable
[1490]
0: Disable
1: Enable
ACMP0 In Voltage
Select
[1628:1624]
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
11010: IO9: EXT_Vref
11011: IO5: ACMP0-
11100: IO9: EXT_Vref/2
11101: IO5: ACMP0-/2
11110: Reserved
11111: Reserved
ACMP0 Positive
Input Divider
[1630:1629]
[1631]
00: 1.00x
01: 0.50x
10: 0.33x
11: 0.25x
ACMP0 Low
Bandwidth (Max: 1
MHz) Enable
0: Off
1: On
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GreenPAK Programmable Mixed-Signal Matrix
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8.2 ACMP1 BLOCK DIAGRAM AND REGISTER SETTINGS
register [1639]
V
= 1.8 V
DD
registers [1171:1170]
100 µA
Current
Source
register [1183]
LBW
Selection
en
Hysteresis
Selection
External V
DD
2.7 V ~ 5.5 V
registers [1638:1637]
11X
10X
0X1
BG_ok
L/S
IO8: ACMP1(+)
Selectable
Gain
+
To Connection
Matrix Input[58]
0
1
From ACMP0's MUX output
Vref
-
PWR UP
Latch
*IO8_aio_en; register [1169]; register [1168]
*IO8_aio_en:
if registers [1093:1092]=’11’ then 1, otherwise: 0
register [1491]
ACMP1 Wake & Sleep function Enable
IO9: EXT_Vref
11010
11011
11100
11101
IO9: EXT_Vref
IO9: EXT_Vref/2
IO9: EXT_Vref/2
From Connection
Matrix Output [52]
11101-
00000
Internal
Vref
registers [1636:1632]
Note: when 100 µA Current Source is enabled input voltage on IO8 should not exceed 1.8 V.
Figure 50: ACMP1 Block Diagram
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 87: ACMP1 Register Settings
Register Bit
Signal Function
Address
Register Definition
ACMP1 100 µA
Current Source
Enable
[1183]
0: Disable
1: Enable
ACMP1 Positive
Input Source Select
[1168]
[1169]
0: IO8
1: ACMP0 IN+ source
ACMP1 Analog
Buffer Enable (max.
band width 1 MHz)
0: Disable analog buffer
1: Enable analog buffer
ACMP1 Hysteresis
Enable
[1171:1170]
00: Disabled (0 mV)
01: Enabled (25 mV)
10: Enabled (50 mV)
11: Enabled (200 mV)
(01: for both external & internal Vref; 10 & 11: for only internal Vref; External Vref will
not have 50 mV & 200 mV hysteresis.)
ACMP1 Wake &
Sleep function
Enable
[1491]
0: Disable
1: Enable
ACMP1 In Voltage
Select
[1636:1632]
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
11010: IO9: EXT_Vref
11011: Reserved
11100: IO9: EXT_Vref/2
11101: Reserved
11110: Reserved
11111: Reserved
ACMP1 Positive
Input Divider
[1638:1637]
[1639]
00: 1.00x
01: 0.50x
10: 0.33x
11: 0.25x
ACMP1 Low
Bandwidth (Max: 1
0: Off
1: On
MHz) Enable
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GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
8.3 ACMP2 BLOCK DIAGRAM AND REGISTER SETTINGS
register [1647]
registers [1182:1181]
LBW
Selection
Hysteresis
Selection
registers [1646:1645]
IO10: ACMP2(+)
10
01
BG_ok
L/S
Selectable
Gain
+
To Connection
Matrix Input[59]
0
1
from ACMP0’s MUX output
Vref
PWR UP
-
Latch
*IO10_aio_en; register [1180]
*IO10_aio_en:
if registers [1109:1108]=’11’ then 1,
otherwise: 0
register [1492]
ACMP2 Wake & Sleep function Enable
IO9: EXT_Vref
11010
11011
11100
11101
IO11: ACMP2(-)
IO9: EXT_Vref/2
IO11: ACMP2(-)/2
From Connection
Matrix Output [53]
11001-
00000
Internal
Vref
registers [1644:1640]
Figure 51: ACMP2 Block Diagram
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 88: ACMP2 Register Settings
Register Bit
Signal Function
Address
Register Definition
ACMP2 Positive
Input Source Select
[1180]
0: IO10
1: ACMP0 IN+ source
ACMP2 Hysteresis
Enable
[1182:1181]
00: Disabled (0 mV)
01: Enabled (25 mV)
10: Enabled (50 mV)
11: Enabled (200 mV)
(01: for both external & internal Vref; 10 & 11: for only internal Vref; External Vref will
not have 50mV & 200mV hysteresis.)
ACMP2 Wake &
Sleep function
Enable
[1492]
0: Disable
1: Enable
ACMP2 In Voltage
Select
[1644:1640]
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
11010: IO9: EXT_Vref
11011: IO11: ACMP2-
11100: IO9: EXT_Vref /2
11101: IO11: ACMP2-/2
11110: Reserved
11111: Reserved
ACMP2 Positive
Input Divider
[1646:1645]
[1647]
00: 1.00x
01: 0.50x
10: 0.33x
11: 0.25x
ACMP2 Low
Bandwidth (Max: 1
MHz) Enable
0: Off
1: On
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8.4 ACMP3 BLOCK DIAGRAM AND REGISTER SETTINGS
register [1655]
registers [1179:1178]
LBW
Selection
Hysteresis
Selection
registers [1654:1653]
IO12: ACMP3(+)
From ACMP0’s MUX output
IO10: ACMP2(+)
00
10
01
BG_ok
L/S
Selectable
Gain
+
To Connection
Matrix Input[60]
0
1
Vref
PWR UP
-
Latch
*IO12_aio_en; register [1177]; register [1176]
*IO12_aio_en:
if registers [1126:1125]=’11’then 1, otherwise:
0
register [1493]
ACMP3 Wake & Sleep function Enable
IO9: EXT_Vref
11011
11010
11100
11101
IO11: ACMP3(-)
IO9: EXT_Vref/2
IO11: ACMP3(-)/2
From Connection
Matrix Output [54]
11001-
00000
Internal
Vref
registers [1652:1648]
Figure 52: ACMP3 Block Diagram
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 89: ACMP3 Register Settings
Register Bit
Signal Function
Address
Register Definition
ACMP3 Positive
Input Source Select
[1177:1176]
00: IO12
01: ACMP2 IN+ source
10: ACMP0 IN+ source
11: Reserved
ACMP3 Hysteresis
Enable
[1179:1178]
00: Disabled (0 mV)
01: Enabled (25 mV)
10: Enabled (50 mV)
11: Enabled (200 mV)
(01: for both external & internal Vref; 10 & 11: for only internal Vref; External Vref will
not have 50 mV & 200 mV hysteresis.)
ACMP3 Wake &
Sleep function
Enable
[1493]
0: Disable
1: Enable
ACMP3 In Voltage
Select
[1652:1648]
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
11010: IO9: EXT_Vref
11011: IO11: ACMP3-
11100: IO9: EXT_Vref/2
11101: IO11: ACMP3-/2
11110: Reserved
11111: Reserved
ACMP3 Positive
Input Divider
[1654:1653]
[1655]
00: 1.00x
01: 0.50x
10: 0.33x
11: 0.25x
ACMP3 Low
Bandwidth (Max: 1
MHz) Enable
0: Off
1: On
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GreenPAK Programmable Mixed-Signal Matrix
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9
Pipe Delay
The SLG46517 has a pipe delay logic cell that is shared with the LUT3_10 in one of the Combination Function macrocells. The
user can select one of these functions to use in a design, but not both. Please see Section 7.3 for the description of this
Combination Function macrocell.
10 Programmable Delay/Edge Detector
The SLG46517 has a programmable time delay logic cell available that can generate a delay that is selectable from one of four
timings configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay patterns,
rising edge detection, falling edge detection, both edge detection, and both edge delay. See the timing diagrams below for further
information.
Note: The input signal must be longer than the delay, otherwise it will be filtered out.
registers [1267:1266]
Delay Value Selection
registers [1265:1264]
Edge Mode Selection
To Connection
Matrix Input [61]
Programmable
From Connection Matrix Output [57]
IN
OUT
Delay
Figure 53: Programmable Delay
10.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT
width
width
IN
time1
Rising Edge Detector
time1
Falling Edge Detector
Edge Detector
Output
Both Edge Detector
Both Edge Delay
time2
time2
time1 is a fixed value
time2 delay value is selected via register
Figure 54: Edge Detector Output
Please refer to Table 13.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
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Table 90: Programmable Delay Register Settings
Register Bit
Signal Function
Address
Register Definition
Select the edge
mode of
programmable
delay & edge
detector
[1265:1264]
00: Rising Edge Detector
01: Falling Edge Detector
10: Both Edge Detector
11: Both Edge Delay
Delay value select
for programmable
delay & edge
detector
[1267:1266]
00: 165 ns
01: 300 ns
10: 440 ns
11: 575 ns
(VDD = 3.3V, typical
condition)
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SLG46517
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11 Additional Logic Function. Deglitch Filter
The SLG46517 has two additional logic functions that are connected directly to the Connection Matrix inputs and outputs. There
are two deglitch filters, each with edge detector functions. See Section 3.5.
11.1 DEGLITCH FILTER/EDGE DETECTOR
Filter_0
R
From Connection Matrix Output [55]
C
To Connection Matrix
Input [30]
Edge
Detect
register [1462]
register [1463]
Edge Select
registers [1461:1460]
Filter_1
R
From Connection Matrix Output [56]
C
Edge
Detect
To Connection Matrix
Input [31]
register [1458]
Edge Select
register [1459]
registers [1457:1456]
Figure 55: Deglitch Filter/Edge Detector
Table 91: Deglitch Filter Register Settings
Register Bit
Signal Function
Address
Register Definition
Filter_1/Edge
[1458]
0: Filter_1 output
Detector_1 output
1: Filter_1 output inverted
Polarity Select
Filter_1 or Edge
Detector_1 Select
(Typ. 30 nS
[1459]
0: Filter_1
1: Edge Detector_1
@VDD=3.3 V)
Filter_0/Edge
Detector_0 output
Polarity Select
[1462]
[1463]
0: Filter_0 output
1: Filter_0 output inverted
Filter_0 or Edge
Detector_0 Select
(Typ. 47 nS
0: Filter_0
1: Edge Detector_0
@VDD=3.3 V)
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GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
12 Voltage Reference
12.1 VOLTAGE REFERENCE OVERVIEW
The SLG46517 has a Voltage Reference (Vref) Macrocell to provide references to the four analog comparators. This macrocell
can supply a user selection of fixed voltage references, /3 and /4 reference off of the VDD power supply to the device, and externally
supplied voltage references from IOs 5, 9, and 11. The macrocell also has the option to output reference voltages on IO 15. See
Table 92 for the available selections for each analog comparator. Also, see Figure 56, which shows the reference output structure.
12.2 VREF SELECTION TABLE
Table 92: Vref Selection Table
SEL[4:0]
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
ACMP0_VREF
ACMP1_VREF
ACMP2_VREF
ACMP3_VREF
vref_ext_acmp0/2
vref_ext_acmp1/2
vref_ext_acmp2/2
vref_ext_acmp2/2
vref_ext_acmp1/2
vref_ext_acmp0
vref_ext_acmp1
VDD/4
VDD/3
1.20
vref_ext_acmp1/2
vref_ext_acmp1
vref_ext_acmp1
VDD/4
VDD/3
1.20
vref_ext_acmp1/2
vref_ext_acmp2
vref_ext_acmp1
VDD/4
VDD/3
1.20
vref_ext_acmp1/2
vref_ext_acmp2
vref_ext_acmp1
VDD/4
VDD/3
1.20
1.15
1.15
1.15
1.15
1.10
1.10
1.10
1.10
1.05
1.05
1.05
1.05
1.00
1.00
1.00
1.00
0.95
0.95
0.95
0.95
0.90
0.90
0.90
0.90
0.85
0.85
0.85
0.85
0.80
0.80
0.80
0.80
0.75
0.75
0.75
0.75
0.70
0.70
0.70
0.70
0.65
0.65
0.65
0.65
0.60
0.60
0.60
0.60
0.55
0.55
0.55
0.55
0.50
0.50
0.50
0.50
0.45
0.45
0.45
0.45
0.40
0.40
0.40
0.40
0.35
0.35
0.35
0.35
0.30
0.30
0.30
0.30
0.25
0.25
0.25
0.25
0.20
0.20
0.20
0.20
0.15
0.15
0.15
0.15
0.10
0.10
0.10
0.10
0.05
0.05
0.05
0.05
VDD
Practical Vref Range Note
2.0 V - 5.5 V
1.7 V - 2.0V
50 mV ~ 1.2 V
50 mV ~ 1.0 V
Do not operate above 1.0 V
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12.3 VREF BLOCK DIAGRAM
reg <1628:1624>
reg <1476>
ACMP0_VREF
ext_vref_acmp0
(IO5)
reg <1636:1632>
ext_vref_acmp1
ACMP1_VREF
(IO9)
ext_vref_acmp2
(IO11)
reg <1644:1640>
IO15_aio_en
reg<1149:1148>=11
ACMP2_VREF
000
001
100
101
110
Vref Out_1 (IO15)
VDD / 3
VDD / 4
reg <1652:1648>
ACMP3_VREF
reg <1482:1480>
VDD / 2
reg <1474>
VDD / 3
VDD / 4
Figure 56: Voltage Reference Block Diagram
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GreenPAK Programmable Mixed-Signal Matrix
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12.4 VREF LOAD REGULATION
Note 1: Vref buffer performance is not guaranteed at VDD < 2.7 V.
650
600
550
500
450
400
350
VDD=5.5V
VDD=3.3V
VDD=2.7V
I (UA)
Figure 57: Typical Load Regulation, Vref = 600 mV, T = -40 °C to +85 °C, Buffer - Enable
1050
VDD=5.5V
VDD=3.3V
VDD=2.7V
1000
950
900
850
800
750
700
I (UA)
Figure 58: Typical Load Regulation, Vref = 1000 mV, T = -40 °C to +85 °C, Buffer - Enable
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1250
1200
1150
1100
1050
1000
950
VDD=5.5V
VDD=3.3V
VDD=2.7V
900
850
I (UA)
Figure 59: Typical Load Regulation, Vref = 1200 mV, T = -40 °C to +85 °C, Buffer - Enable
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13 Clocking
13.1 OSC GENERAL DESCRIPTION
The SLG46517 has three internal oscillators. RC Oscillator that runs at 25 kHz/2 MHz (OSC0), Oscillator that runs at 25 MHz
(OSC1) and Crystal Oscillator. It is possible to use all three oscillators simultaneously. The fundamental frequency can also come
from clock input (IO15 or IO17 for 25 kHz/2 MHz and IO14 for 25 MHz or Crystal OSC), see Section 18.
13.2 25 KHZ/2 MHZ AND 25 MHZ RC OSCILLATORS
There are two divider stages that allow the user flexibility for introducing clock signals on various Connection Matrix Input lines.
The pre-divider allows the selection of /1, /2, /4 or /8 divide down frequency from the fundamental. The second stage divider (only
for 25 kHz/2 MHz Oscillator) has an input of frequency from the pre-divider, and outputs one of seven different frequencies on
Connection Matrix Input lines [27] (OUT0) and [28] (OUT1). See Figure 60 and Figure 61 for details.
There are two modes of the POWER CONTROL pin, (register [1658] for 25 kHz/2 MHz OSC and register [1657] for 25 MHz OSC):
POWER-DOWN [0]. If PWR CONTROL input of oscillator is LOW, the oscillator will be turned on. If PWR CONTROL input of
oscillator is HIGH the oscillator will be turned off and OSC divider will reset.
FORCE ON [1]. If PWR CONTROL input of oscillator is HIGH, the oscillator will be turned on. If PWR CONTROL input of
oscillator is LOW the oscillator will be turned off.
The PWR CONTROL signal has the highest priority.
The SLG46517 has a 25 kHz/2 MHz OSC FAST START-UP function register [1338] (1 – on, 0 – off). It allows the OSC to run
immediately after power-up this decreases the settling time. Note that when OSC FAST START-UP is on, the current consumption
will rise.
The user can select two OSC POWER MODEs (register [1343] for 25 kHz/2 MHz OSC and register [1341] for 25 MHz OSC):
If AUTO POWER-ON [0] is selected, the OSC will run when any macrocell that uses OSC is powered on.
If FORCE POWER-ON [1] is selected, the OSC will run when the SLG46517 is powered on.
OSC can be turned on by:
Register control (force Power-On)
Delay mode, when delay requires OSC
CNT/FSM
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GreenPAK Programmable Mixed-Signal Matrix
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OSC Power Mode register [1343]
Auto Power-On
0
Force Power-On
1
From Connection Matrix Output [58]
PWR DOWN
registers [1340:1339]
Internal RCO
0
1
register [1342]
0: 25 kHz
1: 2 MHz
DIV /1 /2 /4 /8
0
1
Reserved
Pre-divider
0
/ 2
/ 3
IO15 Ext. Clock
1
EXT. CLK Sel
register [1355]
2
3
4
5
6
7
EXT. CLK Sel register [1358]
/ 4
OUT0
OUT1
To Connection Matrix Input [27]
To Connection Matrix Input [28]
/ 8
/ 12
/ 24
/ 64
registers [1349:1347]
registers [1346:1344]
Second Stage
Divider
Figure 60: 25 kHz/2 MHz RC OSC Block Diagram
OSC Power Mode register [1341]
Auto Power-On
Force Power-On
0
1
From Connection Matrix Output [59]
PWR DOWN
registers [1337:1336]
Internal RCO
0
25 MHz Osc
OUT
To Connection Matrix Input [29]
DIV /1 /2 /4 /8
IO14 Ext. Clock
Divider
1
Ext. Clk Sel register [1357]
Figure 61: 25 MHz RC OSC Block Diagram
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GreenPAK Programmable Mixed-Signal Matrix
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13.3 OSCILLATORS POWER-ON DELAY
OSC enable
Power-On
Delay
CLK
Figure 62: Oscillator Startup Diagram
Note 1: OSC power mode: “Auto Power-On”.
Note 2: “OSC enable” signal appears when any macrocell that uses OSC is powered on.
450
NormalꢀStartͲUpꢀMode
FastꢀStartͲUpꢀMode
400
350
300
250
200
150
VDDꢀ(V)
Figure 63: Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 2 MHz
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GreenPAK Programmable Mixed-Signal Matrix
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25
20
15
10
5
NormalꢀStartͲUpꢀMode
FastꢀStartͲUpꢀMode
0
VDDꢀ(V)
Figure 64: Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 25 kHz
90
80
70
60
50
40
30
20
VDDꢀ(V)
Figure 65: Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC1 = 25 MHz
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13.4 OSCILLATORS ACCURACY
Note: OSC power setting: Force Power-On; Clock to matrix input - enable; Bandgap: turn on by register - enable.
Note: For more information see Section 3.6.
2.2
2.15
2.1
2.05
2
1.95
Fmax @ VDD=1.8 V
1.9
Fmin @ VDD=1.8 V
Fmax @ VDD=3.3 V
1.85
Fmin @ VDD=3.3 V
Fmax @ VDD=5.0 V
Fmin @ VDD=5.0 V
1.8
1.75
T (°C)
Figure 66: Oscillator Frequency vs. Temperature, OSC0 = 2 MHz
27
Fmax @ VDD=1.8 V
Fmin @ VDD=1.8 V
Fmax @ VDD=3.3 V
26.5
Fmin @ VDD=3.3 V
26
25.5
25
Fmax @ VDD=5.0 V
Fmin @ VDD=5.0 V
24.5
24
23.5
T (°C)
Figure 67: Oscillator Frequency vs. Temperature, OSC0 = 25 kHz
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GreenPAK Programmable Mixed-Signal Matrix
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31
29
27
25
23
21
19
17
Fmax @ VDD=1.8 V
Fmin @ VDD=1.8 V
Fmax @ VDD=3.3 V
Fmin @ VDD=3.3 V
Fmax @ VDD=5.0 V
Fmin @ VDD=5.0 V
T (°C)
Figure 68: Oscillator Frequency vs. Temperature, OSC1 = 25 MHz
Note: 25 MHz RC OSC1 performance is not guaranteed at VDD < 2.5 V.
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14 Crystal Oscillator
The Crystal OSC provides high precision and stability of the output frequency. IO14 and IO13 are input and output, respectively,
of an inverting amplifier which is configured for use as an On-chip Oscillator, as shown in Figure 70. Either a quartz crystal or a
ceramic resonator may be used. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of
stray capacitance, and the electromagnetic noise of the environment. Refer to Table 93. For ceramic resonators, the capacitor
values given by the manufacturer should be used. It is possible to use an external clock source, it must be connected to IO14. In
this case no external components are required.
OSC Power Mode register [1136]
Disable
0
Enable
1
From Connection Matrix Output [109]
PWR DOWN
IO14
OUT
Crystal OSC
To Connection Matrix Input [53]
IO13
Figure 69: Crystal OSC Block Diagram
C1
SLG46517
IO14
R1
Crystal
IO13
R2
C2
Figure 70: External Crystal Connection
Table 93: External Components Selection
f
C1
C2
R1
R2
20 kΩ
0 Ω
32.768 kHz
4 - 40 MHz
10 pF
12 pF
330 pF
12 pF
20 MΩ
1 MΩ
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GreenPAK Programmable Mixed-Signal Matrix
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15 Power-On Reset
The SLG46517 has a Power-On Reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in
the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first
ramping to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined
sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of
the IO pins.
15.1 GENERAL OPERATION
To start the POR sequence in the SLG46517, the voltage applied on the VDD should be higher than the Power-On threshold
(Note). The full operational VDD range for the SLG46517 is 1.71 V to 5.5 V (1.8 V ±5% to 5 V±10%). This means that the VDD
voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises
to the Power-On threshold. After the POR sequence has started, the SLG46517 will have a typical period of time to go through
all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after the POR
sequence is complete.
Note: The Power-On threshold can vary by PVT, but typically it is 1.6 V.
The SLG46517 is guaranteed to be powered down and nonoperational when the VDD voltage (voltage on VDD) is less than 0.6V,
but not less than -0.6 V. Another essential condition for the chip to be powered down is that no voltage higher (Note) than the VDD
voltage is applied to any other PIN. For example, if VDD voltage is 0.3 V, applying a voltage higher than 0.3 V to any other PIN is
incorrect, and can lead to incorrect or unexpected device behavior.
Note: There is a 0.6V margin due to forward drop voltage of the ESD protection diodes.
To power-down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down it
should be less than 0.6 V.
All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step
in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin
configuration at this point in time is defined by the design programmed into the chip. Also, as it was mentioned before the voltage
on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
15.2 POR SEQUENCE
The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 71.
VDD
t
t
t
t
t
t
t
t
POR_NVM
(reset for NVM)
NVM_ready_out,
I2C enable
POR_GPI
(reset for input enable)
POR_LUT
(reset for LUT output)
POR_CORE
(reset for DLY/RCO/DFF
/LATCH/Pipe DLY)
POR_OUT
(generate low to high to matrix)
POR_GPO
ASM enable
(reset for output enable)
Input: Ignore transition
Output: Initial state (determined by
registers [1354:1352])
Figure 71: POR Sequence
As can be seen from Figure 71 after the VDD has start ramping up and crosses the Power-On threshold, first, the on-chip NVM
memory is reset. Next, the chip reads the data from NVM, and transfers this information to a CMOS LATCH that serves to configure
each macrocell, and the Connection Matrix which routes signals between macrocells. The third stage causes the reset of the input
pins, and then to enable them. After that, the LUTs are reset and become active. After LUTs the Delay cells, RC OSC, DFFs,
LATCHES, and Pipe Delay are initialized. Only after all macrocells are initialized internal POR signal (POR macrocell output) goes
from LOW to HIGH. The last portion of the device to be initialized are the output pins, which transition from high impedance to
active at this point.
The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many
environmental factors, such as: slew rate, VDD value, temperature, and even will vary from chip to chip (process influence).
15.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE
To have a full picture of SLG46517 operation during powering and POR sequence, review the overview the macrocell output
states during the POR sequence (Figure 72 describes the output signals states).
First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output PINs which are in high
impedance state). Before the NVM is ready, all macrocell outputs are unpredictable (except the output PINs). On the next step,
some of the macrocells start initialization: input pins output state becomes LOW; LUTs also output LOW. Only P_DLY macrocell
configured as edge detector becomes active at this time. After that input PINs are enabled. Next, only LUTs are configured. Next,
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
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all other macrocells are initialized. After macrocells are initialized, internal POR matrix signal switches from LOW to HIGH. The
last are output PINs that become active and determined by the input signals.
VDD
Guaranteed HIGH before POR_GPI
Unpredictable
t
VDD_out
to matrix
t
t
Input PIN_out
to matrix
Unpredictable
Unpredictable
Unpredictable
Determined by External Signal
Determined by Input signals
LUT_out
to matrix
Determined by input signals
OUT = IN without Delay
t
t
t
t
t
t
t
Programmable Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
Prog. Edge_Detector_out
to matrix
Unpredictable
Unpredictable
Unpredictable
Determined by Input signals
Determined by initial state
DFF/LATCH_out
to matrix
Determined by Input signals
Determined by input signals
OUT = IN without Delay
Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
POR_out
to matrix
Unpredictable
Ext. GPO
Tri-state
Determined by Input signals
Output State Unpredictable
Figure 72: Internal Macrocell States during POR Sequence
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15.3.1 Initialization
All internal macrocells by default have initial LOW level. Starting from indicated power-up time of 1.15 V to1.6 V, macrocells in
GPAK are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then the
reset signal is released for internal macrocells and they start to initialize according to the following sequence:
1. I2C.
2. Input PINs, ACMP, Pull-up/down.
3. LUTs.
4. DFFs, Delays/Counters, Pipe Delay.
5. POR output to matrix.
6. Output PIN corresponds to the internal logic.
The Vref output pin driving signal can precede POR output signal going high by 3 μs - 5 μs. The POR signal going high indicates
the mentioned power-up sequence is complete.
Note: The maximum voltage applied to any PIN should not be higher than the VDD level. There are ESD Diodes between
PIN → VDD and PIN → GND on each PIN. So, if the input signal applied to PIN is higher than VDD, then current will sink through
the diode to VDD. Exceeding VDD results in leakage current on the input PIN, and VDD will be pulled up, following the voltage on
the input PIN.There is no effect from input pin when input voltage is applied at the same time as VDD
.
15.3.2 Power-Down
V
(V)
DD
2 V
1.6 V
1.15 V
1 V Vref Out Signal
1 V
Time
Outputs can possibly switch state during this time
Figure 73: Power-Down
During power-down, macrocells in SLG46517 are powered off and logic macrocells may switch states after falling below 1.4 V.
The IO buffers are disabled when POR goes low at VDD ~1 V. Please note that during a slow rampdown, outputs can possibly
switch state during this time.
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16 Asynchronous State Machine Macrocell
16.1 ASM MACROCELL OVERVIEW
The Asynchronous State Machine (ASM) macrocell is designed to allow the user to create state machines with between 2 to 8
states. The user has flexibility to define the available states, the available state transitions, and the input signals (a, b, c …) that
will cause transitions from one state to another state, as shown in Figure 74.
This macrocell has a total of 25 inputs, as shown in Figure 75, which come from the Connection Matrix outputs. Of these 25 inputs,
24 are user selectable for driving general state transitions, and 1 is for driving a state transition to an Initial/Reset state. Each of
the 24 inputs is level sensitive and active high, meaning that a high level input will drive the user selected transition from one state
to another. The fact that there are 24 inputs puts the upper bound of 24 possible state transitions total in the user defined state
machine design. There is on nReset input which will drive an immediate state transition to the user-defined Initial/Reset state
when active, shown in red, in the Figure 74. For more details refer to Section 16.2.
There are a total of 8 outputs, which go to the Connections Matrix inputs, and from there can be routed to other internal macrocells
or pins. The 8 outputs are user defined for each of the possible 8 states. This information is held in the Connection Matrix Output
RAM. For more details refer to Section 16.3.
In using this macrocell, the user must take into consideration the critical timing required on all input and output signals. The timing
waveforms and timing specifications for this macrocell are all measured relative to the input signals (which come into the macrocell
on the Connection Matrix outputs) and on the outputs from the macrocell (which are direct connections to Connection Matrix
inputs). The user must consider any delays from other logic and internal chip connections, including IO delays, to ensure that
signals are properly processed, and state transitions are deterministic.
The GPAK Designer development tools support user designs for the ASM macrocell at both the physical level and logic level.
Figure 74 is a representation of the user design at the logical level, and Figure 75 shows the physical resources inside the
macrocell. To best utilize this macrocell, the user must develop a logical representation of their desired state machine, as well as
a physical mapping of the input and outputs required for the desired functionality.
Off
a
d
c
Normal
Speed
Standby
Fault
b
e
f
g
h
High
Speed
Figure 74: Asynchronous State Machine State Transitions
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
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Connection Matrix
Output RAM
(8x8)
State Holding
LATCHES
State 0
State 0 In
State 1 In
State 2 In
State 3 In
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
Output Bits (8)
State 1
Output Bits (8)
State 2
Output Bits (8)
State 3
Output Bits (8)
from
Connection
Matrix
State
Transition
Signal
State 4
Output Bits (8)
State 4 In
State 5 In
State 6 In
Routing
State 5
Output Bits (8)
State 6
Output Bits (8)
State 7
Output Bits (8)
State 7 In
nReset
to Connection Matrix
Figure 75: Asynchronous State Machine
16.2 ASM INPUTS
The ASM macrocell has a total of 25 inputs which come from the Connection Matrix outputs. Of these 25 inputs, 24 are user
selectable for driving general state transitions, and 1 is for driving a state transition to an Initial/Reset state.
There are a total of 24 inputs to the ASM macrocell for general state transitions, highlighted in red in Figure 76. Each of these
inputs is level sensitive, and active high. A high level input will trigger a state transition.
These inputs are grouped so that each set of 3 inputs can drive a state transition going into a particular state. As an example,
there are three inputs that can drive a state transition to State 1. This sets an upper bound on the number of transitions that the
user can select going into a particular state to be 3, shown in Figure 77.
There is no limitation on the number of transitions that can be supported coming out of a particular state, the user can select to
have transitions going from a state to all other states, shown in Figure 78.
The ASM macrocell also has a nReset input highlighted in blue in Figure 76. This input is level sensitive and active low. An
active signal on this input will drive an immediate state transition to the user-defined Initial/Reset state. The user can choose
which state within the ASM Editor inside GPAK Designer is the initial state.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Connection Matrix
Output RAM
(8x8)
State Holding
LATCHES
State 0
State 0 In
State 1 In
State 2 In
State 3 In
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
Output Bits (8)
State 1
Output Bits (8)
State 2
Output Bits (8)
State 3
Output Bits (8)
from
Connection
Matrix
State
Transition
Signal
State 4
Output Bits (8)
State 4 In
State 5 In
State 6 In
Routing
State 5
Output Bits (8)
State 6
Output Bits (8)
State 7
Output Bits (8)
State 7 In
nReset
to Connection Matrix
Figure 76: Asynchronous State Machine Inputs
State 1
State 0
State 3
State 2
Figure 77: Maximum 3 State Transitions into Given State
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GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
State 1
State 7
State 2
State 0
State 6
State 3
State5
State 4
Figure 78: Maximum 7 State Transitions out of a Given State
16.3 ASM OUTPUTS
There are a total of 8 outputs from the ASM macrocell, which go to the Connections Matrix inputs, and from there can be routed
to other internal macrocells or pins. The 8 outputs are user defined for each of the possible 8 states, this information is held in
the Connection Matrix Output RAM, shown in Figure 79. The Connection Matrix Output RAM has a total of 64 bits, arranged as
8 bits per state. The values loaded in each of the 8 bits define the signal level on each of the 8 ASM macrocell outputs.
The ASM Editor inside the GPAK Designer software allows the user to make their selections for the value of each bit in the
Connection Matrix Output RAM, which selects the level of the macrocell outputs based on the current state of the ASM
macrocell, as shown in Figure 78.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Connection Matrix
Output RAM
(8x8)
State Holding
LATCHES
State 0
State 0 In
State 1 In
State 2 In
State 3 In
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
Output Bits (8)
State 1
Output Bits (8)
State 2
Output Bits (8)
State 3
Output Bits (8)
from
Connection
Matrix
State
Transition
Signal
State 4
Output Bits (8)
State 4 In
State 5 In
State 6 In
Routing
State 5
Output Bits (8)
State 6
Output Bits (8)
State 7
Output Bits (8)
State 7 In
nReset
to Connection Matrix
Figure 79: Connection Matrix Output RAM
Table 94: ASM Editor - Connection Matrix Output RAM
RAM
Connection Matrix Output RAM
State name
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
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GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
There is a possibility to configure ASM (it's settings and transitions) via I2C. Registers (registers [197:0]) correspond for ASM
inputs, registers (registers [1727:1664]) correspond for ASM outputs configuration. Using I2C commands (see Section 17.4) it is
possible to read ASM settings and connections, as well as change them. Additionally, user can change Connection Matrix Output
RAM bit configuration (bytes 0xD0 to 0xD7).
Note: After Connection Matrix Output RAM was updated via I2C, ASM outputs to Connection Matrix can be changed only after
ASM changes its state or after reset event. To change ASM outputs to Connection Matrix instantly after I2C write command, ASM
must be in reset all the time.
16.4 BASIC ASM TIMING
The basic state transition timing from input on Matrix Connection output to output on Matrix Connection input is shown
in Figure 80 and Figure 81. The time from a valid input signal to the time that there is a valid change of state and valid signals
being available on the state outputs is State Machine Output Delay Time (Tst_out_delay). The minimum and maximum values of
Tst_out_delay define the differential timing between the shortest state transition (input on matrix output and output on matrix input)
and the longest state transition (input on matrix output and output on matrix input).
a
State 0
State 1
Figure 80: State Transition
Input
Signal (a)
Tst_out_delay
State
Outputs
State 0
State 1
Figure 81: State Transition Timing
16.5 ASYNCHRONOUS STATE MACHINES VS. SYNCHRONOUS STATE MACHINES
It is important to note that this macrocell is designed for asynchronous operation, which means the following:
1. No clock source is needed, it reacts only to input signals.
2. The input signals do not have to be synchronized to each other, the macrocell will react to the earliest valid signal for state
transition.
3. This macrocell does not have traditional set-up and hold time specifications which are related to incoming clock, as this
macrocell has no clock source.
4. The macrocell only consumes power while in state transition.
16.6 ASM POWER CONSIDERATIONS
A benefit of the asynchronous nature of this macrocell is that it will consume power only during state transitions. Shown in
Figure 80 and Figure 82 below, the current consumption of the macrocell will be a fraction of a µA between state transitions, and
will rise only during state transitions. See Section 3.4 to find average current during state transitions.
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GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
a
State 0
State 1
Figure 82: State Transition
Input
Signal (a)
Tst_out_delay
State
Outputs
State 0
State 1
Average Active ASM Power
ASM
Power
Consumption
Sub μA Inactive ASM Power Consumption
Figure 83: State Transition Timing and Power Consumption
16.7 ASM LOGICAL VS. PHYSICAL DESIGN
A successful design with the ASM macrocell must include both the logic level design, as well as the physical level design. The
GPAK Designer development software support user designs for the ASM macrocell at both the logic level and physical level.
The logic level design of the user defined state machine takes place inside the ASM Editor. In the ASM Editor, the user can
select and name states, define and name allowed state transitions, define the Initial/Reset state, and define the output values for
the 8 outputs in the Output RAM Matrix. The physical level design takes place in the general GPAK Designer window, and here
the user makes connections for the sources for ASM input signals, as well as making connections for destinations for ASM
output signals.
16.8 ASM SPECIAL CASE TIMING CONSIDERATIONS
16.8.1 State Transition Pulse Input Timing
All inputs to the ASM macrocell are level sensitive. If the input to the state machine macrocell for a state transition is a pulse,
there is a minimum pulse width on the input to the state machine macrocell (as measured at the matrix input to the macrocell)
which is guaranteed to result in a state transition shown in Figure 84 and Figure 85. This pulse width is defined by the State
Machine Input Pulse Acceptance Time (Tst_pulse). If a pulse width that is shorter than Tst_pulse is input to the state machine
macrocell, it is indeterminate whether the state transition will happen or not. If a pulse that is rejected (invalid due to the pulse
width being narrower than the guaranteed minimum of Tst_pulse), this will not stop a valid pulse on another state transition input
that does meet minimum pulse width.
a
State 0
State 1
Figure 84: State Transition
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GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Input
Signal (a)
Tst_pulse
Tst_pulse
State
Outputs
State 0
State 1
Tst_out_delay
Figure 85: State Transition Pulse Input Timing
16.8.2 State Transition Competing Input Timing
There will be situations where two input signals can be valid inputs that will drive two different state transitions from a given state.
In that sense, the two signals are “competing” (signals a and b in Figure 86), and the signal that arrives sooner should drive the
state transition that will “win”, or drive the state transition. If one signal arrives Tst_comp before the other one, it is guaranteed to
win, and the state transition that it codes for will be taken, as shown in Figure 87. If the two signals arrive within Tst_comp of each
other, it will be indeterminate which state transition will win, but one of the transitions will take place as long as the winning signal
satisfies the pulse width criteria described in the paragraph above, as shown in Figure 88.
a
b
State 0
State 1
State 2
Figure 86: State Transition - Competing Inputs
Input
Signal (a)
Tst_comp
Input
Signal (b)
Tst_out_delay
State
Outputs
State 0
State 1 or State 2
Figure 87: State Transition Timing - Competing Inputs Indeterminate
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GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Input
Signal (a)
Tst_comp
Input
Signal (b)
Tst_out_delay
State
Outputs
State 0
State 1
Figure 88: State Transition Timing - Competing Inputs Determinable
16.8.3 ASM State Transition Sequential Timing
It is possible to have a valid input signal for a transition out from a particular state be active before the state is active. If this is the
case, the macrocell will only stay in that particular state for Tst_out_delay time before making the transition to the next state. An
example of this sequential behavior is shown in Figure 89 and the associated timing is shown in Figure 90.
a
b
State 0
State 1
State 2
Figure 89: State Transition - Sequential
Input
Signal (a)
Input
Signal (b)
Tst_out_delay
Tst_out_delay
State
Outputs
State 0
State 1
State 2
Figure 90: State Transition - Sequential Timing
16.8.4 State Transition Closed Cycling
It is possible to have a closed cycle of state transitions that will run continuously if there are valid inputs that are active at the
same time. The rate at which the state transitions will take place is determined by Tst_out_delay. The example shown here in
Figure 91 involves cycling between two states, but any number of two – eight states can be included in state transition closed
cycling of this nature. Figure 92 shows the associated timing for closed cycling.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
a
State 0
State 1
b
Figure 91: State Transition - Closed Cycling
Input
Signal (a)
Input
Signal (b)
Tst_out_delay
Tst_out_delay
Tst_out_delay
State
Outputs
State 0
State 1
State 0
State 1
Figure 92: State Transition - Closed Cycling Timing
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
2
17 I C Serial Communications Macrocell
17.1 I2C SERIAL COMMUNICATIONS MACROCELL OVERVIEW
In the standard use case for the GreenPAK devices, the configuration choices made by the user are stored as bit settings in the
Non-Volatile Memory (NVM), and this information is transferred at startup time to volatile RAM registers that enable the
configuration of the macrocells. Other RAM registers in the device are responsible for setting the connections in the Connection
Matrix to route signals in the manner most appropriate for the user’s application.
The I2C Serial Communications Macrocell in this device allows an I2C bus Master to read and write this information via a serial
channel directly to the RAM registers, allowing the remote re-configuration of macrocells, and remote changes to signal chains
within the device.
An I2C bus Master is also able read and write other register bits that are not associated with NVM memory. As an example, the
input lines to the Connection Matrix can be read as digital register bits. These are the signal outputs of each of the macrocells in
the device, giving an I2C bus Master the capability to remotely read the current value of any macrocell.
The user has the flexibility to control read access and write access via registers bits register [1832], register [1870], and
register [1871]. See Section 17.5 for more details on I2C read/write memory protection.
Note: GreenPAK I2C is fully compatible with standard I2C protocol.
17.2 I2C SERIAL COMMUNICATIONS DEVICE ADDRESSING
Each command to the I2C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are
shown in Figure 93. After the Start bit, the first four bits are a control code, which can be set by the user in registers [1867:1864].
This gives the user flexibility on the chip level addressing of this device and other devices on the same I2C bus. The Block Address
is the next three bits (A10,A9, A8), which will define the most significant bits in the addressing of the data to be read or written by
the command. The last bit in the Control Byte is the R/W bit, which selects whether a read command or write command is
requested, with a “1” selecting for a Read command, and a “0” selecting for a Write command. This Control Byte will be followed
by an Acknowledge bit (ACK), which is sent by this device to indicate successful communication of the Control Byte data.
In the I2C-bus specification and user manual, there are two groups of eight addresses (0000 xxx and 1111 xxx) that are reserved
for the special functions, such as a system General Call address. If the user of this device choses to set the Control Code to either
“1111” or “0000” in a system with other slave device, please consult the I2C-bus specification and user manual to understand the
addressing and implementation of these special functions, to ensure reliable operation.
In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of
information, resulting in a total address space of 2K bytes. Of this 2K byte address space, the valid addresses accessible to the
I2C Macrocell on the SLG46517 are in the range from 0 (0x00) to 255 (0xFF). The MSB address bits (A10, A9, and A8) will be
“0” for all commands to the SLG46517.
With the exception of the Current Address Read command, all commands will have the Control Byte followed by the Word
Address. Figure 93 shows this basic command structure.
Start
bit
Acknowledge
bit
Control Byte
Word Address
A
10
A
9
A
8
A
7
A
0
S
X
X
X
X
R/W ACK
Control
Code
Block
Address
Not used, set to 0
Read/Write bit
(1 = Read, 0 = Write)
Figure 93: Basic Command Structure
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
17.3 I2C SERIAL GENERAL TIMING
General timing characteristics for the I2C Serial Communications macrocell are shown in Figure 94. Timing specifications can be
found in the Section 3.4.
tHIGH
tF
tR
tLOW
SCL
tSU STA
tHD DAT
tHD STA
tSU DAT
tSU STO
SDA IN
tBUF
tAA
tDH
SDA OUT
Figure 94: I2C General Timing Characteristics
17.4 I2C SERIAL COMMUNICATIONS COMMANDS
17.4.1 Byte Write Command
Following the Start condition from the Master, the Control Code [4 bits], the Block Address [3 bits], and the R/W bit (set to “0”),
are placed onto the I2C bus by the Master. After the SLG46517 sends an Acknowledge bit (ACK), the next byte transmitted by
the Master is the Word Address. The Block Address (A10, A9, A8), combined with the Word Address (A7 through A0), together
set the internal address pointer in the SLG46517, where the data byte is to be written. After the SLG46517 sends another
Acknowledge bit, the Master will transmit the data byte to be written into the addressed memory location. The SLG46517 again
provides an Acknowledge bit and then the Master generates a Stop condition. The internal write cycle for the data will take place
at the time that the SLG46517 generates the Acknowledge bit.
Acknowledge
bit
Acknowledge
bit
Start
bit
Acknowledge
bit
Bus Activity
Control Byte
Word Address
Data
A
10
A
9
A
8
A
7
A
0
D
7
D
0
S
X
X
X
X
W
ACK
ACK
ACK
SDA LINE
P
Control
Code
Block
Address
Stop
bit
Not used, set
to 0
R/W bit = 0
Figure 95: Byte Write Command, R/W = 0
17.4.2 Sequential Write Command
The write Control Byte, Word Address, and the first data byte are transmitted to the SLG46517 in the same way as in a Byte Write
command. However, instead of generating a Stop condition, the Bus Master continues to transmit data bytes to the SLG46517.
Each subsequent data byte will increment the internal address counter, and will be written into the next higher byte in the command
addressing. As in the case of the Byte Write command, the internal write cycle will take place at the time that the SLG46517
generates the Acknowledge bit.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Acknowledge
bit
Data (n + x)
Acknowledge
Start
bit
bit
Bus Activity
SDA LINE
Not used, s
Data (n + 1)
Control Byte
Word Address (n)
Data (n)
A
10
A
8
A
9
ACK
ACK
P
S
X
X
X
X
W
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
et to 0
Write bit
Figure 96: Sequential Write Command
17.4.3 Current Address Read Command
The Current Address Read Command reads from the current pointer address location. The address pointer is incremented at the
first STOP bit following any write control byte. For example, if a Sequential Read command (which contains a write control byte)
reads data up to address n, the address pointer would get incremented to n + 1 upon the STOP of that command. Subsequently,
a Current Address Read that follows would start reading data at n + 1. The Current Address Read Command contains the Control
Byte sent by the Master, with the R/W bit = “1”. The SLG46517 will issue an Acknowledge bit, and then transmit eight data bits
for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition.
Start
bit
Acknowledge
bit
Stop
bit
Bus Activity
Control Byte
Data (n)
A
10
A
9
A
8
S
X
X
X
X
R
ACK
SDA LINE
P
Control
Code
Block
Address
No Ack
bit
Not used, se
t to 0
R/W bit = 1
Figure 97: Current Address Read Command, R/W = 1
17.4.4 Random Read Command
The Random Read command starts with a Control Byte (with R/W bit set to “0”, indicating a write command) and Word Address
to set the internal byte address, followed by a Start bit, and then the Control Byte for the read (exactly the same as the Byte Write
command). The Start bit in the middle of the command will halt the decoding of a Write command, but will set the internal address
counter in preparation for the second half of the command. After the Start bit, the Bus Master issues a second control byte with
the R/W bit set to “1”, after which the SLG46517 issues an Acknowledge bit, followed by the requested eight data bits.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Acknowledge
Stop
bit
Start
bit
bit
Bus Activity
Data (n)
Control Byte
Word Address (n)
Control Byte
A
10
A
9
A
8
A
10
A
9
A
8
S
ACK
X
X
X
X
R ACK
P
SDA LINE
S
X
X
X
X
W
ACK
Control
Code
Block
Address
Control
Code
Block
Address
No Ack
bit
Not used, set to 0
Write bit
Read bit
Figure 98: Random Read Command
17.4.5 Sequential Read Command
The Sequential Read command is initiated in the same way as a Random Read command, except that once the SLG46517
transmits the first data byte, the Bus Master issues an Acknowledge bit as opposed to a Stop condition in a random read. The
Bus Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition.
Acknowledge
Start
bit
bit
Bus Activity
Data (n + 2)
Data (n + x)
Control Byte
Data (n)
Data (n + 1)
A
8
A
10
A
9
ACK
P
SDA LINE
S
X
X
X
X
R
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
No Ack
bit
Read bit
Figure 99: Sequential Read Command
17.4.6 I2C Serial Command Address Space
In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of
information, resulting in a total address space of 2K bytes. Of this 2K byte address space, the valid addresses accessible to the
I2C Macrocell on the SLG46517 are in the range from 0 (0x00) to 255 (0xFF). The MSB address bits (A10, A9, and A8) will be
“0” for all commands to the SLG46517.
17.4.7 I2C Serial Command Register Map
These register addresses are broken down into four Banks to give the user greater control on access to reading and writing
information in each bank. Each of the four banks is 512 bits (64 bytes) in length. Writing information to register bits in these Banks
will change the configuration of the device, resulting in either a change in the interconnection options provided by the Connection
Matrix, or by changing the configuration of individual macrocells. During device use, all register bits can be read or written via I2C,
unless protection bits are set to prevent this.
See Section 20 for detailed information on all register bits.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Byte 255
Bank 3
Bank 2
Bank 1
Bank 0
Byte 192
Byte 191
Byte 128
Byte 127
Byte 64
Byte 63
Byte 0
Figure 100: Register Bank Map
17.5 I2C SERIAL COMMAND REGISTER PROTECTION
The memory space is divided into four banks, each of which has 512bits (64bytes). There are three bits that allow the user to
define rules for reading and writing bits in each of these banks via I2C:
register [1832] I2C lock for read bits [1535:0] (Bank 0/1/2). If the system provides any read commands to the addresses in
these three banks, the device will respond with ‘FFH’ in data field.
register [1871] I2C lock for write bits [1535:0] (Bank 0/1/2). If the system provides any write commands to the addresses in
these three banks, the device will acknowledge these commands, but will not do internal writes to the register space.
register [1870] I2C lock for write all bits (Bank 0/1/2/3). If the system provides any write commands to the addresses in these
four banks, the device will acknowledge these commands, but will not do internal writes to the register space.
Note: register [1870] is higher priority than register [1871], and if register [1870] is set, than register [1871] does not have any
effect.
Note: If the user sets IOs 6 and 7 function to a selection other than SDA and SCL, all access via I2C will be disabled.
If register [1870] is not set, register bits in Bank 3 are open to read and write commands via I2C with the following exceptions:
register [1871] Bank 0/1/2 I2C-write protection bit is always protected from I2C write
registers [1867:1864] I2C Control Code Bit [3:0] is always protected from I2C write
Note: Any write commands that come to the device via I2C that are not blocked, based on the protection bits, will change the
contents of the RAM register bits that mirror the NVM bits. These write commands will not change the NVM bits themselves, and
a POR event will restore the register bits to original programmed contents of the NVM.
See Section 20 for detailed information on all registers.
17.5.1 Register Read/Write Protection
There are six read/write protect modes for the design sequence from being corrupted or copied. See Table 95 for details.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
.
Table 95: Read/Write Protection Options
Lock Status
Locked
for read
bits
<1535:0>
andwrite
all bits
Locked
Locked for read
forwrite andwrite
Locked
for read for write
bits bits
<1535:0> <1535:0>
Locked
Unlocked
Bank
Byte
Bits
Description
all bits
bits
<1535:0>
reg
reg
reg
reg
reg
reg
<1832>=0,
<1871>=0,
<1870>=0
<1832>=1,
<1871>=0,
<1870>=0
<1832>=0,
<1871>=1,
<1870>=0
<1832>=0,
<1871>=x,
<1870>=1
<1832>=1,
<1871>=1,
<1870>=0
<1832>=1,
<1871>=x,
<1870>=1
0
1
0-63
511-0
Connection Matrix
Outputs
Configuration
R/W
R/W
-
W
W
-
R
R
-
R
R
-
-
-
-
-
-
-
64-109
879-512
110-127 880-1023
128-186 1495-1024
Reserved
Function
Configuration for
PINs, LUTs/DFFs,
OSC,ASMandsome
configuration for
DLYs, ACMP
R/W
W
R
R
-
-
2
187-191 1535-1496
192-206 1655-1536
Reserved
-
-
-
-
-
-
CNT/DLY counter
data and some LUTs
truth table, ACMP
Vref
R/W
R/W
R/W
R
R/W
R
I2C reset bit with
reloading NVM into
Data register
1662
R/W
R/W
R/W
R
R/W
R
3
207
1661-1659,
Reserved
R
R
R
R
R
R
R
R
1663
1658-1656 OSC Power Control
R/W
R/W
R/W
R/W
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 95: Read/Write Protection Options (Continued)
Lock Status
Locked
for read
bits
<1535:0>
andwrite
all bits
Locked
Locked for read
forwrite andwrite
Locked
for read for write
bits bits
<1535:0> <1535:0>
Locked
Unlocked
Bank
Byte
Bits
Description
all bits
bits
<1535:0>
reg
reg
reg
reg
reg
reg
<1832>=0,
<1871>=0,
<1870>=0
<1832>=1,
<1871>=0,
<1870>=0
<1832>=0,
<1871>=1,
<1870>=0
<1832>=0,
<1871>=x,
<1870>=1
<1832>=1,
<1871>=1,
<1870>=0
<1832>=1,
<1871>=x,
<1870>=1
ASM output RAM
and User
configurable RAM /
OTP
208-223 1791-1664
224-227 1823-1792
R/W
R/W
R/W
R
R/W
R
Reserved
Reserved
-
-
-
-
-
-
228
1831-1824
R/W
R/W
R/W
R
R/W
R
1839-1836
1835-1834
Product Family ID
Reserved
R
-
R
-
R
-
R
-
R
-
R
-
Reserved
229
1833
R
R
R
R
R
R
I2C Lock for read
bits<1535:0>
1832
R
R/W
R
R
R/W
R
R
R/W
R
R
R
R
R
R/W
R
R
R
R
230
231
1847-1840
1855-1848
Pattern ID
Reserved
Reserved
232
1863-1856
1871
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
3
I2C Lock for write
bits<1535:0>
I2C Lock for write all
bits
1870
233
1869-1868
1867-1864
Reserved
I2C Control Code
-
-
-
-
-
-
R
R
R
R
R
R
Counter Current
Value
234-239 1919-1872
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Macrocells Output
240-243 1951-1920 Values (Connection
Matrix Inputs)
R
R
R
R
Connection Matrix
244
1959-1952
R/W
R
R/W
R
R/W
R
R/W
R
Virtual Inputs
Macrocells Output
245-247 1983-1960 Values (Connection
Matrix Inputs)
Reserved
248-250 2007-1984
R
R
R
R
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 95: Read/Write Protection Options (Continued)
Lock Status
Locked
for read
bits
<1535:0>
andwrite
all bits
Locked
Locked for read
forwrite andwrite
Locked
for read for write
bits bits
<1535:0> <1535:0>
Locked
Unlocked
Bank
Byte
Bits
Description
all bits
bits
<1535:0>
reg
reg
reg
reg
reg
reg
<1832>=0,
<1871>=0,
<1870>=0
<1832>=1,
<1871>=0,
<1870>=0
<1832>=0,
<1871>=1,
<1870>=0
<1832>=0,
<1871>=x,
<1870>=1
<1832>=1,
<1871>=1,
<1870>=0
<1832>=1,
<1871>=x,
<1870>=1
Reserved
Reserved
Reserved
Reserved
251
2015-2008
R/W
R
R/W
R
R/W
R
R
R
R
R
R/W
R
R
R
R
R
252-253 2031-2016
3
254
255
2039-2032
2047-2040
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Allow Read and Write Data
Allow Write Data Only
Allow Read Data Only
W
R
-
The Data is protected for Read and Write
17.5.2 I2C Serial Reset Command
If I2C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including
configuration of all macrocells, and all connections provided by the Connection Matrix. This is implemented by setting
register [1662] I2C reset bit to “1”, which causes the device to re-enable the Power-On Reset (POR) sequence, including the
reload of all register data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has
taken place, the contents of register [1662] will be set to “0” automatically. The timing diagram shown below illustrates the
sequence of events for this reset function.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Acknowledge
bit
Acknowledge
bit
Start
bit
Acknowledge
bit
Bus Activity
Control Byte
Word Address
Data
A
10
A
9
A
8
A
7
A
0
D
7
D
0
S
X
X
X
X
W
ACK
ACK
ACK
SDA LINE
P
Internal Reset bit
Control
Code
Block
Address
Stop
bit
Not used, set to
0
Write bit
by I2C Stop Signal
Reset-bit register output
Internal POR
reloading NVM into Data register
Reset-bit register (register [1662]) is cleared by reloading NVM into Data register
1) I2C write with register [1662] = 1 (I2C reset bit with reloading NVM into Data register)
2) POR go to LOW and reloading NVM into Data register start after “STOP” of I2C
3) POR go to HIGH after reloading NVM into Data register
Figure 101: Reset Command Timing
17.6 I2C ADDITIONAL OPTIONS
17.6.1 Reading Counter Data via I2C
The current count value in three counters in the device can be read via I2C. The counters that have this additional functionality
are 16-bit CNT0, and 8-bit counters CNT2 and CNT4.
17.6.2 User RAM and OTP Memory Array
There are eight bytes of RAM memory that can be read and written remotely by I2C commands. The initial contents of this memory
space can be selected by the user, and this information will be transferred from OTP memory to the RAM memory space during
the power-up sequence. The lowest order byte in this array (User Configurable RAM/OTP Byte 0) is located at I2C address 0xD8,
and the highest order byte in this array is located at I2C address 0xDF.
Table 96: RAM Array Table
I2C Address
(hex)
Highest Bit
Address
Lowest Bit
Address
Memory Byte
D8
D9
DA
DB
DC
DD
DE
1735
1743
1751
1759
1767
1775
1783
1728
1736
1744
1752
1760
1768
1776
User Configurable RAM/OTP Byte 0
User Configurable RAM/OTP Byte 1
User Configurable RAM/OTP Byte 2
User Configurable RAM/OTP Byte 3
User Configurable RAM/OTP Byte 4
User Configurable RAM/OTP Byte 5
User Configurable RAM/OTP Byte 6
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 96: RAM Array Table(Continued)
I2C Address
(hex)
Highest Bit
Address
Lowest Bit
Address
Memory Byte
DF
1791
1784
User Configurable RAM/OTP Byte 7
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
18 External Clocking
The SLG46517 supports several ways to use an external, higher accuracy clock as a reference source for internal operations.
18.1 CRYSTAL MODE
When register [1136] is set to 1, an external crystal can be connected to IOs 13 and 14 for supplying an accurate clock source.
See Section 14. An external clocking signal on IO14 can be used in place of the crystal. The high and low limits for crystal
frequency that can be selected are 32.768 kHz and 40 MHz.
18.2 IO17 OR IO15 SOURCE FOR 25 KHZ/2 MHZ CLOCK
When register [1358] is set to 1, an external clocking signal on IO15 will be routed in place of the internal RC oscillator derived
25 kHz/2 MHz clock source. See Figure 60.
The high and low limits for external frequency that can be selected are 0 MHz and 77 MHz.
18.3 IO14 SOURCE FOR 25 MHZ CLOCK
When register [1357] is set to 1, an external clocking signal on IO14 will be routed in place of the internal RC oscillator derived
25 MHz clock source. See Figure 61. The high and low limits for external frequency that can be selected are 0 MHz and 84 MHz.
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
19 Dual, 2A P-FET Power Switches
19.1 POWER SWITCHES OVERVIEW
The SLG46517 has a dual-channel, 44 mΩ PMOS power switch designed to switch 1.71 to 5.5 V power rails up to 2Aper channel.
Each P-FET Power Switch can be controlled internally via the ONx digital input of the P-FET Power Switch component in
GreenPAK Designer, allowing the user to generate integrated Mixed-Signal control circuits, or externally via PWR_SW_ONx.
Whether controlled externally or internally, a low signal on either ONx or PWR_SW_ONx will close the P-FET Power Switch.
Each P-FET Power Switch need not be used in the same voltage domain as VDD. However, when VIN is not tied to VDD, using a
large pull-up resistor on PWR_SW_ON0 and PWR_SW_ON1 is recommended to prevent current from flowing through the P-FET
Power Switch while the device is not powered.
ILOAD1
ILOAD0
VOUT1
VOUT0
VIN1
VIN0
200 Ω
200 Ω
PWR_SW_ON0
ON0
PWR_SW_ON1
ON1
Control
Selection
Logic
Control
Selection
Logic
SW Open
SW Open
AGND
SW Closed
SW Closed
Figure 102: Dual P-FET Power Switch
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
19.2 DRIVING THE P-FET SWITCH
Gate of P-FET power switch can be driven by either internally generated signal or directly by external source connected to
corresponding PWR_SW_ONx pin. Simplified circuit topologies are illustrated on Figure 103.
PWR
PWR
VINx
VOUTx
D
VINx
VOUTx
D
S
S
Cin
Cin
G
G
PWR_SW_ONx
VDD
PWR_SW_ONx
NC
LOW
HIGH
VDD
VDD
VDD
ON
GND AGND
GND AGND
Figure 103: Typical Circuit Topology for Internal (Left) and External (Right) Drive Modes
Datasheet values for switching times are given for driving the resistive loads. The definitions of rise (tr), fall (tf), and delay times
(td(on) and td(off)) are given on Figure 104. To achieve highest switching performance circuit should be laid off using high speed
PCB layout techniques.
VG
VS
90%
10%
0 V
t
VD
VD(ON)
90%
10%
0 V
td(off)
toff
tf
td(on)
ton
tr
t
Figure 104: Definitions for Rise, Fall and Switching Delay Times
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Typical resistive switching waveforms are given on Figure 106 and Figure 107. Note that fall time is dependent on load current
(see Section 19.4). At low loads turn off process can be delayed, therefore discharge circuit should be provided to reduce load
turn off time in that case.
VD
VINx
VDD
VOUTx
PWR
Cin
VG
RL
PWR_SW_ONx
GPIOx
ON
GND AGND
Figure 105: Test Circuit for Typical Switching Waveforms
ON
V
V
G
D
Time (0.2 ȝs/div)
Figure 106: Typical Switching Waveforms (Internal Drive, Resistive Load, RL = 100 Ω, VDD = VIN = 5.5 V)
ON
V
V
G
D
Time (0.2 ȝs/div)
Figure 107: Typical Switching Waveforms (Internal Drive, Resistive Load, RL = 100 Ω, VDD = VIN = 1.71 V)
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
19.3 POWER DISSIPATION
The junction temperature of the Power Switch depends on factors such as board layout, ambient temperature, external air flow
over the package, load current, and the RDSON-generated voltage drop across each power MOSFET. While the primary
contributor to the increase in the junction temperature of the Power Switch is the power dissipation of its power MOSFETs, its
power dissipation and the junction temperature in nominal operating mode can be calculated using the following equations:
2
PDTOTAL = (RDSON0 x IOUT02) + (RDSON1 x IOUT1
)
where:
PDTOTAL = Total package power dissipation, in Watts (W)
RDSON = Channel 0 and Channel 1 Power MOSFET ON resistance, in Ohms (Ω), respectively
IOUT = Channel 0 and Channel 1 Output current, in Amps (A), respectively
and
TJ = PDTOTAL x ΘJA + TA
where:
TJ = Die junction temperature, in Celsius degrees (°C)
ΘJA = Package thermal resistance, in Celsius degrees per Watt (°C/W) – highly dependent on pcb layout
TA = Ambient temperature, in Celsius degrees (°C)
In nominal operating mode, the Power Switch power dissipation can also be calculated by taking into account the voltage drop
across each switch (VINx-VOUTx) and the magnitude of that channel’s output current (IOUTx):
PDTOTAL = [(VIN0-VOUT0) x IOUT0] + [(VIN1-VOUT1) x IOUT1] or
PDTOTAL = [(VIN0 – (RLOAD0 x IOUT0)) x IOUT0] + [(VIN1 – (RLOAD1 x IOU1)) x IOUT1
]
where:
PDTOTAL = Total package power dissipation, in Watts (W)
VIN = Channel 0 and Channel 1 Input Voltage, in Volts (V), respectively
RLOAD = Channel 0 and Channel 1 Output Load Resistance, in Ohms (Ω), respectively
IOUT = Channel 0 and Channel 1 output current, in Amps (A), respectively
VOUT = Channel 0 and Channel 1 output voltage, or RLOAD x IOUT, respectively
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
1.5
1.25
1
0.75
Mounted on 27.4mm x 30.1 mm PCB
(1.6 mm thick, 1 oz copper, FR-4 material)
0.5
-40
-20
0
20
TA, Ambient temperature (°C)
Figure 108: Power Dissipation Derating Curve
40
60
80
100
19.4 POWER SWITCH TYPICAL PERFORMANCE
TA = 25 °C, VDD = 5.5 V, unless otherwise noted.
-5.00
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
VGS = -5.5 V
Pulse Test
Common Source
VDS = -5.5 V
-4.50
-4.00
-3.50
VGS= -1.8 V
VGS = -1.71V
-3.00
-2.50
Pulse Test
Common Source
-2.00
From left to right:
-1.50
-1.00
-0.50
0.00
VGS = -5.5 V
VGS = -3.3 V
VGS = -2.5 V
VGS = -2.0 V
VGS= -2.5 V
VGS= -3.3 V
V
GS = -1.8 V
VGS = -1.71 V
VGS= -5.5 V
0
-1
-2
-3
-4
-5
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
ID, Drain current (A)
VDS, Drain-source voltage (V)
Figure 110: Drain-Source On-Resistance vs. Drain
Current
Figure 109: Typical Output Characteristics
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
0.15
0.13
0.11
0.09
0.07
0.05
0.03
0.15
Pulse Test
Pulse Test
Common Source
ID = -1 A
Common Source
0.13
0.11
0.09
0.07
0.05
0.03
VDS = 5.5 V
-0,5A / -1.8V
-1A / -2.5V
VDS = -5.5 V
-1,5A / -3.3V
-2A / -5.5V
TA = +85°C
TA = +25°C
TA = -40°C
-1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5
VGS, Gate-Source voltage (V)
-40 -20
0
20
40
60
80 100 120 140
TA, Ambient temperature (°C)
Figure 112: Gate-Source On-Resistance Gate-Source
Voltage
Figure 111: Typical Drain-Source On-Resistance vs.
Ambient Temperature
10.00
-5
Pulse Test
Pulse Test
Common Source
-4.5
Common Source
VDS = - 5.5 V
VDS = -5.5 V
-4
-3.5
1.00
0.10
0.01
TA
= +125°C
-3
-2.5
-2
TA = +85°C
TA = +25°C
TA = -40°C
-1.5
-1
-0.5
0
-0.5
-1.0
-1.5
-2.0
0.001
0.01
0.1
1
10
VGS, Gate-source voltage (V)
-ID, Drain current (A)
Figure 113: Drain Current vs. Gate-Source Voltage
Figure 114: Typical Forward Transconductance
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
-0.75
-0.7
10.00
VGS = VDS
ID = -1 mA
Pulse Test
Common Source
VGS = 0V
-0.65
-0.6
1.00
0.10
-0.55
-0.5
-0.45
-0.4
TA = +125°C +85°C
+25°C
-40°C
-40 -20
0
20
40
60
80 100 120 140
0.01
0.4
0.6
0.8
1.0
TA, Ambient temperature (°C)
VDSF, Body diode forward voltage (V)
Figure 115: Typical Drain-Source Diode Forward Voltage
Figure 116: Gate Threshold Voltage vs Ambient
Temperature
10000
10
VGS = 5.5 V
TA
= +125°C
V
DS = 0 V
1000
100
10
1
0.1
TA = +85°C
TA = +25°C
TA = -40°C
0.01
1
0.001
0.0001
VGS = 0 V
0.1
-40 -20
0
20
40
60
80 100 120 140
0.0
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
TA, Ambient temperature (°C)
VDS, Drain-source voltage (V)
Figure 117: Zero Gate Voltage Drain Current
Figure 118: Gate-Body Leakage vs. Ambient
Temperature
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
10000
10000
1000
100
Common Source
tf
Common Source
VDD = 5.5V
VDD = 1.71V
tf
V
DS = -1.71V
VDS = -5.5V
Internal Drive
Internal Drive
1000
100
10
td(off)
td(on)
td(off)
td(on)
tr
tr
10
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
-ID, Drain current (A)
-ID, Drain current (A)
Figure 120: Typical Switching Time (Internal Gate Drive)
at VDS = 5.5 V
Figure 119: Typical Switching Time (Internal Gate Drive)
at VDS = 1.71 V
-5.5
Common Source
Pulse Test
VDS = -5.5 V
-4.5
ID =2 A
ID =0.1 A
-3.5
-2.5
-1.5
-0.5
0.0
0.5
1.0
1.5
Time (0.1μs/div)
QG, Gate charge (nC)
Figure 122: Typical Gate Charge vs. Gate-Source
Voltage
Figure 121: Typical Gate Input Waveform, Internal Gate
Drive Source (Switching Time Test)
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
250
Ciss
200
Coss
150
100
Crss
50
VGS = 0 V
f = 1 MHz
excluding RG
0
0.0
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
VDS, Drain-source voltage (V)
Figure 123: Typical Capacitance vs. Drain-Source
Voltage
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SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
20 Register Definitions
20.1 REGISTER MAP
Table 97: Register Map
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
Note: For register [0] to register [1495], I2C Read is valid (assuming register [1832] = 0), I2C Write is valid (assuming
register [1871] = 0)
Matrix 64-to-1 MUX's 6 selection bits
5:0
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
ASM-state0-EN0
ASM-state0-EN1
ASM-state0-EN2
ASM-state1-EN0
ASM-state1-EN1
ASM-state1-EN2
ASM-state2-EN0
ASM-state2-EN1
ASM-state2-EN2
ASM-state3-EN0
ASM-state3-EN1
ASM-state3-EN2
ASM-state4-EN0
ASM-state4-EN1
ASM-state4-EN2
ASM-state5-EN0
ASM-state5-EN1
ASM-state5-EN2
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
7:6
13:8
15:14
21:16
23:22
29:24
31:30
37:32
39:38
45:40
47:46
53:48
55:54
61:56
63:62
69:64
71:70
77:72
79:78
85:80
87:86
93:88
95:94
101:96
103:102
109:104
111:110
117:112
119:118
125:120
127:126
133:128
135:134
141:136
143:142
Datasheet
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CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Signal Function
Byte Register Bit
Register Bit Definition
Read Write
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
149:144
151:150
157:152
159:158
165:160
167:166
173:168
175:174
181:176
183:182
189:184
191:190
197:192
199:198
205:200
207:206
213:208
215:214
221:216
223:222
229:224
231:230
237:232
239:238
245:240
247:246
253:248
255:254
261:256
263:262
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
ASM-state6-EN0
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
ASM-state6-EN1
ASM-state6-EN2
ASM-state7-EN0
ASM-state7-EN1
ASM-state7-EN2
ASM-state-nRST
IO1 Digital Output Source
IO1 Output Enable
IO2 Digital Output Source
IO3 Digital Output Source
IO3 Output Enable
IO4 Digital Output Source
IO5 Digital Output Source
IO5 Output Enable
IO6 Digital Output Source (SCL with VI/In-
put & NMOS Open-Drain)
269:264
271:270
277:272
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
21
22
IO7 Digital Output Source (SDA with VI/In-
put & NMOS Open-Drain)
Matrix OUT
279:278
285:280
287:286
293:288
295:294
301:296
303:302
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
IO8 Digital Output Source
IO8 Output Enable
23
24
25
IO9 Digital Output Source
Datasheet
22-Jul-2021
Revision 3.6
153 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Signal Function
Byte Register Bit
Register Bit Definition
Read Write
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
309:304
311:310
317:312
319:318
325:320
327:326
333:328
335:334
341:336
343:342
349:344
351:350
357:352
359:358
365:360
367:366
373:368
375:374
381:376
383:382
389:384
391:390
397:392
399:398
405:400
407:406
413:408
415:414
421:416
423:422
429:424
431:430
437:432
439:438
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
IO10 Digital Output Source
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
IO10 Output Enable
IO11 Digital Output Source
IO11 Output Enable
IO12 Digital Output Source
IO13 Digital Output Source
IO13 Output Enable
IO14 Digital Output Source
IO15 Digital Output Source
IO15 Output Enable
Power Switch ON0, Digital Output Source Valid Valid
Valid Valid
Reserved
Valid Valid
Valid Valid
Power Switch ON1, Digital Output Source Valid Valid
Valid Valid
ACMP0 PWR UP
ACMP1 PWR UP
ACMP2 PWR UP
ACMP3 PWR UP
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Input of Filter_0 with fixed time edge
detector
445:440
447:446
453:448
455:454
461:456
463:462
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Valid Valid
Valid Valid
37
38
39
Input of Filter_1 with fixed time edge
detector
Valid Valid
Valid Valid
Input of Programmable Delay & Edge
Detector
Valid Valid
Valid Valid
Datasheet
22-Jul-2021
Revision 3.6
154 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Signal Function
Byte Register Bit
Register Bit Definition
Read Write
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
469:464
471:470
477:472
479:478
485:480
487:486
493:488
495:494
501:496
503:502
509:504
511:510
517:512
519:518
525:520
527:526
533:528
535:534
541:536
543:542
549:544
551:550
557:552
559:558
565:560
567:566
573:568
575:574
581:576
583:582
589:584
591:590
597:592
599:598
605:600
607:606
613:608
615:614
621:616
623:622
629:624
631:630
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
OSC 25 kHz/2MHz PDB (Power-Down)
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
OSC 25 MHz PDB (Power-Down)
IN0 of LUT2_0 or Clock Input of DFF0
IN1 of LUT2_0 or Data Input of DFF0
IN0 of LUT2_1 or Clock Input of DFF1
IN1 of LUT2_1 or Data Input of DFF1
IN0 of LUT2_2 or Clock Input of DFF2
IN1 of LUT2_2 or Data Input of DFF2
IN0 of LUT2_3 or Clock Input of PGen
IN1 of LUT2_3 or nRST of PGen
IN0 of LUT3_0 or Clock Input of DFF3
IN1 of LUT3_0 or Data Input of DFF3
IN2 of LUT3_0 or nRST (nSET) of DFF3
IN0 of LUT3_1 or Clock Input of DFF4
IN1 of LUT3_1 or Data Input of DFF4
IN2 of LUT3_1 or nRST (nSET) of DFF4
IN0 of LUT3_2 or Clock Input of DFF5
IN1 of LUT3_2 or Data Input of DFF5
IN2 of LUT3_2 or nRST (nSET) of DFF5
IN0 of LUT3_3 or Clock Input of DFF6
IN1 of LUT3_3 or Data Input of DFF6
Datasheet
22-Jul-2021
Revision 3.6
155 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Signal Function
Byte Register Bit
Register Bit Definition
Read Write
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
637:632
639:638
645:640
647:646
653:648
655:654
661:656
663:662
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
IN2 of LUT3_3 or nRST (nSET) of DFF6
4F
50
51
52
IN0 of LUT3_4 or Clock Input of DFF7
IN1 of LUT3_4 or Data Input of DFF7
IN2 of LUT3_4 or nRST (nSET) of DFF7
IN0ofLUT3_5orDelay2Input(orCounter2
RST Input)
669:664
671:670
677:672
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
53
IN1 of LUT3_5 or External Clock Input of
Delay2 (or Counter2)
Matrix OUT
54
55
56
679:678
685:680
687:686
Reserved
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
IN2 of LUT3_5
IN0ofLUT3_6orDelay3Input(orCounter3
RST Input)
693:688
695:694
701:696
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
IN1 of LUT3_6 or External Clock Input of
Delay3 (or Counter3)
Matrix OUT
57
58
59
703:702
709:704
711:710
Reserved
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
IN2 of LUT3_6
IN0ofLUT3_7orDelay4Input(orCounter4
RST Input)
717:712
719:718
725:720
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
IN1 of LUT3_7 or External Clock Input of
Delay4 (or Counter4)
Matrix OUT
5A
5B
5C
727:726
733:728
735:734
Reserved
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
IN2 of LUT3_7
IN0ofLUT3_8orDelay5Input(orCounter5
RST Input)
741:736
743:742
749:744
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
IN1 of LUT3_8 or External Clock Input of
Delay5 (or Counter5)
Matrix OUT
5D
5E
5F
751:750
757:752
759:758
Reserved
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
IN2 of LUT3_8
IN0ofLUT3_9orDelay6Input(orCounter6
RST Input)
765:760
767:766
Matrix OUT
Reserved
Valid Valid
Valid Valid
Datasheet
22-Jul-2021
Revision 3.6
156 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
IN1 of LUT3_9 or External Clock Input of
Delay6 (or Counter6)
773:768
Matrix OUT
Valid Valid
60
775:774
781:776
783:782
789:784
791:790
797:792
799:798
805:800
807:806
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
IN2 of LUT3_9
61
62
63
64
IN0 of LUT3_10 or Input of Pipe Delay
IN1 of LUT3_10 or nRST of Pipe Delay
IN2 of LUT3_10 or Clock of Pipe Delay
IN0ofLUT4_0orDelay0Input(orCounter0
RST/SET Input)
813:808
815:814
821:816
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
65
66
IN1 of LUT4_0 or External Clock Input of
Delay0 (or Counter0)
Matrix OUT
823:822
829:824
831:830
837:832
839:838
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
IN2 of LUT4_0 or UP Input of FSM0
IN3 of LUT4_0 or KEEP Input of FSM0
67
68
IN0ofLUT4_1orDelay1Input(orCounter1
RST/SET Input)
845:840
847:846
853:848
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
69
6A
IN1 of LUT4_1 or External Clock Input of
Delay1 (or Counter1)
Matrix OUT
855:854
861:856
863:862
869:864
871:870
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
IN2 of LUT4_1 or UP Input of FSM1
IN3 of LUT4_1 or KEEP Input of FSM1
6B
6C
PD of either Temp-output with BGAND/OR
crystal oscillator by register [1268]
877:872
Matrix OUT
Valid Valid
6D
879:878
887:880
895:888
903:896
911:904
919:912
927:920
935:928
943:936
951:944
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
6E
6F
70
71
72
73
74
75
76
Datasheet
22-Jul-2021
Revision 3.6
157 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Signal Function
Byte Register Bit
Register Bit Definition
Read Write
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
77
78
79
7A
7B
7C
7D
7E
7F
959:952
967:960
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
975:968
983:976
991:984
999:992
1007:1000
1015:1008
1023:1016
IO0
1024
1025
Reserved
Reserved
Reserved
Valid Valid
Valid Valid
Valid Valid
1027:1026
00: Floating
01: 10 K
10: 100 K
11: 1 M
1029:1028
1031:1030
IO0 Pull-down Resistor Value Selection
IO0 Mode Control
Valid Valid
Valid Valid
80
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
IO1
80
1032
1033
Reserved
Valid Valid
Valid Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO1 Pull-up/down Resistor Selection
00: Floating
01: 10 K
10: 100 K
11: 1 M
1035:1034
1037:1036
1039:1038
IO1 Pull-up/down Resistor Value Selection
IO1 Mode Control (sig_io1_oe = 0)
IO1 Mode Control (sig_io1_oe = 1)
Valid Valid
Valid Valid
Valid Valid
00: Digital Input without Schmitt Trigger,
01: Digital Input with Schmitt Trigger,
10: Low Voltage Digital Input
11: Reserved
81
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
Datasheet
22-Jul-2021
Revision 3.6
158 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
IO2
1040
1041
Reserved
Valid Valid
Valid Valid
0: 1x
1: 2x
IO2 Driver Strength Selection
0: Pull-down Resistor
1: Pull-up Resistor
1042
IO2 Pull-up/down Resistor Selection
Valid Valid
Valid Valid
00: Floating
01: 10 K
10: 100 K
1044:1043
IO2 Pull-up/down Resistor Value Selection
82
11: 1 M
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved 100: Push-Pull
101: Open-Drain NMOS
1047:1045
IO2 Mode Control
Valid Valid
110: Open-Drain PMOS
111: Reserved
IO3
1048
1049
Reserved
Valid Valid
Valid Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO3 Pull-up/down Resistor Selection
00: Floating
01: 10 K
10: 100 K
11: 1 M
1051:1050
1053:1052
1055:1054
IO3 Pull-up/down Resistor Value Selection
IO3 Mode Control (sig_io3_oe = 0)
IO3 Mode Control (sig_io3_oe = 1)
Valid Valid
Valid Valid
Valid Valid
83
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO4
1056
1057
Reserved
Valid Valid
Valid Valid
0: 1x
1: 2x
IO4 Driver Strength Selection
0: Pull-down Resistor
1: Pull-up Resistor
1058
IO4 Pull-up/down Resistor Selection
Valid Valid
Valid Valid
00: Floating
01: 10 K
10: 100 K
11: 1 M
1060:1059
IO4 Pull-up/down Resistor Value Selection
84
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
1063:1061
IO4 Mode Control
Valid Valid
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input & Open-Drain
Datasheet
22-Jul-2021
Revision 3.6
159 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
IO5
1064
1065
Reserved
Valid Valid
Valid Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO5 Pull-up/down Resistor Selection
00: Floating
01: 10 K
10: 100 K
1067:1066
1069:1068
1071:1070
IO5 Pull-up/down Resistor Value Selection
IO5 Mode Control (sig_io5_oe = 0)
IO5 Mode Control (sig_io5_oe = 1)
Valid Valid
Valid Valid
Valid Valid
11: 1 M
85
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO6
1072
1073
Reserved
Valid Valid
Valid Valid
0: 1x
1: 2x
IO6 Driver Strength Selection
0: SCL & Virtual Input 0
1: IO6
1074
Select SCL & Virtual Input 0 or IO6
Valid Valid
Valid Valid
00: Floating
01: 10 K
10: 100 K
1076:1075
IO6 Pull-down Resistor Value Selection
86
11: 1 M
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
IO6 (or SCL) Mode Control
1079:1077
Valid Valid
(input mode is selected by register at SCL) 100: Reserved
101: Open-Drain NMOS
110: Reserved
111: Reserved
IO7
1080
1081
Reserved
Valid Valid
Valid Valid
0: 1x (I2C up to 400 kHz)
1: 2x (I2C up to 1 MHz)
IO7 (or SDA) Driver Strength Selection
0: SDA & Virtual Input 1
1: IO7
1082
Select SDA & Virtual Input 1 or IO7
Valid Valid
Valid Valid
00: Floating
01: 10 K
10: 100 K
11: 1 M
1084:1083
IO7 Pull-down Resistor Value Selection
87
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
IO7 (or SDA) Mode Control
1087:1085
(input mode is selected by register at SDA, 011: Re served 100: Reserved
Valid Valid
output mode is fixed as OD at SDA)
101: Open-Drain NMOS
110: Reserved
111: Reserved
Datasheet
22-Jul-2021
Revision 3.6
160 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
IO8
0: Super Drive OFF
1: SuperDrive ON (if sig_IO8_oe ='1' &IO8 Valid Valid
Mode Control = '1x')
IO8 Super Drive (4x, NMOS Open-Drain)
Selection
1088
0: Pull-down Resistor
Valid Valid
1089
IO8 Pull-up/down Resistor Selection
1: Pull-up Resistor
00: Floating
01: 10K
1091:1090
IO8 Pull-up/down Resistor Value Selection
Valid Valid
10: 100K
88
11: 1M
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
1093:1092
1095:1094
IO8 Mode Control (sig_io8_oe = 0)
IO8 Mode Control (sig_io8_oe = 1)
Valid Valid
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
Valid Valid
11: Open-Drain NMOS 2x
IO9
0: Super Drive OFF
1: Super Drive ON (if IO9 Mode Control = Valid Valid
'101')
IO9 Super Drive (4x, NMOS Open-Drain)
Selection
1096
0: 1x
1: 2x
1097
1098
IO9 Driver Strength Selection
Valid Valid
0: Pull-down Resistor
Valid Valid
IO9 Pull-up/down Resistor Selection
1: Pull-up Resistor
00: Floating
01: 10K
10: 100K
1100:1099
IO9 Pull-up/down Resistor Value Selection
Valid Valid
89
11: 1M
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
100: Push-Pull
1103:1101
IO9 Mode Control
Valid Valid
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input & Open-Drain
Datasheet
22-Jul-2021
Revision 3.6
161 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
IO10
1104
1105
Reserved
Valid Valid
Valid Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO10 Pull-up/down Resistor Selection
00: Floating
01: 10K
10: 100K
1107:1106
1109:1108
1111:1110
IO10 Pull-up/down Resistor Value Selection
IO10 Mode Control (sig_io10_oe = 0)
IO10 Mode Control (sig_io10_oe = 1)
Valid Valid
Valid Valid
Valid Valid
11: 1M
8A
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO11
1112
1113
Reserved
Valid Valid
Valid Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO11 Pull-up/down Resistor Selection
00: Floating
01: 10K
10: 100K
1115:1114
1117:1116
1119:1118
IO11 Pull-up/down Resistor Value Selection
IO11 Mode Control (sig_IO11_oe = 0)
IO11 Mode Control (sig_IO11_oe = 1)
Valid Valid
Valid Valid
Valid Valid
11: 1M
8B
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO12
1120
1121
Reserved
Valid Valid
Valid Valid
0: 1x
1: 2x
IO12 Driver Strength Selection
0: Pull-down Resistor
1: Pull-up Resistor
1122
IO12 Pull-up/down Resistor Selection
Valid Valid
Valid Valid
00: Floating
01: 10K
10: 100K
1124:1123
IO12 Pull-up/down Resistor Value Selection
8C
11: 1M
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
1127:1125
IO12 Mode Control
Valid Valid
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input & Open-Drain
Datasheet
22-Jul-2021
Revision 3.6
162 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
IO13
1128
1129
Reserved
Valid Valid
Valid Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO13 Pull-up/down Resistor Selection
00: Floating
01: 10K
10: 100K
1131:1130
1133:1132
1135:1134
IO13 Pull-up/down Resistor Value Selection
IO13 Mode Control (sig_io13_oe = 0)
IO13 Mode Control (sig_io13_oe = 1)
Valid Valid
Valid Valid
Valid Valid
11: 1M
8D
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Sel for XOSC (X2)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO14
0: Disable
1: Enable
1136
1137
1138
X1 & X2 for crystal OSC enable
IO14 Driver Strength Selection
IO14 Pull-up/down Resistor Selection
Valid Valid
Valid Valid
Valid Valid
0: 1x
1: 2x
0: Pull-down Resistor
1: Pull-up Resistor
00: Floating
01: 10K
10: 100K
11: 1M
1140:1139
IO14 Pull-up/down Resistor Value Selection
Valid Valid
8E
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Sel for XOSC (X1)
1143:1141
IO14 Mode Control
Valid Valid
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Reserved
IO15
1144
1145
Reserved
Valid Valid
Valid Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO15 Pull-up/down Resistor Selection
00: Floating
01: 10K
10: 100K
1147:1146
1149:1148
1151:1150
IO15 Pull-up/down Resistor Value Selection
IO15 Mode Control (sig_io15_oe = 0)
IO15 Mode Control (sig_io15_oe = 1)
Valid Valid
Valid Valid
11: 1M
8F
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
Valid Valid
Datasheet
22-Jul-2021
Revision 3.6
163 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
PWR_SW_ON0
1152
Reserved
Valid Valid
Valid Valid
PWR_SW_ON0
Pull-up/down Resistor Selection
0: Reserved
1: Reserved
1153
00: Reserved
01: Reserved
10: Reserved
11: Reserved
PWR_SW_ON0
Pull-up/down Resistor Value Selection
1155:1154
1157:1156
1159:1158
Valid Valid
Valid Valid
Valid Valid
90
00: Digital Input without Schmitt Trigger
01: Reserved
10: Reserved
PWR_SW_ON0
Mode Control (sig_io16_oe = 0)
11: Reserved
00: Reserved
01: 2x
10: Reserved
11: Reserved
PWR_SW_ON0
Mode Control (sig_io16_oe = 1)
PWR_SW_ON1
1160
Reserved
Valid Valid
Valid Valid
PWR_SW_ON1
Driver Strength Selection
0: Reserved
1: 2x
1161
1162
PWR_SW_ON1
Pull-up/down Resistor Selection
0: Reserved
1: Reserved
Valid Valid
Valid Valid
00: Reserved
01: Reserved
10: Reserved
11: Reserved
PWR_SW_ON1
Pull-up/down Resistor Value Selection
1164:1163
91
000: Digital Input without Schmitt Trigger
001: Reserved
010: Reserved
PWR_SW_ON1
Mode Control
011: Reserved
100: Push-Pull
101: Reserved
1167:1165
Valid Valid
110: Reserved
111: Reserved
ACMP1
ACMP1 Positive Input Source Select
0: IO8
1: ACMP0 IN+ source
1168
1169
Valid Valid
Valid Valid
ACMP1 Analog Buffer Enable (Max. BW
1MHz)
0: Disable analog buffer
1: Enable analog buffer
00: 0mV
01: 25mV
92
10: 50mV
11: 200mV
1171:1170
ACMP1 Hysteresis Enable
Valid Valid
(01: for both external & internal Vref; 10 &
11: for only internal Vref; External Vref will
not have 50mV & 200mV hysteresis.)
Datasheet
22-Jul-2021
Revision 3.6
164 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
ACMP0
ACMP0 Positive Input Source Select
1172
0: IO4
1: VDD
Valid Valid
Valid Valid
ACMP0 Analog Buffer Enable (Max. BW
0: Disable analog buffer
1: Enable analog buffer
1173
1MHz)
00: 0mV
01: 25mV
92
10: 50mV
11: 200mV
(01: for both external & internal Vref; 10 &
11: for only internal Vref; External Vref will
not have 50mV & 200mV hysteresis.)
1175:1174
1177:1176
ACMP0 Hysteresis Enable
Valid Valid
ACMP3
ACMP3 Positive Input Source Select
00: IO12
01: ACMP2 IN+ source
10: ACMP0 IN+ source
11: Reserved
Valid Valid
Valid Valid
00: 0mV
01: 25mV
10: 50mV
11: 200mV
93
1179:1178
ACMP3 Hysteresis Enable
(01: for both external & internal Vref; 10 &
11: for only internal Vref; External Vref will
not have 50mV & 200mV hysteresis.)
ACMP2
ACMP2 Positive Input Source Select
ACMP2 Hysteresis Enable
0: IO10
1: ACMP0 IN+ source
1180
Valid Valid
Valid Valid
00: 0mV
01: 25mV
10: 50mV
11: 200mV
(01: for both external & internal Vref; 10 &
11: for only internal Vref; External Vref will
not have 50mV & 200mV hysteresis.)
93
1182:1181
ACMP1 100 uA Current Source Enable
93 1183 ACMP1 100 uA Current Source Enable
LUT3_x Function Select
0: Disable
1: Enable
Valid Valid
0: LUT3_3
1: DFF6 with nRST/nSET
1184
1185
1186
LUT3_3 or DFF6 with nRST/nSET Select
Valid Valid
Valid Valid
Valid Valid
0: LUT3_2
1: DFF5 with nRST/nSET
LUT3_2 or DFF5 with nRST/nSET Select
LUT3_1 or DFF4 with nRST/nSET Select
94
0: LUT3_1
1: DFF4 with nRST/nSET
LUT3_0 or DFF3 with nRST/nSET Select
(Two consecutive DFFs if register [1471] = 1
for SM)
0: LUT3_0
1: DFF3 with nRST/nSET
1187
Valid Valid
Datasheet
22-Jul-2021
Revision 3.6
165 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
LUT2_x Function Select
0: LUT2_3
1: PGen
1188
1189
1190
1191
LUT2_3 or PGen Select
LUT2_2 or DFF2 Select
LUT2_1 or DFF1 Select
LUT2_0 or DFF0 Select
Valid Valid
Valid Valid
Valid Valid
Valid Valid
0: LUT2_2
1: DFF2
94
0: LUT2_1
1: DFF1
0: LUT2_0
1: DFF0
LUT4_x Function Select
0: LUT4_1
1: DLY/CNT1(16bits)
1192
1193
LUT4_1 or DLY/CNT1(16bits) Select
LUT4_0 or DLY/CNT0(16bits) Select
Valid Valid
Valid Valid
95
0: LUT4_0
1: DLY/CNT0(16bits)
LUT3_x Function Select
0: LUT3_9
1: DLY/CNT6(8bits)
1194
1195
1196
1197
1198
1199
LUT3_9 or DLY/CNT6(8bits) Select
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
0: LUT3_8
1: DLY/CNT5(8bits)
LUT3_8 or DLY/CNT5(8bits) Select
LUT3_7 or DLY/CNT4(8bits) Select
LUT3_6 or DLY/CNT3(8bits) Select
LUT3_5 or DLY/CNT2(8bits) Select
LUT3_4 or DFF7 with nRST/nSET Select
0: LUT3_7
1: DLY/CNT4(8bits)
95
0: LUT3_6
1: DLY/CNT3(8bits)
0: LUT3_5
1: DLY/CNT2(8bits)
0: LUT3_4
1: DFF7 with nRST/nSET
LUT2_1/DFF1
1200
LUT2_1 [0]
Valid Valid
Valid Valid
0: Low
1: High
1201
1202
1203
LUT2_1 [1]/DFF1 Initial Polarity Select
96
0: Q output
1: QB output
LUT2_1 [2]/DFF1 Output Select
LUT2_1 [3]/DFF1 or LATCH Select
Valid Valid
Valid Valid
0: DFF function
1: LATCH function
LUT2_0/DFF0
1204
LUT2_0 [0]
Valid Valid
Valid Valid
0: Low
1: High
1205
1206
1207
LUT2_0 [1]/DFF0 Initial Polarity Select
96
0: Q output
1: QB output
LUT2_0 [2]/DFF0 Output Select
LUT2_0 [3]/DFF0 or LATCH Select
Valid Valid
Valid Valid
0: DFF function
1: LATCH function
LUT2_3/PGen
97
1211:1208
LUT2_3 [3:0] or PGen 4bit counter data[3:0]
Valid Valid
Datasheet
22-Jul-2021
Revision 3.6
166 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
LUT2_2/DFF2
1212
LUT2_2 [0]
Valid Valid
Valid Valid
0: Low
1: High
1213
LUT2_2 [1]/DFF2 Initial Polarity Select
97
0: Q output
1: QB output
1214
1215
LUT2_2 [2]/DFF2 Output Select
LUT2_2 [3]/DFF2 or LATCH Select
Valid Valid
Valid Valid
0: DFF function
1: LATCH function
LUT3_0/DFF3
1219:1216
LUT3_0 [3:0]
Valid Valid
Valid Valid
0: Low
1: High
1220
1221
1222
1223
LUT3_0 [4]/DFF3 Initial Polarity Select
0: nRST from Matrix Output
1: nSET from Matrix Output
LUT3_0 [5]/DFF3 nRST or nSET Select
LUT3_0 [6]/DFF3 Output Select
Valid Valid
Valid Valid
Valid Valid
98
0: Q output
1: QB output
0: DFF function
1: LATCH function
LUT3_0 [7]/DFF3 or LATCH Select
LUT3_1/DFF4
1227:1224
LUT3_1 [3:0]
Valid Valid
Valid Valid
0: Low
1: High
1228
1229
1230
1231
LUT3_1 [4]/DFF4 Initial Polarity Select
0: nRST from Matrix Output
1: nSET from Matrix Output
LUT3_1 [5]/DFF4 nRST or nSET Select
LUT3_1 [6]/DFF4 Output Select
Valid Valid
Valid Valid
Valid Valid
99
0: Q output
1: QB output
0: DFF function
1: LATCH function
LUT3_1 [7]/DFF4 or LATCH Select
LUT3_2/DFF5
1235:1232
LUT3_2 [3:0]
Valid Valid
Valid Valid
0: Low
1: High
1236
1237
1238
1239
LUT3_2 [4]/DFF5 Initial Polarity Select
0: nRST from Matrix Output
1: nSET from Matrix Output
LUT3_2 [5]/DFF5 nRST or nSET Select
LUT3_2 [6]/DFF5 Output Select
Valid Valid
Valid Valid
Valid Valid
9A
0: Q output
1: QB output
0: DFF function
1: LATCH function
LUT3_2 [7]/DFF5 or LATCH Select
Datasheet
22-Jul-2021
Revision 3.6
167 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
LUT3_3/DFF6
1243:1240
LUT3_3 [3:0]
Valid Valid
Valid Valid
0: Low
1: High
1244
LUT3_3 [4]/DFF6 Initial Polarity Select
0: nRST from Matrix Output
1: nSET from Matrix Output
1245
1246
1247
LUT3_3 [5]/DFF6 nRST or nSET Select
LUT3_3 [6]/DFF6 Output Select
Valid Valid
Valid Valid
Valid Valid
9B
0: Q output
1: QB output
0: DFF function
1: LATCH function
LUT3_3 [7]/DFF6 or LATCH Select
LUT3_4/DFF7
1251:1248
LUT3_4 [3:0]
Valid Valid
Valid Valid
0: Low
1: High
1252
1253
1254
1255
LUT3_4 [4]/DFF7 Initial Polarity Select
0: nRST from Matrix Output
1: nSET from Matrix Output
LUT3_4 [5]/DFF7 nRST or nSET Select
LUT3_4 [6]/DFF7 Output Select
Valid Valid
Valid Valid
Valid Valid
9C
0: Q output
1: QB output
0: DFF function
1: LATCH function
LUT3_4 [7]/DFF7 or LATCH Select
LUT3_10/Pipe Delay
1259:1256
9D
LUT3_10 [3:0]/Pipe Delay OUT0 Select
LUT3_10 [7:4]/Pipe Delay OUT1 Select
Valid Valid
Valid Valid
1263:1260
00: Rising Edge Detector
Select the Edge Mode of Programmable De- 01: Falling Edge Detector
1265:1264
1267:1266
Valid Valid
Valid Valid
Valid Valid
lay & Edge Detector
10: Both Edge Detector
11: Both Edge Delay
00: 125ns
Delay Value Select for Programmable Delay 01: 250ns
& Edge Detector (VDD = 3.3V, typical)
10: 375ns
11: 500ns
9E
00: No matrix PD
01: matrix PD for crystal oscillator
10: Reserved
1269:1268
Crystal oscillator Power-down enable
11: Reserved
0: LUT3_10
1: Pipe Delay
1270
1271
LUT3_10 or Pipe Delay Select
Pipe Delay OUT1 Polarity Select
Valid Valid
Valid Valid
0: Non-inverted
1: Inverted
Datasheet
22-Jul-2021
Revision 3.6
168 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
DLY/CNT2
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
DLY2 Mode Select or Asynchronous CNT2 er Reset)
1273:1272
1276:1274
Valid Valid
Reset
10: on Rising Edge only (for Delay & Count-
er Reset)
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12
9F
011: OSC/24
100: OSC/64
DLY/CNT2 Clock Source Select
Valid Valid
101: 25MHz OSC clock
110: External Clock
111: Counter1 Overflow
DLY/CNT2 Output Selection if DLY/CNT2 0: Default Output
1277
Valid Valid
Valid Valid
Mode Selection is "11".
1: Edge Detector Output
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
1279:1278
DLY/CNT2 Mode Selection
DLY/CNT3
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
DLY3 Mode Select or Asynchronous CNT3 er Reset)
1281:1280
Valid Valid
Reset
10: on Rising Edge only (for Delay & Count-
er Reset)
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
A0
1284:1282
DLY/CNT3 Clock Source Select
Valid Valid
101: 25MHz OSC clock
110: External Clock
111: Counter2 Overflow
DLY/CNT3 Output Selection if DLY/CNT3 0: Default Output
1285
Valid Valid
Valid Valid
Mode Selection is "11".
1: Edge Detector Output
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
1287:1286
DLY/CNT3 Mode Selection
Datasheet
22-Jul-2021
Revision 3.6
169 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
DLY/CNT4
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
DLY4 Mode Select or Asynchronous CNT4 er Reset)
1289:1288
1292:1290
Valid Valid
Reset
10: on Rising Edge only (for Delay & Count-
er Reset)
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12
A1
011: OSC/24
100: OSC/64
DLY/CNT4 Clock Source Select
Valid Valid
101: 25MHz OSC clock
110: External Clock
111: Counter3 Overflow
DLY/CNT4 Output Selection if DLY/CNT4 0: Default Output
1293
Valid Valid
Valid Valid
Mode Selection is "11".
1: Edge Detector Output
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
1295:1294
DLY/CNT4 Mode Selection
DLY/CNT5
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
DLY5 Mode Select or Asynchronous CNT5 er Reset)
1297:1296
Valid Valid
Reset
10: on Rising Edge only (for Delay & Count-
er Reset)
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
A2
1300:1298
DLY/CNT5 Clock Source Select
Valid Valid
101: 25MHz OSC clock
110: External Clock
111: Counter4 Overflow
DLY/CNT5 Output Selection if DLY/CNT5 0: Default Output
1301
Valid Valid
Valid Valid
Mode Selection is "11".
1: Edge Detector Output
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
1303:1302
DLY/CNT5 Mode Selection
Datasheet
22-Jul-2021
Revision 3.6
170 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
DLY/CNT6
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
DLY6 Mode Select or Asynchronous CNT6 er Reset)
1305:1304
1308:1306
Valid Valid
Reset
10: on Rising Edge only (for Delay & Count-
er Reset)
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12, 011: OSC/24
100: OSC/64
A3
DLY/CNT6 Clock Source Select
Valid Valid
101: 25MHz OSC clock
110: External Clock
111: Counter5 Overflow
DLY/CNT6 Output Selection if DLY/CNT6 0: Default Output
1309
Valid Valid
Valid Valid
Mode Selection is "11".
1: Edge Detector Output
00: Delay mode
01: One Shot
10: Freq. Detect
1311:1310
DLY/CNT6 Mode Selection
11: Counter mode
DLY/CNT0
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
DLY0 Mode Select or Asynchronous CNT0 er Reset)
1313:1312
Valid Valid
Reset (16bits)
10: on Rising Edge only (for Delay & Count-
er Reset)
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
A4
1316:1314
DLY/CNT0 Clock Source Select (16bits)
Valid Valid
101: 25MHz OSC clock
110: External Clock
111: Counter6 Overflow
0: Reset to 0s
1: Set to data (registers [1583:1576,
1591:1584])
CNT0/FSM0's Q are Set to data or Reset to
0s Selection (16bits)
1317
Valid Valid
Valid Valid
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
1319:1318
DLY/CNT0 Mode Selection (16bits)
Datasheet
22-Jul-2021
Revision 3.6
171 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
DLY/CNT1
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
DLY1 Mode Select or Asynchronous CNT1 er Reset)
1321:1320
1324:1322
Valid Valid
Reset (16bits)
10: on Rising Edge only (for Delay & Count-
er Reset)
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
A5
DLY/CNT1 Clock Source Select (16bits)
Valid Valid
101: 25MHz OSC clock
110: External Clock
111: Counter0 Overflow
0: Reset to 0s
1: Set to data (registers [1599:1592,
1607:1600])
CNT1/FSM1's Q are Set to data or Reset to
0s Selection (16bits)
1325
Valid Valid
Valid Valid
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
1327:1326
DLY/CNT1 Mode Selection (16bits)
DLY/CNTx One-Shot/Freq. Detect Output Polarity
DLY/CNT0 stop & restarting enable in CNT 0: Disable
1328
1329
1330
1331
1332
1333
1334
1335
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
mode when new data is loaded
1: Enable
Select the Polarity of DLY/CNT6's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT5's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT4's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
A6
Select the Polarity of DLY/CNT3's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT2's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT1's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT0's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Datasheet
22-Jul-2021
Revision 3.6
172 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
Oscillator
00: Div1
01: Div2
10: Div4
11: Div8
1337:1336
1338
OSC Clock Pre-divider for 25MHz
Valid Valid
Valid Valid
Valid Valid
0: Disable
1: Enable
A7
OSC Fast Start-Up Enable for 25kHz/2MHz
OSC Clock Pre-divider for 25kHz/2MHz
00: Div1
01: Div2
10: Div4
11: Div8
1340:1339
0: Auto Power-On (If any CNT/DLY use
25MHz source)
1: Force Power-On
1341
1342
1343
Force 25MHz Oscillator ON
Valid Valid
Valid Valid
Valid Valid
Oscillator (25kHz: Ring OSC, 2M: RC-OSC) 0: 25kHz Ring OSC
A7
Select
1: 2MHz RC-OSC
0: Auto Power-On (if any CNT/DLY use
25K/2MHz source)
Force 25kHz/2MHz Oscillator ON
1: Force Power-On
000: OSC/1
001: OSC/2
010: OSC/3
Internal OSC 25kHz/2MHz Frequency Divid- 011: OSC/4
1346:1344
1349:1347
Valid Valid
er Control for matrix input [28]
100: OSC/8
101: OSC/12
110: OSC/24
111: OSC/64
000: OSC/1
001: OSC/2
010: OSC/3
A8
Internal OSC 25kHz/2MHz Frequency Divid- 011: OSC/4
Valid Valid
er Control for matrix input [27]
100: OSC/8
101: OSC/12
110: OSC/24
111: OSC/64
OSC Clock 25kHz/2MHz to matrix input [28] 0: Disable
enable 1: Enable
1350
1351
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
OSC Clock 25kHz/2MHz to matrix input [27] 0: Disable
enable
1: Enable
ASM_reg_init[2:0] for ASM state default set-
up bits
1354:1352
1355
External oscillator pin selection for 25kHz/ 0: IO17
2MHz 1: IO15
OSC Clock 25 MHz to matrix input [29] en- 0: Disable
1356
able
1: Enable
A9
External Clock Source Select instead of
25MHz
0: Internal Oscillator
1: External Clock from IO14
1357
External Clock Source Select instead of
25kHz/2MHz
0: Internal Oscillator
1: External Clock from IO15 or IO17
1358
DLY/CNT1 stop & restarting enable in CNT 0: Disable
mode when new data is loaded 1: Enable
1359
Datasheet
22-Jul-2021
Revision 3.6
173 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
ASM 8-to-1 MUX’s 3 selection bits
1362:1360
1363
ASM_state0_dec8x1_EN1
Reserved
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
AA
AB
1366:1364
1367
ASM_state0_dec8x1_EN0
Reserved
1370:1368
1371
ASM_state1_dec8x1_EN0
Reserved
1374:1372
1375
ASM_state0_dec8x1_EN2
Reserved
1378:1376
1379
ASM_state1_dec8x1_EN2
Reserved
AC
AC
1382:1380
1383
ASM_state1_dec8x1_EN1
Reserved
1386:1384
1387
ASM_state2_dec8x1_EN1
Reserved
AD
AE
AF
B0
B1
B2
B3
1390:1388
1391
ASM_state2_dec8x1_EN0
Reserved
1394:1392
1395
ASM_state3_dec8x1_EN0
Reserved
1398:1396
1399
ASM_state2_dec8x1_EN2
Reserved
1402:1400
1403
ASM_state3_dec8x1_EN2
Reserved
1406:1404
1407
ASM_state3_dec8x1_EN1
Reserved
1410:1408
1411
ASM_state4_dec8x1_EN1
Reserved
1414:1412
1415
ASM_state4_dec8x1_EN0
Reserved
1418:1416
1419
ASM_state5_dec8x1_EN0
Reserved
1422:1420
1423
ASM_state4_dec8x1_EN2
Reserved
1426:1424
1427
ASM_state5_dec8x1_EN2
Reserved
1430:1428
1431
ASM_state5_dec8x1_EN1
Reserved
1434:1432
1435
ASM_state6_dec8x1_EN1
Reserved
1438:1436
1439
ASM_state6_dec8x1_EN0
Reserved
Datasheet
22-Jul-2021
Revision 3.6
174 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Signal Function
Byte Register Bit
Register Bit Definition
Read Write
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
1442:1440
1443
ASM_state7_dec8x1_EN0
Reserved
B4
B5
1446:1444
1447
ASM_state6_dec8x1_EN2
Reserved
1450:1448
1451
ASM_state7_dec8x1_EN2
Reserved
1454:1452
1455
ASM_state7_dec8x1_EN1
Reserved
Filter/Edge Detector
00: Rising Edge
01: Falling Edge
10: Both Edge
11: Delay
1457:1456
Select the edge mode of Edge Detector_1
Valid Valid
Filter_1/Edge Detector_1 output Polarity Se- 0: Filter_1 output
1458
Valid Valid
Valid Valid
lect
1: Filter_1 output inverted
Filter_1or Edge Detector_1 Select
(Typ. 30 ns @VDD = 3.3 V)
0: Filter_1
1: Edge Detector_1
1459
B6
00: Rising Edge
01: Falling Edge
10: Both Edge
11: Delay
1461:1460
Select the edge mode of Edge Detector_0
Valid Valid
Filter_0/Edge Detector_0 output Polarity Se- 0: Filter_0 output
1462
1463
Valid Valid
Valid Valid
lect
1: Filter_0 output inverted
Filter_0 or Edge Detector_0 Select
(Typ. 47 ns @VDD = 3.3 V)
0: Filter_0
1: Edge Detector_0
Vref/Bandgap
1464
Reserved
Valid Valid
00 or 10 with registers [1474:1472] = 100
(WideVDD r a n g e , 1 . 7 V ~ 5 . 5 V ) :
Auto-delay mode, 550 uS for VDD < 2.7V &
100 uS for 2.7 V < VDD
00 or 10 with registers [1474:1472] = X10:
Always 100 uS delay for 2.7 V < VDD
00 or 10 with registers [1474:1472] = XX1:
Always 550uS delay for VDD < 2.7 V,
01: Always 550us delay regardless of
Bandgap OK for ACMP Output Delay Time
Select, the start Time is "nRST_core go to
High"
1466:1465
Valid Valid
registers [1474:1472] & VDD
,
11: Always 100 us delay with 2.7V < VDD
regardless of registers [1474:1472]
B7
Reserved
Reserved
Reserved
Reserved
1467
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
1468
1469
1470
1471
0: Disable
1: Enable
Two consecutive DFFs enable for SM
Datasheet
22-Jul-2021
Revision 3.6
175 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
0XX: Power divider off (if there is no use of
VDD//3, VDD//4 @ ACMP negative in)
100: Reserved
1474:1472
Valid Valid
Power divider (VDD/3, VDD/4) ON/OFF
X10: Reserved
XX1:Reserved
VDD Bypass Enable when device power is 0: Regulator Auto ON
1475
1476
Valid Valid
Valid Valid
1.8 V
1: Regulator OFF (VDD Bypass)
0: Auto-Mode
1: Enable (if chip is Power-down, the
Bandgap will Power-down even if it is Set
to 1).
B8
B9
BA
Force Bandgap ON
0: None (Or Programming Enable)
1: Power-down (Or Programming Disable)
1477
1478
1479
NVM Power-down
Reserved
Valid Valid
Valid Valid
Valid Valid
0: Disable
1: Enable
GPIO Quick Charge Enable
Vref Output Source Select
000: ACMP2 Vref
001: ACMP3 Vref
100: VDD/2
101: VDD/3
110: VDD/4
1482:1480
Valid Valid
111: Hi-Z
Reserved
Reserved
Reserved
1483
Valid Valid
Valid Valid
1486:1484
1487
1488
1489
Valid Valid
Valid Valid
Valid Valid
Reserved
0: short wake time
1: normal wake time
Wake time Selection in Wake Sleep Mode
0: Disable
1: Enable
1490
1491
1492
1493
ACMP0 Wake & Sleep function Enable
ACMP1 Wake & Sleep function Enable
ACMP2 Wake & Sleep function Enable
ACMP3 Wake & Sleep function Enable
Valid Valid
Valid Valid
Valid Valid
Valid Valid
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
Wake Sleep Output State When WS Oscilla-
tor is Power-down if DLY/CNT0 Mode Selec-
tion is "11"
0: Low
1: High
1494
1495
Valid Valid
Wake Sleep Ratio Control Mode Selection if 0: Default Mode
DLY/CNT0 Mode Selection is "11"
Valid Valid
1: Wake Sleep Ratio Control Mode
BB
BC
BD
BE
1503:1496
1511:1504
1519:1512
1527:1520
Reserved
Reserved
Reserved
Reserved
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Datasheet
22-Jul-2021
Revision 3.6
176 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Signal Function
Byte Register Bit
Register Bit Definition
Read Write
BF
1535:1528
Reserved
Valid Valid
LUT/DLY/CNT Control Data
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
C0
C1
C2
C3
C4
1543:1536
1551:1544
1559:1552
1567:1560
1575:1568
LUT3_5 [7:0] or DLY/CNT2 Control Data
LUT3_6 [7:0] or DLY/CNT3 Control Data
LUT3_7 [7:0] or DLY/CNT4 Control Data
LUT3_8 [7:0] or DLY/CNT5 Control Data
LUT3_9 [7:0] or DLY/CNT6 Control Data
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
C5
C6
C7
C8
C9
CA
1583:1576
1591:1584
1599:1592
1607:1600
1615:1608
1623:1616
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
LUT4_0 [15:0] or DLY/CNT0 (16bits, [15:0] 1 - 65535 (Delay Time = [Counter Control
= [1591:1576]) Control Data Data + 2]/Freq)
LUT4_1 [15:0] or DLY/CNT1 (16bits, [15:0] 1 - 65535 (Delay Time = [Counter Control
= [1607:1592]) Control Data
Data + 2]/Freq)
PGen pattern data [15:0] = [1623:1608]
ACMP0
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
1628:1624
ACMP0-IN Voltage Select
Valid Valid
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
CB
11010: IO9: EXT_Vref
11011: IO5: ACMP0-
11100: IO9: EXT_Vref/2
11101: IO5: ACMP0-/2
11110: Reserved
11111: Reserved
00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
1630:1629
1631
ACMP0 Positive Input Divider
Valid Valid
Valid Valid
ACMP0 Low Bandwidth (MAX: 1MHz) En- 0: OFF
able 1:ON
Datasheet
22-Jul-2021
Revision 3.6
177 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
ACMP1
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
1636:1632
ACMP1-IN Voltage Select
Valid Valid
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
CC
11010: IO9: EXT_Vref
11011: Reserved
11100: IO9: EXT_Vref/2
11101: Reserved
11110: Reserved
11111: Reserved
00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
1638:1637
1639
ACMP1 Positive Input Divider
Valid Valid
Valid Valid
ACMP1 Low Bandwidth (MAX: 1MHz) En- 0: OFF
able
1: ON
ACMP2
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
1644:1640
ACMP2-IN Voltage Select
Valid Valid
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
CD
11010: IO9: EXT_Vref
11011: IO11: ACMP2-
11100: IO9: EXT_Vref /2
11101: IO11: ACMP2-/2
11110: Reserved
11111: Reserved
00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
1646:1645
1647
ACMP2 Positive Input Divider
Valid Valid
Valid Valid
ACMP2 Low Bandwidth (MAX: 1MHz) En- 0: OFF
able 1: ON
Datasheet
22-Jul-2021
Revision 3.6
178 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
ACMP3
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
1652:1648
ACMP3-IN Voltage Select
Valid Valid
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
CE
11010: IO9: EXT_Vref
11011: IO11: ACMP3-
11100: IO9: EXT_Vref/2
11101: IO11: ACMP3-/2
11110: Reserved
11111: Reserved
00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
1654:1653
1655
ACMP3 Positive Input Divider
Valid Valid
Valid Valid
ACMP3 Low Bandwidth (MAX: 1MHz) En- 0: OFF
able
1: ON
Misc.
1656
1657
Reserved
Valid Valid
Valid Valid
Switch from “Matrix OUT: OSC 25MHz PD” 0: OSC PD
to “Matrix OUT: OSC 25MHz Force On”
1: OSC Force On (Matrix Output [59])
CF
Switch from “Matrix OUT: OSC 25kHz/2MHz
PD” to “Matrix OUT: OSC 25kHz/2MHz
Force On”
0: OSC PD
1: OSC Force On (Matrix Output [58])
1658
Valid Valid
1659
1660
1661
Reserved Reserved
Reserved Reserved
Reserved Reserved
Valid Valid
Valid Valid
Valid Valid
I2C reset bit with reloading NVM into Data 0: Keep existing condition
CF
1662
Valid Valid
register (TBD)
1: R e se t e xe cu t io n
1663
Reserved
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
1671:1664
1679:1672
1687:1680
1695:1688
1703:1696
1711:1704
1719:1712
1727:1720
1735:1728
1743:1736
RAM 8 outputs for ASM-state0
RAM 8 outputs for ASM-state1
RAM 8 outputs for ASM-state2
RAM 8 outputs for ASM-state3
RAM 8 outputs for ASM-state4
RAM 8 outputs for ASM-state5
RAM 8 outputs for ASM-state6
RAM 8 outputs for ASM-state7
User configurable RAM/OTP Byte 0
User configurable RAM/OTP Byte 1
Datasheet
22-Jul-2021
Revision 3.6
179 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Signal Function
Byte Register Bit
Register Bit Definition
Read Write
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Invalid Invalid
Invalid Invalid
Invalid Invalid
Invalid Invalid
Valid Valid
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
1751:1744
1759:1752
1767:1760
1775:1768
1783:1776
1791:1784
1799:1792
1807:1800
1815:1808
1823:1816
1831:1824
User configurable RAM/OTP Byte 2
User configurable RAM/OTP Byte 3
User configurable RAM/OTP Byte 4
User configurable RAM/OTP Byte 5
User configurable RAM/OTP Byte 6
User configurable RAM/OTP Byte 7
Reserved
Reserved
Reserved
Reserved
Reserved
0: Disable (Programmed data can be
read.),
1832
I2C lock for read bits [1535:0] (Bank 0/1/2)
Valid Invalid
1: Enable (Programmed data can't be
read.)
E5
1833
Valid Invalid
Reserved
Reserved
Reserved
1835:1834
1839:1836
Valid Invalid
Valid Invalid
8-bit Pattern ID Byte 0 (From NVM):
ID[23:16]
E6
1847:1840
Valid Valid
E7
E8
1855:1848
1863:1856
1867:1864
1868
Reserved
Valid Invalid
Valid Invalid
Valid Invalid
Valid Valid
Valid Valid
Reserved
I2C Control Code Bit [3:0]
Value for slave address
Reserved
1869
Reserved
E9
0: writable
1: Non-writable
1870
1871
I2C lock for write all bits (Bank 0/1/2/3)
Valid Valid
Valid Invalid
0: writable
1: Non-writable
I2C lock for write bits [1535:0] (Bank 0/1/2)
CNT4 Counted Value
EA
EB
EC
ED
EE
EF
1879:1872
1887:1880
1895:1888
1903:1896
1911:1904
1919:1912
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
CNT0 (16bits) = [1895:1880] Counted Value
CNT6 Counted Value
CNT1 (16bits) = [1919:1904] Counted Value
Datasheet
22-Jul-2021
Revision 3.6
180 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Read Write
Signal Function
Byte Register Bit
Register Bit Definition
Matrix Input
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
Matrix Input 0
Matrix Input 1
Matrix Input 2
Matrix Input 3
Matrix Input 4
Matrix Input 5
Matrix Input 6
Matrix Input 7
Matrix Input 8
Matrix Input 9
Matrix Input 10
Matrix Input 11
Matrix Input 12
Matrix Input 13
Matrix Input 14
Matrix Input 15
Matrix Input 16
Matrix Input 17
Matrix Input 18
Matrix Input 19
Matrix Input 20
Matrix Input 21
Matrix Input 22
Matrix Input 23
Matrix Input 24
Matrix Input 25
Matrix Input 26
Matrix Input 27
Matrix Input 28
Matrix Input 29
Matrix Input 30
Matrix Input 31
Matrix Input 32
Matrix Input 33
Matrix Input 34
Matrix Input 35
Matrix Input 36
Matrix Input 37
Matrix Input 38
Matrix Input 39
GND
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
IO0 Digital Input
IO1 Digital Input
IO2 Digital Input
F0
F1
F2
F3
IO3 Digital Input
IO4 Digital Input
IO5 Digital Input
IO8 Digital Input
LUT2_0/DFF0 Output
LUT2_1/DFF1 Output
LUT2_2/DFF2 Output
LUT2_3/PGen Output
LUT3_0/DFF3 Output
LUT3_1/DFF4 Output
LUT3_2/DFF5 Output
LUT3_3/DFF6 Output
LUT3_4/DFF7 Output
LUT3_5/CNT_DLY2(8bit) Output
LUT3_6/CNT_DLY3(8bit) Output
LUT3_7/CNT_DLY4(8bit) Output
LUT3_8/CNT_DLY5(8bit) Output
LUT3_9/CNT_DLY6(8bit) Output
LUT4_0/CNT_DLY0(16bit) Output
LUT4_1/CNT_DLY1(16bit) Output
LUT3_10/Pipe Delay (1st stage) Output
Pipe Delay Output0
Pipe Delay Output1
Fixed "L" output because it is OSC clock. Valid Invalid
Fixed "L" output because it is OSC clock. Valid Invalid
Fixed "L" output because it is OSC clock. Valid Invalid
Filter0/Edge Detect0 Output
Filter1/Edge Detect1 Output
Virtual Input [0]
Valid Invalid
Valid Invalid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
Valid Valid
F4
F4
Virtual Input [1]
Virtual Input [2]
Virtual Input [3]
Virtual Input [4]
Virtual Input [5]
Virtual Input [6]
Virtual Input [7]
Datasheet
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Revision 3.6
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Table 97: Register Map (Continued)
Address
I2C Interface
Signal Function
Byte Register Bit
Register Bit Definition
Read Write
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
Valid Invalid
1960
1961
1962
1963
1964
1965
1966
1967
1968]
1969]
1970]
1971]
1972]
1973]
1974]
1975]
1976]
1977]
1978]
1979]
1980]
Matrix Input 40
Matrix Input 41
Matrix Input 42
Matrix Input 43
Matrix Input 44
Matrix Input 45
Matrix Input 46
Matrix Input 47
Matrix Input 48
Matrix Input 49
Matrix Input 50
Matrix Input 51
Matrix Input 52
Matrix Input 53
Matrix Input 54
Matrix Input 55
Matrix Input 56
Matrix Input 57
Matrix Input 58
Matrix Input 59
Matrix Input 60
RAM_0 Output for ASM-state
RAM_1 Output for ASM-state
RAM_2 Output for ASM-state
RAM_3 Output for ASM-state
RAM_4 Output for ASM-state
RAM_5 Output for ASM-state
RAM_6 Output for ASM-state
RAM_7 Output for ASM-state
IO9 Digital Input
F5
IO10 Digital Input
IO11 Digital Input
IO12 Digital Input
F6
IO13 Digital Input
IO14 Digital Input
IO15 Digital Input
IO16 Digital Input
IO17 Digital Input
ACMP_0 Output
ACMP_1 Output
ACMP_2 Output
F7
ACMP_3 Output
Programmable Delay with Edge Detector
Output
1981]
Matrix Input 61
Valid Invalid
1982]
1983]
Matrix Input 62
Matrix Input 63
Resetb_core
VDD
Valid Invalid
Valid Invalid
Reserved
F8
F9
FA
FB
FC
FD
FE
FF
1991:1984]
1999:1992]
2007:2000]
2015:2008]
2023:2016]
2031:2024]
2039:2032]
2047:2040]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Valid Invalid
Valid Invalid
Valid Invalid
Valid Valid
Valid Invalid
Valid Invalid
Valid Valid
Valid Valid
Datasheet
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Revision 3.6
182 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
21 Package Top Marking Definitions
21.1 MSTQFN 28L 2 MM X 3 MM 0.4P PACKAGE
Part Code
Datecode
COO
Lot
Revision
XXXXX – Part ID Field: identifies the specific device configuration
DD
LLL
C
– Date Code Field: Coded date of manufacture
– Lot Code: Designates Lot #
– Assembly Site/COO: Specifies Assembly Site/Country of Origin
– Revision Code: Device Revision
RR
Datasheet
22-Jul-2021
Revision 3.6
183 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
22 Package Information
22.1 PACKAGE OUTLINES FOR MSTQFN 28L 2 MM X 3 MM 0.4P PACKAGE
JEDEC MO-220
IC Net Weight: TBD g
Marking View
BTM View
Side View
Datasheet
22-Jul-2021
Revision 3.6
184 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
22.2 MSTQFN HANDLING
Be sure to handle MSTQFN package only in a clean, ESD-safe environment. Tweezers or vacuum pick-up tools are suitable for
handling. Do not handle MSTQFN package with fingers as this can contaminate the package pins and interface with solder
reflow.
22.3 SOLDERING INFORMATION
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.30 mm3 (nominal) for
MSTQFN 28L Package. More information can be found at www.jedec.org.
23 Ordering Information
Part Number
SLG46517M
Type
28-pin MSTQFN
SLG46517MTR
28-pin MSTQFN - Tape and Reel (3k units)
23.1 TAPE AND REEL SPECIFICATIONS
Max Units
Leader (min)
Length
Trailer (min)
Length
Nominal
# of
Pins
Reel &
Hub Size
(mm)
Tape Part
Width Pitch
(mm) (mm)
Package Type
Package Size
(mm)
per Reel per Box
Pockets
Pockets
(mm)
(mm)
MSTQFN 28L
2 mm x3 mm
0.4P Green
28
2 x 3 x 0.55
3,000
3,000
178/60
100
400
100
400
8
4
23.2 CARRIER TAPE DRAWING AND DIMENSIONS
Index Hole Index Hole
PocketBTMPocketBTM Pocket Index Hole Pocket Index Hole
to Tape
Edge
to Pocket Tape Width
Center
(mm)
Length
(mm)
Width
(mm)
Depth
(mm)
Pitch
(mm)
Pitch Diameter
(mm)
Package Type
(mm)
(mm)
(mm)
A0
B0
K0
P0
P1
D0
E
F
W
MSTQFN 28L
2 mm x 3 mm
0.4P Green
2.2
3.15
0.76
4
4
1.5
1.75
3.5
8
Refer to EIA-481 specification
Datasheet
22-Jul-2021
Revision 3.6
185 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
24 Layout Guidelines
24.1 MSTQFN 28L 2 MM X 3 MM 0.4P PACKAGE
Marking View
Unit: μm
Datasheet
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Revision 3.6
186 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Glossary
A
ACK
Acknowledge bit
ACMP
ASM
Analog Comparator
Asynchronous State Machine
B
BG
Bandgap
C
CLK
CNT
Clock
Counter
D
DFF
DLY
D Flip-Flop
Delay
E
EC
ESD
Electrical Characteristics
Electrostatic discharge
F
FSM
Finite State Machine
G
GPI
GPIO
GPO
General Purpose Input
General Purpose Input/Output
General Purpose Output
I
IN
IO
Input
Input/Output
L
LSB
LB
Least Significant Bit
Low Bandwidth
Look Up Table
LUT
M
MSB
MUX
Most Significant Bit
Multiplexer
Datasheet
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Revision 3.6
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
N
nRST
NVM
Reset
Non-Volatile Memory
O
OD
Open-Drain
OE
Output Enable
Oscillator
OSC
OTP
OUT
One Time Programmable
Output
P
PD
Power-Down
PGen
POR
PP
Pattern Generator
Power-On Reset
Push-Pull
PVT
PWR
P DLY
Process Voltage Temperature
Power
Programmable Delay
R
R/W
Read/Write
S
SCL
SDA
SLA
I2C Clock Input
I2C Data Input/Output
Slave Address
V
Vref
Voltage Reference
W
WS
Wake and Sleep Controller
Datasheet
22-Jul-2021
Revision 3.6
188 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Revision History
Revision
Date
Description
Removed note from section Vref Load Regulation
Corrected registers [1076:1075], [1084:1083], [1087:1085]
3.6
22-Jul-2021
Updated ACMP Spec
Added note for CNTs
Updated Pins Structure Diagrams
Corrected Reset Command Timing figure
3.5
3.4
17-Aug-2020
29-Aug-2019
Updated register <1328> and register <1359>
Figure Wake/Sleep Timing Diagram added to section Wake and Sleep Controller
Updated section 3-Bit LUT or 8-Bit Counter/Delay Macrocells
Updated section 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells
Fixed typo in Package Outline Drawing
Updated according to new template
Updated IDSS and IGSS
Fixed typos
Corrected registers <1466:1464>
Fixed statement regarding C1 and C2 in OSC section
3.3
3.2
2-Jul-2019
Corrected Dual P-FET Power Switch Block Diagram
Fixed typos
Updated according to Dialog’s Writing Guideline
Corrected 2-bit LUT2 or PGen figure
Added new subsection Electrostatic Discharge Ratings
Updated registers [1047:1045], [1143:1141], [1177:1176], [1636:1632]
Corrected Table Read/Write Protection Options
Updated Oscillator Startup Diagram
22-May-2018
3.1
3.0
13-Aug-2018
12-Jul-2018
Updated registers [1079:1077], registers [1087:1085] in Appendix A
Final version
Datasheet
22-Jul-2021
Revision 3.6
189 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46517
GreenPAK Programmable Mixed-Signal Matrix
with ASM and Dual 44 mΩ/2 A P-FET
Status Definitions
Revision Datasheet Status
Product Status
Definition
1.<n>
Target
Development
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
2.<n>
Preliminary
Qualification
Production
This datasheet contains the specifications and preliminary characterization
data for products in pre-production. Specifications may be changed at any
time without notice in order to improve the design.
3.<n>
4.<n>
Final
This datasheet contains the final specifications for products in volume
production. The specifications may be changed at any time in order to
improve the design, manufacturing and supply. Major specification
changes are communicated via Customer Product Notifications. Datasheet
changes are communicated via www.dialog-semiconductor.com.
Obsolete
Archived
This datasheet contains the specifications for discontinued products. The
information is provided for reference only.
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Datasheet
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Revision 3.6
190 of 190
© 2021 Dialog Semiconductor
CFR0011-120-00
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