SLG46538-AP [DIALOG]
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous State Machine and Dual Supply;
| 型号： | SLG46538-AP |
| 厂家： | 
Dialog Semiconductor |
| 描述： | GreenPAK Programmable Mixed-Signal Matrix with Asynchronous State Machine and Dual Supply |
| 文件： | 总172页 (文件大小：1518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
General Description
The SLG46538-A provides a small, low power component for commonly used Mixed-Signal functions. The user creates their
circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the IO Pins, and the
macrocells of the SLG46538-A. This highly versatile device allows a wide variety of Mixed-Signal functions to be designed within
a very small, low power single integrated circuit.
The additional power supply (VDD2) on the SLG46538-A provides the ability to interface two independent voltage domains within
the same design. Users can configure pins, dedicated to each power supply, as inputs, outputs, or both (controlled dynamically
by internal logic) to both VDD and VDD2 voltage domains. Using the available macrocells designers can implement Mixed-Signal
functions bridging both domains or simply pass through level-translation in both High to Low and Low to High directions.
Two Oscillators
Key Features
Configurable 25 kHz or 2 MHz
25 MHz RC Oscillator
Four Analog Comparators (ACMP)
Two Voltage References (Vref)
Nineteen Combination Function Macrocells
Crystal Oscillator
Power-On Reset
Eight Byte RAM + OTP User Memory
Three Selectable DFF/LATCH or 2-bit LUTs
One Selectable Continuous DFF/LATCH or 3-bit LUT
Four Selectable DFF/LATCH or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
One Selectable Programmable Function Generator or
2-bit LUT
RAM Memory Space that is Readable and Writable via
I2C
User Defined Initial Values Transferred from OTP
Logic & Mixed-Signal Circuits
Highly Versatile Macrocells
Read Back Protection (Read Lock)
Power Supply
Five 8-bit Delays/Counters or 3-bit LUTs
Two 16-bit Delays/Counters or 4-bit LUTs
Two Deglitch Filters with Edge Detectors
1.8 V (±5 %) to 5.0 V (±10 %) VDD
State Machine
1.8 V (±5 %) to 5.0 V (±10 %) VDD2 (VDD2 ≤ VDD
)
Eight States
Operating Temperature Range: -40 °C to 125 °C
RoHS Compliant/Halogen-Free
Available Package
Flexible Input Logic from State Transitions
Serial Communications
I2C Protocol Compliant
20-pin TQFN: 3.5 mm x 3.5 mm x 0.75 mm, 0.5 mm
pitch
Pipe Delay – 16 Stage/3 Output (Part of Combination
Function Macrocell)
AEC-Q100 Grade 1 Qualified
Programmable Delay
Additional Logic Functions
One Inverter
Applications
Infotainment
Navigation
Advanced Driver Assistance Systems (ADAS)
Automotive Display Clusters
Body Electronics
Datasheet
22-Jul-2021
Revision 2.3
1 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Contents
General Description.................................................................................................................................................................1
Key Features.............................................................................................................................................................................1
Applications..............................................................................................................................................................................1
1 Block Diagram ......................................................................................................................................................................9
2 Pinout ..................................................................................................................................................................................10
2.1 Pin Configuration - TQFN- 20L ............................................................................................................................10
3 Characteristics ...................................................................................................................................................................15
3.1 Absolute Maximum Ratings .................................................................................................................................15
3.2 Electrostatic Discharge Ratings ...........................................................................................................................15
3.3 Recommended Operating Conditions .................................................................................................................15
3.4 Electrical Characteristics ......................................................................................................................................16
3.5 I2C Pins Electrical Characteristics ........................................................................................................................22
3.6 Asynchronous State Machine Specification .........................................................................................................22
3.7 Macrocells Current Consumption .........................................................................................................................23
3.8 Timing Characteristics ..........................................................................................................................................23
3.9 OSC Characteristics .............................................................................................................................................25
3.10 ACMP Characteristics ........................................................................................................................................29
3.11 Analog Temperature Sensor Characteristics .....................................................................................................33
4 User Programmability ........................................................................................................................................................36
5 IO Pins .................................................................................................................................................................................37
5.1 Input Modes .........................................................................................................................................................37
5.2 Output Modes .......................................................................................................................................................38
5.3 Pull-Up/Down Resistors .......................................................................................................................................38
5.4 GPI Structure .......................................................................................................................................................38
5.5 Matrix OE IO Structure .........................................................................................................................................39
5.6 Register OE IO Structure .....................................................................................................................................43
6 Connection Matrix ..............................................................................................................................................................46
6.1 Matrix Input Table ...............................................................................................................................................47
6.2 Matrix Output Table ..............................................................................................................................................48
6.3 Connection Matrix Virtual Inputs ..........................................................................................................................52
6.4 Connection Matrix Virtual Outputs .......................................................................................................................52
7 Combination Function Macrocells ....................................................................................................................................53
7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................53
7.2 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................56
7.3 3-Bit LUT or Pipe Delay Macrocell .......................................................................................................................65
7.4 3-Bit LUT or 8-Bit Counter/Delay Macrocells .......................................................................................................67
7.5 4-Bit LUT or 16-Bit Counter/Delay Macrocells .....................................................................................................72
7.6 CNT/DLY/FSM Timing Diagrams .........................................................................................................................76
7.7 2-bit LUT or Programmable Pattern Generator ....................................................................................................84
7.8 Wake and Sleep Controller ..................................................................................................................................85
8 Analog Comparators ..........................................................................................................................................................88
8.1 ACMP0 Block Diagram and Register Settings .....................................................................................................91
8.2 ACMP1 Block Diagram and Register Settings .....................................................................................................92
8.3 ACMP2 Block Diagram and Register Settings .....................................................................................................93
8.4 ACMP3 Block Diagram and Register Settings .....................................................................................................94
9 Pipe Delay ...........................................................................................................................................................................95
10 Programmable Delay/Edge Detector ..............................................................................................................................95
10.1 Programmable Delay Timing Diagram - Edge Detector Output .........................................................................95
11 Additional Logic Function. Deglitch Filter .....................................................................................................................96
11.1 Deglitch Filter/Edge Detector .............................................................................................................................96
11.2 INV Gate ............................................................................................................................................................96
12 Voltage Reference ............................................................................................................................................................97
12.1 Voltage Reference Overview .............................................................................................................................97
12.2 Vref Selection Table ..........................................................................................................................................97
12.3 Vref Block Diagram ..........................................................................................................................................98
Datasheet
22-Jul-2021
Revision 2.3
2 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
12.4 Vref Load Regulation .........................................................................................................................................99
13 Clocking ..........................................................................................................................................................................101
13.1 OSC General Description .................................................................................................................................101
13.2 25 kHz/2 MHz and 25 MHz RC Oscillators ......................................................................................................101
13.3 Oscillators Power-On Delay .............................................................................................................................103
13.4 Oscillators Accuracy .........................................................................................................................................105
14 Crystal Oscillator ...........................................................................................................................................................107
15 Power-On Reset ..............................................................................................................................................................108
15.1 General Operation ............................................................................................................................................108
15.2 POR Sequence ................................................................................................................................................109
15.3 Macrocells Output States During POR Sequence ...........................................................................................109
16 Asynchronous State Machine Macrocell .....................................................................................................................112
16.1 ASM Macrocell Overview .................................................................................................................................112
16.2 ASM Inputs .......................................................................................................................................................113
16.3 ASM Outputs ....................................................................................................................................................115
16.4 Basic ASM Timing ............................................................................................................................................117
16.5 Asynchronous State Machines vs. Synchronous State Machines ...................................................................117
16.6 ASM Power Considerations .............................................................................................................................117
16.7 ASM Logical vs. Physical Design .....................................................................................................................118
16.8 ASM Special Case Timing Considerations ......................................................................................................118
17 I2C Serial Communications Macrocell .........................................................................................................................122
17.1 I2C Serial Communications Macrocell Overview .............................................................................................122
17.2 I2C Serial Communications Device Addressing ...............................................................................................122
17.3 I2C Serial General Timing ................................................................................................................................123
17.4 I2C Serial Communications Commands ..........................................................................................................123
17.5 I2C Serial Command Register Protection .........................................................................................................126
17.6 I2C Additional options ......................................................................................................................................129
18 Analog Temperature Sensor .........................................................................................................................................131
19 External Clocking ...........................................................................................................................................................133
19.1 Crystal Mode ....................................................................................................................................................133
19.2 IO17 or IO15 Source for 25 kHz/2 MHz Clock .................................................................................................133
19.3 IO14 Source for 25 MHz Clock ........................................................................................................................133
20 Register Definitions .......................................................................................................................................................134
20.1 Register Map ....................................................................................................................................................134
21 Package Top Marking Definitions .................................................................................................................................165
21.1 TQFN 20L 3.5 mm x 3.5 mm 0.5P Package ....................................................................................................165
22 Package Information ......................................................................................................................................................166
22.1 Package outlines FOR TQFN 20L 3.5 mm x 3.5 mm 0.5P Package ...............................................................166
22.2 TQFN Handling ................................................................................................................................................167
22.3 Soldering Information .......................................................................................................................................167
23 Ordering Information .....................................................................................................................................................167
23.1 Tape and Reel Specifications ..........................................................................................................................167
23.2 Carrier Tape Drawing and Dimensions ............................................................................................................167
24 Layout Guidelines ..........................................................................................................................................................168
24.1 TQFN 20L 3.5 mm x 3.5 mm 0.5P Package ....................................................................................................168
Glossary................................................................................................................................................................................169
Revision History...................................................................................................................................................................171
Datasheet
22-Jul-2021
Revision 2.3
3 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Figures
Figure 1: Block Diagram.............................................................................................................................................................9
Figure 2: Steps to Create a Custom GreenPAK Device...........................................................................................................36
Figure 3: IO0 GPI Structure Diagram.......................................................................................................................................38
Figure 4: Matrix OE IO Structure Diagram...............................................................................................................................39
Figure 5: Matrix OE IO Structure Diagram...............................................................................................................................40
Figure 6: Matrix OE IO Structure Diagram...............................................................................................................................41
Figure 7: Matrix OE IO 4x Drive Structure Diagram.................................................................................................................42
Figure 8: IO Structure Diagram................................................................................................................................................43
Figure 9: IO Structure Diagram................................................................................................................................................44
Figure 10: IO 4x Drive Structure Diagram................................................................................................................................45
Figure 11: Connection Matrix...................................................................................................................................................46
Figure 12: Connection Matrix Example....................................................................................................................................46
Figure 13: 2-bit LUT0 or DFF0.................................................................................................................................................53
Figure 14: 2-bit LUT1 or DFF1.................................................................................................................................................54
Figure 15: 2-bit LUT2 or DFF2.................................................................................................................................................54
Figure 16: DFF Polarity Operations..........................................................................................................................................56
Figure 17: 3-bit LUT0 or DFF3 with RST/SET..........................................................................................................................57
Figure 18: 3-bit LUT1 or DFF4 with RST/SET..........................................................................................................................57
Figure 19: 3-bit LUT2 or DFF5 with RST/SET..........................................................................................................................58
Figure 20: 3-bit LUT3 or DFF6 with RST/SET..........................................................................................................................58
Figure 21: 3-bit LUT4 or DFF7 with RST/SET..........................................................................................................................59
Figure 22: 3-bit LUT11 or DFF8 with RST/SET........................................................................................................................59
Figure 23: 3-bit LUT12 or DFF9 with RST/SET........................................................................................................................60
Figure 24: 3-bit LUT13 or DFF10 with RST/SET......................................................................................................................60
Figure 25: 3-bit LUT14 or DFF11 with RST/SET......................................................................................................................61
Figure 26: 3-bit LUT15 or DFF12 with RST/SET......................................................................................................................61
Figure 27: 3-bit LUT16 or DFF13 with RST/SET......................................................................................................................62
Figure 28: 3-bit LUT17 or DFF14 with RST/SET......................................................................................................................62
Figure 29: DFF Polarity Operations..........................................................................................................................................65
Figure 30: 3-bit LUT10 or Pipe Delay.......................................................................................................................................66
Figure 31: 3-bit LUT5 or CNT/DLY2.........................................................................................................................................68
Figure 32: 3-bit LUT6 or CNT/DLY3.........................................................................................................................................68
Figure 33: 3-bit LUT7 or CNT/DLY4.........................................................................................................................................69
Figure 34: 3-bit LUT8 or CNT/DLY5.........................................................................................................................................70
Figure 35: 3-bit LUT9 or CNT/DLY6.........................................................................................................................................70
Figure 36: 4-bit LUT0 or CNT/DLY0.........................................................................................................................................73
Figure 37: 4-bit LUT1 or CNT/DLY1.........................................................................................................................................74
Figure 38: Delay Mode Timing Diagram...................................................................................................................................76
Figure 39: Counter Mode Timing Diagram...............................................................................................................................76
Figure 40: One-Shot Function Timing Diagram........................................................................................................................77
Figure 41: Frequency Detection Mode Timing Diagram...........................................................................................................79
Figure 42: Edge Detection Mode Timing Diagram...................................................................................................................80
Figure 43: Delay Mode Timing Diagram...................................................................................................................................81
Figure 44: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3.....81
Figure 45: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3 .........82
Figure 46: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3.....82
Figure 47: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3 .........83
Figure 48: Counter Value, Counter Data = 3............................................................................................................................83
Figure 49: 2-bit LUT3 or PGen.................................................................................................................................................84
Figure 50: PGen Timing Diagram.............................................................................................................................................85
Figure 51: Wake/Sleep Controller............................................................................................................................................86
Datasheet
22-Jul-2021
Revision 2.3
4 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Figure 52: Maximum Power-On Delay vs. VDD, BG = Auto-delay ...........................................................................................88
Figure 53: Max Power-On Delay vs. VDD, BG = 550 µs..........................................................................................................89
Figure 54: Max Power-On Delay vs. VDD, BG = 100 µs...........................................................................................................89
Figure 55: Typical Buffer Input Voltage Offset vs. Voltage Reference.....................................................................................90
Figure 56: Typical Input Threshold Variation (Including Vref Variation, ACMP Offset) vs. Voltage Reference........................90
Figure 57: ACMP0 Block Diagram ...........................................................................................................................................91
Figure 58: ACMP1 Block Diagram ...........................................................................................................................................92
Figure 59: ACMP2 Block Diagram ...........................................................................................................................................93
Figure 60: ACMP3 Block Diagram ...........................................................................................................................................94
Figure 61: Programmable Delay ..............................................................................................................................................95
Figure 62: Edge Detector Output .............................................................................................................................................95
Figure 63: Deglitch Filter/Edge Detector..................................................................................................................................96
Figure 64: INV Gate .................................................................................................................................................................96
Figure 65: Voltage Reference Block Diagram..........................................................................................................................98
Figure 66: Typical Load Regulation, Vref = 600 mV, T = -40 °C to +125 °C, Buffer - Enable..................................................99
Figure 67: Typical Load Regulation, Vref = 1000 mV, T = -40 °C to +125 °C, Buffer - Enable................................................99
Figure 68: Typical Load Regulation, Vref = 1200 mV, T = -40 °C to +125 °C, Buffer - Enable..............................................100
Figure 69: 25 kHz/2 MHz RC OSC Block Diagram ................................................................................................................102
Figure 70: 25 MHz RC OSC Block Diagram ..........................................................................................................................102
Figure 71: Oscillator Startup Diagram....................................................................................................................................103
Figure 72: RC Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 2 MHz .................................................103
Figure 73: RC Oscillator Maximum Power-On Delay vs. VDD at T = 125 °C, OSC0 = 25 kHz ..............................................104
Figure 74: OSC1 (25 MHz) Maximum Power-On Delay vs. VDD at T = 125 °C.....................................................................104
Figure 75: RC Oscillator Frequency vs. Temperature, RC OSC0 = 2 MHz ...........................................................................105
Figure 76: RC Oscillator Frequency vs. Temperature, RC OSC0 = 25 kHz ..........................................................................105
Figure 77: OSC1 (25 MHz) Frequency vs. Temperature .......................................................................................................106
Figure 78: Crystal OSC Block Diagram..................................................................................................................................107
Figure 79: External Crystal Connection..................................................................................................................................107
Figure 80: POR Sequence.....................................................................................................................................................109
Figure 81: Internal Macrocell States during POR Sequence..................................................................................................110
Figure 82: Power-Down..........................................................................................................................................................111
Figure 83: Asynchronous State Machine State Transitions ...................................................................................................112
Figure 84: Asynchronous State Machine ...............................................................................................................................113
Figure 85: Asynchronous State Machine Inputs.....................................................................................................................114
Figure 86: Maximum 3 State Transitions into Given State.....................................................................................................114
Figure 87: Maximum 7 State Transitions out of a Given State...............................................................................................115
Figure 88: Connection Matrix Output RAM ............................................................................................................................116
Figure 89: State Transition.....................................................................................................................................................117
Figure 90: State Transition Timing.........................................................................................................................................117
Figure 91: State Transition.....................................................................................................................................................118
Figure 92: State Transition Timing and Power Consumption.................................................................................................118
Figure 93: State Transition.....................................................................................................................................................118
Figure 94: State Transition Pulse Input Timing......................................................................................................................119
Figure 95: State Transition - Competing Inputs......................................................................................................................119
Figure 96: State Transition Timing - Competing Inputs Indeterminate...................................................................................119
Figure 97: State Transition Timing - Competing Inputs Determinable ...................................................................................120
Figure 98: State Transition - Sequential.................................................................................................................................120
Figure 99: State Transition - Sequential Timing.....................................................................................................................120
Figure 100: State Transition - Closed Cycling........................................................................................................................121
Figure 101: State Transition - Closed Cycling Timing............................................................................................................121
Figure 102: Basic Command Structure..................................................................................................................................122
Figure 103: I2C General Timing Characteristics ....................................................................................................................123
Figure 104: Byte Write Command, R/W = 0...........................................................................................................................123
Datasheet
22-Jul-2021
Revision 2.3
5 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Figure 105: Sequential Write Command................................................................................................................................124
Figure 106: Current Address Read Command, R/W = 1........................................................................................................124
Figure 107: Random Read Command ...................................................................................................................................125
Figure 108: Sequential Read Command................................................................................................................................125
Figure 109: Register Bank Map..............................................................................................................................................126
Figure 110: Reset Command Timing .....................................................................................................................................129
Figure 111: Analog Temperature Sensor Structure Diagram.................................................................................................131
Figure 112: TS Output vs. Temperature, VDD = 1.71 V to 5.5 V............................................................................................132
Datasheet
22-Jul-2021
Revision 2.3
6 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Tables
Table 1: Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2: Pin Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4: Electrostatic Discharge Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6: EC at T = -40 °C to 125 °C, VDD = 1.71 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . . . . . . . . . . . 16
Table 7: EC at T = -40 °C to 125 °C, VDD = 1.71 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . . . . . . . . . . . 19
Table 8: I2C Pins Timing Characteristics at T = -40 °C to 125 °C Unless Otherwise Noted . . . . . . . . . . . . . . . . . 22
Table 9: Asynchronous State Machine Specifications at T = -40 °C to 125 °C Unless Otherwise Noted. . . . . . . . . . . 22
Table 10: Typical Current Estimated for Each Macrocell at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11: Typical Delay Estimated for Each Macrocell at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12: Typical Propagations Delays and Pulse Widths at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13: Typical Pulse Width Performance at T = 25 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14: Typical Counter/Delay Offset Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15: 25 kHz RC OSC0 Frequency Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 16: 25 kHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value) . . . . . . . . . . . . . . . . . 25
Table 17: 2 MHz RC OSC0 Frequency Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18: 2 MHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value) . . . . . . . . . . . . . . . . . 26
Table 19: 25 MHz RC OSC1 Frequency Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20: 25 MHz RC OSC1 Frequency Error (Error Calculated Relative to Nominal Value) . . . . . . . . . . . . . . . . 26
Table 21: OSC Power-On Delay, T = 25 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 22: OSC Power-On Delay, T = 25 °C, Fast Start-Up Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 23: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V, Unless Otherwise Noted . . . . . . . . . . 29
Table 24: TS Output vs Temperature (Output Range 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 25: TS Output vs Temperature (Output Range 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 26: TS Output Error (Output Range 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 27: TS Output Error (Output Range 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 28: Matrix Input Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 29: Matrix Output Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 30: Connection Matrix Virtual Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 31: 2-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 32: 2-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 33: 2-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34: 2-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 35: 3-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 36: 3-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 37: 3-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 38: 3-bit LUT3 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 39: 3-bit LUT4 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 40: 3-bit LUT11 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 41: 3-bit LUT12 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 42: 3-bit LUT13 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 43: 3-bit LUT14 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 44: 3-bit LUT15 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 45: 3-bit LUT16 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 46: 3-bit LUT17 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 47: 3-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 48: 3-bit LUT10 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 49: Pipe Delay Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 50: 3-bit LUT5 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 51: 3-bit LUT6 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 52: 3-bit LUT7 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 53: 3-bit LUT8 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 54: 3-bit LUT9 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 55: 3-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 56: 4-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 57: 4-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 58: 4-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 59: DLY/CNTx One-Shot/Freq. Detect Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 60: Gain Divider Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 61: Gain Divider Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 62: Built-In Hysteresis Tolerance at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 63: Vref Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 64: External Components Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 65: ASM Editor - Connection Matrix Output RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 66: Read/Write Protection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 67: RAM Array Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 68: Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
1
Block Diagram
IO17
IO15
IO16
IO14
IO13
IO12
V
DD
Combination Function Macrocells
ACMP0
IO0
Additional Logic
Functions
2-bit
LUT2_0
or DFF0
2-bit
LUT2_1
or DFF1
2-bit
LUT2_2
or DFF2
FILTER_1
with
Edge
FILTER_0
with
INV
Edge
Detect
Detect
2-bit
LUT2_3
or PGen
3bit
LUT3_0
or DFF3
3-bit
LUT3_1
or DFF4
ACMP1
IO1
3-bit
LUT3_2
or DFF5
3-bit
LUT3_3
or DFF6
3-bit
LUT3_4
or DFF7
Programmable
Delay
POR
Vref
V
DD2
IO2
ACMP2
3-bit
LUT3_5 or
CNT/DLY2
3-bit
LUT3_6 or
CNT/DLY3
3-bit
LUT3_7 or
CNT/DLY4
State Machine
8 states
IO10
IO9
IO3
3-bit
3-bit
4-bit
LUT4_0 or
CNT/DLY0
LUT3_8 or
CNT/DLY5
LUT3_9 or
CNT/DLY6
RC Oscillator
25M Oscillator
ACMP3
I2C Serial
Communication
4-bit
LUT4_1 or
CNT/DLY1
3-bit
LUT3_10 or
Pipe Delay
IO4
8 Byte RAM +
OTP Memory
Crystal
Oscillator
Crystal
Oscillator
GND
IO5
IO6
IO8
IO7
Figure 1: Block Diagram
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
2
Pinout
2.1 PIN CONFIGURATION - TQFN- 20L
Pin # Signal Name Pin Functions
1
2
V
Power Supply
GPI
DD
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
GND
IO9
IO10
3
GPIO with OE
GPIO
20 19
18
17
16
4
5
GPIO with OE
GPIO/ACMP0+
GPIO with OE/ACMP0-
GPIO/SCL
15
14
IO12
VDD2
1
2
3
4
5
VDD
IO0
IO1
IO2
IO3
6
7
8
13 IO10
TP
9
GPIO/SDA
12
IO9
10
11
12
13
14
15
16
17
18
19
20
TP
GPIO with OE/ACMP1+
GND
11
GND
GPIO/ACMP0-/ACMP1-/ACMP2-/ACMP3-
GPIO with OE/ACMP2+/ACMP3+
Power Supply
6
7
8
9
10
V
DD2
IO12
GPIO/ACMP3+
IO13
IO14
IO15
IO16
IO17
--
GPIO with OE/XTAL0
TQFN-20
(Top View)
GPIO/XTAL1/EXT_CLK0
GPIO with OE/Vref0/EXT_CLK1
GPIO with OE/Vref0
GPIO/EXT_CLK2
Leave unconnected or connect to GND
Legend:
OE: Output Enable
ACMPx+: ACMPx Positive Input
ACMPx-: ACMPx Negative Input
SCL: I2C Clock Input
SDA: I2C Data Input/Output
Vrefx: Voltage Reference Output
EXT_CLKx: External Clock Input
XTALx: Crystal
TP: Thermal Pad. Thermal Pad is not connected to any pin, but it can
be connected to GND for better thermal performance.
Table 1: Functional Pin Description
TQFN
20L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
1
VDD
VDD
Power Supply
--
--
Digital Input without
Schmitt Trigger
--
IO0
General Purpose Input
Digital Input
with Schmitt Trigger
--
2
IO0
Low Voltage Digital Input
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
3
IO1
IO1
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
Low Voltage Digital Input
--
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 1: Functional Pin Description (Continued)
TQFN
20L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
4
5
IO2
IO3
IO2
IO3
IO4
General Purpose IO
Open-Drain PMOS
(1x) (2x)
Low Voltage Digital Input
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
Low Voltage Digital Input
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
General Purpose IO
6
IO4
Open-Drain PMOS
(1x) (2x)
Low Voltage Digital Input
Analog
Analog Comparator 0
Positive Input
ACMP0+
IO5
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
7
IO5
Low Voltage Digital Input
--
Analog Comparator 0
Negative Input
ACMP0-
IO6
Analog
--
Digital Input without
Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
General Purpose IO
I2C Serial Clock
Digital Input
with Schmitt Trigger
--
Low Voltage Digital Input
--
Digital Input without
Schmitt Trigger
8
IO6
Open-Drain NMOS
SCL
IO7
Digital Input
with Schmitt Trigger
Open-Drain NMOS
Open-Drain NMOS
Low Voltage Digital Input
Digital Input without
Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
General Purpose IO
I2C Serial Data
Digital Input
with Schmitt Trigger
--
Low Voltage Digital Input
--
Digital Input without
Schmitt Trigger
9
IO7
Open-Drain NMOS
SDA
Digital Input
with Schmitt Trigger
Open-Drain NMOS
Open-Drain NMOS
Low Voltage Digital Input
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 1: Functional Pin Description (Continued)
TQFN
20L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x) (4x)
IO8
10
11
IO8
Open-Drain PMOS
(1x) (2x)
Low Voltage Digital Input
Analog Comparator 1
Positive Input
ACMP1+
GND
Analog
--
--
GND
Ground
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
IO9
General Purpose IO
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x) (4x)
12
IO9
Low Voltage Digital Input
--
Analog Comparator
Negative Input
EXT_Vref
IO10
Analog
--
Digital Input without Schmitt Trigger Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
Low Voltage Digital Input
--
Analog Comparator 2
Positive Input
13
14
IO10
VDD2
ACMP2+
Analog
--
Analog Comparator 3
Positive Input
ACMP3+
VDD2
Analog
--
--
Power Supply
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
IO12
General Purpose IO
15
IO12
Open-Drain PMOS
(1x) (2x)
Low Voltage Digital Input
Analog
Analog Comparator 3
Positive Input
ACMP3+
IO13
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
16
IO13
Low Voltage Digital Input
--
External Crystal
Connection 0
XTAL0
--
Analog
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 1: Functional Pin Description (Continued)
TQFN
20L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
IO14
General Purpose IO
Open-Drain PMOS
(1x) (2x)
Low Voltage Digital Input
Analog
17
IO14
External Crystal
Connection 1
XTAL1
--
--
Digital Input without
Schmitt Trigger
External Clock
Connection 0
EXT_CLK0
Digital Input
with Schmitt Trigger
--
--
Low Voltage Digital Input
Digital Input without Schmitt Trigger Push-Pull (1x) (2x)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
General Purpose IO
with OE (Note 1)
IO15
Vref0
Low Voltage
Digital Input
--
Analog
--
Voltage Reference 0
Output
18
IO15
--
Digital Input without
Schmitt Trigger
External Clock
Connection 1
EXT_CLK1
Digital Input
with Schmitt Trigger
--
Low Voltage Digital Input
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
IO16
Vref0
IO17
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
19
IO16
Low Voltage Digital Input
--
--
Voltage Reference 0 Output
General Purpose IO
Analog
Digital Input without Schmitt Trigger Push-Pull (1x) (2x)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
Low Voltage
Digital Input
Open-Drain PMOS
(1x) (2x)
20
IO17
Digital Input without Schmitt Trigger
--
Digital Input
with Schmitt Trigger
External Clock Connection
2
--
EXT_CLK2
Low Voltage
Digital Input
--
--
Thermal Pad. Leave un-
connected or connect to
GND.
TP
TP
--
--
Note 1 General Purpose IO's with OE can be used to implement bidirectional signals under user control via Connection Matrix
to OE signal in IO structure.
Datasheet
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© 2021 Dialog Semiconductor
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 2: Pin Type Definitions
Pin Type
VDD
Description
Power Supply
Input/Output
Ground
IO
GND
VDD2
NC
Power Supply 2
No Connection
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
3
Characteristics
3.1 ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability.
Table 3: Absolute Maximum Ratings
Parameter
Min
-0.5
-0.5
Max
7
Unit
V
Supply voltage on VDD relative to GND
Supply voltage on VDD2 relative to GND
VDD + 0.5
V
IOs 0, 1, 2, 3, 4, 5, 6, 7, 8
VDD + 0.5
DC Input voltage
GND - 0.5
V
IOs 9, 10, 12, 13, 14, 15, 16, 17
TJ = 85 °C
VDD2 + 0.5
45
--
--
mA
mA
mA
mA
mA
mA
Maximum Average or DC Current Through
VDD Pin (per chip side)
TJ = 110 °C
TJ = 85 °C
22
--
45
Maximum Average or DC Current Through
VDD2 Pin (per chip side)
TJ = 110 °C
TJ = 85 °C
--
22
--
86
Maximum Average or DC Current Through
GND Pin (per chip side)
TJ = 110 °C
Push-Pull 1x
Push-Pull 2x
OD 1x
--
41
--
11
--
16
Maximum Average or DC Current
(Through pin)
--
11
mA
OD 2x
--
21
OD 4x
--
43
Current at Input Pin
-1.0
--
1.0
1000
150
150
mA
nA
°C
Input leakage (Absolute Value)
Storage Temperature Range
Junction Temperature
-65
--
°C
Moisture Sensitivity Level
1
Supply voltage on VDD relative to GND
-0.5
7
V
3.2 ELECTROSTATIC DISCHARGE RATINGS
Table 4: Electrostatic Discharge Ratings
Parameter
Min
2000
500
Max
--
Unit
V
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
--
V
3.3 RECOMMENDED OPERATING CONDITIONS
Table 5: Recommended Operating Conditions
Parameter
Condition
Min
1.71
1.71
-40
Max
5.5
Unit
V
Supply Voltage (VDD
)
Supply Voltage 2 (VDD2
Operating Temperature
Programming Voltage
)
VDD2 ≤ VDD
VDD
125
7.75
V
°C
V
7.25
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 5: Recommended Operating Conditions(Continued)
Parameter
Condition
Min
Max
Unit
Maximal Voltage Applied to any PIN in High
Impedance State
--
VDD
V
Capacitor Value at VDD
0.1
0
--
μF
V
Analog Input Common Mode Range
Allowable Input Voltage atAnalog Pins
VDD
3.4 ELECTRICAL CHARACTERISTICS
Table 6: EC at T = -40 °C to 125 °C, VDD = 1.71 V to 5.5 V Unless Otherwise Noted
Parameter Description
VACMP ACMP Input Voltage Range
Condition
Min
Typ
--
Max
VDD
1.2
Unit
Positive Input
Negative Input
0
0
V
V
--
0.7x
VDD
(Note 2)
VDD
0.3
(Note 2)
+
Logic Input (Note 1)
--
--
--
--
--
V
V
V
V
V
0.8x
VDD
(Note 2)
VDD+
0.3
(Note 2)
HIGH-Level Input Voltage
IOs 0, 1, 2, 3, 4, 5, 6, 7, 8
VIH
Logic Input with Schmitt Trigger
Low-Level Logic Input (Note 1)
Logic Input (Note 1)
VDD+
1.25
0.3
(Note 2)
0.3x
VDD
(Note 2)
GND-
0.3
LOW-Level Input Voltage
IOs 0, 1, 2, 3, 4, 5, 6, 7, 8
0.2x
VDD
(Note 2)
GND-
0.3
VIL
Logic Input with Schmitt Trigger
GND-
0.3
Low-Level Logic Input (Note 1)
--
0.5
0.66
0.94
1.38
--
V
V
Logic Input with Schmitt Trigger,
VDD = 1.8 V ± 5 %
0.10
0.29
0.44
1.69
2.74
4.15
1.69
2.74
4.16
0.41
0.62
0.90
1.79
3.12
4.76
1.79
3.12
4.76
Schmitt Trigger Hysteresis
Voltage
Logic Input with Schmitt Trigger,
VDD = 3.3 V ± 10 %
VHYS
IOs 0, 1, 2, 3, 4, 5, 6, 7, 8
Logic Input with Schmitt Trigger,
V
DD = 5.0 V ± 10 %
Push-Pull, IOH = 100 μA, 1x Drive,
VDD = 1.8 V ± 5 %
V
V
V
V
V
V
Push-Pull, IOH = 3 mA, 1x Drive,
VDD = 3.3 V ± 10 %
--
Push-Pull, IOH = 5 mA, 1x Drive,
VDD = 5.0 V ± 10 %
--
HIGH-Level Output Voltage
IOs 0, 1, 2, 3, 4, 5, 6, 7, 8
VOH
PMOS OD, IOH = 100 μA, 1x Drive,
VDD = 1.8 V ± 5 %
--
PMOS OD, IOH = 3 mA, 1x Drive,
VDD = 3.3 V ± 10 %
--
PMOS OD, IOH = 5 mA, 1x Drive,
VDD = 5.0 V ± 10 %
--
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 6: EC at T = -40 °C to 125 °C, VDD = 1.71 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, IOH = 100 μA, 2x Drive,
1.70
1.79
--
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD = 1.8 V ± 5 %
Push-Pull, IOH = 3 mA, 2x Drive,
VDD = 3.3 V ± 10 %
2.87
4.32
1.70
2.87
4.33
--
3.21
4.89
1.79
3.21
4.89
0.01
0.13
0.19
0.01
0.06
0.09
0.01
0.08
0.12
0.01
0.04
0.07
0.001
0.02
0.03
--
--
Push-Pull, IOH = 5 mA, 2x Drive,
VDD = 5.0 V ± 10 %
HIGH-Level Output Voltage
IOs 0, 1, 2, 3, 4, 5, 6, 7, 8
VOH
PMOS OD, IOH = 100 μA, 2x Drive,
VDD = 1.8 V ± 5 %
--
PMOS OD, IOH = 3 mA, 2x Drive,
VDD = 3.3 V ± 10 %
--
PMOS OD, IOH = 5 mA, 2x Drive,
VDD = 5.0 V ± 10 %
--
Push-Pull, IOL= 100 μA, 1x Drive,
VDD = 1.8 V ± 5 %
0.03
0.23
Push-Pull, IOL= 3 mA, 1x Drive,
VDD = 3.3 V ± 10 %
--
Push-Pull, IOL= 5 mA, 1x Drive,
VDD = 5.0 V ± 10 %
--
0.24
Push-Pull, IOL = 100 μA, 2x Drive,
VDD = 1.8 V ± 5 %
--
0.01
0.11
Push-Pull, IOL = 3 mA, 2x Drive,
VDD = 3.3 V ± 10 %
--
Push-Pull, IOL =5 mA, 2x Drive,
VDD = 5.0 V ± 10 %
--
0.12
Open-Drain, IOL = 100 μA, 1x Drive,
VDD = 1.8 V ± 5 %
--
0.02
0.15
LOW-Level Output Voltage
IOs 0, 1, 2, 3, 4, 5, 6, 7, 8
Open-Drain, IOL = 3 mA, 1x Drive,
VDD = 3.3 V ± 10 %
VOL
--
Open-Drain, IOL = 5 mA, 1x Drive,
VDD = 5.0 V ± 10 %
--
0.16
Open-Drain, IOL = 100 μA, 2x Drive,
VDD = 1.8 V ± 5 %
--
0.02
0.08
Open-Drain, IOL = 3 mA, 2x Drive,
VDD = 3.3 V ± 10 %
--
Open-Drain, IOL = 5 mA, 2x Drive,
VDD = 5.0 V ± 10 %
--
0.08
Open-Drain NMOS 4x, IO8,
--
0.002
0.04
0.05
IOL = 100 μA, VDD = 1.8 V ± 5 %
Open-Drain NMOS 4x, IO8,
IOL = 3 mA, VDD = 3.3 V ± 10 %
--
Open-Drain NMOS 4x, IO8,
IOL = 5 mA, VDD = 5.0 V ± 10 %
--
Datasheet
22-Jul-2021
Revision 2.3
17 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 6: EC at T = -40 °C to 125 °C, VDD = 1.71 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, VOH = VDD - 0.2, 1x Drive,
VDD = 1.8 V ± 5 %
1.07
1.70
--
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Push-Pull, VOH = 2.4 V, 1x Drive,
VDD = 3.3 V ± 10 %
6.05
22.08
1.07
12.08
34.04
1.70
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Push-Pull, VOH = 2.4 V, 1x Drive,
VDD = 5.0 V ± 10 %
PMOS OD, VOH = VDD - 0.2, 1x Drive,
VDD = 1.8 V ± 5 %
PMOS OD, VOH = 2.4 V, 1x Drive,
VDD = 3.3 V ± 10 %
6.05
12.08
34.04
3.41
PMOS OD, VOH = 2.4 V, 1x Drive,
VDD = 5.0 V ± 10 %
22.08
2.22
HIGH-Level Output Pulse
Current (Note 3)
IOH
Push-Pull, VOH = VDD - 0.2, 2x Drive,
VDD = 1.8 V ± 5 %
IOs 0, 1, 2, 3, 4, 5, 6, 7, 8
Push-Pull, VOH = 2.4 V, 2x Drive,
VDD = 3.3 V ± 10 %
11.54
41.76
2.22
24.16
68.08
3.41
Push-Pull, VOH = 2.4 V, 2X Drive,
VDD = 5.0 V ± 10 %
PMOS OD, VOH = VDD - 0.2, 2x Drive,
VDD = 1.8 V ± 5 %
PMOS OD, VOH = 2.4 V, 2x Drive,
VDD = 3.3 V ± 10 %
11.52
41.69
0.92
24.16
68.08
1.69
PMOS OD, VOH = 2.4 V, 2x Drive,
VDD = 5.0 V ± 10 %
Push-Pull, VOL = 0.15 V, 1x Drive,
VDD = 1.8 V ± 5 %
Push-Pull, VOL = 0.4 V, 1x Drive,
VDD = 3.3 V ± 10 %
4.88
8.24
Push-Pull, VOL = 0.4 V, 1X Drive,
VDD = 5.0 V ± 10 %
7.22
11.58
3.38
Push-Pull, VOL = 0.15 V, 2x Drive,
VDD = 1.8 V ± 5 %
1.83
Push-Pull, VOL = 0.4 V, 2x Drive,
VDD = 3.3 V ± 10 %
9.75
16.49
23.16
2.53
Push-Pull, VOL = 0.4 V, 2X Drive,
VDD = 5.0 V ± 10 %
13.83
1.38
LOW-Level Output Pulse
Current (Note 3)
IOL
Open-Drain, VOL = 0.15 V, 1x Drive,
VDD = 1.8 V ± 5 %
IOs 0, 1, 2, 3, 4, 5, 6, 7, 8
Open-Drain, VOL = 0.4 V, 1x Drive,
VDD = 3.3 V ± 10 %
7.31
12.37
17.38
5.07
Open-Drain, VOL = 0.4 V, 1X Drive,
VDD = 5.0 V ± 10 %
10.82
2.75
Open-Drain, VOL = 0.15 V, 2x Drive,
VDD = 1.8 V ± 5 %
Open-Drain, VOL = 0.4 V, 2x Drive,
VDD = 3.3 V ± 10 %
14.54
17.34
24.74
34.76
Open-Drain, VOL = 0.4 V, 2X Drive,
VDD = 5.0 V ± 10 %
Datasheet
22-Jul-2021
Revision 2.3
18 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 6: EC at T = -40 °C to 125 °C, VDD = 1.71 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Open-Drain NMOS 4x, IO8,
VOL = 0.15 V, VDD = 1.8 V ± 5 %
7.21
9.00
--
mA
mA
mA
LOW-Level Output Pulse
Current (Note 3)
Open-Drain NMOS 4x, IO8,
VOL = 0.4 V, VDD = 3.3 V ± 10 %
IOL
31.32
41.06
41.06
55.18
--
--
IOs 0, 1, 2, 3, 4, 5, 6, 7, 8
Open-Drain NMOS 4X, IO8,
VOL = 0.4 V, VDD = 5.0 V ± 10 %
TSU
Startup Time
From VDD rising past PONTHR
0.61
1.41
1.24
1.54
1.65
1.66
ms
V
PONTHR Power-On Threshold
VDD Level Required to Start Up the Chip
VDD Level Required to Switch Off the
Chip
POFFTHR Power-Off Threshold
1.00
1.15
1.31
V
1 M Pull-up
873.2
85.17
9.61
1094.7 1364.3
109.30 135.52
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
RPUP
Pull-up Resistance
100 k Pull-up
10 k Pull-up
11.86
14.73
1 M Pull-down
100 k Pull-down
10 k Pull-down
862.5
87.95
8.66
1096.3 1357.4
109.76 136.06
RPDWN
Pull-down Resistance
11.81
15.05
Note 1 No hysteresis.
Note 2 The GreenPAK’s power rails are divided in two sides. IOs 0, 1, 2, 3, 4, 5, 6, 7, and 8 are connected to one side, IOs 9,
10, 12, 13, 14, 15, 16, and 17 to another.
Note 3 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
Table 7: EC at T = -40 °C to 125 °C, VDD = 1.71 V to 5.5 V Unless Otherwise Noted
Parameter Description
Condition
Min
Typ
Max
Unit
0.7x
VDD
(Note 2)
VDD+
0.3
(Note 2)
Logic Input (Note 1)
--
V
HIGH-Level Input Voltage
IOs 9, 10, 12, 13, 14, 15, 16, Logic Input with Schmitt Trigger
17
0.8x
VDD
(Note 2)
VDD+
0.3
(Note 2)
VIH2
--
--
--
--
V
V
V
V
VDD+
Low-Level Logic Input (Note 1)
1.25
0.3
(Note 2)
0.3x
VDD
(Note 2)
GND-
0.3
Logic Input (Note 1)
LOW-Level Input Voltage
IOs 9, 10, 12, 13, 14, 15, 16,
17
0.2x
VDD
(Note 2)
GND-
0.3
VIL2
Logic Input with Schmitt Trigger
GND-
0.3
Low-Level Logic Input (Note 1)
--
0.5
V
V
V
V
Logic Input with Schmitt Trigger,
VDD2 = 1.8 V ± 5 %
0.10
0.29
0.29
0.41
0.62
0.62
0.66
0.94
0.94
Schmitt Trigger Hysteresis
Voltage
Logic Input with Schmitt Trigger,
IOs 9, 10, 12, 13, 14, 15, 16, VDD2 = 3.3 V ± 10 %
VHYS
17
Logic Input with Schmitt Trigger,
V
DD2 = 5.0 V ± 10 %
Datasheet
22-Jul-2021
Revision 2.3
19 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 7: EC at T = -40 °C to 125 °C, VDD = 1.71 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull 1x, Open-Drain PMOS 1x,
IOH = 100 μA, VDD2 = 1.8 V ± 5 %
1.68
1.79
--
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Push-Pull, IOH = 3 mA, 1x Drive,
VDD2 = 3.3 V ± 10 %
2.70
2.70
4.15
1.70
2.85
2.86
4.32
--
3.12
3.12
4.76
1.79
3.21
3.21
4.89
0.010
0.13
0.19
0.007
0.06
0.09
0.007
0.08
0.12
0.003
0.04
0.07
0.001
0.02
0.03
--
--
PMOS OD, IOH = 3 mA, 1x Drive,
VDD2 = 3.3 V ± 10 %
Push-Pull, PMOS OD, IOH = 3 mA,
1x Drive, VDD2 = 5.0 V ± 10 %
--
HIGH-Level Output Voltage
IOs 9, 10, 12, 13, 14, 15, 16,
17
VOH2
Push-Pull 2x, Open-Drain PMOS 2x,
IOH = 100 μA, VDD2 = 1.8 V ± 5 %
--
Push-Pull, IOH = 3 mA, 2x Drive,
VDD2 = 3.3 V ± 10 %
--
PMOS OD, IOH = 3 mA, 2x Drive,
VDD2 = 3.3 V ± 10 %
--
Push-Pull, PMOS OD, IOH = 3 mA,
2x Drive, VDD2 = 5.0 V ± 10 %
--
Push-Pull 1x,
IOL= 100 μA, VDD2 = 1.8 V ± 5 %
0.015
0.23
0.24
0.010
0.11
0.12
0.010
0.15
0.16
0.010
0.08
0.08
0.004
0.04
0.05
Push-Pull, IOL= 3 mA, 1x Drive,
VDD2 = 3.3 V ± 10 %
--
Push-Pull, IOL= 3 mA, 1x Drive,
VDD2 = 5.0 V ± 10 %
--
Push-Pull 2x,
IOL = 100 μA, VDD2 = 1.8 V ± 5 %
--
Push-Pull, IOL = 3 mA, 2x Drive,
VDD2 = 3.3 V ± 10 %
--
Push-Pull, IOL = 3 mA, 2x Drive,
VDD2 = 5.0 V ± 10 %
--
Open-Drain NMOS 1x,
IOL = 100 μA, VDD2 = 1.8 V ± 5 %
--
LOW-Level Output Voltage
IOs 9, 10, 12, 13, 14, 15, 16,
17
Open-Drain, IOL = 3 mA, 1x Drive,
VDD2 = 3.3 V ± 10 %
VOL2
--
Open-Drain NMOS, IOL= 3 mA, 1x Drive,
VDD2 = 5.0 V ± 10 %
--
Open-Drain NMOS 2x,
IOL = 100 μA, VDD2 = 1.8 V ± 5 %
--
Open-Drain, IOL = 3 mA, 2x Drive,
VDD2 = 3.3 V ± 10 %
--
Open-Drain NMOS, IOL= 3 mA, 2x Drive,
VDD2 = 5.0 V ± 10 %
--
Open-Drain NMOS 4x, IO9,
IOL = 100 μA, VDD2 = 1.8 V ± 5 %
--
Open-Drain NMOS 4x, IO9,
IOL = 3 mA, VDD2 = 3.3 V ± 10 %
--
Open-Drain NMOS 4x, IO9,
IOL = 3 mA, VDD2 = 5.0 V ± 10 %
--
Datasheet
22-Jul-2021
Revision 2.3
20 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 7: EC at T = -40 °C to 125 °C, VDD = 1.71 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull 1x,Open-Drain PMOS 1x,
VOH = VDD - 0.2, VDD2 = 1.8 V ± 5 %
1.03
1.70
--
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Push-Pull, VOH = 2.4 V, 1x Drive,
VDD2 = 3.3 V ± 10 %
6.05
22.08
6.05
12.08
34.04
12.08
34.04
3.41
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Push-Pull, VOH = 2.4 V, 1x Drive,
VDD2 = 5.0 V ± 10 %
PMOS OD, VOH = 2.4 V, 1x Drive,
VDD2 = 3.3 V ± 10 %
PMOS OD, VOH = 2.4 V, 1x Drive,
VDD2 = 5.0 V ± 10 %
HIGH-Level Output Pulse
22.08
2.03
Current (Note 3)
IOs 9, 10, 12, 13, 14, 15, 16,
17
IOH2
Push-Pull 2x, Open-Drain PMOS 2x,
VOH = VDD - 0.2, VDD2 = 1.8 V ± 5 %
Push-Pull, VOH = 2.4 V, 2x Drive,
VDD2 = 3.3 V ± 10 %
11.54
41.76
11.52
41.69
0.92
24.16
68.08
24.16
68.08
1.66
Push-Pull, VOH = 2.4 V, 2x Drive,
VDD2 = 5.0 V ± 10 %
PMOS OD, VOH = 2.4 V, 2x Drive,
VDD2 = 3.3 V ± 10 %
PMOS OD, VOH = 2.4 V, 2x Drive,
VDD2 = 5.0 V ± 10 %
Push-Pull 1x,
VOL = 0.15 V, VDD2 = 1.8 V ± 5 %
Push-Pull, VOL = 0.4 V, 1x Drive,
VDD2 = 3.3 V ± 10 %
4.88
8.24
Push-Pull, VOL = 0.4 V, 1x Drive,
VDD2 = 5.0 V ± 10 %
7.22
11.58
3.30
Push-Pull 2x,
VOL = 0.15 V, VDD2 = 1.8 V ± 5 %
1.83
Push-Pull, VOL = 0.4 V, 2x Drive,
VDD2 = 3.3 V ± 10 %
9.75
16.49
23.16
2.53
Push-Pull, VOL = 0.4 V, 2x Drive,
VDD2 = 5.0 V ± 10 %
13.83
1.38
Open-Drain NMOS 1x,
VOL = 0.15 V, VDD2 = 1.8 V ± 5 %
LOW-Level Output Pulse
Current (Note 3)
IOs 9, 10, 12, 13, 14, 15, 16,
17
IOL2
Open-Drain, VOL = 0.4 V, 1x Drive,
VDD2 = 3.3 V ± 10 %
7.31
12.37
17.38
5.07
Open-Drain NMOS, VOL = 0.4 V, 1x
Drive, VDD2 = 5.0 V ± 10 %
10.82
2.75
Open-Drain NMOS 2x,
VOL = 0.15 V, VDD2 = 1.8 V ± 5 %
Open-Drain, VOL = 0.4 V, 2x Drive,
VDD2 = 3.3 V ± 10 %
14.54
17.34
5.50
24.74
34.76
10.14
41.06
Open-Drain NMOS, VOL = 0.4 V, 2x
Drive, VDD2 = 5.0 V ± 10 %
Open-Drain NMOS 4x, IO9,
VOL = 0.15 V, VDD2 = 1.8 V ± 5 %
Open-Drain NMOS 4x, IO9,
31.32
V
DD2 = 3.3 V ± 10 %
Datasheet
22-Jul-2021
Revision 2.3
21 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 7: EC at T = -40 °C to 125 °C, VDD = 1.71 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
LOW-Level Output Pulse
Current (Note 3)
Condition
Min
Typ
Max
Unit
Open-Drain NMOS 4x, IO9,
IOL2
41.06
55.18
--
mA
IOs 9, 10, 12, 13, 14, 15, 16, VDD2 = 5.0 V ± 10 %
17
Note 1 No hysteresis.
Note 2 The GreenPAK’s power rails are divided in two sides. IOs 0, 1, 2, 3, 4, 5, 6, 7, and 8 are connected to one side, IOs 9,
10, 12, 13, 14, 15, 16, and 17 to another.
Note 3 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
3.5 I2C PINS ELECTRICAL CHARACTERISTICS
Table 8: I2C Pins Timing Characteristics at T = -40 °C to 125 °C Unless Otherwise Noted
Parameter Description
Condition
Min
--
Typ
--
Max
400
--
Unit
kHz
ns
FSCL
tLOW
tHIGH
Clock Frequency, SCL
VDD = 1.71 V to 5.5 V
VDD = 1.71 V to 5.5 V
VDD = 1.71 V to 5.5 V
VDD = 1.8 V ± 5 %
VDD = 3.3 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 1.71 V to 5.5 V
Clock Pulse Width Low
Clock Pulse Width High
1300
600
--
--
--
--
ns
--
95
Input Filter Spike Suppression
(SCL, SDA)
tI
--
--
95
ns
--
--
111
900
tAA
Clock Low to Data Out Valid
--
--
ns
ns
Bus Free Time between Stop
and Start
tBUF
VDD = 1.71 V to 5.5 V
1300
--
--
tHD_STA
tSU_STA
tHD_DAT
tSU_DAT
tR
Start Hold Time
Start Set-up Time
Data Hold Time
Data Set-up Time
Inputs Rise Time
Inputs Fall Time
Stop Set-up Time
Data Out Hold Time
VDD = 1.71 V to 5.5 V
VDD = 1.71 V to 5.5 V
VDD = 1.71 V to 5.5 V
VDD = 1.71 V to 5.5 V
VDD = 1.71 V to 5.5 V
VDD = 1.71 V to 5.5 V
VDD = 1.71 V to 5.5 V
VDD = 1.71 V to 5.5 V
600
600
0
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
--
100
--
--
300
300
--
tF
--
tSU_STO
tDH
600
50
--
3.6 ASYNCHRONOUS STATE MACHINE SPECIFICATION
Table 9: Asynchronous State Machine Specifications at T = -40 °C to 125 °C Unless Otherwise Noted
Parameter Description
Condition
DD = 1.8 V ± 5 %
Min
104
44
32
--
Typ
--
Max
213
89
58
165
70
45
--
Unit
V
Asynchronous State Machine
Output Delay Time
tst_out_delay
VDD = 3.3 V ± 10 %
VDD = 5.0 V ± 10 %
--
ns
--
V
DD = 1.8 V ± 5 %
--
Asynchronous State Machine
Output Transition Time
tst_out
VDD = 3.3 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 1.8 V ± 5 %
VDD = 3.3 V ± 10 %
VDD = 5.0 V ± 10 %
--
--
ns
ns
--
--
14
6
--
Asynchronous State Machine
Input Pulse Acceptance Time
tst_pulse
--
--
5
--
--
Datasheet
22-Jul-2021
Revision 2.3
22 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 9: Asynchronous State Machine Specifications at T = -40 °C to 125 °C Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
--
Typ
--
Max
20
8
Unit
VDD = 1.8 V ± 5 %
VDD = 3.3 V ± 10 %
VDD = 5.0 V ± 10 %
Asynchronous State Machine
Input Compete Time
tst_comp
--
--
ns
--
--
5
3.7 MACROCELLS CURRENT CONSUMPTION
Table 10: Typical Current Estimated for Each Macrocell at T = 25 °C
Parameter Description Note
Chip Quiescent, IDD1
VDD/VDD2 = 1.8 V VDD/VDD2 = 3.3 V VDD/VDD2 = 5.0 V Unit
0.45
0.015
41.48
25.68
7.16
0.75
0.021
64.00
32.41
7.94
1.12
0.029
94.89
43.22
9.25
μA
μA
μA
μA
μA
μA
μA
Chip Quiescent, IDD2
OSC 2 MHz, pre-divide = 1
OSC 2 MHz, pre-divide = 8
OSC 25 kHz, pre-divide = 1
OSC 25 kHz, pre-divide = 8
OSC 25 MHz, pre-divide = 1
6.97
7.60
8.68
87.25
238.27
428.66
IDD
Current
OSC 25 MHz, pre-divide = 1,
Force On
87.25
238.27
428.67
μA
OSC 25 MHz, pre-divide = 8
ACMP (each)
78.01
54.96
75.06
49.70
71.93
212.45
52.64
72.74
47.32
71.27
390.17
60.81
81.25
55.60
79.62
μA
μA
μA
μA
μA
ACMP with buffer (each)
Vref (each)
Vref with buffer (each)
3.8 TIMING CHARACTERISTICS
Table 11: Typical Delay Estimated for Each Macrocell at T = 25 °C
VDD/VDD2 = 1.8 V VDD/VDD2 = 3.3 V VDD/VDD2 = 5.0 V
Rising Falling Rising Falling Rising Falling
Parameter Description Note
Unit
tpd
tpd
Delay
Delay
Digital Input to PP 1x
42
45
17
19
12
13
ns
ns
Digital Input with Schmitt Trig-
ger to PP 1x
42
43
16
17
18
12
Low Voltage Digital input to PP
1x
tpd
Delay
45
428
17
177
12
120
ns
tpd
tpd
Delay
Delay
Digital input to PMOS output
Digital input to NMOS output
42
-
-
17
-
-
12
-
-
ns
ns
80
27
18
Output enable from pin,
OE Hi-Z to 1
tpd
tpd
Delay
Delay
53
50
-
-
21
20
-
-
15
14
-
-
ns
ns
Output enable from pin,
OE Hi-Z to 0
tpd
tpd
tpd
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
Delay
Delay
Delay
LUT2bit (LATCH)
LATCH (LUT2bit)
LUT3bit (LATCH)
LATCH+nRESET(LUT3bit)
LUT4bit
34
30
38
45
28
19
28
33
34
37
42
33
26
34
14
14
18
21
14
10
14
13
13
15
17
13
10
13
10
10
13
15
10
7
9
9
ns
ns
ns
ns
ns
ns
ns
10
12
9
LUT2bt
7
LUT3bit
10
9
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 11: Typical Delay Estimated for Each Macrocell at T = 25 °C (Continued)
VDD/VDD2 = 1.8 V VDD/VDD2 = 3.3 V VDD/VDD2 = 5.0 V
Parameter Description Note
Unit
Rising Falling Rising Falling Rising Falling
tpd
tpd
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
Delay
Delay
CNT/DLY Logic
P_DLY1C
P_DLY2C
P_DLY3C
P_DLY4C
Filter
40
38
18
15
13
11
ns
ns
ns
ns
ns
ns
367
356
165
314
462
609
78
160
312
460
609
78
123
233
343
451
53
119
231
341
451
53
720
718
1061
1396
200
1060
1400
200
ACMP (5 mV overdrive,
IN- = 600 mV)
tpd
tw
Delay
3000
20
3000
20
2000
20
2000
20
2000
20
2000
20
ns
ns
ns
Pulse
Width
IO with 1x Push-Pull
(min transmitted)
Pulse
Width
tw
Filter (min transmitted)
150
150
55
55
35
35
Table 12: Typical Propagations Delays and Pulse Widths at T = 25 °C
Parameter Description Note
VDD = 1.8 V VDD = 3.3 V VDD = 5.0 V
Unit
Pulse Width,
tw
tw
tw
tw
mode: (any)edge detect, edge detect output
mode: (any)edge detect, edge detect output
mode: (any)edge detect, edge detect output
mode: (any)edge detect, edge detect output
296
597
135
272
410
546
101
203
305
407
ns
ns
ns
ns
1 cell
Pulse Width,
2 cell
Pulse Width,
3 cell
898
Pulse Width,
4 cell
1195
time1
time1
time1
time1
time2
time2
time2
time2
Delay, 1 cell mode: (any)edge detect, edge detect output
Delay, 2 cell mode: (any)edge detect, edge detect output
Delay, 3 cell mode: (any)edge detect, edge detect output
Delay, 4 cell mode: (any)edge detect, edge detect output
Delay, 1 cell mode: both edge delay, edge detect output
Delay, 2 cell mode: both edge delay, edge detect output
Delay, 3 cell mode: both edge delay, edge detect output
Delay, 4 cell mode: both edge delay, edge detect output
55
55
24
24
18
18
ns
ns
ns
ns
ns
ns
ns
ns
55
24
18
55
24
18
367
667
968
1265
165
300
440
575
106
193
279
365
Table 13: Typical Pulse Width Performance at T = 25 °C
Parameter
VDD = 1.8 V VDD = 3.3 V VDD = 5.0 V
Unit
ns
Filtered Pulse Width for Filter 0
Filtered Pulse Width for Filter 1
< 114
<75
< 47
<30
< 30
<19
ns
Datasheet
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 14: Typical Counter/Delay Offset Measurements
RC OSC
Parameter
RC OSC Power VDD = 1.8 V VDD = 3.3 V VDD = 5.0 V
Unit
Freq
25 kHz
25 kHz
2 MHz
2 MHz
25 MHz
25 kHz
2 MHz
25 kHz
2 MHz
25 MHz
Offset (Power-On Delay)
Offset (Power-On Delay), fast start
Offset (Power-On Delay)
Offset (Power-On Delay), fast start
Offset (Power-On Delay)
Frequency settling time
Frequency settling time
Variable (CLK period)
auto
auto
1.6
2.1
1.6
2.1
1.6
2.1
0.2
0.4
0.04
12
μs
μs
μs
μs
μs
μs
μs
μs
auto
0.4
0.2
auto
0.7
0.5
auto
0.01
19
0.05
14
auto
auto
14
14
14
forced
forced
0-40
0-0.5
0-0.04
0-40
0-0.5
0-0.04
0-40
Variable (CLK period)
0-0.5
μs
μs
Variable (CLK period)
0-0.04
25 kHz/
2 MHz
Tpd (non-delayed edge)
either
35
14
10
ns
3.9 OSC CHARACTERISTICS
Table 15: 25 kHz RC OSC0 Frequency Limits
Temperature Range
0 °C to +125 °C
Power Supply Range
(VDD), V
+25 °C
-40 °C to +125 °C
Minimum
Maximum
Value, kHz
Minimum
Maximum
Minimum
Maximum
Value, kHz
Value, kHz
Value, kHz
Value, kHz
Value, kHz
1.8 V ±5 %
3.3 V ±10 %
5.0 V ±10 %
2.5 V to 4.5 V
1.71 V to 5.5 V
23.792
24.473
24.316
24.438
23.354
26.288
25.526
25.939
25.559
26.670
23.275
27.089
21.728
29.173
27.002
27.181
27.038
29.545
23.357
26.028
23.357
23.309
26.177
23.309
23.336
26.051
23.336
22.828
27.483
21.301
Table 16: 25 kHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
Error (% at
0 °C to +125 °C
-40 °C to +125 °C
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Error (% at
Minimum)
Error (% at
Maximum)
Minimum)
-4.83 %
-2.11 %
-2.73 %
-2.25 %
-6.58 %
Minimum)
-6.90 %
-6.57 %
-6.76 %
-6.66 %
-8.69 %
1.8 V ±5 %
3.3 V ±10 %
5.0 V ±10 %
2.5 V to 4.5 V
1.71 V to 5.5 V
5.15 %
2.10 %
3.76 %
2.24 %
6.68 %
8.36 %
4.11 %
4.71 %
4.21 %
9.93 %
-13.09 %
-6.57 %
-6.76 %
-6.66 %
-14.80 %
16.69 %
8.01 %
8.72 %
8.15 %
18.18 %
Datasheet
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 17: 2 MHz RC OSC0 Frequency Limits
Temperature Range
0 °C to +125 °C
Power Supply Range
(VDD), V
+25 °C
-40 °C to +125 °C
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
1.8 V ±5 %
3.3 V ±10 %
5.0 V ±10 %
2.5 V to 4.5 V
1.71 V to 5.5 V
1.915
2.062
2.070
2.233
2.124
2.274
1.832
2.103
2.132
2.270
2.171
2.305
1.810
2.144
2.145
2.270
2.171
2.305
1.937
1.858
1.813
1.894
1.853
1.767
1.907
1.836
1.784
1.760
1.706
1.629
Table 18: 2 MHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
Error (% at
0 °C to +125 °C
-40 °C to +125 °C
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Error (% at
Minimum)
Error (% at
Maximum)
Minimum)
-4.26 %
-3.14 %
-5.31 %
-4.65 %
-12.01 %
Minimum)
-8.38 %
-7.10 %
-7.37 %
-8.22 %
-14.69 %
1.8 V ±5 %
3.3 V ±10 %
5.0 V ±10 %
2.5 V to 4.5 V
1.71 V to 5.5 V
3.12 %
3.49 %
11.66 %
6.18 %
13.72 %
5.17 %
6.58 %
13.50 %
8.57 %
15.23 %
-9.50 %
-9.33 %
7.20 %
7.24 %
13.50 %
8.57 %
15.23 %
-11.67 %
-10.81 %
-18.57 %
Table 19: 25 MHz RC OSC1 Frequency Limits
Temperature Range
0 °C to +125 °C
Power Supply Range
(VDD), V
+25 °C
-40 °C to +125 °C
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
2.5 V ±10 %
3.3 V ±10 %
5.0 V ±10 %
2.5 V to 4.5 V
1.71 V to 5.5 V
22.316
23.430
23.289
23.383
12.643
27.220
26.220
26.651
26.220
26.220
21.771
27.572
26.679
27.305
26.679
26.679
21.771
22.389
22.500
20.725
11.317
27.912
27.014
27.486
27.014
27.014
22.389
22.500
20.725
12.203
Table 20: 25 MHz RC OSC1 Frequency Error (Error Calculated Relative to Nominal Value)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
0 °C to +125 °C
-40 °C to +125 °C
Error (% at
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Error (% at
Minimum)
Error (% at
Maximum)
Minimum)
-10.73 %
-6.28 %
Minimum)
-12.92 %
-10.44 %
2.5 V ±10 %
3.3 V ±10 %
8.88 %
4.88 %
10.29 %
6.72 %
-12.92 %
-10.44 %
11.65 %
8.06 %
Datasheet
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Revision 2.3
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 20: 25 MHz RC OSC1 Frequency Error (Error Calculated Relative to Nominal Value)(Continued)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
Error (% at
0 °C to +125 °C
-40 °C to +125 °C
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Minimum)
Minimum)
-10.00 %
-17.10 %
-51.19 %
Minimum)
-10.00 %
-17.10 %
-54.73 %
5.0 V ±10 %
2.5 V to 4.5 V
1.71 V to 5.5 V
-6.84 %
6.61 %
4.88 %
4.88 %
9.22 %
6.72 %
6.72 %
9.95 %
8.06 %
8.06 %
-14.47 %
-49.43 %
Note: 25 MHz RC OSC1 performance is not guaranteed at VDD < 2.5 V.
Datasheet
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Revision 2.3
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
3.9.1 OSC Power-On Delay
Note: DLY/CNT Counter Data = 100, RC OSC Power Setting: "Auto Power-On", RC OSC Clock to Matrix Input: "Enable".
Table 21: OSC Power-On Delay, T = 25 °C
RC OSC0 2 MHz
RC OSC0 25 kHz
RC OSC1
Power Supply
Range
Typical
Maximum
Value, ns
Typical
Maximum
Value, µs
Typical
Maximum
Value, ns
(VDD) V
Value, ns
372.7
349.2
330.3
277.2
262.0
250.2
236.6
226.7
219.0
207.4
202.8
196.3
190.8
Value, µs
0.40
0.38
0.35
0.29
0.28
0.26
0.25
0.23
0.22
0.37
1.63
1.67
1.69
Value, ns
71.2
65.0
59.7
43.0
39.6
36.7
33.2
30.4
28.2
25.8
25.0
24.3
23.7
1.71
1.80
1.89
2.30
2.50
2.70
3.00
3.30
3.60
4.20
4.50
5.00
5.50
407.3
379.5
358.0
298.1
281.9
269.8
256.7
247.4
239.9
229.2
224.5
218.7
213.3
0.57
0.41
0.41
0.31
0.30
0.30
0.44
0.47
0.46
0.50
1.92
2.05
1.99
87.3
78.7
71.3
54.0
48.1
43.5
39.8
36.8
34.3
30.6
29.2
27.5
26.8
Table 22: OSC Power-On Delay, T = 25 °C, Fast Start-Up Time Mode
RC OSC0 2 MHz
RC OSC1 25 kHz
Power Supply
Range
Typical
Value, ns
Maximum
Value, ns
Typical
Maximum
(VDD) V
Value, µs
Value, µs
1.71
1.80
1.89
2.30
2.50
2.70
3.00
3.30
3.60
4.20
4.50
5.00
5.50
327.9
309.9
295.5
254.9
243.1
234.1
223.7
215.7
209.4
199.5
195.5
189.8
184.9
360.0
338.3
323.1
278.1
266.1
257.1
246.8
239.1
232.9
223.4
219.8
214.6
209.8
0.68
0.76
0.64
0.64
0.61
0.70
0.53
21.93
21.88
21.94
21.90
21.77
21.74
21.78
21.69
21.71
21.75
3.23
16.68
19.25
19.22
19.21
19.17
19.15
19.12
19.05
Datasheet
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Revision 2.3
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
3.10 ACMP CHARACTERISTICS
Table 23: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V, Unless Otherwise Noted
Parameter Description
Note
Conditions
Min
0
Typ
--
Max
VDD
1.2
Unit
Positive Input
Negative Input
Positive Input
Negative Input
Positive Input
Negative Input
V
V
VDD = 1.8 V ± 5%
0
--
0
--
VDD
1.2
V
ACMP Input Voltage
VACMP
VDD = 3.3 V ± 10%
Range
0
--
V
0
--
VDD
1.2
V
VDD = 5.0 V ± 10%
T = 25 °C
0
--
V
Low Bandwidth -
Enable, Vhys = 0 mV,
Gain = 1,
-9.1
--
8.4
mV
Vref = 50 mV to
1200 mV,
VDD = 1.71 V to 5.5 V
T = -40 °C to 85 °C
T = 25 °C
-10.9
-7.5
--
--
--
10.9
7.2
mV
mV
mV
ACMP Input Offset
Voltage
Voffset
Low Bandwidth -
Disable, Vhys = 0 mV,
Gain =1,
Vref = 50 mV to
1200 mV,
T = -40 °C to 85 °C
-10.7
10.5
VDD = 1.71 V to 5.5 V
BG = 550 μs,
T = 25 °C
VDD = 1.71 V to 5.5 V
--
--
--
--
--
--
--
--
609.7
675.0
132.4
149.4
609.5
674.6
131.6
149.2
862.2
1028.8
176.2
213.5
862.0
1027.5
176.0
213.3
µS
µS
µS
µS
µS
µS
µS
µS
ACMP Power-On
delay, Minimal
required wake time for
the "Wake and Sleep
function",
Regulator and Charge
Pump set to automatic
ON/OFF
BG = 550 μs,
T = -40 °C to 85 °C
VDD = 1.71 V to 5.5 V
BG = 100 μs,
T = 25 °C
DD = 2.7 V to 5.5 V
V
BG = 100 μs,
T = -40 °C to 85 °C
DD = 2.7 V to 5.5 V
V
tstart
ACMP Start Time
BG = 550 μs,
T = 25 °C
VDD = 3V to 5.5 V
ACMP Power-On
delay, Minimal
required wake time for
the "Wake and Sleep
function",
Regulator and Charge
Pump always OFF
BG = 550 μs,
T = -40 °C to 85°C
DD = 3 V to 5.5 V
V
BG = 100 μs,
T = 25 °C
DD = 3 V to 5.5 V
V
BG = 100 μs,
T = -40 °C to 85°C
VDD = 3 V to 5.5 V
Datasheet
22-Jul-2021
Revision 2.3
29 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 23: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V, Unless Otherwise Noted(Continued)
Parameter Description
Note
Conditions
Min
Typ
Max
Unit
LB - Enabled,
T = 25 °C
7.32
--
35.5
mV
VHYS = 25 mV
VIL = Vin - VHYS/2
VIH = Vin + VHYS/2
LB - Disabled,
T = 25 °C
10.0
42.9
--
--
--
--
--
38.5
57.8
mV
mV
mV
mV
mV
LB - Enabled,
T = 25 °C
VHYS = 50 mV
VIL = Vin - VHYS
VIH = VHYS
LB - Disabled,
T = 25 °C
44.2
54.3
LB - Enabled,
T = 25 °C
192.7
193.3
208.7
204.8
V
HYS = 200 mV
VIL = Vin - VHYS
VIH = VHYS
VHYS
Built-in Hysteresis
LB - Disabled,
T = 25 °C
VHYS = 25 mV
VIL = Vin - VHYS/2
VIH = Vin + VHYS/2
LB - Enabled
LB - Disabled
LB - Enabled
LB - Disabled
LB - Enabled
LB - Disabled
0.0
0.0
--
--
--
--
--
--
58.0
52.9
mV
mV
mV
mV
mV
mV
VHYS = 50 mV
VIL = Vin - VHYS
VIH = VHYS
22.5
29.2
157.1
160.2
86.9
76.5
VHYS = 200 mV
VIL = Vin - VHYS
VIH = VHYS
251.6
245.3
Gain = 1x
--
--
--
--
100.0
1.0
--
--
--
--
ΜΩ
ΜΩ
ΜΩ
ΜΩ
Gain = 0.5x
Gain = 0.33x
Gain = 0.25x
Rsin
Series Input Resistance
0.8
1.0
Low Bandwidth -
Enable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 50 mV
Low to High,
T = (-40…+85)°C
--
--
--
--
--
--
--
--
--
--
35.99
39.36
1.85
216.56
208.81
3.04
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 50 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
2.17
4.10
Low Bandwidth -
Enable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 50 mV
Low to High,
T = (-40…+85)°C
25.22
28.31
1.55
129.31
145.47
2.63
Propagation Delay,
Response Time
PROP
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 50 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
1.93
3.83
Low Bandwidth -
Enable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 250 mV
Low to High,
T = (-40…+85)°C
36.46
39.79
216.78
216.05
High to Low,
T = (-40…+85)°C
Datasheet
22-Jul-2021
Revision 2.3
30 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 23: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V, Unless Otherwise Noted(Continued)
Parameter Description
Note
Conditions
Min
Typ
Max
Unit
Low Bandwidth -
Disable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 250 mV
Low to High,
T = (-40…+85)°C
--
2.04
3.37
µs
High to Low,
T = (-40…+85)°C
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
2.21
25.81
28.65
1.74
4.12
132.94
142.43
2.93
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Low Bandwidth -
Enable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 250 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 250 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
1.97
3.96
Low Bandwidth -
Enable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 600 mV
Low to High,
T = (-40…+85)°C
37.36
40.67
2.23
222.82
219.61
4.02
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 600 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
2.23
4.33
Low Bandwidth -
Enable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 600 mV
Low to High,
T = (-40…+85)°C
26.41
29.32
1.92
135.47
149.01
3.53
Propagation Delay,
Response Time
PROP
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 600 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
2.00
4.25
Low Bandwidth -
Enable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 850 mV
Low to High,
T = (-40…+85)°C
38.36
41.67
2.26
232.64
232.78
4.20
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 850 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
2.25
4.60
Low Bandwidth -
Enable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 850 mV
Low to High,
T = (-40…+85)°C
27.08
29.89
1.91
137.02
146.92
3.57
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 850 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
1.98
4.34
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 23: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V, Unless Otherwise Noted(Continued)
Parameter Description
Note
Conditions
Min
Typ
Max
Unit
Low Bandwidth -
Enable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 1200 mV
Low to High,
T = (-40…+85)°C
--
103.93 1853.68
101.06 1656.70
µs
High to Low,
T = (-40…+85)°C
--
--
--
--
--
--
--
µs
µs
µs
µs
µs
µs
µs
Low Bandwidth -
Disable, Gain = 1,
VDD=(1.71..3.3)V,
Overdrive=5 mV,
Vref = 1200 mV
Low to High,
T = (-40…+85)°C
68.29
63.06
30.62
33.54
5.00
1753.33
1568.55
167.56
181.40
32.61
High to Low,
T = (-40…+85)°C
Propagation Delay,
Response Time
PROP
Low Bandwidth -
Enable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 1200 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
Low Bandwidth -
Disable, Gain = 1,
VDD=(3.3..5.5)V,
Overdrive=5 mV,
Vref = 1200 mV
Low to High,
T = (-40…+85)°C
High to Low,
T = (-40…+85)°C
5.24
33.88
G = 1, VDD = 1.71 V
G = 1, VDD = 3.3 V
--
1
1
--
--
--
G = 1, VDD = 5.5 V
--
1
--
G = 0.5, VDD = 1.71 V
G = 0.5, VDD = 3.3 V
G = 0.5, VDD = 5.5 V
G = 0.33, VDD = 1.71V
G = 0.33, VDD = 3.3 V
G = 0.33, VDD = 5.5 V
G = 0.25, VDD = 1.71V
G = 0.25, VDD = 3.3 V
G = 0.25, VDD = 5.5 V
-1.00%
-0.96%
-1.04%
-1.75%
-1.95%
-2.03%
-1.91%
-1.98%
-2.12%
--
--
--
--
--
--
--
--
--
0.93%
0.82%
0.90%
2.10%
1.69%
1.77%
2.13%
1.80%
1.90%
Gain error (including
threshold and internal
Vref error),
Vref = 50 mV to
1200 mV
G
T = -40 °C to +85 °C
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 23: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V, Unless Otherwise Noted(Continued)
Parameter Description
Note
Conditions
T = 25 °C
Min
Typ
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
Unit
-0.58%
-1.01%
-0.59%
-1.06%
-0.64%
-1.16%
-0.57%
-1.14%
-0.59%
-1.04%
-0.67%
-1.15%
-0.64%
-1.11%
-0.63%
-1.10%
-0.72%
-1.15%
0.56%
0.70%
0.58%
0.72%
0.60%
0.74%
0.58%
0.76%
0.58%
0.73%
0.64%
0.73%
0.64%
0.75%
0.63%
0.78%
0.70%
0.80%
VDD = 1.8 V ± 5%
T = 25 °C
T = 25 °C
T = 25 °C
T = 25 °C
T = 25 °C
T = 25 °C
T = 25 °C
T = 25 °C
Internal Vref error,
Vref = 1200 mV
VDD = 3.3 V ± 10%
VDD = 5.0 V ± 10%
VDD = 1.8 V ± 5%
VDD = 3.3 V ± 10%
VDD = 5.0 V ± 10%
VDD = 1.8 V ± 5%
VDD = 3.3 V ± 10%
VDD = 5.0 V ± 10%
Internal Vref error,
Vref = 1000 mV
Vref
Internal Vref error,
Vref = 500 mV
3.11 ANALOG TEMPERATURE SENSOR CHARACTERISTICS
Table 24: TS Output vs Temperature (Output Range 1)
VDD = 1.8 V
Typical, V
VDD = 3.3 V
Typical, V
VDD = 5.0 V
Typical, V Accuracy, %
T, °C
Accuracy, %
±3.33
±3.35
±3.49
±3.42
±3.51
±3.63
±3.72
±4.00
±3.73
±4.01
±4.11
Accuracy, %
±3.29
±3.32
±3.42
±3.33
±3.46
±3.60
±3.61
±3.92
±3.64
±3.90
±4.03
±4.12
±4.36
±4.89
-40
-30
-20
-10
0
1.20
1.16
1.13
1.10
1.06
1.03
0.99
0.96
0.92
0.88
0.85
0.81
0.78
0.75
1.20
1.16
1.13
1.10
1.06
1.03
0.99
0.96
0.92
0.88
0.85
0.81
0.78
0.75
1.20
1.16
1.13
1.10
1.06
1.03
0.99
0.96
0.92
0.88
0.85
0.81
0.78
0.75
±3.29
±3.29
±3.42
±3.38
±3.45
±3.60
±3.58
±3.87
±3.64
±3.92
±3.97
±4.06
±4.26
±4.81
10
20
30
40
50
60
70
80
90
±4.18
±4.43
±4.98
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 25: TS Output vs Temperature (Output Range 2)
VDD = 1.8 V
Typical, V
VDD = 3.3 V
Typical, V
VDD = 5.0 V
T, °C
Accuracy, %
±3.29
±3.33
±3.37
±3.46
±3.45
±3.62
±3.66
±3.93
±3.71
±3.97
±4.02
±4.22
±4.38
±4.89
Accuracy, %
±3.28
±3.24
±3.30
±3.39
±3.39
±3.51
±3.58
±3.81
±3.65
±3.90
±3.97
±4.13
±4.29
±4.88
Typical, V
0.99
0.96
0.93
0.90
0.87
0.85
0.82
0.79
0.76
0.73
0.70
0.67
0.64
0.61
Accuracy, %
±3.28
±3.31
±3.34
±3.40
±3.40
±3.53
±3.53
±3.80
±3.62
±3.91
±4.00
±4.08
±4.26
±4.77
-40
-30
-20
-10
0
0.99
0.96
0.93
0.90
0.87
0.85
0.82
0.79
0.76
0.73
0.70
0.67
0.64
0.61
0.99
0.96
0.93
0.90
0.87
0.85
0.82
0.79
0.76
0.73
0.70
0.67
0.64
0.61
10
20
30
40
50
60
70
80
90
Table 26: TS Output Error (Output Range 1)
Error at T
VDD, V
-40 °C,
%
-20 °C,
%
0 °C,
%
20 °C,
%
40 °C,
%
60 °C,
%
80 °C,
%
1.71
1.80
1.89
2.30
2.50
2.70
3.00
3.30
3.60
4.20
4.50
5.00
5.50
±3.34
±3.33
±3.33
±3.31
±3.31
±3.30
±3.31
±3.29
±3.25
±3.28
±3.32
±3.29
±3.30
±3.50
±3.49
±3.47
±3.46
±3.44
±3.46
±3.46
±3.42
±3.42
±3.42
±3.41
±3.42
±3.47
±3.56
±3.51
±3.55
±3.50
±3.51
±3.46
±3.46
±3.46
±3.46
±3.45
±3.46
±3.45
±3.50
±3.69
±3.72
±3.70
±3.69
±3.62
±3.64
±3.62
±3.61
±3.59
±3.62
±3.63
±3.58
±3.61
±3.73
±3.73
±3.72
±3.66
±3.66
±3.65
±3.64
±3.64
±3.62
±3.62
±3.62
±3.64
±3.64
±4.09
±4.11
±4.11
±4.05
±4.03
±3.97
±4.07
±4.03
±3.98
±4.01
±4.01
±3.97
±4.02
±4.43
±4.43
±4.40
±4.38
±4.36
±4.31
±4.34
±4.36
±4.34
±4.30
±4.29
±4.26
±4.31
Table 27: TS Output Error (Output Range 2)
Error at T
VDD, V
-40 °C,
%
-20 °C,
%
0 °C,
%
20 °C,
%
40 °C,
%
60 °C,
%
80 °C,
%
1.71
1.80
1.89
2.30
2.50
±3.28
±3.29
±3.21
±3.23
±3.27
±3.38
±3.37
±3.38
±3.34
±3.37
±3.43
±3.45
±3.44
±3.46
±3.44
±3.67
±3.66
±3.63
±3.56
±3.59
±3.72
±3.71
±3.72
±3.66
±3.68
±4.13
±4.02
±4.06
±4.03
±4.03
±4.42
±4.38
±4.39
±4.32
±4.26
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 27: TS Output Error (Output Range 2)(Continued)
Error at T
VDD, V
-40 °C,
%
-20 °C,
%
0 °C,
%
20 °C,
%
40 °C,
%
60 °C,
%
80 °C,
%
2.70
3.00
3.30
3.60
4.20
4.50
5.00
5.50
±3.24
±3.27
±3.28
±3.28
±3.23
±3.27
±3.28
±3.26
±3.31
±3.33
±3.30
±3.28
±3.36
±3.31
±3.34
±3.37
±3.39
±3.39
±3.39
±3.34
±3.34
±3.38
±3.40
±3.44
±3.59
±3.57
±3.58
±3.58
±3.58
±3.56
±3.53
±3.57
±3.65
±3.65
±3.65
±3.64
±3.62
±3.61
±3.62
±3.61
±4.04
±4.02
±3.97
±3.96
±4.04
±4.03
±4.00
±4.01
±4.29
±4.26
±4.29
±4.30
±4.28
±4.26
±4.26
±4.22
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
4
User Programmability
Non-volatile memory (NVM) is used to configure the SLG46538-A’s connection matrix routing and macrocells. The NVM is One
Time Programmable (OTP). However, Dialog’s GreenPAK development tools can be used to configure the connection matrix and
macrocells, without programming the NVM, to allow on-chip emulation. This configuration will remain active on the device as long
as it remains powered and can be re-written as needed to facilitate rapid design changes.
When a design is ready for in-circuit testing, the same GreenPAK development tools can be used to program the NVM and create
samples for small quantity builds. Once the NVM is programmed, the device will retain this configuration for the duration of its
lifetime.
Once the design is finalized, the design file can be forwarded to Dialog to integrate into the production process.
Product
Definition
Customer creates their own design in
GreenPAK Designer
E-mail Product Idea, Definition, Drawing or
Schematic to
CMBUGreenPAK@diasemi.com
Emulate design to verify behavior
Dialog Semiconductor Applications
Engineers will review design specifications
with customer
Program Engineering Samples with
GreenPAK Development Tools
Samples, Design and Characterization
Report send to customer
Customer verifies GreenPAK in system
design
GreenPAK Design
approved
GreenPAK Design
approved
Customers verifies GreenPAK design
E-mail .gpx to
CMBUGreenPAK@diasemi.com
GreenPAK Design
Approved in system test
Custom GreenPAK part enters production
Figure 2: Steps to Create a Custom GreenPAK Device
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
5
IO Pins
The SLG46538-A has a total of 17 multi-function IO pins which can function as either a user defined Input or Output, as well as
serving as a special function (such as voltage reference output), or serving as a signal for programming of the on-chip Non Volatile
Memory (NVM).
Refer to Section 2 for normal and programming mode pin definitions.
Normal Mode pin definitions are as follows:
VDD: VDD power supply
IO0: general purpose input
IO1: general purpose input or output with OE
IO2: general purpose input or output
IO3: general purpose input or output with OE
IO4: general purpose input or output or analog comparator 0(+)
IO5: general purpose input or output with OE or analog comparator 0(-)
IO6: general purpose input or OD output I2C SCL
IO7: general purpose input or OD output I2C SDA
IO8: general purpose input or output with OE or analog comparator 1(+)
GND: ground
IO9: general purpose input or output or analog comparator 1(-)
IO10: general purpose input or output with OE or analog comparator 2(+)
VDD2: VDD2 power supply
IO12: general purpose input or output or analog comparator 3(+)
IO13: general purpose input or output with OE
IO14: general purpose input or output
IO15: general purpose input or output with OE and Vref output (Vref1)
IO16: general purpose input or output with OE and Vref output (Vref0)
IO17: general purpose input or output or external clock input
Programming Mode pin definitions are as follows:
VDD: VDD power supply
IO0: VPP programming voltage
IO6: Programming SCL
IO7: Programming SDA
GND: ground
Of the 17 user defined IO pins on the SLG46538-A, all but one of the pins (IO0) can serve as both digital input and digital output.
IO0 can only serve as a digital input pin.
IOs 0, 1, 2, 3, 4, 5, 6, 7, and 8 are powered from VDD and IOs 9, 10, 12, 13, 14, 15, 16, and 17 are powered from VDD2. All internal
macrocells are powered from VDD. Voltage on VDD2 Pin must be less or equal voltage on VDD Pin.
In case VDD2 floating and any Pin powered from VDD2 is configured as input, ESD pin protection diodes must be considered when
applying an input signal to the pin. This will cause a significant current leakage.
In case VDD2 floating and any Pin powered from VDD2 is configured as Output, the pin will behave as NMOS Open-Drain.
It is not recommended to connect VDD2 to the GND.
5.1 INPUT MODES
Each IO pin can be configured as a digital input pin with/without buffered Schmitt Trigger, or can also be configured as a low
voltage digital input. IOs 4, 5, 8, 9, 10, and 12 can also be configured to serve as analog inputs to the on-chip comparators. IOs
15 and 16 can also be configured as analog reference voltage inputs.
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5.2 OUTPUT MODES
IOs 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, and 17 can all be configured as digital output pins.
5.3 PULL-UP/DOWN RESISTORS
All IO pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors
are 10 kΩ, 100 kΩ, and 1 MΩ. In the case of IO0, the resistors are fixed to a pull-down configuration. In the case of all other IO
pins, the internal resistors can be configured as either Pull-up or Pull-downs.
5.4 GPI STRUCTURE
5.4.1 GPI Structure (for IO0)
Non-Schmitt
Trigger Input
Input Mode [1:0]
WOSMT_EN
SMT_EN
00: Digital In without Schmitt Trigger, wosmt_en = 1, OE = 0
01: Digital In with Schmitt Trigger, smt_en = 1, OE = 0
10: Low Voltage Digital In mode, lv_en = 1, OE = 0
11: Reserved
OE
OE
Schmitt
Trigger Input
Digital IN
Note 1: OE cannot be selected by user
Note 2: OE is Matrix output, Digital In is Matrix input
Low Voltage
Input
LV_EN
OE
Floating
PAD
s0
s1
s2
s3
900 kΩ
90 kΩ
10 kΩ
Res_sel [1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Figure 3: IO0 GPI Structure Diagram
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with Asynchronous State Machine and Dual Supply
5.5 MATRIX OE IO STRUCTURE
5.5.1 Matrix OE IO Structure (for IOs 1, 3, 5)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1
WOSMT_EN
01: Digital In with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital In mode, lv_en = 1
11: Analog IO mode
OE
OE
Schmitt
Trigger Input
Digital IN
Output Mode [1:0]
00: Push-Pull 1x mode, pp1x_en = 1
01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1
10: NMOS 1x Open-Drain mode, od1x_en = 1
11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1
SMT_EN
LV_EN
Low Voltage
Input
Note 1: Digital Out and OE are Matrix output, Digital In is Matrix input
Note 2: Can be varied over PVT, for reference only
OE
Analog IO
(For IO5 only)
Floating
s0
s1
s2
s3
VDD
172 Ω
(Note 2)
s1
s0
900 kΩ
Res_sel
90 kΩ
10 kΩ
VDD
[1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
Digital OUT
OE
Digital OUT
OE
OD1x_EN
PP1x_EN
VDD
PAD
VDD
Digital OUT
OE
Digital OUT
OE
PP2x_EN
OD2x_EN
Figure 4: Matrix OE IO Structure Diagram
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with Asynchronous State Machine and Dual Supply
5.5.2 Matrix OE IO Structure (for IOs 10, 13, 15, 16)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1
01: Digital In with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital In mode, lv_en = 1
WOSMT_EN
OE
OE
Schmitt
Trigger Input
Digital IN
Output Mode [1:0]
00: Push-Pull 1x mode, pp1x_en = 1
01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1
10: NMOS 1x Open-Drain mode, od1x_en = 1
11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1
SMT_EN
LV_EN
Low Voltage
Input
Note 1: Digital Out and OE are Matrix output, Digital In is Matrix input
Note 2: Can be varied over PVT, for reference only
OE
Analog IO
(For IOs 10, 15, 16 only)
Floating
s0
s1
s2
s3
VDD2
172 Ω
(Note 2)
s1
s0
900 kΩ
Res_sel
90 kΩ
10 kΩ
VDD2
[1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
Digital OUT
OE
Digital OUT
OE
OD1x_EN
PP1x_EN
VDD2
PAD
VDD2
Digital OUT
OE
Digital OUT
OE
PP2x_EN
OD2x_EN
Figure 5: Matrix OE IO Structure Diagram
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
5.5.3 Matrix OE IO Structure (for IOs 6 and 7)
Non-Schmitt
Trigger Input
IO6, IO7 Mode [2:0]
000: Digital Input without Schmitt Trigger
WOSMT_EN
SMT_EN
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Reserved
101: Open-Drain NMOS
110: Reserved
OE
OE
Schmitt
Trigger Input
Digital IN
111: Reserved
Note: Digital Out and OE are Matrix output, Digital In is Matrix input
Low Voltage
Input
LV_EN
OE
Digital OUT
OE
OD1x_EN
Floating
PAD
s0
s1
s2
s3
900 kΩ
90 kΩ
10 kΩ
Res_sel [1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Figure 6: Matrix OE IO Structure Diagram
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
5.5.4 Matrix OE 4x Drive Structure (for IO8)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1
WOSMT_EN
01: Digital In with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital In mode, lv_en = 1
11: analog IO mode
OE
OE
Schmitt
Trigger Input
Output Mode [1:0]
00: Push-Pull 1x mode, pp1x_en = 1
01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1
10: NMOS Open-Drain 1x mode, od1x_en = 1, odn_en = 1
11: NMOS Open-Drain 2x mode, od2x_en = 1, od1x_en = 1, odn_en = 1
Digital IN
SMT_EN
LV_EN
Low Voltage
Input
Note 1: Digital Out and OE are Matrix output, Digital In is Matrix input
Note 2: Can be varied over PVT, for reference only
OE
Analog IO
Floating
s0
s1
s2
s3
VDD
172 Ω
(Note 2)
s1
s0
900 kΩ
Res_sel
90 kΩ
10 kΩ
VDD
[1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
Digital OUT
OE
Digital OUT
OE
OD1x_EN
4x_EN
PP1x_EN
ODn_EN
VDD
Digital OUT
OE
OD2x_EN
4x_EN
PAD
VDD
ODn_EN
2x
2x
Digital OUT
OE
Digital OUT
OE
4x_EN
ODn_EN
PP2x_EN
Digital OUT
OE
4x_EN
ODn_EN
Figure 7: Matrix OE IO 4x Drive Structure Diagram
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
5.6 REGISTER OE IO STRUCTURE
5.6.1 IO Structure (for IOs 2 and 4)
Non-Schmitt
Trigger Input
Mode [2:0]
000: Digital In without Schmitt Trigger, wosmt_en = 1, OE = 0
WOSMT_EN
001: Digital In with Schmitt Trigger, smt_en = 1, OE = 0
010: Low Voltage Digital In mode, lv_en = 1, OE = 0
011: Analog IO mode
OE
OE
Schmitt
100: Push-Pull mode, pp_en = 1, OE = 1
Trigger Input
101: NMOS Open-Drain mode, odn_en = 1, OE = 1
110: PMOS Open-Drain mode, odp_en = 1, OE = 1
111: Analog IO and NMOS Open-Drain mode, odn_en = 1 and AIO_en = 1
Digital IN
SMT_EN
LV_EN
Note 1: OE cannot be selected by user and is controlled by register
Note 2: Can be varied over PVT, for reference only
Low Voltage
Input
OE
Analog IO
(For IO4 only)
Floating
s0
s1
s2
s3
s1
s0
172 Ω
(Note 2)
900 kΩ
Res_sel
90 kΩ
10 kΩ
[1:0]
VDD
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
ODp_EN
Digital OUT
OE
Digital OUT
OE
ODn_EN
2x_EN
PP_EN
VDD
PAD
VDD
ODp_EN
Digital OUT
OE
Digital OUT
OE
2x_EN
PP_EN
2x_EN
ODn_EN
Figure 8: IO Structure Diagram
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
5.6.2 IO Structure (for IOs 12, 14, 17)
Non-Schmitt
Trigger Input
Mode [2:0]
000: Digital In without Schmitt Trigger, wosmt_en = 1, OE = 0
WOSMT_EN
001: Digital In with Schmitt Trigger, smt_en = 1, OE = 0
010: Low Voltage Digital In mode, lv_en = 1, OE = 0
011: Analog IO mode
OE
OE
Schmitt
100: Push-Pull mode, pp_en = 1, OE = 1
Trigger Input
101: NMOS Open-Drain mode, odn_en = 1, OE = 1
110: PMOS Open-Drain mode, odp_en = 1, OE = 1
111: Analog IO and NMOS Open-Drain mode, odn_en = 1 and AIO_en = 1
Digital IN
SMT_EN
LV_EN
Note 1: OE cannot be selected by user and is controlled by register
Note 2: Can be varied over PVT, for reference only
Low Voltage
Input
OE
Analog IO
(For IO12 only)
Floating
s0
s1
s2
s3
VDD2
s1
s0
172 Ω
(Note 2)
900 kΩ
Res_sel
90 kΩ
10 kΩ
[1:0]
VDD2
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
ODp_EN
Digital OUT
OE
Digital OUT
OE
ODn_EN
2x_EN
PP_EN
VDD2
PAD
VDD2
ODp_EN
Digital OUT
OE
Digital OUT
OE
2x_EN
PP_EN
2x_EN
ODn_EN
Figure 9: IO Structure Diagram
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
5.6.3 4x Drive Structure (for IO9)
Non-Schmitt
Trigger Input
Mode [2:0]
000: Digital In without Schmitt Trigger, wosmt_en = 1, OE = 0
001: Digital In with Schmitt Trigger, smt_en = 1, OE = 0
010: Low Voltage Digital In mode, lv_en = 1, OE = 0
011: Analog IO mode
WOSMT_EN
SMT_EN
OE
OE
Schmitt
Trigger Input
100: Push-Pull mode, pp_en = 1, OE = 1
Digital IN
101: NMOS Open-Drain mode, odn_en = 1, OE = 1
110: PMOS Open-Drain mode, odp_en = 1, OE = 1
111: Analog IO and NMOS Open-Drain mode, odn_en = 1 and AIO_en = 1
Low Voltage
Input
Note 1: OE cannot be selected by user
Note 2: Digital Out and OE are Matrix output, Digital In is Matrix input
Note 3: Can be varied over PVT, for reference only
LV_EN
OE
Analog IO
Floating
s0
s1
s2
s3
VDD
172 Ω
(Note 3)
s1
s0
900 kΩ
Res_sel
90 kΩ
10 kΩ
[1:0]
Pull-up_EN
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
VDD
Digital OUT
OE
Digital OUT
OE
OD1x_EN
4x_EN
PP1x_EN
ODn_EN
Digital OUT
OE
VDD
OD2x_EN
4x_EN
ODn_EN
PAD
VDD
Digital OUT
OE
Digital OUT
OE
4x_EN
PP2x_EN
ODn_EN
Digital OUT
OE
4x_EN
ODn_EN
Figure 10: IO 4x Drive Structure Diagram
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
6
Connection Matrix
The Connection Matrix in the SLG46538-A is used to create the internal routing for internal functional macrocells of the device
once it is programmed. The registers are programmed from the one-time NVM cell during Test Mode Operation. The output of
each functional macrocell within the SLG46538-A has a specific digital bit code assigned to it that is either set to active “High” or
inactive “Low” based on the design that is created. Once the 2048 register bits within the SLG46538-A are programmed a fully
custom circuit will be created.
The Connection Matrix has 64 inputs and 110 outputs. Each of the 64 inputs to the Connection Matrix is hard-wired to the digital
output of a particular source macrocell, including IO pins, LUTs, analog comparators, other digital resources, such as VDD and
GND. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines.
For a complete list of the SLG46538-A’s register table, see Section 20.
Matrix Input Signal
N
Functions
Ground
0
1
2
3
IO0 Digital In
IO1 Digital In
IO2 Digital In
Resetb_core
VDD
62
63
Matrix Inputs
0
1
2
109
N
Registers
Registers [5:0]
Registers [13:8]
Registers [21:16]
Registers [877:872]
Matrix OUT: PD of
either Temp out or
XTAL Osc
Matrix OUT:
ASM-state0-EN0
Matrix OUT:
ASM-state0-EN1
Matrix OUT:
ASM-state0-EN2
Function
Matrix Outputs
Figure 11: Connection Matrix
Function
Connection Matrix
IO10
IO9
LUT
IO9
IO12
IO10
LUT
IO12
Figure 12: Connection Matrix Example
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
6.1 MATRIX INPUT TABLE
Table 28: Matrix Input Table
Matrix Decode
Matrix Input
Matrix Input Signal Function
Number
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GND
IO0 Digital Input
2
IO1 Digital Input
3
IO2 Digital Input
4
IO3 Digital Input
5
IO4 Digital Input
6
IO5 Digital Input
7
IO8 Digital Input
8
LUT2_0/DFF0 Output
LUT2_1/DFF1 Output
LUT2_2/DFF2 Output
LUT2_3/PGen Output
LUT3_0/DFF3 Output
LUT3_1/DFF4 Output
LUT3_2/DFF5 Output
LUT3_3/DFF6 Output
LUT3_4/DFF7 Output
LUT3_5/CNT_DLY2(8bit) Output
LUT3_6/CNT_DLY3(8bit) Output
LUT3_7/CNT_DLY4(8bit) Output
LUT3_8/CNT_DLY5(8bit) Output
LUT3_9/CNT_DLY6(8bit) Output
LUT4_0/CNT_DLY0(16bit) Output
LUT4_1/CNT_DLY1(16bit) Output
LUT3_10/Pipe Delay (1st stage) Output
Pipe Delay Output0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Pipe Delay Output1
Internal OSC Pre-Divided by 1/2/4/8 Output and Post-Divided by 1/
2/3/4/8/12/24/64 Output (25 kHz/2 MHz)
27
28
Internal OSC Pre-Divided by 1/2/4/8 Output and Post-Divided by 1/
2/3/4/8/12/24/64 Output (25 kHz/2 MHz)
0
1
1
1
0
0
29
30
31
32
33
34
35
36
Internal OSC Pre-Divided by 1/2/4/8 Output (25 MHz)
Filter0/Edge Detect0 Output
Filter1/Edge Detect1 Output
IO6 Digital or I2C_virtual_0 Input
IO7 Digital or I2C_virtual_1 Input
I2C_virtual_2 Input
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
I2C_virtual_3 Input
I2C_virtual_4 Input
Datasheet
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 28: Matrix Input Table(Continued)
Matrix Decode
Matrix Input
Matrix Input Signal Function
Number
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
I2C_virtual_5 Input
I2C_virtual_6 Input
I2C_virtual_7 Input
ASM-stateX-dout0
ASM-stateX-dout1
ASM-stateX-dout2
ASM-stateX-dout3
ASM-stateX-dout4
ASM-stateX-dout5
ASM-stateX-dout6
ASM-stateX-dout7
IO9 Digital Input
IO10 Digital Input
Inverter Output
IO12 Digital Input
IO13 Digital Input
IO14 Digital Input
IO15 Digital Input
IO16 Digital Input
IO17 Digital Input
ACMP_0 Output
ACMP_1 Output
ACMP_2 Output
ACMP_3 Output
Programmable Delay with Edge Detector Output
nRST_core (POR) as matrix input
VDD
6.2 MATRIX OUTPUT TABLE
Table 29: Matrix Output Table
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
[7:0]
Matrix OUT: ASM-state0-EN0
Matrix OUT: ASM-state0-EN1
Matrix OUT: ASM-state0-EN2
Matrix OUT: ASM-state1-EN0
Matrix OUT: ASM-state1-EN1
Matrix OUT: ASM-state1-EN2
0
1
2
3
4
5
[15:8]
[23:16]
[31:24]
[39:32]
[47:40]
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 29: Matrix Output Table (Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
[55:48]
Matrix OUT: ASM-state2-EN0
6
[63:56]
Matrix OUT: ASM-state2-EN1
7
[71:64]
Matrix OUT: ASM-state2-EN2
8
[79:72]
Matrix OUT: ASM-state3-EN0
9
[87:80]
Matrix OUT: ASM-state3-EN1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
[95:88]
Matrix OUT: ASM-state3-EN2
[103:96]
Matrix OUT: ASM-state4-EN0
[111:104]
[119:112]
[127:120]
[135:128]
[143:136]
[151:144]
[159:152]
[167:160]
[175:168]
[183:176]
[191:184]
[199:192]
[207:200]
[215:208]
[223:216]
[231:224]
[239:232]
[247:240]
[255:248]
[263:256]
[271:264]
[279:272]
[287:280]
[295:288]
[303:296]
[311:304]
[319:312]
[327:320]
[335:328]
[343:336]
[351:344]
[359:352]
Matrix OUT: ASM-state4-EN1
Matrix OUT: ASM-state4-EN2
Matrix OUT: ASM-state5-EN0
Matrix OUT: ASM-state5-EN1
Matrix OUT: ASM-state5-EN2
Matrix OUT: ASM-state6-EN0
Matrix OUT: ASM-state6-EN1
Matrix OUT: ASM-state6-EN2
Matrix OUT: ASM-state7-EN0
Matrix OUT: ASM-state7-EN1
Matrix OUT: ASM-state7-EN2
Matrix OUT: ASM-state-nRST
Matrix OUT: IO1 Digital Output Source
Matrix OUT: IO1 Output Enable
Matrix OUT: IO2 Digital Output Source
Matrix OUT: IO3 Digital Output Source
Matrix OUT: IO3 Output Enable
Matrix OUT: IO4 Digital Output Source
Matrix OUT: IO5 Digital Output Source
Matrix OUT: IO5 Output Enable
Matrix OUT: IO6 Digital Output Source (SCL with VI/Input & NMOS Open-Drain)
Matrix OUT: IO7 Digital Output Source (SDA with VI/Input & NMOS Open-Drain)
Matrix OUT: IO8 Digital Output Source
Matrix OUT: IO8 Output Enable
Matrix OUT: IO9 Digital Output Source
Matrix OUT: IO10 Digital Output Source
Matrix OUT: IO10 Output Enable
Matrix OUT: Inverter Input
Reserved
Matrix OUT: IO12 Digital Output Source
Matrix OUT: IO13 Digital Output Source
Matrix OUT: IO13 Output Enable
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 29: Matrix Output Table (Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
[367:360]
[375:368]
[383:376]
[391:384]
[399:392]
[407:400]
[415:408]
[423:416]
[431:424]
[439:432]
[447:440]
[455:448]
[463:456]
[471:464]
[479:472]
[487:480]
[495:488]
[503:496]
[511:504]
[519:512]
[527:520]
[535:528]
[543:536]
[551:544]
[559:552]
[567:560]
[575:568]
[583:576]
[591:584]
[599:592]
[607:600]
[615:608]
[623:616]
[631:624]
[639:632]
[647:640]
[655:648]
[663:656]
[671:664]
Matrix OUT: IO14 Digital Output Source
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Matrix OUT: IO15 Digital Output Source
Matrix OUT: IO15 Output Enable
Matrix OUT: IO16 Digital Output Source
Matrix OUT: IO16 Output Enable
Matrix OUT: IO17 Digital Output Source
Matrix OUT: ACMP0 PDB (Power-Down)
Matrix OUT: ACMP1 PDB (Power-Down)
Matrix OUT: ACMP2 PDB (Power-Down)
Matrix OUT: ACMP3 PDB (Power-Down)
Matrix OUT: Input of Filter_0 with fixed time edge detector
Matrix OUT: Input of Filter_1 with fixed time edge detector
Matrix OUT: Input of Programmable Delay & Edge Detector
Matrix OUT: OSC 25 kHz/2 MHz PDB (Power-Down)
Matrix OUT: OSC 25 MHz PDB (Power-Down)
Matrix OUT: IN0 of LUT2_0 or Clock Input of DFF0
Matrix OUT: IN1 of LUT2_0 or Data Input of DFF0
Matrix OUT: IN0 of LUT2_1 or Clock Input of DFF1
Matrix OUT: IN1 of LUT2_1 or Data Input of DFF1
Matrix OUT: IN0 of LUT2_2 or Clock Input of DFF2
Matrix OUT: IN1 of LUT2_2 or Data Input of DFF2
Matrix OUT: IN0 of LUT2_3 or Clock Input of PGen
Matrix OUT: IN1 of LUT2_3 or nRST of PGen
Matrix OUT: IN0 of LUT3_0 or Clock Input of DFF3
Matrix OUT: IN1 of LUT3_0 or Data Input of DFF3
Matrix OUT: IN2 of LUT3_0 or nRST (nSET) of DFF3
Matrix OUT: IN0 of LUT3_1 or Clock Input of DFF4
Matrix OUT: IN1 of LUT3_1 or Data Input of DFF4
Matrix OUT: IN2 of LUT3_1 or nRST (nSET) of DFF4
Matrix OUT: IN0 of LUT3_2 or Clock Input of DFF5
Matrix OUT: IN1 of LUT3_2 or Data Input of DFF5
Matrix OUT: IN2 of LUT3_2 or nRST (nSET) of DFF5
Matrix OUT: IN0 of LUT3_3 or Clock Input of DFF6
Matrix OUT: IN1 of LUT3_3 or Data Input of DFF6
Matrix OUT: IN2 of LUT3_3 or nRST (nSET) of DFF6
Matrix OUT: IN0 of LUT3_4 or Clock Input of DFF7
Matrix OUT: IN1 of LUT3_4 or Data Input of DFF7
Matrix OUT: IN2 of LUT3_4 or nRST (nSET) of DFF7
Matrix OUT: IN0 of LUT3_5 or Delay2 Input (or Counter2 RST Input)
Datasheet
22-Jul-2021
Revision 2.3
50 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 29: Matrix Output Table (Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
[679:672]
[687:680]
[695:688]
[703:696]
[711:704]
[719:712]
[727:720]
[735:728]
[743:736]
[751:744]
[759:752]
[767:760]
[775:768]
[783:776]
[791:784]
[799:792]
[807:800]
[815:808]
[823:816]
[831:824]
[839:832]
[847:840]
[855:848]
[863:856]
[871:864]
Matrix OUT: IN1 of LUT3_5 or External Clock Input of Delay2 (or Counter2)
84
85
Matrix OUT: IN2 of LUT3_5
Matrix OUT: IN0 of LUT3_6 or Delay3 Input (or Counter3 RST Input)
Matrix OUT: IN1 of LUT3_6 or External Clock Input of Delay3 (or Counter3)
Matrix OUT: IN2 of LUT3_6
86
87
88
Matrix OUT: IN0 of LUT3_7 or Delay4 Input (or Counter4 RST Input)
Matrix OUT: IN1 of LUT3_7 or External Clock Input of Delay4 (or Counter4)
Matrix OUT: IN2 of LUT3_7
89
90
91
Matrix OUT: IN0 of LUT3_8 or Delay5 Input (or Counter5 RST Input)
Matrix OUT: IN1 of LUT3_8 or External Clock Input of Delay5 (or Counter5)
Matrix OUT: IN2 of LUT3_8
92
93
94
Matrix OUT: IN0 of LUT3_9 or Delay6 Input (or Counter6 RST Input)
Matrix OUT: IN1 of LUT3_9 or External Clock Input of Delay6 (or Counter6)
Matrix OUT: IN2 of LUT3_9
95
96
97
Matrix OUT: IN0 of LUT3_10 or Input of Pipe Delay
98
Matrix OUT: IN1 of LUT3_10 or nRST of Pipe Delay
Matrix OUT: IN2 of LUT3_10 or Clock of Pipe Delay
Matrix OUT: IN0 of LUT4_0 or Delay0 Input (or Counter0 RST/SET Input)
Matrix OUT: IN1 of LUT4_0 or External Clock Input of Delay0 (or Counter0)
Matrix OUT: IN2 of LUT4_0 or UP Input of FSM0
99
100
101
102
103
104
105
106
107
108
Matrix OUT: IN3 of LUT4_0 or KEEP Input of FSM0
Matrix OUT: IN0 of LUT4_1 or Delay1 Input (or Counter1 RST/SET Input)
Matrix OUT: IN1 of LUT4_1 or External Clock Input of Delay1 (or Counter1)
Matrix OUT: IN2 of LUT4_1 or UP Input of FSM1
Matrix OUT: IN3 of LUT4_1 or KEEP Input of FSM1
Matrix OUT: PD ofeither Temp-output with BG AND/OR crystal oscillator by register
[1268]
[879:872]
109
Note 1 For each Address, the two most significant bits are unused.
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
6.3 CONNECTION MATRIX VIRTUAL INPUTS
As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macrocells on the device. Eight
of the Connection Matrix inputs have the special characteristic that the state of these signal lines comes from a corresponding
data bit written as a register value via I2C. This gives the user the ability to write data via the serial channel, and have this
information translated into signals that can be driven into the Connection Matrix and from the Connection Matrix to the digital
inputs of other macrocells on the device. The I2C address for reading and writing these register values is at byte 0244.
Six of the eight Connection Matrix Virtual Inputs are dedicated to this virtual input function. An I2C write command to these register
bits will set the signal values going into the Connection Matrix to the desired state. A read command to these register bits will read
either the original data values coming from the NVM memory bits (that were loaded during the initial device startup), or the values
from a previous write command (if that has happened).
Two of the eight Connection Matrix Virtual Inputs are shared with Pin digital inputs,(IO6 Digital or I2C_virtual_0 Input) and (IO7
Digital or I2C_virtual_1 Input). If the virtual input mode is selected, an I2C write command to these register bits will set the signal
values going into the Connection Matrix to the desired state. Two register bits select whether the Connection Matrix input comes
from the pin input or from the virtual register:
register [1074] Select SCL & Virtual Input 0 or IO6
register [1082] Select SDA & Virtual Input 1 or IO7
See Table 30 for Connection Matrix Virtual Inputs.
Table 30: Connection Matrix Virtual Inputs
Matrix Input
Register Bit
Addresses (d)
Matrix Input Signal Function
Number
32
I2C_virtual_0 Input
I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
I2C_virtual_5 Input
I2C_virtual_6 Input
I2C_virtual_7 Input
[1952]
[1953]
[1954]
[1955]
[1956]
[1957]
[1958]
[1959]
33
34
35
36
37
38
39
6.4 CONNECTION MATRIX VIRTUAL OUTPUTS
The digital outputs of the various macrocells are routed to the Connection Matrix to enable interconnections to the inputs of other
macrocells in the device. At the same time, it is possible to read the state of each of the macrocell outputs as a register value via
I2C. This option, called Connection Matrix Virtual Outputs, allows the user to remotely read the values of each macrocell output.
The I2C addresses for reading these register values are at bytes 0240 to 0247. Write commands to these same register values
will be ignored (with the exception of the Virtual Input register bits at byte 0244).
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
7
Combination Function Macrocells
The SLG46538-A has seventeen combination function macrocells that can serve more than one logic or timing function. In each
case, they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that
can be implemented in these macrocells.
Three macrocells that can serve as either 2-bit LUTs or as D Flip-Flops;
Five macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input;
One macrocell that can serve as either 3-bit LUT or as Pipe Delay;
One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGen);
Five macrocells that can serve as either 3-bit LUTs or as 8-Bit Counter/Delays;
Two macrocells that can serve as either 4-bit LUTs or as 16-Bit Counter/Delays.
Inputs/Outputs for the 17 combination function macrocells are configured from the connection matrix with specific logic functions
being defined by the state of NVM bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined
function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
7.1 2-BIT LUT OR D FLIP-FLOP MACROCELLS
There are three macrocells that can serve as either 2-bit LUTs or as D Flip-Flops. When used to implement LUT functions, the
2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the
connection matrix. When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data
(D) and clock (CLK) inputs for the Flip-Flop, with the output going back to the connection matrix.
The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:
DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change
LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK
is High).
Register [1207] DFF or LATCH Select
Register [1206] Output Select (Q or nQ)
Register [1205] DFF Initial Polarity Select
IN1
IN0
S0
S1
From Connection Matrix Output [61]
OUT
2-bit LUT0
0: 2-bit LUT0 IN1
1: DFF0 Data
LUT Truth
Table
To Connection Matrix
S0
Input [8]
4-bits NVM
Registers [1207:1204]
0: 2-bit LUT0 OUT
1: DFF0 OUT
S1
DFF
Registers
D
S0
S1
From Connection Matrix Output [60]
Q/nQ
DFF0
0: 2-bit LUT0 IN0
1: DFF0 clk
clk
1-bit NVM
Register [1191]
Figure 13: 2-bit LUT0 or DFF0
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Register [1203] DFF or LATCH Select
Register [1202] Output Select (Q or nQ)
Register [1201] DFF Initial Polarity Select
IN1
S0
From Connection Matrix Output [63]
OUT
2-bit LUT1
0: 2-bit LUT1 IN1
1: DFF1 Data
S1
IN0
LUT Truth
Table
To Connection Matrix
S0
Input [9]
4-bits NVM
Registers [1203:1200]
0: 2-bit LUT1 OUT
1: DFF1 OUT
S1
DFF
Registers
D
S0
S1
From Connection Matrix Output [62]
Q/nQ
DFF1
0: 2-bit LUT1 IN0
1: DFF1 clk
clk
1-bit NVM
Register [1190]
Figure 14: 2-bit LUT1 or DFF1
Register [1215] DFF or LATCH Select
Register [1214] Output Select (Q or nQ)
Register [1213] DFF Initial Polarity Select
IN1
S0
S1
From Connection Matrix Output [65]
OUT
2-bit LUT2
0: 2-bit LUT2 IN1
1: DFF2 Data
IN0
LUT Truth
Table
To Connection Matrix
S0
Input [10]
4-bits NVM
Registers [1215:1212]
0: 2-bit LUT2 OUT
1: DFF2 OUT
S1
DFF
Registers
D
S0
S1
From Connection Matrix Output [64]
Q/nQ
DFF2
0: 2-bit LUT2 IN0
1: DFF2 clk
clk
1-bit NVM
Register [1189]
Figure 15: 2-bit LUT2 or DFF2
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
7.1.1 2-Bit LUT or D Flip-Flop Macrocells Used as 2-Bit LUTs
Table 31: 2-bit LUT0 Truth Table
Table 33: 2-bit LUT2 Truth Table
IN1
0
IN0
0
OUT
IN1
0
IN0
0
OUT
register [1204]
register [1205]
register [1206]
register [1207]
LSB
register [1212]
register [1213]
register [1214]
register [1215]
LSB
0
1
0
1
1
0
1
0
1
1
MSB
1
1
MSB
Table 32: 2-bit LUT1 Truth Table
IN1
0
IN0
0
OUT
register [1200]
register [1201]
register [1202]
register [1203]
LSB
0
1
1
0
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-Bit LUT0 is defined by registers [1207:1204]
2-Bit LUT1 is defined by registers [1203:1200]
2-Bit LUT2 is defined by registers [1215:1212]
Table 34 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the 2-bit LUT logic cells.
Table 34: 2-bit LUT Standard Digital Functions
Function
AND-2
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-2
OR-2
NOR-2
XOR-2
XNOR-2
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
7.1.2 Initial Polarity Operations
Figure 16: DFF Polarity Operations
7.2 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELLS
There are five macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset inputs. When used to implement
LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce a single output, which goes
back into the connection matrix. When used to implement D Flip-Flop function, the three input signals from the connection matrix
go to the data (D) and clock (CLK), and Reset/Set (rRST/nSET) inputs for the Flip-Flop, with the output going back to the
connection matrix.
DFF3 has a user selectable option to allow the macrocell output to either come from the Q/nQ output of one D Flip-Flop, or two
D Flip-Flops in series, with the first D Flip-Flop triggering on the rising clock edge, and the second D Flip-Flop triggering on the
falling clock edge.
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Register [1223] DFF or LATCH Select
Register [1222] Output Select (Q or nQ)
Register [1221] DFF nRST or nSET Select
Register [1220] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [70]
S0
IN1
OUT
3-bit LUT0
0: 3-bit LUT0 IN2
1: DFF3 nRST/nSET
S1
IN0
LUT Truth
Table
From Connection
Matrix Output [69]
To Connection Matrix
S0
S1
Input [12]
S0
8-bits NVM
0: 3-bit LUT0 IN1
1: DFF3 D
Registers [1223:1216]
Register [1471]
0: 3-bit LUT0 OUT
1: DFF3 OUT
S1
DFF3
nRST/nSET
From Connection
S0
S1
D
Q/nQ
Matrix Output [68]
Q
D
D
Q
0: 3-bit LUT0 IN0
1: DFF3 clk
clk
Register [1222]
Register [1471] Selects output from one or two DFF
1-bit NVM
Register [1187]
Figure 17: 3-bit LUT0 or DFF3 with RST/SET
Register [1231] DFF or LATCH Select
Register [1230] Output Select (Q or nQ)
Register [1229] DFF nRST or nSET Select
Register [1228] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [73]
S0
S1
IN1
IN0
OUT
3-bit LUT1
0: 3-bit LUT1 IN2
1: DFF4 nRST/nSET
LUT Truth
Table
From Connection
To Connection Matrix
Matrix Output [72]
S0
S1
Input [13]
S0
8-bits NVM
Registers [1231:1224]
0: 3-bit LUT1 IN1
1: DFF4 D
0: 3-bit LUT1 OUT
S1
1: DFF4 OUT
DFF
Registers
D
From Connection
Matrix Output [71]
S0
S1
nRST/nSET
clk
DFF4
Q/nQ
0: 3-bit LUT1 IN0
1: DFF4 clk
1-bit NVM
Register [1186]
Figure 18: 3-bit LUT1 or DFF4 with RST/SET
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Register [1239] DFF or LATCH Select
Register [1238] Output Select (Q or nQ)
Register [1237] DFF nRST or nSET Select
Register [1236] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [76]
S0
IN1
IN0
OUT
3-bit LUT2
0: 3-bit LUT2 IN2
S1
1: DFF5 nRST/nSET
LUT Truth
Table
From Connection
Matrix Output [75]
To Connection Matrix
S0
S1
S0
S1
Input [14]
8-bits NVM
Registers [1239:1232]
0: 3-bit LUT2 IN1
1: DFF5 D
0: 3-bit LUT2 OUT
1: DFF5 OUT
DFF
Registers
D
From Connection
Matrix Output [74]
S0
S1
nRST/nSET
clk
DFF5
Q/nQ
0: 3-bit LUT2 IN0
1: DFF5 clk
1-bit NVM
Register [1185]
Figure 19: 3-bit LUT2 or DFF5 with RST/SET
Register [1247] DFF or LATCH Select
Register [1246] Output Select (Q or nQ)
Register [1245] DFF nRST or nSET Select
Register [1244] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [79]
S0
S1
IN1
IN0
OUT
3-bit LUT3
0: 3-bit LUT3 IN2
1: DFF6 nRST/nSET
LUT Truth
Table
From Connection
To Connection Matrix
Matrix Output [78]
S0
S1
Input [15]
S0
8-bits NVM
Registers [1247:1240]
0: 3-bit LUT3 IN1
1: DFF6 D
0: 3-bit LUT3 OUT
S1
1: DFF6 OUT
DFF
Registers
D
From Connection
Matrix Output [77]
S0
S1
nRST/nSET
clk
DFF6
Q/nQ
0: 3-bit LUT3 IN0
1: DFF6 clk
1-bit NVM
Register [1184]
Figure 20: 3-bit LUT3 or DFF6 with RST/SET
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Register [1255] DFF or LATCH Select
Register [1254] Output Select (Q or nQ)
Register [1253] DFF nRST or nSET Select
Register [1252] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [82]
S0
IN1
OUT
3-bit LUT4
0: 3-bit LUT4 IN2
S1
1: DFF7 nRST/nSET
IN0
LUT Truth
Table
From Connection
Matrix Output [81]
To Connection Matrix
S0
S1
S0
S1
Input [16]
8-bits NVM
Registers [1255:1248]
0: 3-bit LUT4 IN1
1: DFF7 D
0: 3-bit LUT4 OUT
1: DFF7 OUT
DFF
Registers
D
From Connection
Matrix Output [80]
S0
S1
nRST/nSET
clk
DFF7
Q/nQ
0: 3-bit LUT4 IN0
1: DFF7 clk
1-bit NVM
Register [1199]
Figure 21: 3-bit LUT4 or DFF7 with RST/SET
Register [1375] DFF or LATCH Select
Register [1374] Output Select (Q or nQ)
Register [1373] DFF nRST or nSET Select
Register [1372] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [2]
S0
S1
IN1
IN0
OUT
3-bit LUT11
0: 3-bit LUT11 IN2
1: DFF8 nRST/nSET
LUT Truth
Table
From Connection
To Connection Matrix
S0
S1
Matrix Output [1]
S0
S1
Input [40]
8-bits NVM
Registers [1375:1368]
0: 3-bit LUT11 IN1
1: DFF8 D
0: 3-bit LUT11 OUT
1: DFF8 OUT
DFF
Registers
D
From Connection
Matrix Output [0]
S0
S1
nRST/nSET
clk
DFF8
Q/nQ
0: 3-bit LUT11 IN0
1: DFF8 clk
1-bit NVM
Register [1367]
Figure 22: 3-bit LUT11 or DFF8 with RST/SET
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Register [1383] DFF or LATCH Select
Register [1382] Output Select (Q or nQ)
Register [1381] DFF nRST or nSET Select
Register [1380] DFF Initial Polarity Select
IN2
IN1
From Connection
Matrix Output [5]
S0
S1
OUT
3-bit LUT12
0: 3-bit LUT12 IN2
1: DFF9 nRST/nSET
IN0
LUT Truth
Table
From Connection
To Connection Matrix
Matrix Output [4]
S0
S1
Input [41]
S0
8-bits NVM
Registers [1383:1376]
0: 3-bit LUT12 IN1
1: DFF9 D
0: 3-bit LUT12 OUT
1: DFF9 OUT
S1
DFF
Registers
D
From Connection
Matrix Output [3]
S0
S1
nRST/nSET
clk
DFF9
Q/nQ
0: 3-bit LUT12 IN0
1: DFF9 clk
1-bit NVM
Register [1366]
Figure 23: 3-bit LUT12 or DFF9 with RST/SET
Register [1391] DFF or LATCH Select
Register [1390] Output Select (Q or nQ)
Register [1389] DFF nRST or nSET Select
Register [1388] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [8]
S0
S1
IN1
IN0
OUT
3-bit LUT13
0: 3-bit LUT13 IN2
1: DFF10 nRST/nSET
LUT Truth
Table
From Connection
To Connection Matrix
S0
S1
Matrix Output [7]
S0
S1
Input [42]
8-bits NVM
Registers [1391:1384]
0: 3-bit LUT13 IN1
1: DFF10 D
0: 3-bit LUT13 OUT
1: DFF10 OUT
DFF
Registers
D
From Connection
Matrix Output [6]
S0
S1
nRST/nSET
clk
DFF10
Q/nQ
0: 3-bit LUT13 IN0
1: DFF10 clk
1-bit NVM
Register [1365]
Figure 24: 3-bit LUT13 or DFF10 with RST/SET
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Register [1399] DFF or LATCH Select
Register [1398] Output Select (Q or nQ)
Register [1397] DFF nRST or nSET Select
Register [1396] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [11]
S0
IN1
OUT
3-bit LUT14
0: 3-bit LUT14 IN2
S1
1: DFF11 nRST/nSET
IN0
LUT Truth
Table
From Connection
Matrix Output [10]
To Connection Matrix
S0
S1
S0
S1
Input [43]
8-bits NVM
Registers [1399:1392]
0: 3-bit LUT14 IN1
1: DFF11 D
0: 3-bit LUT14 OUT
1: DFF11 OUT
DFF
Registers
D
From Connection
Matrix Output [9]
S0
S1
nRST/nSET
clk
DFF11
Q/nQ
0: 3-bit LUT14 IN0
1: DFF11 clk
1-bit NVM
Register [1364]
Figure 25: 3-bit LUT14 or DFF11 with RST/SET
Register [1407] DFF or LATCH Select
Register [1406] Output Select (Q or nQ)
Register [1405] DFF nRST or nSET Select
Register [1404] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [14]
S0
S1
IN1
IN0
OUT
3-bit LUT15
0: 3-bit LUT15 IN2
1: DFF12 nRST/nSET
LUT Truth
Table
From Connection
To Connection Matrix
S0
S1
Matrix Output [13]
S0
S1
Input [44]
8-bits NVM
Registers [1407:1400]
0: 3-bit LUT15 IN1
1: DFF12 D
0: 3-bit LUT15 OUT
1: DFF12 OUT
DFF
Registers
D
From Connection
Matrix Output [12]
S0
S1
nRST/nSET
clk
DFF12
Q/nQ
0: 3-bit LUT15 IN0
1: DFF12 clk
1-bit NVM
Register [1363]
Figure 26: 3-bit LUT15 or DFF12 with RST/SET
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Register [1415] DFF or LATCH Select
Register [1414] Output Select (Q or nQ)
Register [1413] DFF nRST or nSET Select
Register [1412] DFF Initial Polarity Select
IN2
IN1
From Connection
Matrix Output [17]
S0
S1
OUT
3-bit LUT16
0: 3-bit LUT16 IN2
1: DFF13 nRST/nSET
IN0
LUT Truth
Table
From Connection
To Connection Matrix
S0
S1
Matrix Output [16]
S0
S1
Input [45]
8-bits NVM
Registers [1415:1408]
0: 3-bit LUT16 IN1
1: DFF13 D
0: 3-bit LUT16 OUT
1: DFF13 OUT
DFF
Registers
D
From Connection
Matrix Output [15]
S0
S1
nRST/nSET
clk
DFF13
Q/nQ
0: 3-bit LUT16 IN0
1: DFF13 clk
1-bit NVM
Register [1362]
Figure 27: 3-bit LUT16 or DFF13 with RST/SET
Register [1423] DFF or LATCH Select
Register [1422] Output Select (Q or nQ)
Register [1421] DFF nRST or nSET Select
Register [1420] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [20]
S0
S1
IN1
IN0
OUT
3-bit LUT17
0: 3-bit LUT17 IN2
1: DFF14 nRST/nSET
LUT Truth
Table
From Connection
To Connection Matrix
S0
S1
Matrix Output [19]
S0
S1
Input [4]
8-bits NVM
Registers [1423:1416]
0: 3-bit LUT17 IN1
1: DFF14 D
0: 3-bit LUT17 OUT
1: DFF14 OUT
DFF
Registers
D
From Connection
Matrix Output [18]
S0
S1
nRST/nSET
clk
DFF14
Q/nQ
0: 3-bit LUT17 IN0
1: DFF14 clk
1-bit NVM
Register [1361]
Figure 28: 3-bit LUT17 or DFF14 with RST/SET
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
7.2.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs
Table 35: 3-bit LUT0 Truth Table
Table 39: 3-bit LUT4 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1216]
register [1217]
register [1218]
register [1219]
register [1220]
register [1221]
register [1222]
register [1223]
LSB
register [1248]
register [1249]
register [1250]
register [1251]
register [1252]
register [1253]
register [1254]
register [1255]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 36: 3-bit LUT1 Truth Table
Table 40: 3-bit LUT11 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1224]
register [1225]
register [1226]
register [1227]
register [1228]
register [1229]
register [1230]
register [1231]
register [1368]
register [1369]
register [1370]
register [1371]
register [1372]
register [1373]
register [1374]
register [1375]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 37: 3-bit LUT2 Truth Table
Table 41: 3-bit LUT12 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1232]
register [1233]
register [1234]
register [1235]
register [1236]
register [1237]
register [1238]
register [1239]
register [1376]
register [1377]
register [1378]
register [1379]
register [1380]
register [1381]
register [1382]
register [1383]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 38: 3-bit LUT3 Truth Table
Table 42: 3-bit LUT13 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1240]
register [1241]
register [1242]
register [1243]
register [1244]
register [1245]
register [1246]
register [1247]
register [1384]
register [1385]
register [1386]
register [1387]
register [1388]
register [1389]
register [1390]
register [1391]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
1
1
1
MSB
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 43: 3-bit LUT14 Truth Table
Table 45: 3-bit LUT16 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1392]
register [1393]
register [1394]
register [1395]
register [1396]
register [1397]
register [1398]
register [1399]
LSB
register [1408]
register [1409]
register [1410]
register [1411]
register [1412]
register [1413]
register [1414]
register [1415]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 44: 3-bit LUT15 Truth Table
Table 46: 3-bit LUT17 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1400]
register [1401]
register [1402]
register [1403]
register [1404]
register [1405]
register [1406]
register [1407]
register [1416]
register [1417]
register [1418]
register [1419]
register [1420]
register [1421]
register [1422]
register [1423]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
1
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT0 is defined by registers [1223:1216]
3-Bit LUT1 is defined by registers [1231:1224]
3-Bit LUT2 is defined by registers [1239:1232]
3-Bit LUT3 is defined by registers [1247:1240]
3-Bit LUT4 is defined by registers [1255:1248]
3-Bit LUT11 is defined by registers [1375:1368]
3-Bit LUT12 is defined by registers [1383:1376]
3-Bit LUT13 is defined by registers [1391:1384]
3-Bit LUT14 is defined by registers [1399:1392]
3-Bit LUT15 is defined by registers [1407:1400]
3-Bit LUT16 is defined by registers [1415:1408]
3-Bit LUT17 is defined by registers [1423:1416]
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 47 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the six 3-bit LUT logic cells.
Table 47: 3-bit LUT Standard Digital Functions
Function
AND-3
MSB
LSB
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-3
OR-3
NOR-3
XOR-3
XNOR-3
7.2.2 Initial Polarity Operations
VDD
Data
Clock
POR
Initial Polarity: High
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Figure 29: DFF Polarity Operations
7.3 3-BIT LUT OR PIPE DELAY MACROCELL
There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay.
When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a
single output, which goes back into the connection matrix.
When used as a Pipe Delay, there are three inputs signals from the matrix: Input (IN), Clock (CLK), and Reset (nRST). The Pipe
Delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell. The first delay option (OUT2) is fixed at
the output of the first Flip-Flop stage. The other two outputs (OUT0 and OUT1) provide user selectable options for 1 to 16 stages
of delay.There are delay output points for each set of the OUT0 and OUT1 outputs to a 16-input mux that is controlled by registers
[1259:1256] for OUT0 and registers [1263:1260] for OUT1. The 16-input mux is used to select the amount of delay.
The overall time of the delay is based on the clock used in the SLG46538-A design. Each DFF cell has a time delay of the inverse
of the clock time (either external clock or the RC Oscillator within the SLG46538-A). The sum of the number of DFF cells used
will be the total time delay of the Pipe Delay logic cell.
Note: CLK is rising edge triggered.
Registers [1263:1256]
LUT Truth
Table
From Connection
Matrix Output [98]
IN0
IN1
From Connection
Matrix Output [99]
OUT
3-bit LUT10
From Connection
Matrix Output [100]
IN2
Registers [1263:1260]
Register [1271]
S0
S1
OUT1
To Connection
Matrix Input [26]
From Connection
Matrix Output [98]
IN
nRST
From Connection
Matrix Output [99]
16 Flip-Flops
CLK
From Connection
Matrix Output [100]
OUT0
To Connection
Matrix Input [25]
S0
S1
1 Pipe OUT
Registers [1259:1256]
To Connection
Matrix Input [24]
Register [1270]
Figure 30: 3-bit LUT10 or Pipe Delay
7.3.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUTs
Table 48: 3-bit LUT10 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [1256]
register [1257]
LSB
0
0
1
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 48: 3-bit LUT10 Truth Table (Continued)
IN2
0
IN1
1
IN0
0
OUT
register [1258]
register [1259]
register [1260]
register [1261]
register [1262]
register [1263]
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT10 is defined by registers [1263:1256]
7.3.2 3-Bit LUT or Pipe Delay Macrocells Used as Pipe Delay Register Settings
Table 49: Pipe Delay Register Settings
Register Bit
Address
Signal Function
Register Definition
LUT3_10 or Pipe
[1270]
0: LUT3_10
Delay Output Select
1: 1 Pipe Delay Output
OUT0 select
OUT1 select
[1259:1256]
[1263:1260]
[1271]
Pipe Delay OUT1
Polarity Select Bit
0: Non-inverted
1: Inverted
7.4 3-BIT LUT OR 8-BIT COUNTER/DELAY MACROCELLS
There are five macrocells that can serve as either 3-bit LUTs or as Counter/Delays. When used to implement LUT function, the
3-bit LUT takes in three input signals from the connection matrix and produces a single output, which goes back into the
connection matrix. When used to implement 8-Bit Counter/Delay function, two of the three input signals from the connection matrix
go to the external clock (EXT_CLK) and reset (DLY_IN/CNT Reset) for the Counter/Delay, with the output going back to the
connection matrix.
These macrocells can also operate in a one-shot mode, which will generate an output pulse of user-defined width.
These macrocells can also operate in a frequency detection or edge detection mode.
For timing diagrams refer to Section 7.6
Note Counters initialize with counter data after POR.
Two of the five macrocells can have their active count value read via I2C (CNT4 and CNT6). See Section 17.6.1 for further details.
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
7.4.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams
From Connection
Matrix Output [85]
IN2
3-bit LUT5
From Connection
Matrix Output [84]
IN1
IN0
S0
S1
OUT
0: 3-bit LUT5 IN1
1: CNT/DLY2 clk
LUT Truth
Table
To Connection
S0
S1
Matrix Input [17]
8-bits NVM
Registers [1543:1536]
0: 3-bit LUT5 OUT
1: CNT/DLY2 OUT
CNT
Data
clk
From Connection
Matrix Output [83]
S0
S1
OUT
CNT/DLY2
0: 3-bit LUT5 IN0
1: CNT/DLY2 RST
DLY_IN/CNT_Reset
1-bit NVM
Register [1198]
Figure 31: 3-bit LUT5 or CNT/DLY2
From Connection
Matrix Output [88]
IN2
3-bit LUT6
From Connection
Matrix Output [87]
IN1
S0
S1
OUT
0: 3-bit LUT6 IN1
1: CNT/DLY3 clk
IN0
LUT Truth
Table
To Connection
S0
S1
Matrix Input [18]
8-bits NVM
Registers [1551:1544]
0: 3-bit LUT6 OUT
1: CNT/DLY3 OUT
CNT
Data
clk
From Connection
Matrix Output [86]
S0
S1
OUT
CNT/DLY3
DLY_IN/CNT_Reset
0: 3-bit LUT6 IN0
1: CNT/DLY3 RST
1-bit NVM
Register [1197]
Figure 32: 3-bit LUT6 or CNT/DLY3
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
From Connection
Matrix Output [91]
IN2
3-bit LUT7
From Connection
Matrix Output [90]
IN1
IN0
S0
S1
OUT
0: 3-bit LUT7 IN1
1: CNT/DLY4 clk
LUT Truth
Table
To Connection
S0
S1
Matrix Input [19]
8-bits NVM
Registers [1559:1552]
0: 3-bit LUT7 OUT
1: CNT/DLY4 OUT
CNT
Data
clk
From Connection
Matrix Output [89]
S0
S1
OUT
CNT/DLY4
DLY_IN/CNT_Reset
0: 3-bit LUT7 IN0
1: CNT/DLY4 RST
1-bit NVM
Register [1196]
Figure 33: 3-bit LUT7 or CNT/DLY4
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
From Connection
Matrix Output [94]
IN2
3-bit LUT8
From Connection
Matrix Output [93]
IN1
IN0
S0
S1
OUT
0: 3-bit LUT8 IN1
1: CNT/DLY5 clk
LUT Truth
Table
To Connection
S0
S1
Matrix Input [20]
8-bits NVM
Registers [1567:1560]
0: 3-bit LUT8 OUT
1: CNT/DLY5 OUT
CNT
Data
clk
From Connection
Matrix Output [92]
S0
S1
OUT
CNT/DLY5
DLY_IN/CNT_Reset
0: 3-bit LUT8 IN0
1: CNT/DLY5 RST
1-bit NVM
Register [1195]
Figure 34: 3-bit LUT8 or CNT/DLY5
From Connection
Matrix Output [97]
IN2
3-bit LUT9
From Connection
Matrix Output [96]
IN1
S0
S1
OUT
0: 3-bit LUT9 IN1
1: CNT/DLY6 clk
IN0
LUT Truth
Table
To Connection
S0
S1
Matrix Input [21]
8-bits NVM
Registers [1575:1568]
0: 3-bit LUT9 OUT
1: CNT/DLY6 OUT
CNT
Data
clk
From Connection
Matrix Output [95]
S0
S1
OUT
CNT/DLY6
DLY_IN/CNT_Reset
0: 3-bit LUT9 IN0
1: CNT/DLY6 RST
1-bit NVM
Register [1194]
Figure 35: 3-bit LUT9 or CNT/DLY6
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7.4.2 3-Bit LUT or Counter/Delay Macrocells Used as 3-Bit LUTs
Table 50: 3-bit LUT5 Truth Table
Table 53: 3-bit LUT8 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1536]
register [1537]
register [1538]
register [1539]
register [1540]
register [1541]
register [1542]
register [1543]
LSB
register [1560]
register [1561]
register [1562]
register [1563]
register [1564]
register [1565]
register [1566]
register [1567]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 51: 3-bit LUT6 Truth Table
Table 54: 3-bit LUT9 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1544]
register [1545]
register [1546]
register [1547]
register [1548]
register [1549]
register [1550]
register [1551]
register [1568]
register [1569]
register [1570]
register [1571]
register [1572]
register [1573]
register [1574]
register [1575]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
Table 52: 3-bit LUT7 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [1552]
register [1553]
register [1554]
register [1555]
register [1556]
register [1557]
register [1558]
register [1559]
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT5 is defined by registers [1543:1536]
3-Bit LUT6 is defined by registers [1551:1544]
3-Bit LUT7 is defined by registers [1559:1552]
3-Bit LUT8 is defined by registers [1567:1560]
3-Bit LUT9 is defined by registers [1575:1568]
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 55 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the six 3-bit LUT logic cells.
Table 55: 3-bit LUT Standard Digital Functions
Function
AND-3
MSB
LSB
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-3
OR-3
NOR-3
XOR-3
XNOR-3
7.5 4-BIT LUT OR 16-BIT COUNTER/DELAY MACROCELLS
There are two macrocells that can serve as either 4-bit LUTs or as 16-bit Counter/Delays. When used to implement LUT function,
the 4-bit LUT takes in four input signals from the Connection Matrix and produces a single output, which goes back into the
Connection Matrix. When used to implement 16-Bit Counter/Delay function, four input signals from the connection matrix go to
the external clock (EXT_CLK) and reset (DLY_IN/CNT_Reset), Keep and Up for the Counter/Delay, with the output going back
to the connection matrix.
These two macrocells have an optional Finite State Machine (FSM) function. There are two matrix inputs for Up and Keep to
support FSM functionality. Any counter within GreenPAK is counting down by default. In FSM mode (CNT/DLY0 and CNT/DLY1)
it is possible to reverse counting by applying High level to Up input. Also, there is a possibility to pause counting by applying High
level to Keep input, after the level goes Low, the counter will proceed counting.These macrocells can also operate in a one-shot
mode, which will generate an output pulse of user-defined width.
These macrocells can also operate in a frequency detection.
Delay time and Output Period can be calculated using the following formulas:
Delay time: [(Counter data + 2)/CLK input frequency – Offset*];
Output Period: [(Counter data + 1)/CLK input frequency – Offset*].
One Shot pulse width can be calculated using formula:
Pulse width = [(Counter Data + 2)/CLK input frequency – Offset*];
*Offset is the asynchronous time offset between the input signal and the first clock pulse.
Note Counters initialize with counter data after POR
For timing diagrams refer to Section 7.6.
Both of these macrocells can have their active count value read via I2C. See Section 17.6.1 for further details.
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
7.5.1 4-Bit LUT or 16-Bit CNT/DLY Block Diagram
From Connection
Matrix Output [104]
S0
0: 4-bit LUT0 IN3
1: FSM KEEP
S1
IN3
From Connection
S0
S1
Matrix Output [103]
0: 4-bit LUT0 IN2
1: FSM UP
IN2
IN1
4-bit LUT0
From Connection
Matrix Output [102]
S0
S1
OUT
0: 4-bit LUT0 IN1
1: CNT/DLY0 clk
IN0
LUT Truth
Table
To Connection
S0
S1
Matrix Input [22]
16-bits NVM
Registers [1591:1576]
0: 4-bit LUT0 OUT
1: CNT/DLY0 OUT
CNT
Data
clk
From Connection
S0
S1
Matrix Output [101]
OUT
CNT/DLY0
0: 4-bit LUT0 IN0
1: CNT/DLY0 RST
DLY_IN/CNT_Reset
KEEP
FSM
UP
1-bit NVM
Register [1193]
Figure 36: 4-bit LUT0 or CNT/DLY0
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From Connection
Matrix Output [108]
S0
0: 4-bit LUT1 IN3
1: FSM KEEP
S1
IN3
From Connection
S0
S1
Matrix Output [107]
0: 4-bit LUT1 IN2
1: FSM UP
IN2
IN1
4-bit LUT1
From Connection
Matrix Output [106]
S0
S1
OUT
0: 4-bit LUT1 IN1
1: CNT/DLY1 clk
IN0
LUT Truth
Table
To Connection
Matrix Input [23]
S0
S1
16-bits NVM
Registers [1607:1592]
CNT
Data
clk
From Connection
S0
S1
Matrix Output [105]
OUT
CNT/DLY1
0: 4-bit LUT1 IN0
1: CNT/DLY1 RST
DLY_IN/CNT_Reset
KEEP
FSM
UP
1-bit NVM
Register [1192]
Figure 37: 4-bit LUT1 or CNT/DLY1
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7.5.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs
Table 56: 4-bit LUT0 Truth Table
Table 57: 4-bit LUT1 Truth Table
IN3
0
IN2
0
IN1
0
IN0
0
OUT
IN3
0
IN2
0
IN1
0
IN0
0
OUT
register [1576] LSB
register [1577]
register [1578]
register [1579]
register [1580]
register [1581]
register [1582]
register [1583]
register [1584]
register [1585]
register [1586]
register [1587]
register [1588]
register [1589]
register [1590]
register [1591] MSB
register [1592] LSB
register [1593]
register [1594]
register [1595]
register [1596]
register [1597]
register [1598]
register [1599]
register [1600]
register [1601]
register [1602]
register [1603]
register [1604]
register [1605]
register [1606]
register [1607] MSB
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
Each macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:
4-Bit LUT0 is defined by registers [1591:1576]
4-Bit LUT1 is defined by registers [1607:1592]
Table 58: 4-bit LUT Standard Digital Functions
Function
AND-4
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-4
OR-4
NOR-4
XOR-4
XNOR-4
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7.6 CNT/DLY/FSM TIMING DIAGRAMS
7.6.1 Delay Mode (Edge Select: Both, Counter Data: 3) CNT/DLY2 to CNT/DLY6
Delay In
Asynchronous delay variable
Asynchronous delay variable
RC OSC: force Power-On
(always running)
Delay Output
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
Delay In
offset
offset
RC OSC: auto Power-On
(powers up from delay in)
Delay Output
delay = offset + period x (counter data + 1)
See offset in table 3
delay = offset + period x (counter data + 1)
See offset in table 3
Figure 38: Delay Mode Timing Diagram
7.6.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY2 to CNT/DLY6
RESET_IN
CLK
Counter OUT
4 clk period pulse
Count start in 0 clk after reset
Figure 39: Counter Mode Timing Diagram
7.6.3 One-Shot Mode CNT/DLY0 to CNT/DLY6
This macrocell will generate a pulse whenever a selected edge is detected on its input. Register bits set the edge selection. The
pulse width determines by counter data and clock selection properties. The output pulse polarity (non-inverted or inverted) is
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selected by register bit. See Table 59. Any incoming edges will be ignored during the pulse width generation. The following
diagram shows one-shot function for non-inverted output.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
Delay time
One-Shot Function
Rising Edge Detection
t
One-Shot Function
Falling Edge Detection
t
One-Shot Function
Both Edge Detection
t
Figure 40: One-Shot Function Timing Diagram
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Table 59: DLY/CNTx One-Shot/Freq. Detect Output Polarity
Address
I2C Interface
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
Select the Polarity of DLY/CNT6's One Shot/ 0: Default Output
[1329]
Valid
Valid
Freq. Detect Output
Select the Polarity of DLY/CNT5's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT4's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT3's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT2's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT1's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT0's One Shot/ 0: Default Output
Freq. Detect Output 1: Inverted Output
1: Inverted Output
[1330]
[1331]
[1332]
[1333]
[1334]
[1335]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
A6
This macrocell generates a high level pulse with a set width (defined by counter data) when detecting the respective edge. It does
not restart while pulse is high.
7.6.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6
Rising Edge: The output goes high if the time between two successive edges is less than the delay. The output goes low if the
second rising edge has not come after the last rising edge in specified time.
Falling Edge: The output goes high if the time between two falling edges is less than the set time. The output goes low if the
second falling edge has not come after the last falling edge in specified time.
Both Edge: The output goes high if the time between the rising and falling edges is less than the set time, which is equivalent to
the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not come.
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Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Delay time
Frequency Detector Function
Rising Edge Detection
Frequency Detector Function
Falling Edge Detection
t
t
Frequency Detector Function
Both Edge Detection
Figure 41: Frequency Detection Mode Timing Diagram
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7.6.5 Edge Detection Mode CNT/DLY2 to CNT/DLY6
The macrocell generates high level short pulse when detecting the respective edge. See Table 12.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Edge Detector Function
Rising Edge Detection
Edge Detector Function
Falling Edge Detection
t
t
Edge Detector Function
Both Edge Detection
Figure 42: Edge Detection Mode Timing Diagram
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7.6.6 Delay Mode CNT/DLY0 to CNT/DLY6
The macrocell shifts the respective edge to a set time and restarts by appropriate edge. It works as a filter if the input signal is
shorter than the delay time.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
Delay time
Delay Function
Rising Edge Detection
t
Delay Function
Falling Edge Detection
t
Delay Function
Both Edge Detection
t
Figure 43: Delay Mode Timing Diagram
7.6.7 CNT/FSM Mode CNT/DLY0, CNT/DLY1
RESET IN
KEEP
COUNT END
CLK
3
2
1
0
3
2
1
0
3
2
1
3
2
1
0
0
Q
Note: Q = current counter value
Figure 44: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3
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SET IN
KEEP
COUNT END
CLK
2
1
0
3
2
1
0
3
3
2
1
2
1
0
3
3
Q
Note: Q = current counter value
Figure 45: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3
RESETI N
KEEP
COUNT END
CLK
65535
4
5
5
6
7
8
9
65533 65534
3
3
4
5
1
2
3
4
0
Q
Note: Q = current counter value
Figure 46: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3
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SET IN
KEEP
COUNT END
CLK
8
9
10 11 12
65533 65534 65535
3
4
5
3
4
5
4
5
6
7
3
Q
Note: Q = current counter value
Figure 47: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3
7.6.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes
There is a difference in counter value for Counter and Delay/One-Shot/Frequency Detect modes. The counter value is shifted
for two rising edges of the clock signal in Delay/One-Shot/Frequency Detect modes compared to Counter mode. See Figure 48.
One-Shot/Freq.SET/Delay IN
CLK
CNT Out
3
2
1
0
0
CNT Data
3
2
DLY Out
Delay Data
3
3
2
1
3
3
3
One-Shot Out
One-Shot Data
3
3
3
2
1
3
3
Figure 48: Counter Value, Counter Data = 3
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7.7 2-BIT LUT OR PROGRAMMABLE PATTERN GENERATOR
The SLG46538-A has one combination function macrocell that can serve as a logic or timing function. This macrocell can serve
as a Look Up Table (LUT), or Programmable Pattern Generator (PGen).
When used to implement LUT functions, the 2-bit LUT takes in four input signals from the connection matrix and produces a single
output, which goes back into the connection matrix. When used as a LUT to implement combinatorial logic functions, the outputs
of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND,
OR, NOR, XOR, XNOR). The user can also define the combinatorial relationship between inputs and outputs to be any selectable
function.
When operating as a Programmable Pattern Generator, the output of the macrocell with clock out a sequence of two to sixteen
bits that are user selectable in their bit values, and user selectable in the number of bits (up to sixteen) that are output before the
pattern repeats. See Figure 50.
From Connection Matrix Output [66]
From Connection Matrix Output [67]
In0
In1
OUT
2-bit LUT3
LUT Truth
Table
To Connection Matrix Input [11]
S0
S1
Registers [1623:1608]
0: 2-bit LUT3 OUT
1: PGen OUT
Pattern
Size
nRST
clk
PGen
OUT
PGen
Data
Register [1188]
Register [1211:1208]
Figure 49: 2-bit LUT3 or PGen
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VDD
t
t
nRST
CLK
1
2
6
8
16 17
0
3
4
5
7
9
11
10
14 15
12 13
t
t
OUT
D7
D6
D5
D10
D8
D4
D3
D2
D1
D15
D11
D9
D0
D0
D15
D14
D13
D12
D0
Figure 50: PGen Timing Diagram
7.8 WAKE AND SLEEP CONTROLLER
The SLG46538-A has a Wake and Sleep (WS) function for all ACMPs. The macrocell CNT/DLY0 can be reconfigured for this
purpose registers [1319:1318] = 11 and registers [1495] = 1. The WS serves for power saving, it allows to switch on and off
selected ACMPs on selected bit of 16-bit counter.
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WS Controller
OSC
000:/1
001:/4
010:/12
011:/24
100:/64
CNT0 out
CNT
ck
cnt_end
WS out
WS_PD
To Connection Matrix Input [22]
Power Control
Register [1489]
WS time selection
CK_OSC
WS_PD
From Connection
Matrix Output[58]
From Connection
Matrix Output [54:51]
4
ACMPs_pdb
Analog
Registers
[1316:1314]
Control
Block
bg/regulator pdb
WS out
WS clock freq.
selection
Registers [1591:1576]
WS ratio control data
Registers [1493:1490]
ACMP WS enable
Register [1494]
WS out state for OSC off
WS_PD to W&S out state selection block
4
ACMPs_pdb
ACMP0..3 OUT
4
Latches
+
-
WS out
Note: WS_PD is High at WS OSC (25 kHz/2 MHz OSC) Power-down
WS
To Connection
Matrix Input
[60:57]
Figure 51: Wake/Sleep Controller
To use any ACMP under WS controller the following settings must be done:
ACMP Power Up Input from matrix = 1 (for each ACMP separately);
CNT/DLY0 must be set to Wake and Sleep Controller function (for all ACMPs);
Register WS => enable (for each ACMP separately);
CNT/DLY0 set/reset input = 0 (for all ACMPs);
In case of using OSC1 (25 MHz), OSC0 must be set to Force Power-On.
As the OSC any oscillator with any pre-divider can be used. The user can select a period of time while the ACMPs are sleeping
in a range of 1 - 65535 clock cycles. Before they are sent to sleep their outputs are latched, so the ACMPs remain their state
(High or Low) while sleeping.
WS controller has the following settings:
Wake and Sleep Output State (High/Low)
If OSC is powered off (Power-Down option is selected; power-down input = 1) and Wake and Sleep Output State = High, the
ACMP is continuously on.
If OSC is powered off (Power-Down option is selected; power-down input = 1) and Wake and Sleep Output State = Low, the
ACMP is continuously off.
Both cases WS function is turned off.
Counter Data (Range: 1 - 65535)
User can select wake and sleep ratio of the ACMP; counter data = sleep time, one clock = wake time.
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Q mode - defines the state of WS counter data when Set/Reset signal appears
Reset - when active signal appears, the WS counter will reset to zero and High level signal on its output will turn the ACMPs
on. When Reset signal goes out, the WS counter will go Low and turn the ACMPs off until the counter counts up to the end
Set - when active signal appears, the WS counter will stop and Low level signal on its output will turn the ACMPs off. When
Set signal goes out, the WS counter will go on counting and High level signal will turn the ACMPs on while counter is counting
up to the end.
Edge Select defines the edge for Q mode
High level Set/Reset - switches mode Set/Reset when level is High
Note: Q mode operates only in case of “High Level Set/Reset”.
Wake time selection - time required for wake signal to turn the ACMPs on
Normal Wake Time - when WS signal is High, it takes a BG time (100/550 µs) to turn the ACMPs on. They will stay on until
WS signal is Low again. Wake time is one clock period. It should be longer than BG turn on time and minimal required
comparing time of the ACMP.
Short Wake Time - when WS signal is High, it takes a BG time (100/550 µs) to turn the ACMPs on. They will stay on for 1 µs
and turn off regardless of WS signal. The WS signal width does not matter.
Keep - pauses counting while Keep = 1
Up - reverses counting
If Up = 1, CNT is counting up from user selected value to 65535.
If Up = 0, CNT is counting down from user selected value to 1.
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8
Analog Comparators
There are four Analog Comparator (ACMP) macrocells in the SLG46538-A. In order for the ACMP cells to be used in a GreenPAK
design, the power up signals (ACMPx_pdb) need to be active. By connecting to signals coming from the Connection Matrix, it is
possible to have each ACMP be always on, always off, or power cycled based on a digital signal coming from the Connection
Matrix. Also, all ACMPs have Wake and Sleep function (WS), see Section 7.8. When ACMP is powered down, output is low.
PWR UP = 1 => ACMP is powered up.
PWR UP = 0 => ACMP is powered down.
During ACMP power up, its output will remain low, and then becomes valid 1.03 ms (max) after ACMP power up signal goes high,
see Figure 53. If VDD is greater or equal to 2.7 V, it is possible to decrease turn-on time by setting the BG ok delay to 100 µs, see
Figure 54. The ACMP cells have an input "Low bandwidth" signal selection, which can be used to save power and reduce noise
impact when lower bandwidth signals are being compared. To ensure proper chip startup operation, it is recommended to enable
the ACMPs with the POR signal, and not the VDD signal.
Note: Regulator and Charge Pump set to automatic ON/OFF.
240
220
200
180
160
-40⁰C
+25⁰C
140
+125⁰C
120
VDD (V)
Figure 52: Maximum Power-On Delay vs. VDD, BG = Auto-delay
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1100
1050
1000
950
900
850
800
750
700
650
600
220
210
200
190
180
170
160
150
140
130
120
-40⁰C
+25⁰C
+125⁰C
-40⁰C
+25⁰C
+125⁰C
VDD (V)
Figure 53: Max Power-On Delay vs. VDD, BG = 550 µs
VDD (V)
Figure 54: Max Power-On Delay vs. VDD, BG = 100 µs
Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources. There is also a selectable
gain stage (1x, 0.5x, 0.33x, 0.25x) before connection to the analog comparator. The Gain divider is unbuffered and consists of
250 KΩ (typ) resistors, see Table 60. For gain divider accuracy refer to Table 61. IN- voltage range: 0 - 1.2 V. Can use Vref selection
VDD/4 and VDD/3 to maintain this input range.
Input bias current < 1 nA (typ).
Table 60: Gain Divider Input Resistance
Gain
x1
x0.5
x0.33
x0.25
1 MΩ
Input Resistance
100 MΩ
1 MΩ
0.75 MΩ
Table 61: Gain Divider Accuracy
Gain
x0.5
±0.51 %
x0.33
x0.25
±0.25 %
Accuracy
±0.34 %
Each cell also has a hysteresis selection, to offer hysteresis of (0, 25, 50, 200) mV. The 50 mV and 200 mV hysteresis options
can be used with internal voltage reference only, while 25 mV hysteresis option can be used with both internal and external voltage
reference. The 50 mV and 200 mV hysteresis options are one way hysteresis. It means that the actual thresholds will be Vref
(high threshold) and Vref - hysteresis (low threshold). The ACMP output will retain its previous value, if the input voltage is within
threshold window (between Vref and Vref - hysteresis). Please note: for the 25 mV hysteresis option threshold levels will be Vref +
hysteresis/2 (high threshold) and Vref – hysteresis/2 (low threshold).
Note: Any ACMP powered on enables the BandGap internal circuit as well. An analog voltage will appear on Vref even when the
Force BandGap option is set as Disabled.
For high input impedance when using the gain divider (x0.25, x0.33, x0.5), it is possible to use the input buffer. However, this will
add some offset, see Figure 55 to Figure 56. It is not recommended to use ACMP buffer when VDD < 2.5 V.
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40
30
20
10
Upper Limit @ VDD≥2.7V
Lower Limit @ VDD≥2.7V
VOLTAGE REFERENCE (mV)
0
50
250
600
850
1200
-10
-20
-30
-40
Note: Buffer Bandwidth = 1 kHz, Vhys = 0 mV, Gain = 1, T = -40 °C to +125 °C
Figure 55: Typical Buffer Input Voltage Offset vs. Voltage Reference
20%
15%
10%
5%
Upper Limit
Lower Limit
0%
50
150
250
350
450
550
650
750
850
950
1050
1150
-5%
-10%
-15%
-20%
-25%
VOLTAGE REFERENCE (mV)
Note: LMB Mode - Disable, Vhys = 0 mV, T = -40 °C to +125 °C
Figure 56: Typical Input Threshold Variation (Including Vref Variation, ACMP Offset) vs. Voltage Reference
Note: When VDD < 1.8 V voltage reference should not exceed 1100 mV.
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Table 62: Built-In Hysteresis Tolerance at T = 25 °C
VDD= 1.7 V to 1.8 V
VDD = 1.89 V to 5.5 V
Vref = 50 mV to Vref = 550 V to Vref = 1050 V to
Vhys (mV)
Vref =
50 V to 500 mV
Vref = 550 V to Vref = 1050 V to
500)mV
1000 mV
1200 mV
1000 mV 1200 mV
min
max
32.2
min
max
32.3
min
max
32.5
min
8.5
max
32.3
min
max
32.3
min
max
34.0
25
50
8.6
44.8
192.8
8.6
43.9
194.0
7.0
42.7
192.7
8.5
43.6
193.0
7.8
43.1
190.8
56.5
56.7
56.4
44.2
192.0
56.8
57.3
56.0
200
207.9
208.0
205.4
208.6
209.5
207.7
8.1 ACMP0 BLOCK DIAGRAM AND REGISTER SETTINGS
to ACMP1, ACMP2, AC-
Register [1631]
MP3’s MUX input
Registers [1175:1174]
LBW
Selection
Hysteresis
Selection
External VDD
2.7 V ~ 5.5 V
Registers [1630:1629]
110
100
0X1
BG_ok
IO4: ACMP0(+)
Selectable
Gain
+
-
To Connection
Matrix Input [57]
L/S
0
1
External VDD 1.71 V ~ 5.5 V
pdb
Vref
Latch
*IO4_aio_en; register [1173]; register [1172]
*IO4_aio_en:
if registers [1062:1061] = ’11’ then 1,
otherwise: 0
Register [1490]
ACMP0 Wake & Sleep function Enable
IO9: EXT_Vref
IO5: ACMP0(-)
IO9: EXT_Vref/2
IO5: ACMP0(-)/2
11010
11011
11100
11101
From Connection
Matrix Output [51]
11001-
00000
Internal
Vref
Registers [1628:1624]
Figure 57: ACMP0 Block Diagram
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8.2 ACMP1 BLOCK DIAGRAM AND REGISTER SETTINGS
Register [1639]
AVD = 1.8 V
Registers [1171:1170]
100 µA
Current
Source
Register [1183]
LBW
Selection
en
Hysteresis
Selection
External VDD
2.7 V ~ 5.5 V
Registers [1638:1637]
11X
10X
0X1
BG_ok
IO8: ACMP1(+)
Selectable
Gain
+
To Connection
Matrix Input [58]
L/S
0
1
From ACMP0's MUX output
pdb
Vref
-
Latch
*IO8_aio_en; register [1169]; register [1168]
*IO8_aio_en:
if registers [1093:1092] = ’11’ then 1,
otherwise: 0
Register [1491]
ACMP1 Wake & Sleep function Enable
IO9: EXT_Vref
11010
11011
11100
11101
IO9: EXT_Vref
IO9: EXT_Vref/2
IO9: EXT_Vref/2
From Connection
Matrix Output [52]
11101-
00000
Internal
Vref
Registers [1636:1632]
Note: when 100 µA Current Source is enabled input voltage on IO8 should not exceed 1.8 V
Figure 58: ACMP1 Block Diagram
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8.3 ACMP2 BLOCK DIAGRAM AND REGISTER SETTINGS
Register [1647]
Registers [1182:1181]
LBW
Selection
Hysteresis
Selection
Registers [1646:1645]
IO10: ACMP2(+)
10
01
BG_ok
Selectable
Gain
+
To Connection
Matrix Input [59]
L/S
0
1
from ACMP0’s MUX output
pdb
Vref
-
Latch
*IO10_aio_en; register [1180]
*IO10_aio_en:
if registers [1109:1108] = ’11’ then 1,
otherwise: 0
Register [1492]
ACMP2 Wake & Sleep function Enable
IO9: EXT_Vref
11010
11011
11100
11101
Reserved
IO9: EXT_Vref/2
Reserved
From Connection
Matrix Output [53]
11001-
00000
Internal
Vref
Registers [1644:1640]
Figure 59: ACMP2 Block Diagram
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8.4 ACMP3 BLOCK DIAGRAM AND REGISTER SETTINGS
Register [1655]
Registers [1179:1178]
LBW
Selection
Hysteresis
Selection
Registers [1654:1653]
IO12: ACMP3(+)
From ACMP0’s MUX output
IO10 : ACMP2(+)
00
10
01
BG_ok
L/S
Selectable
Gain
+
To Connection
Matrix Input [60]
0
1
pdb
Vref
-
Latch
*IO12_aio_en; register [1177]; register [1176]
*IO12_aio_en:
if registers [1126:1125] = ’11’ then 1,
otherwise: 0
Register [1493]
ACMP3 Wake & Sleep function Enable
IO9: ACMP3(-)
Reserved
11010
11011
11100
11101
IO9: ACMP3(-)/2
Reserved
From Connection
Matrix Output [54]
11001-
00000
Internal
Vref
Registers [1652:1648]
Figure 60: ACMP3 Block Diagram
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9
Pipe Delay
The SLG46538-A has a pipe delay logic cell that is shared with the LUT3_10 in one of the Combination Function macrocells. The
user can select one of these functions to use in a design, but not both. Please see Section 7.3 for the description of this
Combination Function macrocell.
10 Programmable Delay/Edge Detector
The SLG46538-A has a programmable time delay logic cell available, that can generate a delay, that is selectable from one of
four timings configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay
patterns, rising edge detection, falling edge detection, both edge detection, and both edge delay. See Figure 61 and Figure 62
for further information.
Note: The input signal must be longer than the delay, otherwise it will be filtered out.
Registers [1267:1266]
Delay Value Selection
Registers [1265:1264]
Edge Mode Selection
To Connection
Matrix Input [61]
Programmable
From Connection Matrix Output [57]
IN
OUT
Delay
Figure 61: Programmable Delay
10.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT
width
width
IN
time1
Rising Edge Detector
time1
Falling Edge Detector
Edge Detector
Output
Both Edge Detector
Both Edge Delay
time2
time2
time1 is a fixed value
time2 delay value is selected via register
Figure 62: Edge Detector Output
Please refer to Table 12.
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11 Additional Logic Function. Deglitch Filter
The SLG46538-A has three additional logic functions that are connected directly to the Connection Matrix inputs and outputs.
There are two deglitch filters, each with edge detector functions. See Section 3.8.
11.1 DEGLITCH FILTER/EDGE DETECTOR
Filter_0
R
From Connection Matrix Output [55]
C
To Connection Matrix
Input [30]
Edge
Detect
Register [1462]
Register [1463]
Edge Select
Registers [1461:1460]
Filter_1
R
From Connection Matrix Output [56]
C
Edge
Detect
To Connection Matrix
Input [31]
Register [1458]
Edge Select
Register [1459]
Registers [1457:1456]
Figure 63: Deglitch Filter/Edge Detector
11.2 INV GATE
INV Gate
From Connection Matrix Output [40]
To Connection Matrix Input [50]
Figure 64: INV Gate
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12 Voltage Reference
12.1 VOLTAGE REFERENCE OVERVIEW
The SLG46538-A has a Voltage Reference (Vref) Macrocell to provide references to the four analog comparators. This macrocell
can supply a user selection of fixed voltage references, /3 and /4 reference off of the VDD power supply to the device, and externally
supplied voltage references from IOs 5 and 9. The macrocell also has an option to output reference voltages on IOs 15 and 16.
See Table 63 for the available selections for each analog comparator. Also, see Figure 65, which shows the reference output
structure.
12.2 VREF SELECTION TABLE
Table 63: Vref Selection Table
SEL[4:0]
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
ACMP0_Vref
ACMP1_Vref
ACMP2_Vref
ACMP3_Vref
vref_ext_acmp0/2
vref_ext_acmp1/2
vref_ext_acmp2/2
vref_ext_acmp2/2
vref_ext_acmp1/2
vref_ext_acmp0
vref_ext_acmp1
VDD /4
VDD/3
1.20
vref_ext_acmp1/2
vref_ext_acmp1
vref_ext_acmp1
VDD/4
VDD/3
1.20
vref_ext_acmp1/2
vref_ext_acmp2
vref_ext_acmp1
VDD/4
VDD/3
1.20
vref_ext_acmp1/2
vref_ext_acmp2
vref_ext_acmp1
VDD/4
VDD/3
1.20
1.15
1.15
1.15
1.15
1.10
1.10
1.10
1.10
1.05
1.05
1.05
1.05
1.00
1.00
1.00
1.00
0.95
0.95
0.95
0.95
0.90
0.90
0.90
0.90
0.85
0.85
0.85
0.85
0.80
0.80
0.80
0.80
0.75
0.75
0.75
0.75
0.70
0.70
0.70
0.70
0.65
0.65
0.65
0.65
0.60
0.60
0.60
0.60
0.55
0.55
0.55
0.55
0.50
0.50
0.50
0.50
0.45
0.45
0.45
0.45
0.40
0.40
0.40
0.40
0.35
0.35
0.35
0.35
0.30
0.30
0.30
0.30
0.25
0.25
0.25
0.25
0.20
0.20
0.20
0.20
0.15
0.15
0.15
0.15
0.10
0.10
0.10
0.10
0.05
0.05
0.05
0.05
VDD
Practical Vref Range Note
2.0 V - 5.5 V
1.7 V - 2.0 V
50 mV ~ 1.2 V
50 mV ~ 1.0 V
Do not operate above 1.0 V
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12.3 VREF BLOCK DIAGRAM
Registers [1628:1624]
Register [1476]
IO16_aio_en
Registers [1157:1156]=11
CMP0_VREF
000
001
100
101
110
ext_vref_acmp0
(IO5)
Vref Out_0 (IO16)
Registers [1636:1632]
ext_vref_acmp1
(IO9)
CMP1_VREF
Registers [1644:1640]
ext_vref_acmp2
(IO11)
Registers [1486:1484]
IO15_aio_en
Registers [1149:1148]=11
CMP2_VREF
000
001
100
101
110
Vref Out_1 (IO15)
V
DD/3
Registers [1652:1648]
CMP3_VREF
VDD/4
Registers [1482:1480]
VDD/2
Register [1474]
VDD/3
VDD/4
Figure 65: Voltage Reference Block Diagram
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12.4 VREF LOAD REGULATION
Note 1: Vref buffer performance is not guaranteed at VDD < 2.7 V.
650
600
550
500
450
400
350
VDD=5.5V
VDD=3.3V
VDD=2.7V
I (UA)
Figure 66: Typical Load Regulation, Vref = 600 mV, T = -40 °C to +125 °C, Buffer - Enable
1050
VDD=5.5V
VDD=3.3V
VDD=2.7V
1000
950
900
850
800
750
700
I (UA)
Figure 67: Typical Load Regulation, Vref = 1000 mV, T = -40 °C to +125 °C, Buffer - Enable
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1250
1200
1150
1100
1050
1000
950
VDD=5.5V
VDD=3.3V
VDD=2.7V
900
850
I (UA)
Figure 68: Typical Load Regulation, Vref = 1200 mV, T = -40 °C to +125 °C, Buffer - Enable
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13 Clocking
13.1 OSC GENERAL DESCRIPTION
The SLG46538-A has three internal oscillators. RC Oscillator that runs at 25 kHz/2 MHz (OSC0), Oscillator that runs at 25 MHz
(OSC1) and Crystal Oscillator. It is possible to use all three oscillators simultaneously. The fundamental frequency can also come
from clock input (IO15 or IO17 for 25 kHz/2 MHz and IO14 for 25 MHz or Crystal OSC), see Section 19.
13.2 25 KHZ/2 MHZ AND 25 MHZ RC OSCILLATORS
There are two divider stages that allow the user flexibility for introducing clock signals on various Connection Matrix Input lines.
The pre-divider allows the selection of /1, /2, /4, or /8 divide down frequency from the fundamental. The second stage divider (only
for 25 kHz/2 MHz Oscillator) has an input of frequency from the pre-divider, and outputs one of seven different frequencies on
Connection Matrix Input lines [27] (OUT0) and [28] (OUT1). See Figure 69 and Figure 70 for details.
There are two modes of the POWER CONTROL pin, (register [1658] for 25 kHz/2 MHz OSC and register [1657] for 25 MHz OSC):
POWER-DOWN [0]. If PWR CONTROL input of oscillator is LOW, the oscillator will be turned on. If PWR CONTROL input of
oscillator is HIGH the oscillator will be turned off and OSC divider will reset.
FORCE ON [1]. If PWR CONTROL input of oscillator is HIGH, the oscillator will be turned on. If PWR CONTROL input of
oscillator is LOW the oscillator will be turned off.
The PWR CONTROL signal has the highest priority.
The SLG46538-A has a 25 kHz/2 MHz OSC FAST START-UP function register [1338] (1 – on, 0 – off). It allows the OSC to run
immediately after power-up this decreases the settling time. Note that when OSC FAST START-UP is on, the current consumption
will rise.
The user can select two OSC POWER MODEs (register [1343] for 25 kHz/2 MHz OSC and register [1341] for 25 MHz OSC):
If AUTO POWER-ON [0] is selected, the OSC will run when any macrocell that uses OSC is powered on.
If FORCE POWER-ON [1] is selected, the OSC will run when the SLG46538-A is powered on.
OSC can be turned on by:
Register control (force Power-On)
Delay mode, when delay requires OSC
CNT/FSM
The Power-Down Mode is paired with temperature sensor, Section 18. If it is enabled for Crystal OSC, it is not available for Temp
Sensor and vice versa. However, it is possible to enable Power-Down Mode for Crystal OSC and Temp Sensor simultaneously.
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OSC Power Mode register [1343]
Auto Power-On
0
Force Power-On
1
From Connection Matrix Output [58]
PWR DOWN
Registers [1340:1339]
Internal RCO
0
1
Register [1342]
0: 25 kHz
1: 2 MHz
DIV /1 /2 /4 /8
0
1
IO17 EXT_CLK
Pre-divider
0
1
/ 2
/ 3
IO15 EXT_CLK
EXT_CLK Sel
register [1355]
2
3
4
5
6
7
EXT_CLK Sel register [1358]
/ 4
OUT0
OUT1
To Connection Matrix Input [27]
To Connection Matrix Input [28]
/ 8
/ 12
/ 24
/ 64
Registers [1349:1347]
Registers [1346:1344]
Second Stage
Divider
Figure 69: 25 kHz/2 MHz RC OSC Block Diagram
OSC Power Mode register [1341]
Auto Power-On
Force Power-On
0
1
From Connection Matrix Output [59]
Registers [1337:1336]
PWR DOWN
Internal RCO
0
25 MHz Osc
OUT
To Connection Matrix Input [29]
DIV /1 /2 /4 /8
IO14 EXT_CLK
Divider
1
EXT_CLK Sel register [1357]
Figure 70: 25 MHz RC OSC Block Diagram
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13.3 OSCILLATORS POWER-ON DELAY
OSC enable
Power-On
Delay
CLK
Figure 71: Oscillator Startup Diagram
Note 1: OSC power mode: “Auto Power-On”.
Note 2: “OSC enable” signal appears when any macrocell that uses OSC is powered on.
450
NormalꢀStartͲUpꢀMode
FastꢀStartͲUpꢀMode
400
350
300
250
200
150
VDDꢀ(V)
Figure 72: RC Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 2 MHz
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25
20
15
10
5
NormalꢀStartͲUpꢀMode
FastꢀStartͲUpꢀMode
0
VDDꢀ(V)
Figure 73: RC Oscillator Maximum Power-On Delay vs. VDD at T = 125 °C, OSC0 = 25 kHz
90
80
70
60
50
40
30
20
VDDꢀ(V)
Figure 74: OSC1 (25 MHz) Maximum Power-On Delay vs. VDD at T = 125 °C
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13.4 OSCILLATORS ACCURACY
Note: OSC power setting: Force Power-On; Clock to matrix input - enable; Bandgap: turn on by register - enable.
Note: For more information see Section 3.9.
2.2
2.15
2.1
2.05
2
1.95
Fmax @ VDD=1.8 V
1.9
Fmin @ VDD=1.8 V
Fmax @ VDD=3.3 V
1.85
Fmin @ VDD=3.3 V
Fmax @ VDD=5.0 V
Fmin @ VDD=5.0 V
1.8
1.75
T (°C)
Figure 75: RC Oscillator Frequency vs. Temperature, RC OSC0 = 2 MHz
27
Fmax @ VDD=1.8 V
Fmin @ VDD=1.8 V
26.5
Fmax @ VDD=3.3 V
Fmin @ VDD=3.3 V
Fmax @ VDD=5.0 V
Fmin @ VDD=5.0 V
26
25.5
25
24.5
24
23.5
T (°C)
Figure 76: RC Oscillator Frequency vs. Temperature, RC OSC0 = 25 kHz
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31
29
27
25
23
Fmax @ VDD=1.8 V
21
19
17
Fmin @ VDD=1.8 V
Fmax @ VDD=3.3 V
Fmin @ VDD=3.3 V
Fmax @ VDD=5.0 V
Fmin @ VDD=5.0 V
T (°C)
Figure 77: OSC1 (25 MHz) Frequency vs. Temperature
Note: 25 MHz RC OSC1 performance is not guaranteed at VDD < 2.5 V.
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14 Crystal Oscillator
The Crystal OSC provides high precision and stability of the output frequency. IO14 and IO13 are input and output, respectively,
of an inverting amplifier which is configured for use as an On-chip Oscillator, as shown in Figure 79. Either a quartz crystal or a
ceramic resonator may be used. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of
stray capacitance, and the electromagnetic noise of the environment. Refer to Table 64. For ceramic resonators, the capacitor
values given by the manufacturer should be used. It is possible to use an external clock source, it must be connected to IO14. In
this case no external components are required.
The Power-Down Mode is paired with temperature sensor. If it is enabled for Crystal OSC, it is not available for Temp Sensor and
vice versa. However, it is possible to enable Power-Down Mode for Crystal OSC and Temp Sensor simultaneously.
OSC Power Mode register [1136]
Disable
0
Enable
1
From Connection Matrix Output [109]
PWR DOWN
IO14
OUT
Crystal OSC
To Connection Matrix Input [53]
IO13
Figure 78: Crystal OSC Block Diagram
C1
SLG46538-A
IO14
R1
Crystal
IO13
R2
C2
Figure 79: External Crystal Connection
Table 64: External Components Selection
f
C1
C2
R1
R2
20 kΩ
0 Ω
32.768 kHz
4 - 40 MHz
10 pF
12 pF
330 pF
12 pF
20 MΩ
1 MΩ
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15 Power-On Reset
The SLG46538-A has a Power-On Reset (POR) macrocell to ensure correct device initialization and operation of all macrocells
in the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first
ramping to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined
sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of
the IO pins.
15.1 GENERAL OPERATION
To start the POR sequence in the SLG46538-A, the voltage applied on the VDD should be higher than the Power-On threshold,
see (Note 1). The full operational VDD range for the SLG46538-A is 1.71 V to 5.5 V (1.8 V ±5 % to 5.0 V±10 %). This means that
the VDD voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage
rises to the Power-On threshold. After the POR sequence has started, the SLG46538-A will have a typical period of time to go
through all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after
the POR sequence is complete.
The SLG46538-A is guaranteed to be powered down and nonoperational when the VDD voltage (voltage on VDD) is less than
Power-Off Threshold (see in Electrical Characteristics table), but not less than -0.6 V. Another essential condition for the chip to
be powered down is that no voltage higher (see (Note 2)) than the VDD voltage is applied to any other PIN. For example, if VDD
voltage is 0.3 V, applying a voltage higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device
behavior.
Note 1 The Power-On threshold is defined in Electrical Characteristics table.
Note 2 There is a 0.6V margin due to forward drop voltage of the ESD protection diodes.
To power down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down it
should be less than Power-Off Threshold.
All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step
in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin
configuration at this point in time is defined by the design programmed into the chip. Also, as it was mentioned before the voltage
on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.
Note that VDD2 has no influence on POR sequence, all internal macrocells are powered from VDD. It means, VDD2 can be switched
on/off while VDD is on. If voltage on VDD2 appears after the POR sequence, IOs 9, 10, 12, 13, 14, 15, 16, 17 become available
when VDD2 reaches 0.6 V.
For proper power up sequence, make sure VDD2 will not exceed VDD at any point during startup.
For normal operation VDD should not be switched off while VDD2 is on, due to VDD2 ≤ VDD, see Section 3.
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15.2 POR SEQUENCE
The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 80.
VDD
t
t
t
t
t
t
t
t
POR_NVM
(reset for NVM)
NVM_ready_out
POR_GPI
(reset for input enable)
POR_LUT
(reset for LUT output)
POR_CORE
(reset for DLY/RCO/DFF
/LATCH/Pipe DLY
POR_OUT
(generate low to high to matrix)
POR_GPO
(reset for output enable)
Figure 80: POR Sequence
As can be seen from Figure 80 after the VDD has start ramping up and crosses the Power-On threshold, first, the on-chip NVM
memory is reset. Next, the chip reads the data from NVM, and transfers this information to SRAM registers that serve to configure
each macrocell, and the Connection Matrix which routes signals between macrocells. The third stage causes the reset of the input
pins, and then to enable them. After that, the LUTs are reset and become active. After LUTs, the Delay cells, RC OSC, DFFs,
LATCHES, and Pipe Delay are initialized. Only after all macrocells are initialized internal POR signal (POR macrocell output) goes
from LOW to HIGH. The last portion of the device to be initialized are the output PINs, which transition from high impedance to
active at this point.
The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many
environmental factors, such as: slew rate, VDD value, temperature, and even will vary from chip to chip (process influence).
15.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE
To have a full picture of SLG46538-A operation during powering and POR sequence, review the overview the macrocell output
states during the POR sequence (Figure 81 describes the output signals states).
First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output PINs which are in high
impedance state). Before the NVM is ready, all macrocell outputs are unpredictable (except the output PINs). On the next step,
some of the macrocells start initialization: input pins output state becomes LOW; LUTs also output LOW. Only P DLY macrocell
configured as edge detector becomes active at this time. After that input PINs are enabled. Next, only LUTs are configured. Next,
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all other macrocells are initialized. After macrocells are initialized, internal POR matrix signal switches from LOW to HIGH. The
last are output PINs that become active and determined by the input signals.
VDD
Guaranteed HIGH before POR_GPI
Unpredictable
t
VDD_out
to matrix
t
t
Input PIN_out
to matrix
Unpredictable
Unpredictable
Unpredictable
Determined by External Signal
Determined by Input signals
LUT_out
to matrix
Determined by input signals
OUT = IN without Delay
t
t
t
t
t
t
t
Programmable Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
Prog. Edge_Detector_out
to matrix
Unpredictable
Unpredictable
Unpredictable
Determined by Input signals
Determined by initial state
DFF/LATCH_out
to matrix
Determined by Input signals
Determined by input signals
OUT = IN without Delay
Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
POR_out
to matrix
Unpredictable
Ext. GPO
Tri-state
Determined by Input signals
Output State Unpredictable
Figure 81: Internal Macrocell States during POR Sequence
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15.3.1 Initialization
All internal macrocells by default have initial LOW level. Starting from indicated power-up time of 1.15 V to 1.6 V, macrocells in
GPAK are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then the
reset signal is released for internal macrocells and they start to initialize according to the following sequence:
1. I2C.
2. Input PINs, ACMP, Pull-up/down.
3. LUTs.
4. DFFs, Delays/Counters, Pipe Delay.
5. POR output to matrix.
6. Output PIN corresponds to the internal logic.
The Vref output pin driving signal can precede POR output signal going high by 3 μs - 5 μs. The POR signal going high indicates
the mentioned power-up sequence is complete.
Note: The maximum voltage applied to any PIN should not be higher than the VDD level. There are ESD Diodes between
PIN → VDD and PIN → GND on each PIN. So, if the input signal applied to PIN is higher than VDD, then current will sink through
the diode to VDD. Exceeding VDD results in leakage current on the input PIN, and VDD will be pulled up, following the voltage on
the input PIN.There is no effect from input pin when input voltage is applied at the same time as VDD
.
15.3.2 Power-Down
VDD (V)
2 V
1.6 V
1.15 V
1 V Vref Out Signal
1 V
Time
Not guaranteed output state
Figure 82: Power-Down
During power-down, macrocells in SLG46538-A are powered off after VDD falling down below Power-Off Threshold. Please note
that during a slow rampdown, outputs can possibly switch state during this time.
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16 Asynchronous State Machine Macrocell
16.1 ASM MACROCELL OVERVIEW
The Asynchronous State Machine (ASM) macrocell is designed to allow the user to create state machines with between 2 to 8
states. The user has flexibility to define the available states, the available state transitions, and the input signals (a, b, c …) that
will cause transitions from one state to another state, as shown in Figure 83.
This macrocell has a total of 25 inputs, as shown in Figure 84, which come from the Connection Matrix outputs. Of these 25 inputs,
24 are user selectable for driving general state transitions, and 1 is for driving a state transition to an Initial/Reset state. Each of
the 24 inputs is level sensitive and active high, meaning that a high level input will drive the user selected transition from one state
to another. The fact that there are 24 inputs puts the upper bound of 24 possible state transitions total in the user defined state
machine design. There is on nReset input which will drive an immediate state transition to the user-defined Initial/Reset state
when active, shown in red, in the Figure 83. For more details refer to Section 16.2.
There are a total of 8 outputs, which go to the Connections Matrix inputs, and from there can be routed to other internal macrocells
or pins. The 8 outputs are user defined for each of the possible 8 states. This information is held in the Connection Matrix Output
RAM. For more details refer to Section 16.3.
In using this macrocell, the user must take into consideration the critical timing required on all input and output signals. The timing
waveforms and timing specifications for this macrocell are all measured relative to the input signals (which come into the macrocell
on the Connection Matrix outputs) and on the outputs from the macrocell (which are direct connections to Connection Matrix
inputs). The user must consider any delays from other logic and internal chip connections, including IO delays, to ensure that
signals are properly processed, and state transitions are deterministic.
The GPAK Designer development tools support user designs for the ASM macrocell at both the physical level and logic level.
Figure 83 is a representation of the user design at the logical level, and Figure 84 shows the physical resources inside the
macrocell. To best utilize this macrocell, the user must develop a logical representation of their desired state machine, as well as
a physical mapping of the input and outputs required for the desired functionality.
Off
a
d
c
Normal
Speed
Standby
Fault
b
e
f
g
h
High
Speed
Figure 83: Asynchronous State Machine State Transitions
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Connection Matrix
State Holding
Output RAM
(8x8)
Latches
State 0
State 0 In
State 1 In
State 2 In
State 3 In
State 4 In
State 5 In
State 6 In
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
Output Bits (8)
State 1
Output Bits (8)
State 2
Output Bits (8)
State 3
Output Bits (8)
from
Connection
Matrix
State
Transition
Signal
State 4
Output Bits (8)
Routing
State 5
Output Bits (8)
State 6
Output Bits (8)
State 7
Output Bits (8)
State 7 In
nReset
to Connection Matrix
Figure 84: Asynchronous State Machine
16.2 ASM INPUTS
The ASM macrocell has a total of 25 inputs which come from the Connection Matrix outputs. Of these 25 inputs, 24 are user
selectable for driving general state transitions, and 1 is for driving a state transition to an Initial/Reset state.
There are a total of 24 inputs to the ASM macrocell for general state transitions, highlighted in red in Figure 85. Each of these
inputs is level sensitive, and active high. A high level input will trigger a state transition.
These inputs are grouped so that each set of 3 inputs can drive a state transition going into a particular state. As an example,
there are three inputs that can drive a state transition to State 1. This sets an upper bound on the number of transitions that the
user can select going into a particular state to be 3, shown in Figure 86.
There is no limitation on the number of transitions that can be supported coming out of a particular state, the user can select to
have transitions going from a state to all other states, shown in Figure 87.
The ASM macrocell also has a nReset input highlighted in blue in Figure 85. This input is level sensitive and active low. An
active signal on this input will drive an immediate state transition to the user-defined Initial/Reset state. The user can choose
which state within the ASM Editor inside GPAK Designer is the initial state.
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Connection Matrix
Output RAM
(8x8)
State Holding
Latches
State 0
State 0 In
State 1 In
State 2 In
State 3 In
State 4 In
State 5 In
State 6 In
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
Output Bits (8)
State 1
Output Bits (8)
State 2
Output Bits (8)
State 3
Output Bits (8)
from
Connection
Matrix
State
Transition
Signal
State 4
Output Bits (8)
Routing
State 5
Output Bits (8)
State 6
Output Bits (8)
State 7
Output Bits (8)
State 7 In
nReset
to Connection Matrix
Figure 85: Asynchronous State Machine Inputs
State 1
State 0
State 3
State 2
Figure 86: Maximum 3 State Transitions into Given State
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State 1
State 7
State 2
State 0
State 6
State 3
State5
State 4
Figure 87: Maximum 7 State Transitions out of a Given State
16.3 ASM OUTPUTS
There are a total of 8 outputs from the ASM macrocell, which go to the Connections Matrix inputs, and from there can be routed
to other internal macrocells or pins. The 8 outputs are user defined for each of the possible 8 states, this information is held in
the Connection Matrix Output RAM, shown in Figure 88. The Connection Matrix Output RAM has a total of 64 bits, arranged as
8 bits per state. The values loaded in each of the 8 bits define the signal level on each of the 8 ASM macrocell outputs.
The ASM Editor inside the GPAK Designer software allows the user to make their selections for the value of each bit in the
Connection Matrix Output RAM, which selects the level of the macrocell outputs based on the current state of the ASM
macrocell, as shown in Figure 88.
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Connection Matrix
Output RAM
(8x8)
State Holding
Latches
State 0
State 0 In
State 1 In
State 2 In
State 3 In
State 4 In
State 5 In
State 6 In
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
Output Bits (8)
State 1
Output Bits (8)
State 2
Output Bits (8)
State 3
Output Bits (8)
from
Connection
Matrix
State
Transition
Signal
State 4
Output Bits (8)
Routing
State 5
Output Bits (8)
State 6
Output Bits (8)
State 7
Output Bits (8)
State 7 In
nReset
to Connection Matrix
Figure 88: Connection Matrix Output RAM
Table 65: ASM Editor - Connection Matrix Output RAM
RAM
Connection Matrix Output RAM
State name
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
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There is a possibility to configure ASM (it's settings and transitions) via I2C. Registers (registers [197:0]) correspond for ASM
inputs, registers (registers [1727:1664]) correspond for ASM outputs configuration. Using I2C commands (see Section 17.4) it is
possible to read ASM settings and connections, as well as change them. Additionally, user can change Connection Matrix Output
RAM bit configuration (bytes 0xD0 to 0xD7).
Note: After Connection Matrix Output RAM was updated via I2C, ASM outputs to Connection Matrix can be changed only after
ASM changes its state or after reset event. To change ASM outputs to Connection Matrix instantly after I2C write command, ASM
must be in reset all the time.
16.4 BASIC ASM TIMING
The basic state transition timing from input on Matrix Connection output to output on Matrix Connection input is shown in Figure
89 and Figure 90. The time from a valid input signal to the time that there is a valid change of state and valid signals being
available on the state outputs is State Machine Output Delay Time (Tst_out_delay). The minimum and maximum values of
Tst_out_delay define the differential timing between the shortest state transition (input on matrix output and output on matrix input)
and the longest state transition (input on matrix output and output on matrix input).
a
State 0
State 1
Figure 89: State Transition
Input
Signal (a)
Tst_out_delay
State
Outputs
State 0
State 1
Figure 90: State Transition Timing
16.5 ASYNCHRONOUS STATE MACHINES VS. SYNCHRONOUS STATE MACHINES
It is important to note that this macrocell is designed for asynchronous operation, which means the following:
1. No clock source is needed, it reacts only to input signals.
2. The input signals do not have to be synchronized to each other, the macrocell will react to the earliest valid signal for state
transition.
3. This macrocell does not have traditional set-up and hold time specifications which are related to incoming clock, as this
macrocell has no clock source.
4. The macrocell only consumes power while in state transition.
16.6 ASM POWER CONSIDERATIONS
A benefit of the asynchronous nature of this macrocell is that it will consume power only during state transitions. Shown in
Figure 89 and Figure 91, the current consumption of the macrocell will be a fraction of a µA between state transitions, and will
rise only during state transitions. See Section 3.4 to find average current during state transitions.
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a
State 0
State 1
Figure 91: State Transition
Input
Signal (a)
Tst_out_delay
State
Outputs
State 0
State 1
Average Active ASM Power
ASM
Power
Consumption
Sub μA Inactive ASM Power Consumption
Figure 92: State Transition Timing and Power Consumption
16.7 ASM LOGICAL VS. PHYSICAL DESIGN
A successful design with the ASM macrocell must include both the logic level design, as well as the physical level design. The
GPAK Designer development software support user designs for the ASM macrocell at both the logic level and physical level.
The logic level design of the user defined state machine takes place inside the ASM Editor. In the ASM Editor, the user can
select and name states, define and name allowed state transitions, define the Initial/Reset state, and define the output values for
the 8 outputs in the Output RAM Matrix. The physical level design takes place in the general GPAK Designer window, and here
the user makes connections for the sources for ASM input signals, as well as making connections for destinations for ASM
output signals.
16.8 ASM SPECIAL CASE TIMING CONSIDERATIONS
16.8.1 State Transition Pulse Input Timing
All inputs to the ASM macrocell are level sensitive. If the input to the state machine macrocell for a state transition is a pulse,
there is a minimum pulse width on the input to the state machine macrocell (as measured at the matrix input to the macrocell)
which is guaranteed to result in a state transition shown in Figure 93 and Figure 94. This pulse width is defined by the State
Machine Input Pulse Acceptance Time (Tst_pulse). If a pulse width that is shorter than Tst_pulse is input to the state machine
macrocell, it is indeterminate whether the state transition will happen or not. If a pulse that is rejected (invalid due to the pulse
width being narrower than the guaranteed minimum of Tst_pulse), this will not stop a valid pulse on another state transition input
that does meet minimum pulse width.
a
State 0
State 1
Figure 93: State Transition
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Input
Signal (a)
Tst_pulse
Tst_pulse
State
Outputs
State 0
State 1
Tst_out_delay
Figure 94: State Transition Pulse Input Timing
16.8.2 State Transition Competing Input Timing
There will be situations where two input signals can be valid inputs that will drive two different state transitions from a given state.
In that sense, the two signals are “competing” (signals a and b in Figure 95), and the signal that arrives sooner should drive the
state transition that will “win”, or drive the state transition. If one signal arrives Tst_comp before the other one, it is guaranteed to
win, and the state transition that it codes for will be taken, as shown in Figure 96. If the two signals arrive within Tst_comp of each
other, it will be indeterminate which state transition will win, but one of the transitions will take place as long as the winning signal
satisfies the pulse width criteria described in the paragraph above, as shown in Figure 97.
a
b
State 0
State 1
State 2
Figure 95: State Transition - Competing Inputs
Input
Signal (a)
Tst_comp
Input
Signal (b)
Tst_out_delay
State
Outputs
State 0
State 1 or State 2
Figure 96: State Transition Timing - Competing Inputs Indeterminate
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Input
Signal (a)
Tst_comp
Input
Signal (b)
Tst_out_delay
State
Outputs
State 0
State 1
Figure 97: State Transition Timing - Competing Inputs Determinable
16.8.3 ASM State Transition Sequential Timing
It is possible to have a valid input signal for a transition out from a particular state be active before the state is active. If this is the
case, the macrocell will only stay in that particular state for Tst_out_delay time before making the transition to the next state. An
example of this sequential behavior is shown in Figure 98 and the associated timing is shown in Figure 99.
a
b
State 0
State 1
State 2
Figure 98: State Transition - Sequential
Input
Signal (a)
Input
Signal (b)
Tst_out_delay
Tst_out_delay
State
Outputs
State 0
State 1
State 2
Figure 99: State Transition - Sequential Timing
16.8.4 State Transition Closed Cycling
It is possible to have a closed cycle of state transitions that will run continuously if there are valid inputs that are active at the
same time. The rate at which the state transitions will take place is determined by Tst_out_delay. The example shown here in
Figure 100 involves cycling between two states, but any number of two – eight states can be included in state transition closed
cycling of this nature. Figure 101 shows the associated timing for closed cycling.
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a
State 0
State 1
b
Figure 100: State Transition - Closed Cycling
Input
Signal (a)
Input
Signal (b)
Tst_out_delay
Tst_out_delay
Tst_out_delay
State
Outputs
State 0
State 1
State 0
State 1
Figure 101: State Transition - Closed Cycling Timing
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2
17 I C Serial Communications Macrocell
17.1 I2C SERIAL COMMUNICATIONS MACROCELL OVERVIEW
In the standard use case for the GreenPAK devices, the configuration choices made by the user are stored as bit settings in the
Non-Volatile Memory (NVM), and this information is transferred at startup time to volatile RAM registers that enable the
configuration of the macrocells. Other RAM registers in the device are responsible for setting the connections in the Connection
Matrix to route signals in the manner most appropriate for the user’s application.
The I2C Serial Communications Macrocell in this device allows an I2C bus Master to read and write this information via a serial
channel directly to the RAM registers, allowing the remote re-configuration of macrocells, and remote changes to signal chains
within the device.
An I2C bus Master is also able read and write other register bits that are not associated with NVM memory. As an example, the
input lines to the Connection Matrix can be read as digital register bits. These are the signal outputs of each of the macrocells in
the device, giving an I2C bus Master the capability to remotely read the current value of any macrocell.
The user has the flexibility to control read access and write access via registers bits register [1832], register [1870], and
register [1871]. See Section 17.5 for more details on I2C read/write memory protection.
Note: GreenPAK I2C is fully compatible with standard I2C protocol.
17.2 I2C SERIAL COMMUNICATIONS DEVICE ADDRESSING
Each command to the I2C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are
shown in Figure 102. After the Start bit, the first four bits are a control code, which can be set by the user in registers [1867:1864].
This gives the user flexibility on the chip level addressing of this device and other devices on the same I2C bus. The Block Address
is the next three bits (A10, A9, A8), which will define the most significant bits in the addressing of the data to be read or written
by the command. The last bit in the Control Byte is the R/W bit, which selects whether a read command or write command is
requested, with a “1” selecting for a Read command, and a “0” selecting for a Write command. This Control Byte will be followed
by an Acknowledge bit (ACK), which is sent by this device to indicate successful communication of the Control Byte data.
In the I2C-bus specification and user manual, there are two groups of eight addresses (0000 xxx and 1111 xxx) that are reserved
for the special functions, such as a system General Call address. If the user of this device choses to set the Control Code to either
“1111” or “0000” in a system with other slave device, please consult the I2C-bus specification and user manual to understand the
addressing and implementation of these special functions, to ensure reliable operation.
In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of
information, resulting in a total address space of 2K bytes. Of this 2K byte address space, the valid addresses accessible to the
I2C Macrocell on the SLG46538-A are in the range from 0 (0x00) to 255 (0xFF). The MSB address bits (A10, A9, and A8) will be
“0” for all commands to the SLG46538-A.
With the exception of the Current Address Read command, all commands will have the Control Byte followed by the Word
Address. Figure 102 shows this basic command structure.
Start
bit
Acknowledge
bit
Control Byte
Word Address
A
10
A
9
A
8
A
7
A
0
S
X
X
X
X
R/W ACK
Control
Code
Block
Address
Not used, set to 0
Read/Write bit
(1 = Read, 0 = Write)
Figure 102: Basic Command Structure
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
17.3 I2C SERIAL GENERAL TIMING
General timing characteristics for the I2C Serial Communications macrocell are shown in Figure 103. Timing specifications can
be found in the Section 3.4.
tHIGH
tF
tR
tLOW
SCL
tSU STA
tHD DAT
tHD STA
tSU DAT
tSU STO
SDA IN
tBUF
tAA
tDH
SDA OUT
Figure 103: I2C General Timing Characteristics
17.4 I2C SERIAL COMMUNICATIONS COMMANDS
17.4.1 Byte Write Command
Following the Start condition from the Master, the Control Code [4 bits], the Block Address [3 bits], and the R/W bit (set to “0”),
are placed onto the I2C bus by the Master. After the SLG46538-A sends an Acknowledge bit (ACK), the next byte transmitted by
the Master is the Word Address. The Block Address (A10, A9, A8), combined with the Word Address (A7 through A0), together
set the internal address pointer in the SLG46538-A, where the data byte is to be written. After the SLG46538-A sends another
Acknowledge bit, the Master will transmit the data byte to be written into the addressed memory location. The SLG46538-A again
provides an Acknowledge bit and then the Master generates a Stop condition. The internal write cycle for the data will take place
at the time that the SLG46538-A generates the Acknowledge bit.
Acknowledge
bit
Acknowledge
bit
Start
bit
Acknowledge
bit
Bus Activity
Control Byte
Word Address
Data
A
10
A
9
A
8
A
7
A
0
D
7
D
0
S
X
X
X
X
W
ACK
ACK
ACK
SDA LINE
P
Control
Code
Block
Address
Stop
bit
Not used, set to 0
R/W bit = 0
Figure 104: Byte Write Command, R/W = 0
17.4.2 Sequential Write Command
The write Control Byte, Word Address, and the first data byte are transmitted to the SLG46538-A in the same way as in a Byte
Write command. However, instead of generating a Stop condition, the Bus Master continues to transmit data bytes to the
SLG46538-A. Each subsequent data byte will increment the internal address counter, and will be written into the next higher byte
in the command addressing. As in the case of the Byte Write command, the internal write cycle will take place at the time that the
SLG46538-A generates the Acknowledge bit.
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Acknowledge
bit
Data (n + x)
Acknowledge
Start
bit
bit
Bus Activity
Data (n + 1)
Control Byte
Word Address (n)
Data (n)
A
10
A
8
A
9
ACK
ACK
P
SDA LINE
S
X
X
X
X
W
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
Not used, set t
o 0
R/W bit = 0
Figure 105: Sequential Write Command
17.4.3 Current Address Read Command
The Current Address Read Command reads from the current pointer address location. The address pointer is incremented at the
first STOP bit following any write control byte. For example, if a Sequential Read command (which contains a write control byte)
reads data up to address n, the address pointer would get incremented to n + 1 upon the STOP of that command. Subsequently,
a Current Address Read that follows would start reading data at n + 1. The Current Address Read Command contains the Control
Byte sent by the Master, with the R/W bit = “1”. The SLG46538-A will issue an Acknowledge bit, and then transmit eight data bits
for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition.
Start
bit
Acknowledge
bit
Stop
bit
Bus Activity
Control Byte
Data (n)
A
10
A
9
A
8
S
X
X
X
X
R
ACK
NACK
SDA LINE
P
Control
Code
Block
Address
No Ack
bit
Not used, set
to 0
R/W bit = 1
Figure 106: Current Address Read Command, R/W = 1
17.4.4 Random Read Command
The Random Read command starts with a Control Byte (with R/W bit set to “0”, indicating a write command) and Word Address
to set the internal byte address, followed by a Start bit, and then the Control Byte for the read (exactly the same as the Byte Write
command). The Start bit in the middle of the command will halt the decoding of a Write command, but will set the internal address
counter in preparation for the second half of the command. After the Start bit, the Bus Master issues a second control byte with
the R/W bit set to “1”, after which the SLG46538-A issues an Acknowledge bit, followed by the requested eight data bits.
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Acknowledge
Stop
bit
Start
bit
bit
Bus Activity
Data (n)
Control Byte
Word Address (n)
Control Byte
A
10
A
9
A
8
A
10
A
9
A
8
S
ACK
X
X
X
X
R ACK
P
SDA LINE
S
X
X
X
X
W
ACK
Control
Code
Block
Address
Control
Code
R/W bit = 1
No Ack
bit
Not used, set to 0
R/W bit = 0
Figure 107: Random Read Command
17.4.5 Sequential Read Command
The Sequential Read command is initiated in the same way as a Current Address Read or Random Read command, except that
once the SLG46538-A transmits the first data byte, the Master issues an Acknowledge bit as opposed to a Stop condition in a
random read. The Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition.
Acknowledge
Start
bit
bit
Bus Activity
Data (n + 2)
Data (n + x)
Control Byte
Data (n)
Data (n+1)
A
8
A
10
A
9
ACK
P
SDA LINE
S
X
X
X
X
R
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
Not used, set
to 0
No Ack
bit
R/W bit = 1
Figure 108: Sequential Read Command
17.4.6 I2C Serial Command Address Space
In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of
information, resulting in a total address space of 2K bytes. Of this 2K byte address space, the valid addresses accessible to the
I2C Macrocell on the SLG46538-A are in the range from 0 (0x00) to 255 (0xFF). The MSB address bits (A10, A9, and A8) will be
“0” for all commands to the SLG46538-A.
17.4.7 I2C Serial Command Register Map
These register addresses are broken down into four Banks to give the user greater control on access to reading and writing
information in each bank. Each of the four banks is 512 bits (64 bytes) in length. Writing information to register bits in these Banks
will change the configuration of the device, resulting in either a change in the interconnection options provided by the Connection
Matrix, or by changing the configuration of individual macrocells. During device use, all register bits can be read or written via I2C,
unless protection bits are set to prevent this.
See Section 20 for detailed information on all register bits.
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Byte 255
Bank 3
Byte 192
Byte 191
Bank 2
Byte 128
Byte 127
Bank 1
Byte 64
Byte 63
Bank 0
Byte 0
Figure 109: Register Bank Map
17.5 I2C SERIAL COMMAND REGISTER PROTECTION
The memory space is divided into four banks, each of which has 512bits (64bytes). There are three bits that allow the user to
define rules for reading and writing bits in each of these banks via I2C:
register [1832] I2C lock for read bits [1535:0] (Bank 0/1/2). If the system provides any read commands to the addresses in
these three banks, the device will respond with ‘FFH’ in data field.
register [1871] I2C lock for write bits [1535:0] (Bank 0/1/2). If the system provides any write commands to the addresses in
these three banks, the device will acknowledge these commands, but will not do internal writes to the register space.
register [1870] I2C lock for write all bits (Bank 0/1/2/3). If the system provides any write commands to the addresses in these
four banks, the device will acknowledge these commands, but will not do internal writes to the register space.
Note: register [1870] is higher priority than register [1871], and if register [1870] is set, than register [1871] does not have any
effect.
Note: If the user sets IOs 6 and 7 function to a selection other than SDA and SCL, all access via I2C will be disabled.
If register [1870] is not set, register bits in Bank 3 are open to read and write commands via I2C with the following exceptions:
register [1871] Bank 0/1/2 I2C-write protection bit is always protected from I2C write
registers [1867:1864] I2C Control Code Bit [3:0] is always protected from I2C write
Note: Any write commands that come to the device via I2C that are not blocked, based on the protection bits, will change the
contents of the RAM register bits that mirror the NVM bits. These write commands will not change the NVM bits themselves, and
a POR event will restore the register bits to original programmed contents of the NVM.
See Section 20 for detailed information on all registers.
17.5.1 Register Read/Write Protection
There are six read/write protect modes for the design sequence from being corrupted or copied. See Table 66 for details.
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
.
Table 66: Read/Write Protection Options
Lock Status
Locked
for read
bits
[1535:0]
andwrite
all bits
Locked
Locked for read
forwrite andwrite
Locked
Locked
for read for write
Unlocked
bits
bits
Bank
Byte
Bits
Description
all bits
bits
[1535:0]
[1535:0]
[1535:0]
register
[1832] = 0,
[1871] = 0,
[1870] = 0
register
[1832] = 1,
[1871] = 0,
[1870] = 0
register
[1832] = 0,
[1871] = 1,
[1870] = 0
register
[1832] =0,
[1871] = x,
[1870] = 1
register
[1832] = 1,
[1871] = 1,
[1870] = 0
register
[1832] = 1,
[1871] = x,
[1870] = 1
0
1
0-63
511-0
Connection Matrix
Outputs
Configuration
R/W
R/W
-
W
W
-
R
R
-
R
R
-
-
-
-
-
-
-
64-109
879-512
110-127 880-1023
128-186 1495-1024
Reserved
Function
Configuration for
PINs, LUTs/DFFs,
OSC,ASMandsome
configuration for
DLYs, ACMP
R/W
W
R
R
-
-
2
187-191 1535-1496
192-206 1655-1536
Reserved
-
-
-
-
-
-
CNT/DLY counter
data and some LUTs
truth table, ACMP
Vref
R/W
R/W
R/W
R
R/W
R
I2C reset bit with
reloading NVM into
Data register
1662
R/W
R/W
R/W
R
R/W
R
3
207
1661-1659,
Reserved
R
R
R
R
R
R
R
R
1663
1658-1656 OSC Power Control
R/W
R/W
R/W
R/W
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 66: Read/Write Protection Options (Continued)
Lock Status
Locked
for read
bits
[1535:0]
andwrite
all bits
Locked
Locked for read
forwrite andwrite
Locked
Locked
for read for write
Unlocked
bits
bits
Bank
Byte
Bits
Description
all bits
bits
[1535:0]
[1535:0]
[1535:0]
register
[1832] = 0,
[1871] = 0,
[1870] = 0
register
[1832] = 1,
[1871] = 0,
[1870] = 0
register
[1832] = 0,
[1871] = 1,
[1870] = 0
register
[1832] =0,
[1871] = x,
[1870] = 1
register
[1832] = 1,
[1871] = 1,
[1870] = 0
register
[1832] = 1,
[1871] = x,
[1870] = 1
ASM output RAM
and User
configurable RAM /
OTP
208-223 1791-1664
224-227 1823-1792
R/W
R/W
R/W
R
R/W
R
Reserved
Reserved
-
R/W
R
-
R/W
R
-
R/W
R
-
-
R/W
R
-
228
1831-1824
1839-1836
1835-1834
1833
R
R
-
R
R
-
Product Family ID
Reserved
-
-
-
-
229
Reserved
R
R
R
R
R
R
I2C Lock for read bits
[1535:0]
1832
R
R
R
R
R
R
230
231
232
1847-1840
1855-1848
1863-1856
Pattern ID
Reserved
Reserved
R/W
R
R/W
R
R/W
R
R
R
R
R/W
R
R
R
R
R
R
R
R
I2C Lockfor writebits
[1535:0]
I2C Lock for write all
bits
3
1871
1870
R
R
R
R
R
R
R
R
R
R
R
R
233
1869-1868
1867-1864
Reserved
I2C Control Code
-
-
-
-
-
-
R
R
R
R
R
R
Counter Current
Value
234-239 1919-1872
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Macrocells Output
240-243 1951-1920 Values (Connection
Matrix Inputs)
Connection Matrix
244
1959-1952
R/W
R
R/W
R
R/W
R
R/W
R
Virtual Inputs
Macrocells Output
245-247 1983-1960 Values (Connection
Matrix Inputs)
248-250 2007-1984
251 2015-2008
252-253 2031-2016
Reserved
Reserved
Reserved
Reserved
Reserved
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R
R/W
R
R/W
R
R/W
R
3
254
255
2039-2032
2047-2040
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Allow Read and Write Data
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with Asynchronous State Machine and Dual Supply
W
R
-
Allow Write Data Only
Allow Read Data Only
The Data is protected for Read and Write
17.5.2 I2C Serial Reset Command
If I2C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including
configuration of all macrocells, and all connections provided by the Connection Matrix. This is implemented by setting
register [1662] I2C reset bit to “1”, which causes the device to re-enable the Power-On Reset (POR) sequence, including the
reload of all register data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has
taken place, the contents of register [1662] will be set to “0” automatically. Figure 110 illustrates the sequence of events for this
reset function.
Note: I2C Serial Reset Command is not available during emulation.
Acknowledge
bit
Acknowledge
bit
Start
bit
Acknowledge
bit
Bus Activity
Control Byte
Word Address
Data
A
10
A
9
A
8
A
7
A
0
D
7
D
0
S
X
X
X
X
W
ACK
ACK
ACK
SDA LINE
P
Control
Code
Block
Address
Stop
bit
Internal Reset bit
Not used, set to 0
Write bit
by I2C Stop Signal
Reset-bit register output
Internal POR
reloading NVM into Data register
Reset-bit register (register [1662]) is cleared by reloading NVM into Data register
1) I2C write with register [1662] = 1 (I2C reset bit with reloading NVM into Data register)
2) POR go to LOW and reloading NVM into Data register start after “STOP” of I2C
3) POR go to HIGH after reloading NVM into Data register
Figure 110: Reset Command Timing
17.6 I2C ADDITIONAL OPTIONS
17.6.1 Reading Counter Data via I2C
The current count value in four counters in the device can be read via I2C. The counters that have this additional functionality are
16-bit CNT0 and CNT1, and 8-bit counters CNT4 and CNT6.
17.6.2 User RAM and OTP Memory Array
There are eight bytes of RAM memory that can be read and written remotely by I2C commands. The initial contents of this memory
space can be selected by the user, and this information will be transferred from OTP memory to the RAM memory space during
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the power-up sequence. The lowest order byte in this array (User Configurable RAM/OTP Byte 0) is located at I2C address 0xD8,
and the highest order byte in this array is located at I2C address 0xDF.
Table 67: RAM Array Table
I2C Address
(hex)
Highest Bit
Address
Lowest Bit
Address
Memory Byte
D8
D9
DA
DB
DC
DD
DE
DF
1735
1743
1751
1759
1767
1775
1783
1791
1728
1736
1744
1752
1760
1768
1776
1784
User Configurable RAM/OTP Byte 0
User Configurable RAM/OTP Byte 1
User Configurable RAM/OTP Byte 2
User Configurable RAM/OTP Byte 3
User Configurable RAM/OTP Byte 4
User Configurable RAM/OTP Byte 5
User Configurable RAM/OTP Byte 6
User Configurable RAM/OTP Byte 7
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18 Analog Temperature Sensor
The SLG46538-A has an Analog Temperature sensor (TS) with an output voltage linearly-proportional to the Centigrade
temperature. The TS is rated to operate over a -40 °C to 180 °C temperature range. The error in the whole temperature range
does not exceed ±10.3 % (±5.7 % in a range from -40 °C to 100 °C). TS output voltage variation over VDD at constant
temperature is less than ±10.3 %. For more detail refer to section 3.11.
TS
Register [1470] = 0 Vref Op Amp Offset Chopper Clock frequency 2 MHz
Register [1469] = 1 Bandgap Op Amp Offset Chopper Enable
VDD
From Connection Matrix Output [109]
Register [1464]
PWR DOWN
1
0
+
-
VREF0
IO16
VCP, registers [1474:1472] = 100
(always CP should be on)
Open
TS_O
Register [1464] = 1
Registers [1486:1484]
Register [1478]
Vref
select
0
1
TS_On
Register [1464] = 1
Closed
Figure 111: Analog Temperature Sensor Structure Diagram
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1.2
1.1
1
Output Range 1
Output Range 2
0.9
0.8
0.7
0.6
0.5
0.4
T (°C)
Figure 112: TS Output vs. Temperature, VDD = 1.71 V to 5.5 V
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19 External Clocking
The SLG46538-A supports several ways to use an external, higher accuracy clock as a reference source for internal operations.
19.1 CRYSTAL MODE
When register [1136] is set to 1, an external crystal can be connected to IOs 13 and 14 for supplying an accurate clock source.
See Section 14. An external clocking signal on IO14 can be used in place of the crystal. The high and low limits for crystal
frequency that can be selected are 32.768 kHz and 40 MHz.
19.2 IO17 OR IO15 SOURCE FOR 25 KHZ/2 MHZ CLOCK
When register [1358] is set to 1, an external clocking signal on IOs 15 or 17 will be routed in place of the internal RC oscillator
derived 25 kHz/2 MHz clock source. When register [1355] is set to 0, IO17 is in use, when set to 1, IO15 is in use. See Figure 69.
The high and low limits for external frequency that can be selected are 0 MHz and 77 MHz.
19.3 IO14 SOURCE FOR 25 MHZ CLOCK
When register [1357] is set to 1, an external clocking signal on IO14 will be routed in place of the internal RC oscillator derived
25 MHz clock source. See Figure 70. The high and low limits for external frequency that can be selected are 0 MHz and 84 MHz.
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20 Register Definitions
20.1 REGISTER MAP
Table 68: Register Map
Address
I2C Interface
Read Write
Signal Function
Register Bit Definition
Byte
Register Bit
Note: For register [0] to register [1495], I2C Read is valid (assuming register [1832] = 0), I2C Write is valid (assuming
register [1871] = 0)
Matrix 64-to-1 MUX's 6 selection bits
5:0
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
ASM-state0-EN0
ASM-state0-EN1
ASM-state0-EN2
ASM-state1-EN0
ASM-state1-EN1
ASM-state1-EN2
ASM-state2-EN0
ASM-state2-EN1
ASM-state2-EN2
ASM-state3-EN0
ASM-state3-EN1
ASM-state3-EN2
ASM-state4-EN0
ASM-state4-EN1
ASM-state4-EN2
ASM-state5-EN0
ASM-state5-EN1
ASM-state5-EN2
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
7:6
13:8
15:14
21:16
23:22
29:24
31:30
37:32
39:38
45:40
47:46
53:48
55:54
61:56
63:62
69:64
71:70
77:72
79:78
85:80
87:86
93:88
95:94
101:96
103:102
109:104
111:110
117:112
119:118
125:120
127:126
133:128
135:134
141:136
143:142
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GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
149:144
151:150
157:152
159:158
165:160
167:166
173:168
175:174
181:176
183:182
189:184
191:190
197:192
199:198
205:200
207:206
213:208
215:214
221:216
223:222
229:224
231:230
237:232
239:238
245:240
247:246
253:248
255:254
261:256
263:262
Read
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Write
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
ASM-state6-EN0
12
ASM-state6-EN1
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
ASM-state6-EN2
ASM-state7-EN0
ASM-state7-EN1
ASM-state7-EN2
ASM-state-nRST
IO1 Digital Output Source
IO1 Output Enable
IO2 Digital Output Source
IO3 Digital Output Source
IO3 Output Enable
IO4 Digital Output Source
IO5 Digital Output Source
IO5 Output Enable
IO6 Digital Output Source (SCL with VI/In-
put & NMOS Open-Drain)
269:264
271:270
277:272
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
21
22
IO7 Digital Output Source (SDA with VI/In-
put & NMOS Open-Drain)
Matrix OUT
279:278
285:280
287:286
293:288
295:294
301:296
303:302
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
IO8 Digital Output Source
IO8 Output Enable
23
24
25
IO9 Digital Output Source
Datasheet
22-Jul-2021
Revision 2.3
135 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
309:304
311:310
317:312
319:318
325:320
327:326
333:328
335:334
341:336
343:342
349:344
351:350
357:352
359:358
365:360
367:366
373:368
375:374
381:376
383:382
389:384
391:390
397:392
399:398
405:400
407:406
413:408
415:414
421:416
423:422
429:424
431:430
437:432
439:438
Read
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Write
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Reserved
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
IO10 Digital Output Source
IO10 Output Enable
Inverter Input
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
IO12 Digital Output Source
IO13 Digital Output Source
IO13 Output Enable
IO14 Digital Output Source
IO15 Digital Output Source
IO15 Output Enable
IO16 Digital Output Source
IO16 Output Enable
IO17 Digital Output Source
ACMP0 PDB (Power-Down)
ACMP1 PDB (Power-Down)
ACMP2 PDB (Power-Down)
ACMP3 PDB (Power-Down)
Input of Filter_0 with fixed time edge
detector
445:440
447:446
453:448
455:454
461:456
463:462
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
37
38
39
Input of Filter_1 with fixed time edge
detector
Input of Programmable Delay & Edge
Detector
Datasheet
22-Jul-2021
Revision 2.3
136 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
469:464
471:470
477:472
479:478
485:480
487:486
493:488
495:494
501:496
503:502
509:504
511:510
517:512
519:518
525:520
527:526
533:528
535:534
541:536
543:542
549:544
551:550
557:552
559:558
565:560
567:566
573:568
575:574
581:576
583:582
589:584
591:590
597:592
599:598
605:600
607:606
613:608
615:614
621:616
623:622
629:624
631:630
Read
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Write
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
OSC 25 kHz/2 MHz PDB (Power-Down)
OSC 25 MHz PDB (Power-Down)
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
IN0 of LUT2_0 or Clock Input of DFF0
IN1 of LUT2_0 or Data Input of DFF0
IN0 of LUT2_1 or Clock Input of DFF1
IN1 of LUT2_1 or Data Input of DFF1
IN0 of LUT2_2 or Clock Input of DFF2
IN1 of LUT2_2 or Data Input of DFF2
IN0 of LUT2_3 or Clock Input of PGen
IN1 of LUT2_3 or nRST of PGen
IN0 of LUT3_0 or Clock Input of DFF3
IN1 of LUT3_0 or Data Input of DFF3
IN2 of LUT3_0 or nRST (nSET) of DFF3
IN0 of LUT3_1 or Clock Input of DFF4
IN1 of LUT3_1 or Data Input of DFF4
IN2 of LUT3_1 or nRST (nSET) of DFF4
IN0 of LUT3_2 or Clock Input of DFF5
IN1 of LUT3_2 or Data Input of DFF5
IN2 of LUT3_2 or nRST (nSET) of DFF5
IN0 of LUT3_3 or Clock Input of DFF6
IN1 of LUT3_3 or Data Input of DFF6
Datasheet
22-Jul-2021
Revision 2.3
137 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
637:632
639:638
645:640
647:646
653:648
655:654
661:656
663:662
Read
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Write
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
IN2 of LUT3_3 or nRST (nSET) of DFF6
IN0 of LUT3_4 or Clock Input of DFF7
IN1 of LUT3_4 or Data Input of DFF7
IN2 of LUT3_4 or nRST (nSET) of DFF7
4F
50
51
52
IN0ofLUT3_5orDelay2Input(orCounter2
RST Input)
669:664
671:670
677:672
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
53
IN1 of LUT3_5 or External Clock Input of
Delay2 (or Counter2)
Matrix OUT
54
55
56
679:678
685:680
687:686
Reserved
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
IN2 of LUT3_5
IN0ofLUT3_6orDelay3Input(orCounter3
RST Input)
693:688
695:694
701:696
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
IN1 of LUT3_6 or External Clock Input of
Delay3 (or Counter3)
Matrix OUT
57
58
59
703:702
709:704
711:710
Reserved
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
IN2 of LUT3_6
IN0ofLUT3_7orDelay4Input(orCounter4
RST Input)
717:712
719:718
725:720
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
IN1 of LUT3_7 or External Clock Input of
Delay4 (or Counter4)
Matrix OUT
5A
5B
5C
727:726
733:728
735:734
Reserved
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
IN2 of LUT3_7
IN0ofLUT3_8orDelay5Input(orCounter5
RST Input)
741:736
743:742
749:744
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
IN1 of LUT3_8 or External Clock Input of
Delay5 (or Counter5)
Matrix OUT
5D
5E
5F
751:750
757:752
759:758
Reserved
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
IN2 of LUT3_8
IN0ofLUT3_9orDelay6Input(orCounter6
RST Input)
765:760
767:766
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Datasheet
22-Jul-2021
Revision 2.3
138 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
IN1 of LUT3_9 or External Clock Input of
Delay6 (or Counter6)
773:768
Matrix OUT
Valid
Valid
60
775:774
781:776
783:782
789:784
791:790
797:792
799:798
805:800
807:806
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
IN2 of LUT3_9
61
62
63
64
IN0 of LUT3_10 or Input of Pipe Delay
IN1 of LUT3_10 or nRST of Pipe Delay
IN2 of LUT3_10 or Clock of Pipe Delay
IN0ofLUT4_0orDelay0Input(orCounter0
RST/SET Input)
813:808
815:814
821:816
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
65
66
IN1 of LUT4_0 or External Clock Input of
Delay0 (or Counter0)
Matrix OUT
823:822
829:824
831:830
837:832
839:838
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
IN2 of LUT4_0 or UP Input of FSM0
IN3 of LUT4_0 or KEEP Input of FSM0
67
68
IN0ofLUT4_1orDelay1Input(orCounter1
RST/SET Input)
845:840
847:846
853:848
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
69
6A
IN1 of LUT4_1 or External Clock Input of
Delay1 (or Counter1)
Matrix OUT
855:854
861:856
863:862
869:864
871:870
Reserved
Matrix OUT
Reserved
Matrix OUT
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
IN2 of LUT4_1 or UP Input of FSM1
IN3 of LUT4_1 or KEEP Input of FSM1
6B
6C
PD of either Temp-output with BG AND/
ORcrystal oscillator by register [1268]
877:872
Matrix OUT
Valid
Valid
6D
879:878
887:880
895:888
903:896
911:904
919:912
927:920
935:928
943:936
951:944
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
6E
6F
70
71
72
73
74
75
76
Datasheet
22-Jul-2021
Revision 2.3
139 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
77
Register Bit
959:952
Read
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Write
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
78
967:960
79
975:968
7A
7B
7C
7D
7E
7F
983:976
991:984
999:992
1007:1000
1015:1008
1023:1016
IO0
1024
1025
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
1027:1026
00: Floating
01: 10 K
10: 100 K
11: 1 M
1029:1028
1031:1030
IO0 Pull Down Resistor Value Selection
IO0 Mode Control
Valid
Valid
Valid
Valid
80
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
IO1
80
1032
1033
Reserved
Valid
Valid
Valid
Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO1 Pull-up/down Resistor Selection
00: Floating
IO1 Pull-up/down Resistor Value Se- 01: 10 K
1035:1034
1037:1036
1039:1038
Valid
Valid
Valid
Valid
Valid
Valid
lection
10: 100 K
11: 1 M
00: Digital Input without Schmitt Trigger,
01: Digital Input with Schmitt Trigger,
10: Low Voltage Digital Input
11: Reserved
81
IO1 Mode Control (sig_io1_oe = 0)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
IO1 Mode Control (sig_io1_oe = 1)
11: Open-Drain NMOS 2x
Datasheet
22-Jul-2021
Revision 2.3
140 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
IO2
Register Bit
Read
Write
1040
1041
Reserved
Valid
Valid
Valid
Valid
0: 1x
1: 2x
IO2 Driver Strength Selection
0: Pull-down Resistor
1: Pull-up Resistor
1042
IO2 Pull-up/down Resistor Selection
Valid
Valid
Valid
Valid
00: Floating
IO2 Pull-up/down Resistor Value Se- 01: 10 K
1044:1043
lection
10: 100 K
82
11: 1 M
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved 100: Push-Pull
101: Open-Drain NMOS
1047:1045
IO2 Mode Control
Valid
Valid
110: Open-Drain PMOS
111: Reserved
IO3
1048
1049
Reserved
Valid
Valid
Valid
Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO3 Pull-up/down Resistor Selection
00: Floating
IO3 Pull-up/down Resistor Value Se- 01: 10 K
1051:1050
1053:1052
1055:1054
Valid
Valid
Valid
Valid
Valid
Valid
lection
10: 100 K
11: 1 M
83
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
IO3 Mode Control (sig_io3_oe = 0)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO3 Mode Control (sig_io3_oe = 1)
IO4
1056
1057
Reserved
Valid
Valid
Valid
Valid
0: 1x
1: 2x
IO4 Driver Strength Selection
0: Pull-down Resistor
1: Pull-up Resistor
1058
IO4 Pull-up/down Resistor Selection
Valid
Valid
Valid
Valid
00: Floating
IO4 Pull-up/down Resistor Value Se- 01: 10 K
1060:1059
lection
10: 100 K
11: 1 M
84
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
1063:1061
IO4 Mode Control
Valid
Valid
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input & Open-Drain
Datasheet
22-Jul-2021
Revision 2.3
141 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
IO5
Register Bit
Read
Write
1064
1065
Reserved
Valid
Valid
Valid
Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO5 Pull-up/down Resistor Selection
00: Floating
IO5 Pull-up/down Resistor Value Se- 01: 10 K
1067:1066
1069:1068
1071:1070
Valid
Valid
Valid
Valid
Valid
Valid
lection
10: 100 K
11: 1 M
85
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
IO5 Mode Control (sig_io5_oe = 0)
11: Analog Input/Output
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO5 Mode Control (sig_io5_oe = 1)
IO6
1072
1073
Reserved
Valid
Valid
Valid
Valid
0: 1x
1: 2x
IO6 Driver Strength Selection
0: SCL & Virtual Input 0
1: IO6
1074
Select SCL & Virtual Input 0 or IO6
Valid
Valid
Valid
Valid
00: Floating
01: 10 K
10: 100 K
1076:1075
IO6 Pull-down Resistor Value Selection
86
11: 1 M
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Reserved
101: Open-Drain NMOS
110: Reserved
IO6 (or SCL) Mode Control
(input mode is selected by register at
SCL)
1079:1077
Valid
Valid
111: Reserved
IO7
1080
1081
Reserved
Valid
Valid
Valid
Valid
0: 1x (I2C up to 400 kHz)
1: 2x (I2C up to 1 MHz)
IO7 (or SDA) Driver Strength Selection
0: SDA & Virtual Input 1
1: IO7
1082
Select SDA & Virtual Input 1 or IO7
Valid
Valid
Valid
Valid
00: Floating
01: 10 K
10: 100 K
11: 1 M
1084:1083
IO7 Pull-down Resistor Value Selection
87
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved 100: Reserved
101: Open-Drain NMOS
IO7 (or SDA) Mode Control
(input mode is selected by register at
SDA, output mode is fixed as OD at
SDA)
1087:1085
Valid
Valid
110: Reserved
111: Reserved
Datasheet
22-Jul-2021
Revision 2.3
142 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
IO8
Register Bit
Read
Write
0: Super Drive OFF
1: Super Drive ON (if sig_io8_oe = '1' & IO8 Valid
Mode Control = '1x')
IO8 Super Drive (4x, NMOS
Open-Drain) Selection
1088
1089
Valid
Valid
0: Pull-down Resistor
Valid
IO8 Pull-up/down Resistor Selection
1: Pull-up Resistor
00: Floating
IO8 Pull-up/down Resistor Value Se- 01: 10 K
1091:1090
1093:1092
1095:1094
Valid
Valid
Valid
Valid
Valid
Valid
lection
10: 100 K
11: 1 M
88
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
IO8 Mode Control (sig_io8_oe = 0)
11: Analog Input/Output
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
IO8 Mode Control (sig_io8_oe = 1)
11: Open-Drain NMOS 2x
IO9
0: Super Drive OFF
1: Super Drive ON (if IO9 Mode Control =
'101')
IO9 Super Drive (4x, NMOS
Open-Drain) Selection
1096
Valid
Valid
0: 1x
1: 2x
1097
1098
IO9 Driver Strength Selection
Valid
Valid
Valid
Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO9 Pull-up/down Resistor Selection
00: Floating
IO9 Pull-up/down Resistor Value Se- 01: 10 K
1100:1099
Valid
Valid
89
lection
10: 100 K
11: 1 M
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
1103:1101
IO9 Mode Control
Valid
Valid
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input & Open-Drain
Datasheet
22-Jul-2021
Revision 2.3
143 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
IO10
Register Bit
Read
Write
1104
1105
Reserved
Valid
Valid
Valid
Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO10 Pull-up/down Resistor Selection
00: Floating
IO10 Pull-up/down Resistor Value Se- 01: 10 K
1107:1106
1109:1108
1111:1110
Valid
Valid
Valid
Valid
Valid
Valid
lection
10: 100 K
11: 1 M
8A
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
IO10 Mode Control (sig_io10_oe = 0)
11: Analog Input/Output
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO10 Mode Control (sig_io10_oe = 1)
Reserved
1112
Reserved
Reserved
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
1113
8B
1115:1114
1117:1116
1119:1118
IO12
1120
1121
Reserved
Valid
Valid
Valid
Valid
0: 1x
1: 2x
IO12 Driver Strength Selection
0: Pull-down Resistor
1: Pull-up Resistor
1122
IO12 Pull-up/down Resistor Selection
Valid
Valid
Valid
Valid
00: Floating
01: 10 K
10: 100 K
11: 1 M
IO12 Pull-up/down Resistor Value
Selection
1124:1123
8C
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
1127:1125
IO12 Mode Control
Valid
Valid
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input & Open-Drain
Datasheet
22-Jul-2021
Revision 2.3
144 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
IO13
Register Bit
Read
Write
1128
1129
Reserved
Valid
Valid
Valid
Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO13 Pull-up/down Resistor Selection
00: Floating
IO13 Pull-up/down Resistor Value Se- 01: 10 K
1131:1130
1133:1132
1135:1134
Valid
Valid
Valid
Valid
Valid
Valid
lection
10: 100 K
11: 1 M
8D
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
IO13 Mode Control (sig_io13_oe = 0)
11: Sel for XSOC (X2)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO13 Mode Control (sig_io13_oe = 1)
IO14
0: Disable
1: Enable
1136
1137
1138
X1 & X2 for crystal OSC enable
IO14 Driver Strength Selection
IO14 Pull-up/down Resistor Selection
Valid
Valid
Valid
Valid
Valid
Valid
0: 1x
1: 2x
0: Pull-down Resistor
1: Pull-up Resistor
00: Floating
IO14 Pull-up/down Resistor Value Se- 01: 10 K
1140:1139
Valid
Valid
lection
10: 100 K
11: 1 M
8E
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Sel for XOSC (X1)
1143:1141
IO14 Mode Control
Valid
Valid
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Reserved
IO15
1144
1145
Reserved
Valid
Valid
Valid
Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO15 Pull-up/down Resistor Selection
00: Floating
IO15 Pull-up/down Resistor Value Se- 01: 10 K
1147:1146
1149:1148
1151:1150
Valid
Valid
Valid
Valid
Valid
Valid
lection
10: 100 K
11: 1 M
8F
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
IO15 Mode Control (sig_io15_oe = 0)
11: Analog Input/Output
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO15 Mode Control (sig_io15_oe = 1)
Datasheet
22-Jul-2021
Revision 2.3
145 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
IO16
Register Bit
Read
Write
1152
1153
Reserved
Valid
Valid
Valid
Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO16 Pull-up/down Resistor Selection
00: Floating
IO16 Pull-up/down Resistor Value Se- 01: 10 K
1155:1154
1157:1156
1159:1158
Valid
Valid
Valid
Valid
Valid
Valid
lection
10: 100 K
11: 1 M
90
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
IO16 Mode Control (sig_io16_oe = 0)
11: Analog Input/Output
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO16 Mode Control (sig_io16_oe = 1)
IO17
1160
1161
Reserved
Valid
Valid
Valid
Valid
0: 1x
1: 2x
IO17 Driver Strength Selection
0: Pull-down Resistor
1: Pull-up Resistor
1162
IO17 Pull-up/down Resistor Selection
Valid
Valid
Valid
Valid
00: Floating
IO17 Pull-up/down Resistor Value Se- 01: 10 K
1164:1163
lection
10: 100 K
91
11: 1 M
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
1167:1165
IO17 Mode Control
Valid
Valid
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Reserved
ACMP1
ACMP1 Positive Input Source Select 0: IO8
1: ACMP0 IN+ source
1168
1169
Valid
Valid
Valid
Valid
ACMP1AnalogBufferEnable(MaxBW 0: Disable analog buffer
1 MHz)
1: Enable analog buffer
00: 0 mV
01: 25 mV
92
10: 50 mV
11: 200 mV
1171:1170
ACMP1 Hysteresis Enable
Valid
Valid
(01: for both external & internal Vref; 10 &
11: for only internal Vref; External Vref will
not have 50 mV & 200 mV hysteresis)
Datasheet
22-Jul-2021
Revision 2.3
146 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
ACMP0
1172
ACMP0 Positive Input Source Select 0: IO4
1: VDD
Valid
Valid
Valid
Valid
ACMP0AnalogBufferEnable(MaxBW 0: Disable analog buffer
1173
1 MHz)
1: Enable analog buffer
00: 0 mV
01: 25 mV
92
10: 50 mV
11: 200 mV
(01: for both external & internal Vref; 10 &
11: for only internal Vref; External Vref will
not have 50 mV & 200 mV hysteresis)
1175:1174
1177:1176
ACMP0 Hysteresis Enable
Valid
Valid
ACMP3
ACMP3 Positive Input Source Select 00: IO12
01: ACMP2 IN+ source
Valid
Valid
Valid
Valid
10: ACMP0 IN+ source
11: Reserved
00: 0 mV
01: 25 mV
10: 50 mV,
11: 200 mV
93
1179:1178
ACMP3 Hysteresis Enable
(01: for both external & internal Vref; 10 &
11: for only internal Vref; External Vref will
not have 50 mV & 200 mV hysteresis.)
ACMP2
ACMP2 Positive Input Source Select 0: IO10
1: ACMP0 IN+ source
1180
Valid
Valid
Valid
Valid
00: 0 mV
01: 25 mV
93
10: 50 mV
11: 200 mV
1182:1181
ACMP2 Hysteresis Enable
(01: for both external & internal Vref; 10 &
11: for only internal Vref; External Vref will
not have 50 mV & 200 mV hysteresis)
ACMP1 100 uA Current Source Enable
93 1183 ACMP1 100 uA Current Source Enable
0: Disable
1: Enable
Valid
Valid
LUT3_x Function Select
LUT3_3 or DFF6 with nRST/nSET Se- 0: LUT3_3
1184
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
lect
1: DFF6 with nRST/nSET
LUT3_2 or DFF5 with nRST/nSET Se- 0: LUT3_2
1185
lect
1: DFF5 with nRST/nSET
94
LUT3_1 or DFF4 with nRST/nSET Se- 0: LUT3_1
1186
1187
lect
1: DFF4 with nRST/nSET
LUT3_0 or DFF3 with nRST/nSET Se- 0: LUT3_0
lect
1: DFF3 with nRST/nSET
Datasheet
22-Jul-2021
Revision 2.3
147 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
LUT2_x Function Select
0: LUT2_3
1: PGen
1188
LUT2_3 or PGen Select
LUT2_2 or DFF2 Select
LUT2_1 or DFF1 Select
LUT2_0 or DFF0 Select
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
0: LUT2_2
1: DFF2
1189
94
0: LUT2_1
1: DFF1
1190
0: LUT2_0
1: DFF0
1191
LUT4_x Function Select
0: LUT4_1
1: DLY/CNT1(16bits)
1192
LUT4_1 or DLY/CNT1(16bits) Select
LUT4_0 or DLY/CNT0(16bits) Select
Valid
Valid
Valid
Valid
95
0: LUT4_0
1: DLY/CNT0(16bits)
1193
LUT3_x Function Select
0: LUT3_9
1: DLY/CNT6(8bits)
1194
LUT3_9 or DLY/CNT6(8bits) Select
LUT3_8 or DLY/CNT5(8bits) Select
LUT3_7 or DLY/CNT4(8bits) Select
LUT3_6 or DLY/CNT3(8bits) Select
LUT3_5 or DLY/CNT2(8bits) Select
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
0: LUT3_8
1: DLY/CNT5(8bits)
1195
0: LUT3_7
1: DLY/CNT4(8bits)
1196
95
0: LUT3_6
1: DLY/CNT3(8bits)
1197
0: LUT3_5
1: DLY/CNT2(8bits)
1198
1199
LUT3_4 or DFF7 with nRST/nSET Se- 0: LUT3_4
lect 1: DFF7 with nRST/nSET
LUT2_1/DFF1
1200
LUT2_1 [0]
Valid
Valid
Valid
Valid
0: Low
1: High
1201
1202
1203
LUT2_1 [1]/DFF1 Initial Polarity Select
96
0: Q output
1: QB output
LUT2_1 [2]/DFF1 Output Select
LUT2_1 [3]/DFF1 or LATCH Select
Valid
Valid
Valid
Valid
0: DFF function
1: LATCH function
LUT2_0/DFF0
1204
LUT2_0 [0]
Valid
Valid
Valid
Valid
0: Low
1: High
1205
1206
1207
LUT2_0 [1]/DFF0 Initial Polarity Select
96
0: Q output
1: QB output
LUT2_0 [2]/DFF0 Output Select
LUT2_0 [3]/DFF0 or LATCH Select
Valid
Valid
Valid
Valid
0: DFF function
1: LATCH function
LUT2_3/PGen
LUT2_3[3:0] or PGen4bit counter data
[3:0]
97
1211:1208
Valid
Valid
Datasheet
22-Jul-2021
Revision 2.3
148 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
LUT2_2/DFF2
1212
Register Bit
Read
Write
LUT2_2 [0]
Valid
Valid
Valid
Valid
0: Low
1: High
1213
1214
1215
LUT2_2 [1]/DFF2 Initial Polarity Select
97
0: Q output
1: QB output
LUT2_2 [2]/DFF2 Output Select
LUT2_2 [3]/DFF2 or LATCH Select
Valid
Valid
Valid
Valid
0: DFF function
1: LATCH function
LUT3_0/DFF3
1219:1216
LUT3_0 [3:0]
Valid
Valid
Valid
Valid
0: Low
1: High
1220
1221
1222
1223
LUT3_0 [4]/DFF3 Initial Polarity Select
LUT3_0 [5]/DFF3 nRST or nSET Se- 0: nRST from Matrix Output
lect
Valid
Valid
Valid
Valid
Valid
Valid
98
1: nSET from Matrix Output
0: Q output
1: QB output
LUT3_0 [6]/DFF3 Output Select
0: DFF function
1: LATCH function
LUT3_0 [7]/DFF3 or LATCH Select
LUT3_1/DFF4
1227:1224
LUT3_1 [3:0]
Valid
Valid
Valid
Valid
0: Low
1: High
1228
1229
1230
1231
LUT3_1 [4]/DFF4 Initial Polarity Select
LUT3_1 [5]/DFF4 nRST or nSET Se- 0: nRST from Matrix Output
lect
Valid
Valid
Valid
Valid
Valid
Valid
99
1: nSET from Matrix Output
0: Q output
1: QB output
LUT3_1 [6]/DFF4 Output Select
0: DFF function
1: LATCH function
LUT3_1 [7]/DFF4 or LATCH Select
LUT3_2/DFF5
1235:1232
LUT3_2 [3:0]
Valid
Valid
Valid
Valid
0: Low
1: High
1236
1237
1238
1239
LUT3_2 [4]/DFF5 Initial Polarity Select
LUT3_2 [5]/DFF5 nRST or nSET Se- 0: nRST from Matrix Output
lect
Valid
Valid
Valid
Valid
Valid
Valid
9A
1: nSET from Matrix Output
0: Q output
1: QB output
LUT3_2 [6]/DFF5 Output Select
0: DFF function
1: LATCH function
LUT3_2 [7]/DFF5 or LATCH Select
Datasheet
22-Jul-2021
Revision 2.3
149 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
LUT3_3/DFF6
1243:1240
Register Bit
Read
Write
LUT3_3 [3:0]
Valid
Valid
Valid
Valid
0: Low
1: High
1244
1245
1246
1247
LUT3_3 [4]/DFF6 Initial Polarity Select
LUT3_3 [5]/DFF6 nRST or nSET Se- 0: nRST from Matrix Output
Valid
Valid
Valid
Valid
Valid
Valid
9B
lect
1: nSET from Matrix Output
0: Q output
1: QB output
LUT3_3 [6]/DFF6 Output Select
0: DFF function
1: LATCH function
LUT3_3 [7]/DFF6 or LATCH Select
LUT3_4/DFF7
1251:1248
LUT3_4 [3:0]
Valid
Valid
Valid
Valid
0: Low
1: High
1252
1253
1254
1255
LUT3_4 [4]/DFF7 Initial Polarity Select
LUT3_4 [5]/DFF7 nRST or nSET Se- 0: nRST from Matrix Output
lect
Valid
Valid
Valid
Valid
Valid
Valid
9C
1: nSET from Matrix Output
0: Q output
1: QB output
LUT3_4 [6]/DFF7 Output Select
0: DFF function
1: LATCH function
LUT3_4 [7]/DFF7 or LATCH Select
LUT3_10/Pipe Delay
1259:1256
9D
LUT3_10 [3:0]/Pipe Delay OUT0 Select
LUT3_10 [7:4]/Pipe Delay OUT1 Select
Valid
Valid
Valid
Valid
1263:1260
00: Rising Edge Detector
Select the Edge Mode of Programma- 01: Falling Edge Detector
1265:1264
1267:1266
Valid
Valid
Valid
Valid
ble Delay & Edge Detector
10: Both Edge Detector
11: Both Edge Delay
00: 125 ns
01: 250 ns
10: 375 ns
11: 500 ns
Delay Value Select for Programmable
Delay & Edge Detector (VDD = 3.3V,
typical)
9E
00: No matrix PD
01: matrix PD for crystal oscillator
10: Reserved matrix PD for temp sensor
11: matrix PD for both crystal oscillator and
temp sensor
Crystal oscillator and temp output Pow-
er-down enable
1269:1268
Valid
Valid
0: LUT3_10
1: Pipe Delay
1270
1271
LUT3_10 or Pipe Delay Select
Pipe Delay OUT1 Polarity Select
Valid
Valid
Valid
Valid
0: Non-inverted
1: Inverted
Datasheet
22-Jul-2021
Revision 2.3
150 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
DLY/CNT2
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
er Reset)
10: on Rising Edge only (for Delay & Count-
er Reset)
DLY2 Mode Select or Asynchronous
CNT2 Reset
1273:1272
Valid
Valid
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
9F
1276:1274
DLY/CNT2 Clock Source Select
Valid
Valid
101: 25 MHz OSC clock
110: External Clock
111: Counter1 Overflow
DLY/CNT2 Output Selection if DLY/
CNT2 Mode Selection is "11"
0: Default Output
1: Edge Detector Output
1277
Valid
Valid
Valid
Valid
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
1279:1278
DLY/CNT2 Mode Selection
DLY/CNT3
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
er Reset)
10: on Rising Edge only (for Delay & Count-
er Reset)
DLY3 Mode Select or Asynchronous
CNT3 Reset
1281:1280
Valid
Valid
Valid
Valid
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
A0
1284:1282
DLY/CNT3 Clock Source Select
101: 25 MHz OSC clock
110: External Clock
111: Counter2 Overflow
DLY/CNT3 Output Selection if DLY/
CNT3 Mode Selection is "11"
0: Default Output
1: Edge Detector Output
1285
Valid
Valid
Valid
Valid
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
1287:1286
DLY/CNT3 Mode Selection
Datasheet
22-Jul-2021
Revision 2.3
151 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
DLY/CNT4
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
er Reset)
10: on Rising Edge only (for Delay & Count-
er Reset)
DLY4 Mode Select or Asynchronous
CNT4 Reset
1289:1288
Valid
Valid
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
A1
1292:1290
DLY/CNT4 Clock Source Select
Valid
Valid
101: 25 MHz OSC clock
110: External Clock
111: Counter3 Overflow
DLY/CNT4 Output Selection if DLY/
CNT4 Mode Selection is "11"
0: Default Output
1: Edge Detector Output
1293
Valid
Valid
Valid
Valid
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
1295:1294
DLY/CNT4 Mode Selection
DLY/CNT5
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
er Reset)
10: on Rising Edge only (for Delay & Count-
er Reset)
DLY5 Mode Select or Asynchronous
CNT5 Reset
1297:1296
Valid
Valid
Valid
Valid
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
A2
1300:1298
DLY/CNT5 Clock Source Select
101: 25 MHz OSC clock
110: External Clock
111: Counter4 Overflow
DLY/CNT5 Output Selection if DLY/
CNT5 Mode Selection is "11"
0: Default Output
1: Edge Detector Output
1301
Valid
Valid
Valid
Valid
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
1303:1302
DLY/CNT5 Mode Selection
Datasheet
22-Jul-2021
Revision 2.3
152 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
DLY/CNT6
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
er Reset)
10: on Rising Edge only (for Delay & Count-
er Reset)
DLY6 Mode Select or Asynchronous
CNT6 Reset
1305:1304
Valid
Valid
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12, 011: OSC/24
100: OSC/64
A3
1308:1306
DLY/CNT6 Clock Source Select
Valid
Valid
101: 25 MHz OSC clock
110: External Clock
111: Counter5 Overflow
DLY/CNT6 Output Selection if DLY/
CNT6 Mode Selection is "11"
0: Default Output
1: Edge Detector Output
1309
Valid
Valid
Valid
Valid
00: Delay mode
01: One Shot
10: Freq. Detect
1311:1310
DLY/CNT6 Mode Selection
11: Counter mode
DLY/CNT0
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
er Reset)
10: on Rising Edge only (for Delay & Count-
er Reset)
DLY0 Mode Select or Asynchronous
CNT0 Reset (16bits)
1313:1312
Valid
Valid
Valid
Valid
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
DLY/CNT0 Clock Source Select
(16bits)
A4
1316:1314
101: 25 MHz OSC clock
110: External Clock
111: Counter6 Overflow
0: Reset to 0s
1: Set to data (Registers [1583:1576,
1591:1584])
CNT0/FSM0's Q are Set to data or Re-
set to 0s Selection (16bits)
1317
Valid
Valid
Valid
Valid
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
1319:1318
DLY/CNT0 Mode Selection (16bits)
Datasheet
22-Jul-2021
Revision 2.3
153 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
DLY/CNT1
00: On both Falling and Rising Edges (for
Delay & Counter Reset)
01: on Falling Edge only (for Delay & Count-
er Reset)
10: on Rising Edge only (for Delay & Count-
er Reset)
DLY1 Mode Select or Asynchronous
CNT1 Reset (16bits)
1321:1320
Valid
Valid
11: No Delay on either Falling or Rising
Edges/High Level Reset
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
DLY/CNT1 Clock Source Select
(16bits)
A5
1324:1322
Valid
Valid
101: 25 MHz OSC clock
110: External Clock
111: Counter0 Overflow
0: Reset to 0s
1: Set to data (Registers [1599:1592,
1607:1600])
CNT1/FSM1's Q are Set to data or Re-
set to 0s Selection (16bits)
1325
Valid
Valid
Valid
Valid
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
1327:1326
DLY/CNT1 Mode Selection (16bits)
DLY/CNTx One-Shot/Freq. Detect Output Polarity
DLY/CNT0 stop & restarting enable in 0: Disable
CNT mode when new data is loaded 1: Enable
Select the Polarity of DLY/CNT6's One 0: Default Output
Shot/Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT5's One 0: Default Output
Shot/Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT4's One 0: Default Output
Shot/Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT3's One 0: Default Output
Shot/Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT2's One 0: Default Output
Shot/Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT1's One 0: Default Output
Shot/Freq. Detect Output 1: Inverted Output
Select the Polarity of DLY/CNT0's One 0: Default Output
Shot/Freq. Detect Output 1: Inverted Output
1328
1329
1330
1331
1332
1333
1334
1335
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
A6
Datasheet
22-Jul-2021
Revision 2.3
154 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
Oscillator
00: Div1
01: Div2
10: Div4
11: Div8
1337:1336
OSC Clock Pre-divider for 25 MHz
Valid
Valid
Valid
Valid
Valid
Valid
OSC Fast Start-Up Enable for 25 kHz/ 0: Disable
A7
1338
2 MHz
1: Enable
00: Div1
01: Div2
10: Div4
11: Div8
OSC Clock Pre-divider for
25 kHz/2 MHz
1340:1339
0: Auto Power-On (If any CNT/DLY use 25
MHz source)
1: Force Power-On
1341
1342
1343
Force 25 MHz Oscillator ON
Valid
Valid
Valid
Valid
Valid
Valid
Oscillator (25 kHz: Ring OSC, 2 M:
RC-OSC) Select
0: 25 kHz Ring OSC
1: 2 MHz RC-OSC
A7
0: Auto Power-On (if any CNT/DLY use
25k/2 MHz source)
Force 25 kHz/2 MHz Oscillator ON
1: Force Power-On
000: OSC/1
001: OSC/2
010: OSC/3
Internal OSC 25 kHz/2 MHz Frequency 011: OSC/4
1346:1344
1349:1347
Valid
Valid
Valid
Valid
Divider Control for matrix input [28]
100: OSC/8
101: OSC/12
110: OSC/24
111: OSC/64
000: OSC/1
001: OSC/2
010: OSC/3
A8
Internal OSC 25 kHz/2 MHz Frequency 011: OSC/4
Divider Control for matrix input [27]
100: OSC/8
101: OSC/12
110: OSC/24
111: OSC/64
OSC Clock 25 kHz/2 MHz to matrix in- 0: Disable
put [28] enable 1: Enable
1350
1351
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
OSC Clock 25 kHz/2 MHz to matrix in- 0: Disable
put [27] enable
1: Enable
SM_reg_init [2:0] for SM state default
setup bits
1354:1352
1355
External oscillator pin selection
for 25 kHz/2 MHz
0: IO17
1: IO15
OSC Clock 25 MHz to matrix input [29] 0: Disable
enable 1: Enable
1356
A9
External Clock Source Select instead 0: Internal Oscillator
1357
of 25 MHz
1: External Clock from IO14
External Clock Source Select instead 0: Internal Oscillator
1358
of 25 kHz/2 MHz
1: External Clock from IO15 or IO17
DLY/CNT1 stop & restarting enable in 0: Disable
CNT mode when new data is loaded 1: Enable
1359
Datasheet
22-Jul-2021
Revision 2.3
155 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
ASM 8-to-1 MUX’s 3 selection bits
1362:1360
1363
ASM_state0_dec8x1_EN1
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Reserved
AA
AB
1366:1364
1367
ASM_state0_dec8x1_EN0
Reserved
1370:1368
1371
ASM_state1_dec8x1_EN0
Reserved
1374:1372
1375
ASM_state0_dec8x1_EN2
Reserved
1378:1376
1379
ASM_state1_dec8x1_EN2
Reserved
AC
AC
1382:1380
1383
ASM_state1_dec8x1_EN1
Reserved
1386:1384
1387
ASM_state2_dec8x1_EN1
Reserved
AD
AE
AF
B0
B1
B2
B3
1390:1388
1391
ASM_state2_dec8x1_EN0
Reserved
1394:1392
1395
ASM_state3_dec8x1_EN0
Reserved
1398:1396
1399
ASM_state2_dec8x1_EN2
Reserved
1402:1400
1403
ASM_state3_dec8x1_EN2
Reserved
1406:1404
1407
ASM_state3_dec8x1_EN1
Reserved
1410:1408
1411
ASM_state4_dec8x1_EN1
Reserved
1414:1412
1415
ASM_state4_dec8x1_EN0
Reserved
1418:1416
1419
ASM_state5_dec8x1_EN0
Reserved
1422:1420
1423
ASM_state4_dec8x1_EN2
Reserved
1426:1424
1427
ASM_state5_dec8x1_EN2
Reserved
1430:1428
1431
ASM_state5_dec8x1_EN1
Reserved
1434:1432
1435
ASM_state6_dec8x1_EN1
Reserved
1438:1436
1439
ASM_state6_dec8x1_EN0
Reserved
Datasheet
22-Jul-2021
Revision 2.3
156 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
1442:1440
1443
Read
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Write
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
ASM_state7_dec8x1_EN0
Reserved
B4
1446:1444
1447
ASM_state6_dec8x1_EN2
Reserved
1450:1448
1451
ASM_state7_dec8x1_EN2
Reserved
B5
1454:1452
1455
ASM_state7_dec8x1_EN1
Reserved
Filter/Edge Detector
00: Rising Edge
Select the edge mode of Edge Detec- 01: Falling Edge
1457:1456
Valid
Valid
tor_1
10: Both Edge
11: Delay
Filter_1/Edge Detector_1 output Polar- 0: Filter_1 output
1458
Valid
Valid
Valid
Valid
ity Select
1: Filter_1 output inverted
Filter_1 or Edge Detector_1 Select
(Typ 30 ns @VDD = 3.3 V)
0: Filter_1
1: Edge Detector_1
1459
B6
00: Rising Edge
Select the edge mode of Edge Detec- 01: Falling Edge
1461:1460
Valid
Valid
tor_0
10: Both Edge
11: Delay
Filter_0/Edge Detector_0 output Polar- 0: Filter_0 output
1462
1463
Valid
Valid
Valid
Valid
ity Select
1: Filter_0 output inverted
Filter_0 or Edge Detector_0 Select
(Typ 47 ns @VDD = 3.3 V)
0: Filter_0
1: Edge Detector_0
Vref/Bandgap
0: Disable
1: Enable
1464
Enable temp. sensor
Valid
Valid
00 or 10 with registers [1474:1472] = 100
(WideVDD r a n g e , 1 . 7 V ~ 5 . 5 V ) :
Auto-delay mode, 550 uS for VDD < 2.7 V
& 100 uS for 2.7 V < VDD
00 or 10 with registers [1474:1472] = X10:
Always 100 uS delay for 2.7 V < VDD
00 or 10 with registers [1474:1472] = XX1:
Always 550 uS delay for VDD < 2.7 V,
01: Always 550 us delay regardless of
Bandgap OK for ACMP Output Delay
Time Select, the start Time is "Reset-
b_core go to High"
1466:1465
Valid
Valid
B7
registers [1474:1472] & VDD
,
11: Always 100 us delay with 2.7 V < VDD
regardless of registers [1474:1472]
1467
1468
1469
1470
Reserved
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
0: Disable
1: Enable
1471
Two consecutive DFFs enable for SM
Valid
Valid
Datasheet
22-Jul-2021
Revision 2.3
157 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
0XX: Power divider off (if there is no use of
VDD/3, VDD/4 @ ACMP negative in)
100: Reserved
Power divider (VDD/3, VVDD/4) ON/
OFF
1474:1472
Valid
Valid
X10: Reserved
XX1: Reserved
В8
VDD Bypass Enable when device
power is 1.8 V
0: Regulator Auto ON
1: Regulator OFF (VDD Bypass)
1475
1476
Valid
Valid
Valid
0: Auto-Mode
1: Enable (if chip is Power-down, the Band- Valid
Force Bandgap ON
gap will Power-down even if it is Set to 1).
0: None (Or Programming Enable)
Valid
1477
1478
1479
NVM Power-down
Valid
Valid
Valid
1: Power-down (Or Programming Disable)
Temp output range control (temp. de- 0: 0.62 V ~ 0.99 V (Typ)
B8
Valid
Valid
tector is not available)
1: 0.75 V ~ 1.2 V (Typ)
0: Disable
1: Enable
GPIO Quick Charge Enable
000: ACMP2 Vref
001: ACMP3 Vref
100: VDD/2
101: VDD/3
110: VDD/4
1482:1480
1483
Vref1 Output Source Select
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
111: Hi-Z
B9
000: ACMP0 Vref
001: ACMP1 Vref
100: VDD/2
1486:1484
Vref0 Output Source Select
101: VDD/3
110: VDD/4
111: Hi-Z
1487
1488
Reserved
Reserved
Valid
Valid
Valid
Valid
Wake time Selection in Wake Sleep
Mode
0: Short wake time
1: Normal wake time
1489
1490
1491
1492
1493
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
0: Disable
1: Enable
ACMP0 Wake & Sleep function Enable
ACMP1 Wake & Sleep function Enable
ACMP2 Wake & Sleep function Enable
ACMP3 Wake & Sleep function Enable
0: Disable
1: Enable
0: Disable
1: Enable
BA
0: Disable
1: Enable
Wake Sleep Output State When WS
Oscillator is Power-down if DLY/CNT0
Mode Selection is "11"
0: Low
1: High
1494
Valid
Valid
Wake Sleep Ratio Control Mode Selec- 0: Default Mode
tion if DLY/CNT0 Mode Selection is "11" 1: Wake Sleep Ratio Control Mode
1495
Valid
Valid
BB
BC
BD
BE
1503:1496
1511:1504
1519:1512
1527:1520
Reserved
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Datasheet
22-Jul-2021
Revision 2.3
158 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
BF
1535:1528
Reserved
Valid
Valid
LUT/DLY/CNT Control Data
LUT3_5 [7:0] or DLY/CNT2 Control
Data
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
C0
C1
C2
C3
C4
1543:1536
1551:1544
1559:1552
1567:1560
1575:1568
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
LUT3_6 [7:0] or DLY/CNT3 Control
Data
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
LUT3_7 [7:0] or DLY/CNT4 Control
Data
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
LUT3_8 [7:0] or DLY/CNT5 Control
Data
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
LUT3_9 [7:0] or DLY/CNT6 Control
Data
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
C5
C6
C7
C8
C9
CA
1583:1576
1591:1584
1599:1592
1607:1600
1615:1608
1623:1616
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
LUT4_0 [15:0] or DLY/CNT0 (16bits, 1 - 65535 (Delay Time = [Counter Control
[15:0] = [1591:1576]) Control Data Data + 2]/Freq)
LUT4_1 [15:0] or DLY/CNT1 (16bits, 1 - 65535 (Delay Time = [Counter Control
[15:0] = [1607:1592]) Control Data
Data + 2]/Freq)
PGen pattern data [15:0] = [1623:1608]
ACMP0
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
1628:1624
ACMP0-IN Voltage Select
Valid
Valid
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
CB
11010: IO9: EXT_Vref
11011: IO5: ACMP0-
11100: IO9: EXT_Vref/2
11101: IO5: ACMP0-/2
11110: Reserved
11111: Reserved
00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
1630:1629
1631
ACMP0 Positive Input Divider
Valid
Valid
Valid
Valid
ACMP0 Low Bandwidth (MAX: 1 MHz) 0: OFF
E n a b l e
1: ON
Datasheet
22-Jul-2021
Revision 2.3
159 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
ACMP1
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
1636:1632
ACMP1-IN Voltage Select
Valid
Valid
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
CC
11010: EXT_Vref(IO9)
11011: Reserved
11100: EXT_Vref(IO9)/2
11101: Reserved
11110: Reserved
11111: Reserved
00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
1638:1637
1639
ACMP1 Positive Input Divider
Valid
Valid
Valid
Valid
ACMP1 Low Bandwidth (MAX: 1 MHz) 0: OFF
E n a b l e
1: ON
ACMP2
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
1644:1640
ACMP2-IN Voltage Select
Valid
Valid
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
CD
11010: IO9: EXT_Vref
11011: Reserved
11100: IO9: EXT_Vref/2
11101: Reserved
11110: Reserved
11111: Reserved
00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
1646:1645
1647
ACMP2 Positive Input Divider
Valid
Valid
Valid
Valid
ACMP2 Low Bandwidth (MAX: 1 MHz) 0: OFF
E n a b l e
1: ON
Datasheet
22-Jul-2021
Revision 2.3
160 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
Read
Write
ACMP3
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
11000: VDD/3
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
1652:1648
ACMP3-IN Voltage Select
Valid
Valid
10101: 1.1 V
10111: 1.2 V
11001: VDD/4
CE
11010: IO9: EXT_Vref
11011: Reserved
11100: IO9: EXT_Vref/2
11101: Reserved
11110: Reserved
11111: Reserved
00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
1654:1653
1655
ACMP3 Positive Input Divider
Valid
Valid
Valid
Valid
ACMP3 Low Bandwidth (MAX: 1 MHz) 0: OFF
E n a b l e
1: ON
Misc.
1656
1657
Reserved
Valid
Valid
Valid
Valid
Switch from “Matrix OUT: OSC 25 MHz
PD” to “Matrix OUT: OSC 25 MHz Force
On”
0: OSC PD
1: OSC Force On (Matrix Output [59])
Switch from “Matrix OUT: OSC 25 kHz/
2 MHz PD” to “Matrix OUT:
OSC 25 kHz/2 MHz Force On”
0: OSC PD
1: OSC Force On (Matrix Output [58])
1658
Valid
Valid
CF
1659
1660
1661
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
I2C reset bit with reloading NVM into 0: Keep existing condition
1662
Valid
Valid
Data register
1: Reset execution
1663
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
D0
D1
D2
D3
D4
D5
D6
D7
D8
1671:1664
1679:1672
1687:1680
1695:1688
1703:1696
1711:1704
1719:1712
1727:1720
1735:1728
RAM 8 outputs for ASM-state0
RAM 8 outputs for ASM-state1
RAM 8 outputs for ASM-state2
RAM 8 outputs for ASM-state3
RAM 8 outputs for ASM-state4
RAM 8 outputs for ASM-state5
RAM 8 outputs for ASM-state6
RAM 8 outputs for ASM-state7
User configurable RAM/OTP Byte 0
Datasheet
22-Jul-2021
Revision 2.3
161 of 172
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
D9
DA
DB
DC
DD
DE
DF
E0
Register Bit
1743:1736
1751:1744
1759:1752
1767:1760
1775:1768
1783:1776
1791:1784
1799:1792
1807:1800
1815:1808
1823:1816
1831:1824
Read
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Write
Valid
Valid
Valid
Valid
Valid
Valid
Valid
User configurable RAM/OTP Byte 1
User configurable RAM/OTP Byte 2
User configurable RAM/OTP Byte 3
User configurable RAM/OTP Byte 4
User configurable RAM/OTP Byte 5
User configurable RAM/OTP Byte 6
User configurable RAM/OTP Byte 7
Reserved
Invalid Invalid
Invalid Invalid
Invalid Invalid
Invalid Invalid
E1
Reserved
E2
Reserved
E3
Reserved
E4
Reserved
Valid
Valid
I2C lock for read bits [1535:0] (Bank 0/ 0: Disable (Programmed data can be read)
1832
Valid
Invalid
1/2)
1: Enable (Programmed data can't be read)
1833
Reserved
Reserved
Reserved
Valid
Valid
Valid
Invalid
Invalid
Invalid
E5
1835:1834
1839:1836
8-bit Pattern ID Byte 0 (From NVM):
ID[23:16]
E6
1847:1840
Valid
Valid
E7
E8
1855:1848
1863:1856
1867:1864
1868
Reserved
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
Invalid
Valid
Reserved
I2C Control Code Bit [3:0]
Value for slave address
Reserved
1869
Reserved
Valid
E9
0: Writable
1: Non-writable
I2C lock for write bits [1535:0] (Bank 0/ 0: Writable
1870
1871
BANK0/1/2/3 I2C-write protection bit
Valid
Valid
Invalid
Invalid
1/2)
1: Non-writable
EA
EB
EC
ED
EE
EF
1879:1872
1887:1880
1895:1888
1903:1896
1911:1904
1919:1912
CNT4 Counted Value
Valid
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
CNT0 (16bits) = [1895:1880] Counted
Value
CNT6 Counted Value
CNT1 (16bits) = [1919:1904] Counted
Value
Matrix Input
1920
1921
1922
1923
1924
1925
1926
1927
Matrix Input 0
Matrix Input 1
Matrix Input 2
Matrix Input 3
Matrix Input 4
Matrix Input 5
Matrix Input 6
Matrix Input 7
Ground
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
IO0 Digital Input
IO1 Digital Input
IO2 Digital Input
IO3 Digital Input
IO4 Digital Input
IO5 Digital Input
IO8 Digital Input
F0
Datasheet
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SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
Read
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Write
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Valid
Matrix Input 8
Matrix Input 9
Matrix Input 10
Matrix Input 11
Matrix Input 12
Matrix Input 13
Matrix Input 14
Matrix Input 15
Matrix Input 16
Matrix Input 17
Matrix Input 18
Matrix Input 19
Matrix Input 20
Matrix Input 21
Matrix Input 22
Matrix Input 23
Matrix Input 24
Matrix Input 25
Matrix Input 26
Matrix Input 27
Matrix Input 28
Matrix Input 29
Matrix Input 30
Matrix Input 31
Matrix Input 32
Matrix Input 33
Matrix Input 34
Matrix Input 35
Matrix Input 36
Matrix Input 37
Matrix Input 38
Matrix Input 39
Matrix Input 40
Matrix Input 41
Matrix Input 42
Matrix Input 43
Matrix Input 44
Matrix Input 45
Matrix Input 46
Matrix Input 47
LUT2_0/DFF0 Output
LUT2_1/DFF1 Output
LUT2_2/DFF2 Output
LUT2_3/PGen Output
F1
LUT3_0/DFF3 Output
LUT3_1/DFF4 Output
LUT3_2/DFF5 Output
LUT3_3/DFF6 Output
LUT3_4/DFF7 Output
LUT3_5/CNT_DLY2(8bit) Output
LUT3_6/CNT_DLY3(8bit) Output
LUT3_7/CNT_DLY4(8bit) Output
LUT3_8/CNT_DLY5(8bit) Output
LUT3_9/CNT_DLY6(8bit) Output
LUT4_0/CNT_DLY0(16bit) Output
LUT4_1/CNT_DLY1(16bit) Output
LUT3_10/Pipe Delay (1st stage) Output
Pipe Delay Output0
F2
F3
F4
F5
Pipe Delay Output1
Fixed "L" output because it is OSC clock
Fixed "L" output because it is OSC clock
Fixed "L" output because it is OSC clock
Filter0/Edge Detect0 Output
Filter1/Edge Detect1 Output
Virtual Input [0]
Virtual Input [1]
Valid
Virtual Input [2]
Valid
Virtual Input [3]
Valid
Virtual Input [4]
Valid
Virtual Input [5]
Valid
Virtual Input [6]
Valid
Virtual Input [7]
Valid
RAM_0 Output for ASM-state
RAM_1 Output for ASM-state
RAM_2 Output for ASM-state
RAM_3 Output for ASM-state
RAM_4 Output for ASM-state
RAM_5 Output for ASM-state
RAM_6 Output for ASM-state
RAM_7 Output for ASM-state
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Datasheet
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Revision 2.3
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CFR0011-120-00
SLG46538-A
Preliminary
I2C Interface
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte
Register Bit
1968
Read
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Write
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Matrix Input 48
Matrix Input 49
Matrix Input 50
Matrix Input 51
Matrix Input 52
Matrix Input 53
Matrix Input 54
Matrix Input 55
Matrix Input 56
Matrix Input 57
Matrix Input 58
Matrix Input 59
Matrix Input 60
IO9 Digital Input
IO10 Digital Input
Inverter Output
1969
1970
1971
IO12 Digital Input
IO13 Digital Input
IO14 Digital Input
IO15 Digital Input
IO16 Digital Input
IO17 Digital Input
ACMP_0 Output
ACMP_1 Output
ACMP_2 Output
ACMP_3 Output
F6
1972
1973
1974
1975
1976
1977
1978
1979
F7
1980
Programmable Delay with Edge Detector
Output
1981
Matrix Input 61
Valid
Invalid
1982
1983
Matrix Input 62
Matrix Input 63
nRST_core
VDD
Valid
Valid
Invalid
Invalid
Reserved
F8
1991:1984
1999:1992
2007:2000
2015:2008
2023:2016
2031:2024
2039:2032
2047:2040
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
Invalid
Valid
F9
FA
FB
FC
Invalid
Invalid
Valid
FD
FE
FF
Valid
Datasheet
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Revision 2.3
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CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
21 Package Top Marking Definitions
21.1 TQFN 20L 3.5 MM X 3.5 MM 0.5P PACKAGE
Part Code
PPPPP
Week Code
WWNNN S/N Code
Pin 1
Identifier
Assembly Code
+ Revision Code
ARR
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
22 Package Information
22.1 PACKAGE OUTLINES FOR TQFN 20L 3.5 MM X 3.5 MM 0.5P PACKAGE
TOP (Marking View)
Side View
Bottom (Bump View)
Datasheet
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CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
22.2 TQFN HANDLING
Be sure to handle TQFN package only in a clean, ESD-safe environment. Tweezers or vacuum pick-up tools are suitable for
handling. Do not handle TQFN package with fingers as this can contaminate the package pins and interface with solder reflow.
22.3 SOLDERING INFORMATION
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 25.74 mm3 (nominal) for
TQFN 20L Package. More information can be found at www.jedec.org.
23 Ordering Information
Part Number
Type
SLG46538-AP
SLG46538-APTR
20-pin TQFN
20-pin TQFN - Tape and Reel (5k units)
23.1 TAPE AND REEL SPECIFICATIONS
Max Units
Trailer (min)
Leader (min)
Nominal
# of
Pins
Reel &
Hub Size
(mm)
Tape Part
Width Pitch
Package Type
Package Size
(mm)
Length
Length
(mm)
per Reel per Box
Pockets
Pockets
(mm)
TQFN 20L3.5 mm x
3.5 mm Green
20 3.5 x 3.5 x 0.75 5,000 10,000 330/100
42
336
42
336
12
8
23.2 CARRIER TAPE DRAWING AND DIMENSIONS
Index Hole Index Hole
PocketBTMPocketBTM Pocket Index Hole Pocket Index Hole
to Tape
Edge
to Pocket Tape Width
Center
(mm)
Length
(mm)
Width
(mm)
Depth
(mm)
Pitch
(mm)
Pitch Diameter
(mm)
Package Type
(mm)
(mm)
(mm)
A0
B0
K0
P0
P1
D0
E
F
W
TQFN 20L
3.5 mm x
3.8
3.8
0.95
4
8
1.5
1.75
5.5
12
3.5 mm Green
Section Y-Y
Note: 1.Orientation in carrier: Pin1 is at upper left corner (Quadrant 1).
2.Other material is available.
Datasheet
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Revision 2.3
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
24 Layout Guidelines
24.1 TQFN 20L 3.5 MM X 3.5 MM 0.5P PACKAGE
Unit: μm
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Glossary
A
ACK
Acknowledge bit
ACMP
ASM
Analog Comparator
Asynchronous State Machine
B
BG
Bandgap
C
CLK
CNT
Clock
Counter
D
DFF
DLY
D Flip-Flop
Delay
E
EC
ESD
Electrical Characteristics
Electrostatic discharge
F
FSM
Finite State Machine
G
GPI
GPIO
GPO
General Purpose Input
General Purpose Input/Output
General Purpose Output
I
IN
IO
Input
Input/Output
L
LSB
LB
Least Significant Bit
Low Bandwidth
Look Up Table
LUT
M
MSB
MUX
Most Significant Bit
Multiplexer
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
N
nRST
NVM
Reset
Non-Volatile Memory
O
OD
Open-Drain
OE
Output Enable
Oscillator
OSC
OTP
OUT
One Time Programmable
Output
P
PD
Power-Down
Pattern Generator
Power-On Reset
Push-Pull
PGen
POR
PP
PWR
P DLY
Power
Programmable Delay
R
R/W
Read/Write
S
SCL
SDA
I2C Clock Input
I2C Data Input/Output
T
TP
TS
Thermal Pad
Temperature Sensor
V
Vref
Voltage Reference
W
WS
Wake and Sleep Controller
Datasheet
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SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Revision History
Revision
2.3
Date
Description
Removed note from section Vref Load Regulation
Corrected registers [1076:1075], [1084:1083], [1087:1085]
22-Jul-2021
19-Feb-2021
2.2
Corrected section Pin Configuration - TQFN - 20L
Corrected section Pin Configuration - TQFN - 20L
Updated Ordering Information
Updated ACMP Spec
2.1
2.0
16-Jul-2020
16-Jun-2020
Preliminary version
Datasheet
22-Jul-2021
Revision 2.3
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG46538-A
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with Asynchronous State Machine and Dual Supply
Status Definitions
Revision Datasheet Status
Product Status
Definition
1.<n>
Target
Development
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
2.<n>
Preliminary
Qualification
Production
This datasheet contains the specifications and preliminary characterization
data for products in pre-production. Specifications may be changed at any
time without notice in order to improve the design.
3.<n>
4.<n>
Final
This datasheet contains the final specifications for products in volume
production. The specifications may be changed at any time in order to
improve the design, manufacturing and supply. Major specification
changes are communicated via Customer Product Notifications. Datasheet
changes are communicated via www.dialog-semiconductor.com.
Obsolete
Archived
This datasheet contains the specifications for discontinued products. The
information is provided for reference only.
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Datasheet
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CFR0011-120-00
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