SLG47004V [DIALOG]
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features;
| 型号： | SLG47004V |
| 厂家： | 
Dialog Semiconductor |
| 描述： | GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features |
| 文件： | 总292页 (文件大小：13302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
General Description
The SLG47004 provides a small, low power component for commonly used analog signal processing and mixed-signal
functions. Individual, tunable, analog components used in conjunction with configurable logic provide a way to solve a wide
variety of tasks with minimal costs. The user creates their circuit design by programming the multiple time Non-Volatile
Memory (NVM) to configure the interconnect logic, the analog and digital macrocell, and the IO Pins of the SLG47004.
Key Features
Two Programmable Bandwidth Op Amps
3-bit LUT
3-Op Amp Instrumentation Amplifier Function
(including Additional Internal Op Amp)
Rail to Rail Input
Low Quiescent Current
Low Offset Voltage
One Selectable DFF/LATCH or 4-bit LUT
Seven Multi-Function Macrocells
Six Selectable DFF/LATCH or 3-bit LUTs + 8-bit
Delay/Counters
One Selectable DFF/LATCH or 4-bit LUT + 16-bit
Delay/Counter
Analog Comparator Mode
Optional Vref Voltage Connection for Input Pins
Serial Communications
2-kbit (256 x 8) I2C-Compatible (2-Wire) Serial EEPROM
Emulation with Software Write Protection
Programmable Delay with Edge Detector Output
Deglitch Filter or Edge Detector
Two 1024 Position Digital Rheostats
I2C Protocol Interface
User Defined Auto-Trim Option
Manual Control Option
I2C Control Option
Potentiometer Mode
Two Single-Pole/Single-Throw Analog Switches
Voltage or Current Source/Sink Mode
Three Oscillators
2.048 kHz Oscillator
2.048 MHz Oscillator
25 MHz Oscillator
One Low Offset Chopper Comparator
Two Low Power General Purpose ACMPs
ACMP Sampling Mode
Hysteresis with Independently-Selectable Thresholds
Analog Temperature Sensor
Power-On Reset
In-System Programmability
Multiple Time Programmable Memory
Wide Range Power Supply
Three Voltage References
Two ACMP Vref Output Buffers
One High Drive Buffer
Thirteen Combination Function Macrocells
2.5 V (±4 %) to 5 V (±10 %) VDD
Three Selectable DFF/LATCH or 2-bit LUTs
One Selectable Programmable Pattern Generator or
2-bit LUT
Operating Temperature Range: -40 °C to +85 °C
RoHS Compliant/Halogen-Free
Package Available
Seven Selectable DFF/LATCH or 3-bit LUTs
One Selectable Pipe Delay or Ripple Counter or
24-pin STQFN: 3 mm x 3 mm x 0.55 mm, 0.4 mm pitch
Applications
Adjust Precision Threshold
Sensor Offset Trimming/Calibration
Tunable Analog Filters
Operational Amplifier Adjustable Gain and Offset
Adjustable Voltage-to-Current Conversions
Personal Computers and Servers
PC Peripherals
Consumer Electronics
Data Communications Equipment
Handheld and Portable Electronics
Smartphones and Fitness Bands
Notebook and Tablet PCs
Datasheet
10-Mar-2021
Revision 2.4
1 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Contents
General Description.................................................................................................................................................................1
Key Features ............................................................................................................................................................................1
Applications..............................................................................................................................................................................1
1 Block Diagram ....................................................................................................................................................................12
2 Pinout ..................................................................................................................................................................................13
2.1 Pin Configuration - STQFN-24L ...........................................................................................................................13
3 Characteristics ...................................................................................................................................................................16
3.1 Absolute Maximum Ratings .................................................................................................................................16
3.2 Electrostatic Discharge Ratings ...........................................................................................................................16
3.3 Recommended Operating Conditions ..................................................................................................................16
3.4 Electrical Characteristics ......................................................................................................................................17
3.5 I2C Pins Electrical Characteristics ........................................................................................................................22
3.6 Macrocells Current Consumption .........................................................................................................................24
3.7 Timing Characteristics .........................................................................................................................................25
3.8 Oscillator Characteristics .....................................................................................................................................26
3.9 ACMP Characteristics ..........................................................................................................................................27
3.10 Internal Vref Characteristics ...............................................................................................................................28
3.11 Output Buffers Characteristics ...........................................................................................................................28
3.12 Analog Temperature Sensor Characteristics .....................................................................................................29
3.13 Programmable Operational Amplifier Characteristics ........................................................................................30
3.14 100K Digital Rheostat Characteristics ...............................................................................................................33
3.15 Analog Switches Characteristics .......................................................................................................................35
4 User Programmability ........................................................................................................................................................36
5 IO Pins .................................................................................................................................................................................37
5.1 GPIO Pins ............................................................................................................................................................37
5.2 GPI Pins ...............................................................................................................................................................37
5.3 Pull-Up/Down Resistors .......................................................................................................................................37
5.4 Fast Pull-Up/Down during Power-Up ...................................................................................................................37
5.5 I2C Mode IO Structure .........................................................................................................................................38
5.6 Matrix OE IO Structure .........................................................................................................................................39
5.7 GPI Structure .......................................................................................................................................................40
5.8 IO Pins Typical Performance ...............................................................................................................................41
6 Connection Matrix ..............................................................................................................................................................44
6.1 Matrix Input Table ................................................................................................................................................45
6.2 Matrix Output Table .............................................................................................................................................46
6.3 Connection Matrix Virtual Inputs ..........................................................................................................................49
6.4 Connection Matrix Virtual Outputs .......................................................................................................................50
7 Combination Function Macrocells ....................................................................................................................................51
7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................51
7.2 2-bit LUT or Programmable Pattern Generator ....................................................................................................54
7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................56
7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell ...............................................................................................64
7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell ..............................................................................................66
8 Multi-Function Macrocells .................................................................................................................................................70
8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells ..............................................................................70
8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell ..............................................................................79
8.3 CNT/DLY/FSM Timing Diagrams .........................................................................................................................82
8.4 Wake and Sleep Controller ..................................................................................................................................91
9 Analog Comparators ..........................................................................................................................................................95
9.1 Analog Comparators Overview ............................................................................................................................95
9.2 Chopper Analog Comparator ...............................................................................................................................97
9.3 ACMP Sampling Mode .........................................................................................................................................98
9.4 ACMP Typical Performance .................................................................................................................................99
10 Programmable Operational Amplifiers .........................................................................................................................102
10.1 General Description .........................................................................................................................................102
Datasheet
10-Mar-2021
Revision 2.4
2 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
10.2 Modes of Operation ..........................................................................................................................................104
10.3 Op Amps Typical Performance ........................................................................................................................108
11 Analog Switch Macrocell ...............................................................................................................................................154
11.1 Analog Switch General Description ..................................................................................................................154
11.2 Half Bridge Mode .............................................................................................................................................156
11.3 Analog Switches Typical Performance .............................................................................................................157
12 Digital Rheostats and Programmable Trim Block .......................................................................................................159
12.1 Potentiometer Mode .........................................................................................................................................161
12.2 Calculating Actual Resistance ..........................................................................................................................161
12.3 Digital Rheostat Value Self-programming into the NVM ..................................................................................162
12.4 Trimming process Using Programmable Trim Block ........................................................................................165
12.5 Using Chopper ACMP ......................................................................................................................................171
13 Programmable Delay/Edge Detector ............................................................................................................................177
13.1 Programmable Delay Timing Diagram - Edge Detector Output .......................................................................177
14 Additional Logic Function. Deglitch Filter ...................................................................................................................178
15 Voltage Reference ..........................................................................................................................................................179
15.1 Voltage Reference Overview ...........................................................................................................................179
15.2 Vref Selection Table ........................................................................................................................................179
15.3 Vref Block Diagram ..........................................................................................................................................181
15.4 Voltage Reference Typical Performance .........................................................................................................185
16 Clocking ..........................................................................................................................................................................188
16.1 OSC General Description .................................................................................................................................188
16.2 Oscillator0 (2.048 kHz) .....................................................................................................................................189
16.3 Oscillator1 (2.048 MHz) ...................................................................................................................................190
16.4 Oscillator2 (25 MHz) ........................................................................................................................................191
16.5 CNT/DLY Clock Scheme ..................................................................................................................................191
16.6 External Clocking .............................................................................................................................................192
16.7 Oscillators Power-On Delay .............................................................................................................................193
16.8 Oscillators Accuracy .........................................................................................................................................195
16.9 Oscillators Settling time ....................................................................................................................................197
16.10 Oscillators Current Consumption ..................................................................................................................199
17 Power-On Reset ..............................................................................................................................................................203
17.1 General Operation ............................................................................................................................................203
17.2 POR Sequence ................................................................................................................................................204
17.3 Macrocells Output States During POR Sequence ...........................................................................................204
18 I2C Serial Communications Macrocell ..........................................................................................................................207
18.1 I2C Serial Communications Macrocell Overview ..............................................................................................207
18.2 I2C Serial Communications Device Addressing ...............................................................................................207
18.3 I2C Serial General Timing ................................................................................................................................208
18.4 I2C Serial Communications Commands ...........................................................................................................208
18.5 Chip Configuration Data Protection ..................................................................................................................211
18.6 I2C Serial Command Register Map ..................................................................................................................212
18.7 I2C Additional Options ......................................................................................................................................215
19 Non-Volatile Memory ......................................................................................................................................................217
19.1 Serial NVM Write Operations ...........................................................................................................................217
19.2 Serial NVM Read Operations ...........................................................................................................................219
19.3 Serial NVM Erase Operations ..........................................................................................................................219
19.4 Acknowledge Polling ........................................................................................................................................220
19.5 Low power standby mode ................................................................................................................................220
19.6 Emulated EEPROM Write Protection ...............................................................................................................220
20 Analog Temperature Sensor .........................................................................................................................................222
21 Register Definitions .......................................................................................................................................................225
21.1 Register Map ....................................................................................................................................................225
22 Package Top Marking System Definition .....................................................................................................................284
22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package ............................................................................284
23 Package Information ......................................................................................................................................................285
23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package ......................................285
Datasheet
10-Mar-2021
Revision 2.4
3 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
23.2 STQFN Handling ..............................................................................................................................................285
23.3 Soldering Information .......................................................................................................................................285
24 Ordering Information .....................................................................................................................................................286
24.1 Tape and Reel Specifications ..........................................................................................................................286
24.2 Carrier Tape Drawing and Dimensions ............................................................................................................286
25 Layout Guidelines ..........................................................................................................................................................287
25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package ...........................................................................287
Glossary................................................................................................................................................................................288
Revision History...................................................................................................................................................................291
Datasheet
10-Mar-2021
Revision 2.4
4 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Figures
Figure 1: Block Diagram...........................................................................................................................................................12
Figure 2: Steps to Create a Custom GreenPAK Device...........................................................................................................36
Figure 3: IO with I2C Mode IO Structure Diagram....................................................................................................................38
Figure 4: Matrix OE IO Structure Diagram...............................................................................................................................39
Figure 5: IO0 GPI Structure Diagram.......................................................................................................................................40
Figure 6: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C.......................................................41
Figure 7: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range......................41
Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C .........................................42
Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range......................42
Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C .......................................43
Figure 11: Connection Matrix...................................................................................................................................................44
Figure 12: Connection Matrix Example....................................................................................................................................44
Figure 13: 2-bit LUT0 or DFF0.................................................................................................................................................51
Figure 14: 2-bit LUT1 or DFF1.................................................................................................................................................52
Figure 15: 2-bit LUT2 or DFF2.................................................................................................................................................52
Figure 16: DFF Polarity Operations..........................................................................................................................................54
Figure 17: 2-bit LUT3 or PGen.................................................................................................................................................55
Figure 18: PGen Timing Diagram.............................................................................................................................................55
Figure 19: 3-bit LUT0 or DFF3.................................................................................................................................................57
Figure 20: 3-bit LUT1 or DFF4.................................................................................................................................................58
Figure 21: 3-bit LUT2 or DFF5.................................................................................................................................................58
Figure 22: 3-bit LUT3 or DFF6.................................................................................................................................................59
Figure 23: 3-bit LUT4 or DFF7.................................................................................................................................................59
Figure 25: 3-bit LUT6 or DFF9.................................................................................................................................................60
Figure 24: 3-bit LUT5 or DFF8.................................................................................................................................................60
Figure 26: DFF Polarity Operations with nReset......................................................................................................................63
Figure 27: DFF Polarity Operations with nSet..........................................................................................................................64
Figure 28: 4-bit LUT0 or DFF10...............................................................................................................................................65
Figure 29: 3-bit LUT13/Pipe Delay/Ripple Counter..................................................................................................................67
Figure 30: Example: Ripple Counter Functionality...................................................................................................................68
Figure 31: Possible Connections Inside Multi-Function Macrocell...........................................................................................70
Figure 32: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT7/DFF11, CNT/DLY1) ...................................................71
Figure 33: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF12, CNT/DLY2) ...................................................72
Figure 34: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF13, CNT/DLY3) ...................................................73
Figure 35: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF14, CNT/DLY4) .................................................74
Figure 36: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF15, CNT/DLY5) .................................................75
Figure 37: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF16, CNT/DLY6) .................................................76
Figure 38: 4-bit LUT1 or CNT/DLY0.........................................................................................................................................80
Figure 39: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3 ........................................................................82
Figure 40: Delay Mode Timing Diagram for Different Edge Select Modes...............................................................................83
Figure 41: Counter Mode Timing Diagram without Two DFFs Synced Up ..............................................................................83
Figure 42: Counter Mode Timing Diagram with Two DFFs Synced Up ...................................................................................84
Figure 43: One-Shot Function Timing Diagram........................................................................................................................85
Figure 44: Frequency Detection Mode Timing Diagram...........................................................................................................86
Figure 45: Edge Detection Mode Timing Diagram...................................................................................................................87
Figure 46: Delayed Edge Detection Mode Timing Diagram.....................................................................................................88
Figure 47: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3.....88
Figure 48: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3 .........89
Figure 49: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3.....89
Figure 50: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3 .........90
Figure 51: Counter Value, Counter Data = 3............................................................................................................................90
Figure 52: Wake and Sleep Controller.....................................................................................................................................91
Figure 53: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used ...................................................92
Figure 54: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used ......................................................92
Figure 55: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used .......................................................93
Datasheet
10-Mar-2021
Revision 2.4
5 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Figure 56: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Set is Used ..........................................................93
Figure 57: ACMP0L Block Diagram .........................................................................................................................................96
Figure 58: ACMP1L Block Diagram .........................................................................................................................................97
Figure 59: Chopper ACMP Block Diagram...............................................................................................................................98
Figure 60: Propagation Delay vs. Vref for ACMPx at T = 25 °C, VDD = 2.4 V to 5.5 V, Hysteresis = 0 ...................................99
Figure 61: ACMPx Power-On Delay vs. VDD at BG - Forced...................................................................................................99
Figure 62: ACMPx Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, VDD = 2.4 V to 5.5 V, Gain = 1 ..............................100
Figure 63: Chopper ACMP Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, VDD = 2.4 V to 5.5 V, Gain = 1 .................100
Figure 64: ACMPx Current Consumption vs. VDD................................................................................................................................................101
Figure 65: Chopper ACMP Current Consumption vs. VDD (with 2.048 kHz Clock)................................................................101
Figure 66: Programmable Operational Amplifier OA0, OA1 Internal Circuit ..........................................................................102
Figure 67: Internal Operational Amplifier Circuit ....................................................................................................................103
Figure 68: Example of Input Offset Voltage Compensation...................................................................................................104
Figure 69: Instrumentation Amplifier Structure.......................................................................................................................105
Figure 70: Instrumentation Operational Amplifier Configuration for Users Trim.....................................................................106
Figure 71: Typical Implementation of Voltage Regulator (A) and Current Sources (B, C).....................................................107
Figure 72: Constant Current Sink...........................................................................................................................................108
Figure 73: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 128 kHz.............................................108
Figure 74: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 512 kHz.............................................109
Figure 75: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 2 MHz ...............................................109
Figure 76: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 8 MHz ............................................... 110
Figure 77: Internal Op Amp Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 128 kHz ................................. 110
Figure 78: Internal Op Amp at Input CM Voltage = VDD/2, BW = 512 kHz............................................................................. 111
Figure 79: Internal Op Amp at Input CM Voltage = VDD/2, BW = 2 MHz ............................................................................... 111
Figure 80: Internal Op Amp Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 8 MHz .................................... 112
Figure 81: OpAmp0, 1 Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 2.4 V ............................................112
Figure 82: OpAmp0, 1 Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 5.5 V ............................................113
Figure 83: Internal OpAmp Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 2.4 V .....................................113
Figure 84: Internal OpAmp Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 5.5 V .....................................114
Figure 85: Quiescent Current vs. Power Supply Voltage for BW = 128 kHz.......................................................................... 114
Figure 86: Quiescent Current vs. Power Supply Voltage for BW = 512 kHz.......................................................................... 115
Figure 87: Quiescent Current vs. Power Supply Voltage for BW = 2 MHz ............................................................................ 115
Figure 88: Quiescent Current vs. Power Supply Voltage or BW = 8 MHz ............................................................................. 116
Figure 89: OA0 Open Loop Gain and Phase vs. Frequency for BW = 128 kHz .................................................................... 116
Figure 90: OA0 Open Loop Gain and Phase vs. Frequency for BW = 512 kHz .................................................................... 117
Figure 91: OA0 Open Loop Gain and Phase vs. Frequency for BW = 2 MHz .......................................................................117
Figure 92: OA0 Open Loop Gain and Phase vs. Frequency for BW = 8 MHz .......................................................................118
Figure 93: OA1 Open Loop Gain and Phase vs. Frequency for BW = 128 kHz .................................................................... 118
Figure 94: OA1 Open Loop Gain and Phase vs. Frequency for BW = 512 kHz .................................................................... 119
Figure 95: OA1 Open Loop Gain and Phase vs. Frequency for BW = 2 MHz .......................................................................119
Figure 96: OA1 Open Loop Gain and Phase vs. Frequency for BW = 8 MHz .......................................................................120
Figure 97: PSRR vs. Frequency VDD = 2.4 V to 5.5 V..........................................................................................................120
Figure 98: 0.1 Hz to 10 Hz Noise, BW = 128 kHz..................................................................................................................121
Figure 99: 0.1 Hz to 10 Hz Noise, BW = 512 kHz..................................................................................................................121
Figure 100: 0.1 Hz to 10 Hz Noise, BW = 2 MHz...................................................................................................................122
Figure 101: 0.1 Hz to 10 Hz Noise, BW = 2 MHz...................................................................................................................122
Figure 102: Channel Separation vs. Frequency.....................................................................................................................123
Figure 103: Op Ampx Noise Voltage Density vs. Frequency..................................................................................................123
Figure 104: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 128 kHz ................................................124
Figure 105: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 512 kHz ................................................124
Figure 106: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 2 MHz ...................................................125
Figure 107: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 8 MHz....................................................125
Figure 108: Small Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 128 kHz..............................126
Figure 109: Small Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 512 kHz..............................126
Figure 110: Small Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 2 MHz ................................127
Figure 111: Small Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 8 MHz ................................127
Figure 112: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 128 kHz......................128
Datasheet
10-Mar-2021
Revision 2.4
6 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Figure 113: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 512 kHz......................128
Figure 114: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 2 MHz.........................129
Figure 115: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 8 MHz.........................129
Figure 116: Large Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 80 pF, BW = 128 kHz .............................130
Figure 117: Large Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 80 pF, BW = 512kHz ..............................130
Figure 118: Large Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 80 pF, BW = 2 MHz ................................131
Figure 119: Large Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 80 pF, BW = 8 MHz ................................131
Figure 120: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 128 kHz......................132
Figure 121: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 512 kHz......................132
Figure 122: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 2 MHz ........................133
Figure 123: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 8 MHz ........................133
Figure 124: Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 128 kHz ............................................134
Figure 125: Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 512 kHz ............................................134
Figure 126: Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 2 MHz ...............................................135
Figure 127: Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 8 MHz ...............................................135
Figure 128: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 128 kHz.....................................136
Figure 129: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 512 kHz.....................................136
Figure 130: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 2 MHz .......................................137
Figure 131: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 8 MHz .......................................137
Figure 132: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 128 kHz.......................................138
Figure 133: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 512 kHz.......................................138
Figure 134: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 2 MHz..........................................139
Figure 135: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 8 MHz..........................................139
Figure 136: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 128 kHz, RLOAD = 600 Ω....................................140
Figure 137: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 128 kHz, RLOAD = 50 kΩ ....................................140
Figure 138: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 128 kHz, RLOAD = 600 Ω....................................141
Figure 139: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 128 kHz, RLOAD = 50 kΩ....................................141
Figure 140: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 512 kHz, RLOAD = 50 kΩ ....................................142
Figure 141: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 512 kHz, RLOAD = 50 kΩ ....................................142
Figure 142: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 512 kHz, RLOAD = 600 Ω....................................143
Figure 143: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 512kHz, RLOAD = 50 kΩ.....................................143
Figure 144: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 2 MHz, RLOAD = 600 Ω.......................................144
Figure 145: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 2 MHz, RLOAD = 50 kΩ.......................................144
Figure 146: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 2 MHz, RLOAD = 600 Ω ......................................145
Figure 147: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 2 MHz, RLOAD = 50 kΩ.......................................145
Figure 148: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 8MHz, RLOAD = 600 Ω........................................146
Figure 149: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 8 MHz, RLOAD = 50 kΩ.......................................146
Figure 150: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 8 MHz, RLOAD = 600 Ω ......................................147
Figure 151: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 8 MHz, RLOAD = 50 kΩ.......................................147
Figure 152: Overload Recovery Time vs. Power Supply Voltage RL= 50 kΩ; G = 1 V/V, Rising...........................................148
Figure 153: Overload Recovery Time vs. Power Supply Voltage RL= 50 kΩ; G = 1 V/V, Falling..........................................148
Figure 154: Output Response to Power Down Signal G = 1 V/V; RL = 50 kΩ; CL = 20 pF; VIN = VS/2, BW = 128 kHz ......149
Figure 155: Output Response to Power Down Signal G = 1 V/V; RL = 50 kΩ; CL = 20 pF; VIN = VS/2, BW = 512 kHz ......149
Figure 156: Output Response to Power Down Signal G = 1 V/V; RL = 50 kΩ; CL = 20 pF; VIN = VS/2, BW = 2 MHz.........150
Figure 157: Output Response to Power Down Signal G = 1 V/V; RL = 50 kΩ; CL = 20 pF; VIN = VS/2, BW = 8 MHz.........150
Figure 158: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 128 kHz ................................................................151
Figure 159: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 512 kHz ................................................................151
Figure 160: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 2 MHz ...................................................................152
Figure 161: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 8MHz ....................................................................152
Figure 162: Opamps Quiescent Current Consumption vs. VDD......................................................................................................................153
Figure 163: Analog Switch 0 Control Circuit...........................................................................................................................154
Figure 164: Analog Switch 1 Control Circuit...........................................................................................................................155
Figure 165: Structure of Half Bridge.......................................................................................................................................156
Figure 166: Typical RON vs. Input Voltage (Vi) for Vi = 0 to VDDA, LOAD = 1 mA,
I
VDDA = 2.4 V................................................157
VDDA = 5.5 V................................................157
Figure 167: Typical RON vs. Input Voltage (Vi) for Vi = 0 to VDDA, LOAD = 1 mA,
I
Figure 168: Turn-On Time vs. VDD at RLOAD = 100 Ω to GND, VIN = VDD/2.......................................................................................................158
Figure 169: Turn-Off Time vs. VDD at RLOAD = 100 Ω to GND, VIN = VDD/2.......................................................................................................158
Datasheet
10-Mar-2021
Revision 2.4
7 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Figure 170: Programmable Trim Blocks and Digital Rheostat’s Internal Circuit.....................................................................160
Figure 171: Rheostats in Potentiometer Mode......................................................................................................................161
Figure 172: Rheostat Tolerance Registers............................................................................................................................162
Figure 173: Flowchart of "Program" and "Reload" Signals ....................................................................................................163
Figure 174: Example of Latching and Processing "Program" and "Reload" Signals..............................................................164
Figure 175: Example of Auto-Trim Process for a Single Rheostat.........................................................................................166
Figure 176: Example of Auto-Trim Process with External Clock Signal.................................................................................167
Figure 177: Example of Auto-Trim Process for Two Rheostats .............................................................................................168
Figure 178: Example of Auto-Trim Process via I2C................................................................................................................169
Figure 179: Example of Hardware Configuration...................................................................................................................170
Figure 180: Example of User Specific Trimming Process under I2C Master Control.............................................................171
Figure 181: DNL vs. Digital Code, Rheostat Mode (VAB = 1 V) at T = 25 °C.........................................................................172
Figure 182: INL vs. Digital Code, Rheostat Mode (VAB = 1 V) at T = 25 °C ..........................................................................172
Figure 183: DNL vs. Digital Code, Potentiometer Mode (VAB = 1 V) at T = 25 °C.................................................................173
Figure 184: INL vs. Digital Code, Potentiometer Mode (VAB = 1 V) at T = 25 °C ..................................................................173
Figure 185: (ΔRAB/RAB)/ΔTA Rheostat Mode Tempco...........................................................................................................174
Figure 186: RHx Zero Scale Error vs. Temperature (VIN = 1 V) ............................................................................................174
Figure 187: Transition Glitch in Worst Case (Code = 511 to Code = 512).............................................................................175
Figure 188: Gain vs. Frequency (Code = 512) at T = 25 °C, VDDA = 5 V...............................................................................175
Figure 189: RHx Settling Time vs. VDD at ILOAD = 1 mA, T = 25 °C .........................................................................................176
Figure 190: Programmable Delay ..........................................................................................................................................177
Figure 191: Edge Detector Output .........................................................................................................................................177
Figure 192: Deglitch Filter or Edge Detector..........................................................................................................................178
Figure 193: Generalized Vref Structure..................................................................................................................................181
Figure 194: ACMP0L, ACMP1L Voltage Reference Block Diagram......................................................................................182
Figure 195: HD Buffer and Chopper ACMP Reference Block Diagram.................................................................................183
Figure 196: Operational Amplifiers Voltage Reference Block Diagram..................................................................................184
Figure 197: Typical Load Regulation, Vref = 320 mV, T = -40 °C to +85 °C, Buffer - Enable................................................185
Figure 198: Typical Load Regulation, Vref = 640 mV, T = -40 °C to +85 °C, Buffer - Enable................................................185
Figure 199: Typical Load Regulation, Vref = 1280 mV, T = -40 °C to +85 °C, Buffer - Enable..............................................186
Figure 200: Typical Load Regulation, Vref = 2048 mV, T = -40 °C to +85 °C, Buffer - Enable..............................................186
Figure 201: Typical Input Offset Voltage vs. Vref at VDD = 2.4 V to 5.5 V, T = 25 °C, Buffer Disabled .................................187
Figure 202: Oscillator0 Block Diagram...................................................................................................................................189
Figure 203: Oscillator1 Block Diagram...................................................................................................................................190
Figure 204: Oscillator2 Block Diagram...................................................................................................................................191
Figure 205: Clock Scheme.....................................................................................................................................................192
Figure 206: Oscillator Startup Diagram..................................................................................................................................193
Figure 207: OSC0 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 2.048 kHz....................................................193
Figure 208: OSC1 Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC1 = 2.048 MHz....................................194
Figure 209: OSC2 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC2 = 25 MHz.........................................................194
Figure 210: OSC0 Frequency vs. Temperature, OSC0 = 2.048 kHz.....................................................................................195
Figure 211: OSC1 Frequency vs. Temperature, OSC1 = 2.048 MHz....................................................................................195
Figure 212: OSC2 Frequency vs. Temperature, OSC2 = 25 MHz.........................................................................................196
Figure 213: Oscillators Total Error vs. Temperature ..............................................................................................................196
Figure 214: Oscillator0 Settling Time, VDD = 3.3 V, T = 25 °C, OSC0 = 2 kHz......................................................................197
Figure 215: Oscillator1 Settling Time, VDD = 3.3 V, T = 25 °C, OSC1 = 2 MHz ....................................................................197
Figure 216: Oscillator2 Settling Time, VDD = 3.3 V, T = 25 °C, OSC2 = 25 MHz (Normal Start)...........................................198
Figure 217: Oscillator2 Settling Time, VDD = 3.3 V, T = 25 °C, OSC2 = 25 MHz (Start with Delay)......................................198
Figure 218: OSC1 Current Consumption vs. VDD (Pre-Divider = 1).......................................................................................199
Figure 219: OSC1 Current Consumption vs. VDD (Pre-Divider = 4).......................................................................................199
Figure 220: OSC1 Current Consumption vs. VDD (Pre-Divider = 8).......................................................................................200
Figure 221: OSC2 Current Consumption vs. VDD (Pre-Divider = 1).......................................................................................200
Figure 222: OSC2 Current Consumption vs. VDD (Pre-Divider = 4).......................................................................................201
Figure 223: OSC2 Current Consumption vs. VDD (Pre-Divider = 8).......................................................................................202
Figure 224: POR Sequence...................................................................................................................................................204
Figure 225: Internal Macrocell States During POR Sequence...............................................................................................205
Figure 226: Power-Down........................................................................................................................................................206
Datasheet
10-Mar-2021
Revision 2.4
8 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Figure 227: Basic Command Structure..................................................................................................................................207
Figure 228: I2C General Timing Characteristics.....................................................................................................................208
Figure 229: Byte Write Command, R/W = 0...........................................................................................................................208
Figure 230: Sequential Write Command................................................................................................................................209
Figure 231: Current Address Read Command, R/W = 1........................................................................................................209
Figure 232: Random Read Command ...................................................................................................................................210
Figure 233: Sequential Read Command................................................................................................................................210
Figure 234: Reset Command Timing .....................................................................................................................................211
Figure 235: Example of I2C Byte Write Bit Masking...............................................................................................................216
Figure 236: Page Write Command.........................................................................................................................................218
Figure 237: I2C Block Addressing ..........................................................................................................................................219
Figure 238: Analog Temperature Sensor Structure Diagram.................................................................................................223
Figure 239: TS Output vs. Temperature, VDD = 3.3 V ...........................................................................................................224
Datasheet
10-Mar-2021
Revision 2.4
9 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Tables
Table 1: Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2: Pin Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4: Electrostatic Discharge Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . . . . . . . . . . . 17
Table 7: EC of the I2C Pins at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . . . 22
Table 8: I2C Pins Timing Characteristics at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted. . . . . . 23
Table 9: Typical Current Estimated for Each Macrocell at T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10: Typical Delay Estimated for Each Macrocell at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11: Programmable Delay Expected Typical Delays and Widths at T = 25 °C . . . . . . . . . . . . . . . . . . . . . 25
Table 12: Typical Filter Rejection Pulse Width at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13: Typical Counter/Delay Offset Measurements at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14: Oscillators Frequency Limits, VDD = 2.4 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15: Oscillators Power-On Delay at T = 25 °C, OSC Power Setting: "Auto Power-On" . . . . . . . . . . . . . . . . . 27
Table 16: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . 27
Table 17: Internal Vref Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18: HD Buffer Electrical Characteristics at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . . . 28
Table 19: Vref0 Output Buffer at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . . 28
Table 20: TS Output vs Temperature (Output Range 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21: TS Output vs Temperature (Output Range 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22: EC of OA, VDDA = 2.4 V to 5.5 V, VCM = VDDA/2, VOUT ≈ VDDA/2, RL = 100 kΩ to VDDA/2, CL = 50 pF, T = 25 °C 30
Table 23: 100K Digital Rheostat EC at VA=VDD, VB=GND, T=-40°C to +85°C, VDD= 2.4V to 5.5V Unless Otherwise Noted33
Table 24: Analog Switch0/Voltage Regulator EС at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . 35
Table 25: Analog Switch1/Current Sink EС at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . . . . 35
Table 26: Matrix Input Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 27: Matrix Output Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 28: Connection Matrix Virtual Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 29: 2-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 30: 2-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 31: 2-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 32: 2-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 33: 2-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 34: 2-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 35: 3-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 36: 3-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 37: 3-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 38: 3-bit LUT3 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 39: 3-bit LUT4 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 40: 3-bit LUT5 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 41: 3-bit LUT6 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 42: 3-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 43: 4-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 44: 4-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 45: 3-bit LUT13 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 46: 3-bit LUT7 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 47: 3-bit LUT8 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 48: 3-bit LUT9 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 49: 3-bit LUT10 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 50: 3-bit LUT11 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 51: 3-bit LUT12 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 52: 4-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 53: 4-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 54: Op Amp Bandwidth Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 55: Analog Switch 0 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 56: Analog Switch 1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 57: Vref Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 58: Oscillator Operation Mode Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 59: RPR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 60: RPR Bit Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 61: NPR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Datasheet
10-Mar-2021
Revision 2.4
10 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 62: NPR Bit Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 63: Read/Write Register Protection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 64: Erase Register Bit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 65: Erase Register Bit Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 66: Write/Erase Protect Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 67: Write/Erase Protect Register Bit Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 68: Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Datasheet
10-Mar-2021
Revision 2.4
11 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
1
Block Diagram
AGND
OA1-
OA1_OUT
IO6
IO7
OA1+
Oscillators
1024 Position
Rheostat
2.048
MHz
2.048
kHz
25
MHz
HD
Buffer
1024 Position
Rheostat
2K bits
EEPROM
Emulation
VDDA
Multiple Time
Programmable
Memory
IO5
IO4
In-System
Programmability
Programmable
Trim Block
Combination Function Macrocells
OA0+
OA0-
2-bit
LUT2_0
or DFF0
2-bit
LUT2_1
or DFF1
2-bit
LUT2_2
or DFF2
2-bit
LUT2_3
or PGen
Chopper
ACMP
ACMP1L
ACMP0L
3bit
LUT3_0
or DFF3
3-bit
LUT3_1
or DFF4
3-bit
LUT3_2
or DFF5
3-bit
LUT3_3
or DFF6
IO3
IO2
Prog,
OA0
3-bit
LUT3_4
or DFF7
3-bit
LUT3_5
or DFF8
3-bit
LUT3_6
or DFF9
4-bit
LUT4_0
or DFF10
Int.
OA
3-bit LUT3_13
or Pipe Delay
or Ripple CNT
OA0_OUT
Prog,
OA1
Multi-Function Macrocells
Temperature
Sensor
RH0_A
RH0_B
IO1
Low Power Vref
3-bit LUT3_9
/DFF13
3-bitLUT3_10
/DFF14
3-bitLUT3_7
/DFF11
3-bit LUT3_8
/DFF12
+8bit
+8bit
+8bit
+8bit
CNT/DLY3
CNT/DLY4
Analog Switch 0/
Voltage Regulator Mode
CNT/DLY1
CNT/DLY2
3-bit LUT3_12
/DFF16
4-bitLUT4_1
/DFF17+
16bit
3-bitLUT3_11
/DFF15
+8bit
CNT/DLY5
VDD
+8bit
Analog Switch 1/
Current Sink Mode
CNT/DLY6
CNT/DLY0
I2C Serial
Communication
Programmable
Delay or Edge
Detect
Filter with
Edge Detect
POR
RH1_B
GND
RH1_A
IO0
SCL
SDA
Figure 1: Block Diagram
Datasheet
10-Mar-2021
Revision 2.4
12 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
2
Pinout
2.1 PIN CONFIGURATION - STQFN-24L
Pin # Signal Name Pin Functions
1
2
V
Analog Power Supply
Analog Ground
DDA
AGND
OA0-
3
Op Amp0 Inverting Input
Op Amp0 Non-Inverting Input
4
OA0+
5
OA0_OUT Op Amp0_OUT/ACMP0L+ /
6
RH0_A
RH0_B
RH1_A
RH1_B
SCL
Digital Rheostat 0 Terminal A
Digital Rheostat 0 Terminal B
Digital Rheostat 1 Terminal A
Digital Rheostat 1 Terminal B
I2C_SCL
24
1
19
23
21
20
22
V
IO4
IO3
IO2
IO1
GND
18
17
16
15
14
DDA
7
8
AGND
OA0-
2
3
4
5
9
10
11
I2C_SDA
OA0+
SDA
GPIO, ACMP0L-, ACMP1L-, EXT_OSC0_IN,
Vref0_Out or Temp_Sens_Out
OA0_OUT
RH0_A
12
IO0
6
7
13
12
V
DD
8
9
10 11
13
14
V
Digital Power Supply
Digital Ground
DD
GND
GPIO, Chop_ACMP+, Vref1_OUT or
Temp_Sens_Out, EXT_OSC1_IN or SLA_0
15
IO1
16
17
18
19
20
21
22
23
24
IO2
IO3
IO4
IO5
IO6
I0
GPIO, ACMP0L+, EXT_OSC2_IN, SLA_1
GPIO, AS_1_A, ACMP1L+ or SLA_2
GPIO, AS_1_B, Chop_ACMP-or SLA_3
GPIO, AS_0_B
STQFN-24
(Top View)
GPIO, AS_0_A, HD_Buff_Out, In Amp_Vref
GPI, In Amp_OUT
OA1_OUT Op Amp1_OUT, ACMP1L+
OA1+
OA1-
Op Amp1 Non-inverting Input
Op Amp1 Inverting Input
Legend:
ACMPx+: ACMPx Positive Input
ACMPx-: ACMPx Negative Input
SCL: I2C Clock Input
SDA: I2C Data Input/Output
Vrefx: Voltage Reference Output
SLA: Slave Address
Table 1: Functional Pin Description
Pin No.
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
STQFN 24L
1
2
VDDA
VDDA
Analog Power Supply
Analog Ground
--
--
--
--
AGND
AGND
Op Amp0
Inverting Input
3
4
OA0-
OA0-
Analog
--
Op Amp0
Non-Inverting Input
OA0+
OA0+
Analog
--
--
Analog
--
OA0_OUT
ACMP0L+
Op Amp0 Output
OA0_OUT
RH0_A
Analog Comparator 0 Positive In-
5
6
Analog
put
Digital Rheostat 0
Terminal A
RH0_A
--
--
Datasheet
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 1: Functional Pin Description(Continued)
Pin No.
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
STQFN 24L
Digital Rheostat 0
Terminal B
7
RH0_B
RH1_A
RH1_B
RH0_B
RH1_A
RH1_B
--
--
--
--
--
--
Digital Rheostat 1
Terminal A
8
9
Digital Rheostat 1
Terminal B
10
11
SCL
SDA
SCL
SDA
IO0
I2C Serial Clock
I2C Serial Data
--
--
--
--
--
General Purpose IO
--
Analog Comparator 0
Negative Input
Analog
ACMP0L-
ACMP1L-
--
--
--
Analog Comparator 1
Negative Input
Analog
12
IO0
External Clock
Connection
EXT_OSC0_IN
--
Vref0_Out
VDD
Voltage Reference 0 Output
Digital Power Supply
Digital Ground
--
--
--
--
Analog
13
14
VDD
--
--
--
GND
GND
IO1
General Purpose IO
CHOP_ACMP+
Chopper ACMP
Positive Input
Analog
--
Analog
--
Temp_Sens_Out
EXT_OSC1_IN
Temperature Sensor Output
--
--
15
IO1
External Clock
Connection
Slave
Address 0
SLA_0
IO2
--
--
--
--
--
General Purpose IO
Analog Comparator 0
Positive Input
ACMP0L+
Analog
16
IO2
External Clock
Connection
EXT_OSC2_IN
SLA_1
--
--
--
--
Slave
Address 1
IO3
General Purpose IO
--
--
AS_1_A
Analog Switch 1Input A
Analog
Analog
Analog Comparator 1
Positive Input
17
18
IO3
IO4
ACMP1L+
SLA_2
--
--
--
--
Slave
Address 2
IO4
General Purpose IO
--
--
AS_1_B
Analog Switch 1 Input B
Analog
Analog
Chopper ACMP
Negative Input
Analog
--
--
--
Slave
Address 3
SLA_3
Datasheet
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 1: Functional Pin Description(Continued)
Pin No.
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
STQFN 24L
IO5
AS_0_B
IO6
General Purpose IO
Analog Switch 0 Input B
General Purpose IO
--
Analog
--
--
19
IO5
Analog
--
AS_0_A
HD_Buffer_Out
Analog Switch 0 Input A
High Drive Buffer Out put
Analog
--
Analog
Analog
20
IO6
Instrumentation
Amplifier
In Amp_Vref
Analog
--
Voltage Reference
I0
General Purpose Input
--
--
--
21
22
I0
Instrumentation
Amplifier Output
In Amp Out
OA1_OUT
ACMP1L+
Analog
--
Op Amp1 Output
Analog
--
OA1_OUT
Analog Comparator 1
Positive Input
Analog
Op Amp1
Non-inverting Input
23
24
OA1+
OA1-
OA1+
OA1-
Analog
Analog
--
--
Op Amp1
Inverting Input
Table 2: Pin Type Definitions
Pin Type
VDDA
AGND
OA-
Description
Analog Power Supply
Analog Ground
Op Amp Inverting Input
Op Amp Non-Inverting Input
Op Amp Output
OA+
OA_OUT
RH_A
RH_B
SCL
Digital Rheostat Terminal A
Digital Rheostat Terminal B
I2C Serial Clock
SDA
I2C Serial Data
IO
General Purpose Input/Output
Digital Power Supply
Digital Ground
VDD
GND
I
General Purpose Input
Datasheet
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© 2021 Dialog Semiconductor
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
3
Characteristics
3.1 ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability.
Analog and digital grounds must be connected together on the PCB board. The place of connection depends on users schematic.
For application cases with low digital current of SLG47004, both AGND and GND should be connected to analog ground plane.
Table 3: Absolute Maximum Ratings
Parameter
VDD to GND, VDDA to AGND (Note 1)
Maximum Slew Rate of VDDA
Voltage at Input Pin
Min
Max
7
Unit
V
-0.3
--
2
V/µs
V
GND-0.3
VDD+0.3
1.0
Current at Input Pin
-1.0
--
mA
mA
mA
mA
mA
nA
TJ = 85 °C
110
50
MaximumAverage or DC Current through
DDA or AGND Pin (Per chip side)
V
TJ = 110°C
TJ = 85 °C
TJ = 110°C
--
--
100
50
MaximumAverage or DC Current through
DD or GND Pin (Per chip side)
V
--
Input leakage (Absolute Value)
--
1000
150
150
132
Storage Temperature Range
Junction Temperature
-65
--
°C
°C
Thermal Resistance (Note 2)
Moisture Sensitivity Level
--
°C/W
1
Note 1 VDDA must be equal to VDD
Note 2 Measurements based on Analog Switches
3.2 ELECTROSTATIC DISCHARGE RATINGS
Table 4: Electrostatic Discharge Ratings
Parameter
Min
2000
1300
Max
--
Unit
V
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
--
V
3.3 RECOMMENDED OPERATING CONDITIONS
Table 5: Recommended Operating Conditions
Parameter
Condition
Min
Max
Unit
2.4
5.5
V
Supply Voltage (VDDA
)
During NVM Write and Erase
commands
2.5
5.5
V
Operating Temperature
Capacitor Value at VDD
-40
0.1
85
--
°C
µF
Allowable Input Voltage at Analog
Pins
Analog Input Common Mode Range
-0.2
VDDA+0.2
V
Datasheet
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
3.4 ELECTRICAL CHARACTERISTICS
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter Description
Condition
Min
Typ
Max
Unit
0.7x
VDD
Logic Input (Note 1)
--
VDD+ 0.3
V
VIH
HIGH-Level Input Voltage
0.8x
VDD
Logic Input with Schmitt Trigger
Low-Level Logic Input (Note 1)
Logic Input (Note 1)
--
--
--
VDD+ 0.3
VDD+ 0.3
V
V
V
1.25
GND-
0.3
0.3x
VDD
GND-
0.3
0.2x
VDD
VIL
LOW-Level Input Voltage
Logic Input with Schmitt Trigger
--
--
V
V
GND-
0.3
Low-Level Logic Input (Note 1)
0.5
VDD = 2.5 V +/- 8 % (Note 1)
VDD = 3.3 V +/- 10 % (Note 1)
VDD = 5 V +/- 10 % (Note 1)
0.28
0.34
0.50
0.43
0.46
0.63
0.54
0.56
0.74
V
V
V
Schmitt Trigger Hysteresis
Voltage
VHYS
Maximal Voltage Applied to
any PIN in High Impedance
State
VDD
+
VO
--
--
V
0.3
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Push-Pull, 1x Drive, IOH = 1 mA,
VDD = 2.4 V (Note 1)
2.178
2.389
2.598
2.712
3.039
3.36
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Push-Pull, 1x Drive, IOH = 1 mA,
VDD = 2.5 V (Note 1)
Push-Pull, 1x Drive, IOH = 1 mA,
VDD = 2.7 V (Note 1)
Push-Pull, 1x Drive, IOH = 3 mA,
VDD = 3.0 V (Note 1)
Push-Pull, 1x Drive, IOH = 3 mA,
VDD = 3.3 V (Note 1)
Push-Pull, 1x Drive, IOH = 3 mA,
VDD = 3.6 V (Note 1)
Push-Pull, 1x Drive, IOH = 5 mA,
VDD = 4.5 V (Note 1)
4.157
4.678
5.201
2.239
2.443
2.648
2.854
3.165
3.474
Push-Pull, 1x Drive, IOH = 5 mA,
VDD = 5.0 V (Note 1)
VOH
HIGH-Level Output Voltage
Push-Pull, 1x Drive, IOH = 5 mA,
VDD = 5.5 V (Note 1)
Push-Pull, 2x Drive, IOH = 1 mA,
VDD = 2.4 V (Note 1)
Push-Pull, 2x Drive, IOH = 1 mA,
VDD = 2.5 V (Note 1)
Push-Pull, 2x Drive, IOH = 1 mA,
VDD = 2.7 V (Note 1)
Push-Pull, 2x Drive, IOH = 3 mA,
VDD = 3.0 V (Note 1)
Push-Pull, 2x Drive, IOH = 3 mA,
VDD = 3.3 V (Note 1)
Push-Pull, 2x Drive, IOH = 3 mA,
VDD = 3.6 V (Note 1)
Datasheet
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Revision 2.4
17 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 2x Drive, IOH = 5 mA,
VDD = 4.5 V (Note 1)
4.314
--
--
V
Push-Pull, 2x Drive, IOH = 5 mA,
VDD = 5.0 V (Note 1)
VOH
HIGH-Level Output Voltage
4.821
5.329
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Push-Pull, 2x Drive, IOH = 5 mA,
VDD = 5.5 V (Note 1)
--
Push-Pull, 1x Drive, IOL= 1 mA,
VDD = 2.4 V (Note 1)
0.085
0.079
0.074
0.210
0.195
0.183
0.271
0.256
0.246
0.046
0.043
0.040
0.114
0.107
0.102
0.152
0.145
0.140
0.038
0.035
0.033
0.094
Push-Pull, 1x Drive, IOL= 1 mA,
VDD = 2.5 V (Note 1)
--
Push-Pull, 1x Drive, IOL= 1 mA,
VDD = 2.7 V (Note 1)
--
Push-Pull, 1x Drive, IOL = 3 mA,
VDD = 3.0 V (Note 1)
--
Push-Pull, 1x Drive, IOL = 3 mA,
VDD = 3.3 V (Note 1)
--
Push-Pull, 1x Drive, IOL = 3 mA,
VDD = 3.6 V (Note 1)
--
Push-Pull, 1x Drive, IOL= 5 mA,
VDD = 4.5 V (Note 1)
--
Push-Pull, 1x Drive, IOL= 5 mA,
VDD = 5.0 V (Note 1)
--
Push-Pull, 1x Drive, IOL= 5 mA,
VDD = 5.5 V (Note 1)
--
Push-Pull, 2x Drive, IOL= 1 mA,
VDD = 2.4 V (Note 1)
--
Push-Pull, 2x Drive, IOL = 1 mA,
VDD = 2.5 V (Note 1)
--
VOL
LOW-Level Output Voltage
Push-Pull, 2x Drive, IOL = 1 mA,
VDD = 2.7 V (Note 1)
--
Push-Pull, 2x Drive, IOL= 3 mA,
VDD = 3.0 V (Note 1)
--
Push-Pull, 2x Drive, IOL= 3 mA,
VDD = 3.3 V (Note 1)
--
Push-Pull, 2x Drive, IOL= 3 mA,
VDD = 3.6 V (Note 1)
--
Push-Pull, 2x Drive, IOL = 5 mA,
VDD = 4.5 V (Note 1)
--
Push-Pull, 2x Drive, IOL = 5 mA,
VDD = 5.0 V (Note 1)
--
Push-Pull, 2x Drive, IOL = 5 mA,
VDD = 5.5 V (Note 1)
--
NMOS OD, 1x Drive, IOL= 1 mA,
VDD = 2.4 V (Note 1)
--
NMOS OD, 1x Drive, IOL = 1 mA,
VDD = 2.5 V (Note 1)
--
NMOS OD, 1x Drive, IOL = 1 mA,
VDD = 2.7 V (Note 1)
--
NMOS OD, 1x Drive, IOL = 3 mA,
VDD = 3.0 V (Note 1)
--
Datasheet
10-Mar-2021
Revision 2.4
18 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
NMOS OD, 1x Drive, IOL = 3 mA,
VDD = 3.3 V (Note 1)
--
--
0.088
0.084
0.127
0.121
0.117
0.032
0.03
0.029
0.064
0.062
0.059
0.085
0.081
0.08
--
V
NMOS OD, 1x Drive, IOL = 3 mA,
VDD = 3.6 V (Note 1)
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
V
V
NMOS OD, 1x Drive, IOL = 5 mA,
VDD = 4.5 V (Note 1)
NMOS OD, 1x Drive, IOL = 5 mA,
VDD = 5.0 V (Note 1)
--
V
NMOS OD, 1x Drive, IOL = 5 mA,
VDD = 5.5 V (Note 1)
--
V
NMOS OD, 2x Drive, IOL= 1 mA,
VDD2 = 2.4 V (Note 1)
--
V
NMOS OD, 2x Drive, IOL = 1 mA,
VDD = 2.5 V (Note 1)
--
V
VOL
LOW-Level Output Voltage
NMOS OD, 2x Drive, IOL = 1 mA,
VDD = 2.7 V (Note 1)
--
V
NMOS OD, 2x Drive, IOL = 3 mA,
VDD = 3.0 V (Note 1)
--
V
NMOS OD, 2x Drive, IOL = 3 mA,
VDD = 3.3 V (Note 1)
--
V
NMOS OD, 2x Drive, IOL = 3 mA,
VDD = 3.6 V (Note 1)
--
V
NMOS OD, 2x Drive, IOL = 5 mA,
VDD = 4.5 V (Note 1)
--
V
NMOS OD, 2x Drive, IOL = 5 mA,
VDD = 5.0 V (Note 1)
--
V
NMOS OD, 2x Drive, IOL = 5 mA,
VDD = 5.5 V (Note 1)
--
V
Push-Pull, 1x Drive, VOH = VDD - 0.2
VDD = 2.4 V (Note 1)
1.60
1.76
1.92
5.64
8.56
11.51
20.46
25.12
29.34
3.10
3.40
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Push-Pull, 1x Drive, VOH = VDD - 0.2
VDD = 2.5 V (Note 1)
--
Push-Pull, 1x Drive, VOH = VDD - 0.2
VDD = 2.7 V (Note 1)
--
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 3.0 V (Note 1)
--
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 3.3 V (Note 1)
--
HIGH-Level Output Current Push-Pull, 1x Drive,
IOH
--
(Note 2)
VOH = 2.4 V, VDD = 3.6 V (Note 1)
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 4.5 V (Note 1)
--
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 5.0 V (Note 1)
--
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 5.5 V (Note 1)
--
Push-Pull, 2x Drive, VOH = VDD - 0.2
VDD = 2.4 V (Note 1)
--
Push-Pull, 2x Drive, VOH = VDD - 0.2
VDD = 2.5 V (Note 1)
--
Datasheet
10-Mar-2021
Revision 2.4
19 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 2x Drive, VOH = VDD - 0.2
VDD = 2.7 V (Note 1)
3.69
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
mA
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 3.0 V (Note 1)
10.89
16.54
22.28
39.61
48.49
56.39
1.73
--
--
--
--
--
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 3.3 V (Note 1)
HIGH-Level Output Current Push-Pull, 2x Drive,
IOH
(Note 2)
VOH = 2.4 V, VDD = 3.6 V (Note 1)
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 4.5 V (Note 1)
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 5.0 V (Note 1)
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 5.5 V (Note 1)
--
--
Push-Pull, 1x Drive, VOL = 0.15 V,
VDD = 2.4 V (Note 1)
Push-Pull, 1x Drive, VOL = 0.15 V,
VDD = 2.5 V (Note 1)
1.87
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Push-Pull, 1x Drive, VOL = 0.15 V,
VDD = 2.7 V (Note 1)
2.00
Push-Pull, 1x Drive, VOL = 0.4 V,
VDD = 3.0 V (Note 1)
5.45
Push-Pull, 1x Drive, VOL = 0.4 V,
VDD = 3.3 V (Note 1)
5.90
Push-Pull, 1x Drive, VOL = 0.4 V,
VDD = 3.6 V (Note 1)
6.29
Push-Pull, 1x Drive, VOL = 0.4 V,
VDD = 4.5 V (Note 1)
7.25
Push-Pull, 1x Drive, VOL = 0.4 V,
VDD = 5.0 V (Note 1)
7.67
LOW-Level Output Current Push-Pull, 1x Drive, VOL = 0.4 V,
IOL
8.01
(Note 2)
VDD = 5.5 V (Note 1)
Push-Pull, 2x Drive, VOL = 0.15 V,
VDD = 2.4 V (Note 1)
3.20
Push-Pull, 2x Drive, VOL = 0.15 V,
VDD = 2.5 V (Note 1)
3.44
Push-Pull, 2x Drive, VOL = 0.15 V,
VDD = 2.7 V (Note 1)
3.65
Push-Pull, 2x Drive, VOL = 0.4 V,
VDD = 3.0 (Note 1)
10.01
10.73
11.36
12.85
13.52
Push-Pull, 2x Drive, VOL = 0.4 V,
VDD = 3.3 (Note 1)
Push-Pull, 2x Drive, VOL = 0.4 V,
VDD = 3.6 (Note 1)
Push-Pull, 2x Drive, VOL = 0.4 V,
VDD = 4.5 (Note 1)
Push-Pull, 2x Drive, VOL = 0.4 V,
VDD = 5.0 (Note 1)
Datasheet
10-Mar-2021
Revision 2.4
20 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 2x Drive, VOL = 0.4 V,
VDD = 5.5 (Note 1)
14.05
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
mA
NMOS OD, 1x Drive, VOL = 0.15 V,
VDD = 2.4 V (Note 1)
3.91
4.19
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NMOS OD, 1x Drive, VOL = 0.15 V,
VDD = VDD2 = 2.5 V (Note 1)
NMOS OD, 1x Drive, VOL = 0.15 V,
VDD = 2.7 V (Note 1)
4.44
NMOS OD, 1x Drive, VOL = 0.4 V,
VDD = 3.0 V (Note 1)
12.18
13.02
13.75
15.47
16.19
16.80
6.28
NMOS OD, 1x Drive, VOL = 0.4 V,
VDD = 3.3 V (Note 1)
NMOS OD, 1x Drive, VOL = 0.4 V,
VDD = 3.6 V (Note 1)
NMOS OD, 1x Drive, VOL = 0.4 V,
VDD = 4.5 V (Note 1)
NMOS OD, 1x Drive, VOL = 0.4 V,
VDD = 5.0 V (Note 1)
LOW-Level Output Current NMOS OD, 1x Drive, VOL = 0.4 V,
IOL
(Note 2)
VDD = 5.5 V (Note 1)
NMOS OD, 2x Drive, VOL = 0.15 V,
VDD = 2.4 V (Note 1)
NMOS OD, 2x Drive, VOL = 0.15 V,
VDD = 2.5 V (Note 1)
6.68
NMOS OD, 2x Drive, VOL = 0.15 V,
VDD = 2.7 V (Note 1)
7.02
NMOS OD, 2x Drive, VOL = 0.4 V,
VDD = 3.0 V (Note 1)
20.14
21.23
22.12
24.84
26.08
26.72
NMOS OD, 2x Drive, VOL = 0.4 V,
VDD = 3.3 V (Note 1)
NMOS OD, 2x Drive, VOL = 0.4 V,
VDD = 3.6 V (Note 1)
NMOS OD, 2x Drive, VOL = 0.4 V,
VDD = 4.5 V (Note 1)
NMOS OD, 2x Drive, VOL = 0.4 V,
VDD = 5.0 V (Note 1)
NMOS OD, 2x Drive, VOL = 0.4 V,
VDD = 5.5 V (Note 1)
TSU
TWR
Startup Time
From VDD rising past PONTHR
VDD = 2.5 V to 5.5 V
--
--
1.904
2.651
20
ms
ms
ms
V
NVM Page Write Time
NVM Page Erase Time
Power-On Threshold
--
--
--
TER
VDD = 2.5 V to 5.5 V
--
20
PONTHR
VDD Level Required to Start Up the Chip
1.60
2.07
VDD Level Required to Switch Off the
Chip
POFFTHR Power-Off Threshold
0.97
--
1.531
V
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
1 M for Pull-up: VIN = GND;
for Pull-down: VIN = VDD (Note 1)
0.72
1.12
1.4
134.4
13.5
MΩ
Pull-up or Pull-down
Resistance
100 k for Pull-up: VIN = GND;
for Pull-down: VIN = VDD (Note 1)
RPULL
72
110
10
kΩ
kΩ
10 k For Pull-up: VIN = GND;
for Pull-down: VIN = VDD (Note 1)
6.32
PINs 10, 11
PIN 12
--
--
--
--
--
--
2.905
3.476
3.677
10.228
27.964
5.671
--
--
--
--
--
--
pF
pF
pF
pF
pF
pF
PINs 15, 16
PINs 17, 18, 19
PIN 20
CIN
Input Capacitance
PIN 21
Note 1 No hysteresis.
Note 2 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
3.5 I2C PINS ELECTRICAL CHARACTERISTICS
Table 7: EC of the I2C Pins at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Fast-Mode
Fast-Mode Plus
Parameter Description
Condition
Unit
Min
Max
Min
Max
LOW-level Input
Voltage
VIL
-0.5
0.3xVDD
-0.5
0.3xVDD
V
V
V
HIGH-level Input
Voltage
VIH
0.7xVDD
0.05xVDD
5.5
--
0.7xVDD
5.5
--
Hysteresis of Schmitt
Trigger Inputs
VHYS
0.05xVDD
(Open-Drain) at 3 mA sink
current
LOW-Level Output
Voltage 1
VOL1
0
0
0.4
0
0
0.4
V
V
V
DD > 2 V
(Open-Drain) at 2 mA sink
current
VDD ≤ 2 V
LOW-Level Output
Voltage 2
VOL2
0.2xVDD
0.2xVDD
VOL = 0.4 V, VDD = 2.4 V
VOL = 0.4 V, VDD = 3.0 V
VOL = 0.4 V, VDD = 4.5 V
VOL= 0.6 V
3
3
3
6
--
--
--
--
16.75
20
--
--
--
--
mA
mA
mA
mA
LOW-Level Output
IOL
Current (Note 1)
20
--
Output Fall Time from
VIHmin to VILmax
(Note 1)
14x
(VDD/5.5
V)
10x
(VDD/5.5
V)
tof
250
50
120
50
ns
ns
PulseWidthofSpikes
that must be
suppressed by the
tSP
0
0
Input Filter
Input Current (each
IO Pin)
Ii
0.1xVDD < VI < 0.9xVDDmax
-10
--
+10
10
-10
--
+10
10
µA
pF
Capacitance(eachIO
Pin)
Ci
Datasheet
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 7: EC of the I2C Pins at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted(Continued)
Fast-Mode
Min Max
Fast-Mode Plus
Min Max
Parameter Description
Condition
Unit
Note 1 Does not meet standard I2C specifications: tof = 20x(VDD/5.5 V) (min); For Fast-mode Plus IOL = 20 mA (min) at
VOL = 0.4 V.
Note 2 For Fast-mode Plus SDA pin must be configured as NMOS 2x Open-Drain, see register [1155] in Section 21.
Table 8: I2C Pins Timing Characteristics at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Fast-Mode
Fast-Mode
Plus
Parameter Description
Condition
Unit
Min
--
Max
400
--
Min
--
Max
1000
--
FSCL
tLOW
tHIGH
Clock Frequency, SCL
kHz
ns
Clock Pulse Width Low
Clock Pulse Width High
1300
600
500
260
--
--
ns
Input Filter Spike Suppression
(SCL, SDA)
tI
--
--
50
900
--
--
--
50
450
--
ns
ns
ns
tAA
tBUF
Clock Low to Data Out Valid
Bus Free Time between Stop and
Start
1300
500
tHD_STA
tSU_STA
tHD_DAT
tSU_DAT
tR
Start Hold Time
Start Set-up Time
Data Hold Time
Data Set-up Time
Inputs Rise Time
Inputs Fall Time
Stop Set-up Time
Data Out Hold Time
600
600
0
--
--
260
260
0
--
--
ns
ns
ns
ns
ns
ns
ns
ns
--
--
100
--
--
50
--
--
300
300
--
120
120
--
tF
--
--
tSU_STD
tDH
600
50
260
50
--
--
Note 1 Timing diagram can be found in Figure 228.
Datasheet
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© 2021 Dialog Semiconductor
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
3.6 MACROCELLS CURRENT CONSUMPTION
Table 9: Typical Current Estimated for Each Macrocell at T = 25°C
Parameter
Description Note
Chip Quiescent, BG disabled
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
Unit
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
0.056
0.357
0.079
0.391
0.13
0.472
Chip Quiescent, BG enabled
OSC2 25 MHz, pre-divider = 1
OSC2 25 MHz, pre-divider = 4
OSC2 25 MHz, pre-divider = 8
OSC1 2.048 MHz, pre-divider = 1
OSC1 2.048 MHz, pre-divider = 4
OSC1 2.048 MHz, pre-divider = 8
OS00 2.048 kHz, pre-divider = 1
OSC0 2.048 kHz, pre-divider = 4
OSC0 2.048 kHz, pre-divider = 8
Push-Pull 1x + 4 pF @ 2.048 kHz
Push-Pull 1x + 4 pF @ 2.048 MHz
Temperature Sensor, range 1
40.954
31.716
29.897
18.951
18.255
18.116
0.330
49.907
37.448
34.998
19.751
18.809
18.622
0.363
71.075
51.515
47.664
21.507
20.023
19.730
0.443
0.327
0.359
0.437
0.326
0.359
0.436
0.384
0.436
0.554
66.582
11.001
11.140
6.198
82.354
11.050
11.188
6.260
115.785
11.356
11.493
6.484
Temperature Sensor, range 2
One ACMPx_L (includes internal Vref)
Two ACMPx_L (includes internal Vref)
8.530
8.616
8.954
I
Current
Op AmpX Quiescent Current
(128 kHz bandwidth)
31.663
32.227
33.005
µA
µA
Op AmpX Quiescent Current
(8.192 MHz bandwidth)
604.144
607.979
609.342
In Amp Quiescent Current (three Op
Amps are ON, Rf1 = Rf2 = 50 kΩ,
Rg =1 kΩ, 128 kHz bandwidth, Charge
Pump - Disabled)
95.33
72.352
97.105
73.973
99.895
76.688
µA
µA
µA
In Amp Quiescent Current (three Op
Amps are ON, Rf1 = Rf2 = 50 kΩ,
Rg =1 kΩ, 128 kHz bandwidth, Charge
Pump - Enabled)
In Amp Quiescent Current (three Op
Amps are ON, Rf1 = Rf2 = 50 kΩ,
Rg =1 kΩ, 8.192 MHz bandwidth,
Charge Pump - Disabled)
1810.631
1821.938
1826.541
In Amp Quiescent Current (three Op
Amps are ON, Rf1 = Rf2 = 50 kΩ,
Rg =1 kΩ, 8.192 MHz bandwidth,
Charge Pump - Enabled)
1229.011
31.719
1236.282
33.940
1241.784
38.717
µA
µA
Chopper ACMP (with 2.048 kHz clock)
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
3.7 TIMING CHARACTERISTICS
Table 10: Typical Delay Estimated for Each Macrocell at T = 25 °C
VDD = 2.5 V
VDD = 3.3 V
VDD = 5.0 V
Unit
Parameter Description Conditions
Rising Falling Rising Falling Rising Falling
tpd
tpd
Delay
Delay
Digital Input to PP 1x
26
27
18
20
13
15
ns
ns
Digital Input with Schmitt Trigger to
PP 1x
27
28
19
21
15
15
tpd
tpd
tpd
Delay
Delay
Delay
Digital Input to PP 2x
24
28
--
25
246
24
17
20
--
18
163
18
12
15
--
14
95
13
ns
ns
ns
Low Voltage Digital input to PP 1x
Digital input to NMOS output
Output enable from Pin, OE Hi-Z
to 1
tpd
tpd
tpd
Delay
Delay
Delay
26
--
--
26
--
19
--
--
19
--
13
--
--
14
--
ns
ns
ns
Output enable from Pin, OE Hi-Z
to 0
Digital input to 1x3-State
(Z to 1)
26
19
13
Digital input to x3-State
(Z to 0)
tpd
tpd
tpd
Delay
Delay
Delay
--
24
--
26
--
--
17
--
17
--
--
13
--
14
--
ns
ns
ns
Digital input to 2x3-State
(Z to 1)
Digital input to 2x3-State
(Z to 0)
24
19
12
tpd
tpd
tpd
tpd
tpd
tpd
tw
Delay
Delay
Delay
Delay
Delay
Delay
Width
Delay
Delay
Delay
Delay
Delay
Delay
Delay
LUT2bt
17
19
17
20
12
13
15
17
16
77
12
14
14
18
18
74
8
9
8
ns
ns
ns
ns
ns
ns
LUT3bit
10
10
12
12
70
LUT4bit
20
21
9
LATCH
25
25
12
11
48
DFF
24
25
CNT/DLY
Edge detect
Edge detect
Edge detect Delayed
Ripple Counter
PGen
107
107
206
19
205
20
161
13
160
13
116
8
116
8
ns
ns
ns
ns
tpd
tpd
tpd
tpd
tpd
tpd
tpd
241
45
241
60
175
32
175
44
125
22
125
31
20
177
115
36
20
177
115
37
14
121
83
14
121
83
9
10
78
57
18
ns
ns
ns
ns
Filter
77
57
17
Inverter Filter
Pipe Delay
25
26
Table 11: Programmable Delay Expected Typical Delays and Widths at T = 25 °C
Parameter
Description
Note
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V Unit
tw
tw
Pulse Width, 1 cell mode: (any) edge detect, edge detect output
Pulse Width, 2 cell mode: (any) edge detect, edge detect output
Pulse Width, 3 cell mode: (any) edge detect, edge detect output
Pulse Width, 4 cell mode: (any) edge detect, edge detect output
223
444
663
882
18
163
324
484
643
12
118
233
347
461
8
ns
ns
ns
ns
ns
tw
tw
time1
Delay, 1 cell
mode: (any) edge detect, edge detect output
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 11: Programmable Delay Expected Typical Delays and Widths at T = 25 °C (Continued)
Parameter
time1
Description
Delay, 2 cell
Delay, 3 cell
Delay, 4 cell
Delay, 1 cell
Delay, 2 cell
Delay, 3 cell
Delay, 4 cell
Note
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V Unit
mode: (any) edge detect, edge detect output
mode: (any) edge detect, edge detect output
mode: (any) edge detect, edge detect output
mode: both edge delay, edge detect output
mode: both edge delay, edge detect output
mode: both edge delay, edge detect output
mode: both edge delay, edge detect output
18
18
12
12
8
ns
ns
ns
ns
ns
ns
ns
time1
8
time1
18
12
8
time2
243
464
683
902
176
337
497
655
126
241
356
470
time2
time2
time2
Table 12: Typical Filter Rejection Pulse Width at T = 25 °C
Parameter
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
< 177 < 122 < 78
Unit
Filtered Pulse Width
ns
Table 13: Typical Counter/Delay Offset Measurements at T = 25 °C
Parameter
OSC Freq
25 MHz
OSC Power
auto
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
Power-On time
<0.04
<0.5
<500
4
<0.13
<0.5
<500
4
<0.13
<0.5
<500
4
Power-On time
2.048 MHz
2.048 kHz
25 MHz
auto
Power-On time
auto
frequency settling time
frequency settling time
frequency settling time
variable (CLK period)
variable (CLK period)
variable (CLK period)
auto
2.048 MHz
2.048 kHz
25 MHz
auto
0.3
0.4
0.4
auto
660
570
480
forced
forced
forced
0-40
0-0.5
0-488
0-40
0-0.5
0-488
0-40
0-0.5
0-488
2.048 MHz
2.048 kHz
25 MHz/
2.048 kHz
tpd (non-delayed edge)
either
35
14
10
ns
3.8 OSCILLATOR CHARACTERISTICS
Table 14: Oscillators Frequency Limits, VDD = 2.4 V to 5.5 V
Temperature Range
+25 °C
-40 °C to +85 °C
OSC
Minimum
Value, kHz
Maximum
Value, kHz
Minimum
Value, kHz
Maximum
Value, kHz
Error, %
Error, %
+2.00
-2.00
+2.00
-2.00
+2.00
-2.00
+3.03
-7.13
+1.63
-2.20
+3.60
-4.80
2.048 kHz OSC0
2.048 MHz OSC1
25 MHz OSC2
2.007
2007
2.089
2089
1.902
2.110
2003.017
23799.64
2081.296
25900.32
24500
25500
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
3.8.1 OSC Power-On Delay
Table 15: Oscillators Power-On Delay at T = 25 °C, OSC Power Setting: "Auto Power-On"
OSC2 25 MHz
Start with Delay
Power
OSC0 2.048 kHz
OSC1 2.048 MHz
OSC2 25 MHz
Supply
Range
(VDD) V
Typical
Maximum
Value, µs
Typical
Maximum
Value, ns
Typical
Maximum
Value, ns
Typical
Maximum
Value, ns
Value, µs
688.658
673.305
584.854
494.549
470.605
Value, ns
521.838
511.273
461.524
417.841
410.224
Value, ns
47.316
44.580
31.229
21.331
19.924
Value, ns
149.854
148.574
143.901
142.340
142.158
2.40
2.50
3.30
5.00
5.50
890.850
862.190
716.920
582.281
549.359
534.426
524.612
476.126
433.196
425.767
52.408
49.272
34.985
24.667
23.143
156.326
154.942
149.772
147.284
147.092
3.9 ACMP CHARACTERISTICS
Table 16: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter Description
Conditions
Note
Min
Typ
--
Max
Unit
V
Positive Input
Negative Input
0
0
VDD
VDD
ACMP Input Voltage
VACMP
Range
--
V
T = -40 °C to +85 °C
T = 25 °C
-6.364
--
3.709
3.425
2.61
mV
mV
mV
mV
ACMP Input Offset
ACMPxL, Vhys = 0 mV,
Gain = 1,
-5.853 -1.025
Voffset
T = -40 °C to +85 °C
T = 25 °C
-4.30
-2.74
--
Chopper ACMP Input Vref = 32 mV to 2048 mV
Offset
-0.79
1.37
ACMP Startup Time
when BG ON
ACMP Power-On delay,
--
--
--
--
91.02
µs
Minimalrequiredwaketime
for the "Wake and Sleep
function", for ACMPxL
tstart
T = -40 °C to +85 °C
ACMP Startup Time
when BG OFF
2797.95 µs
Gain = 1x
--
--
--
--
--
10
--
--
GΩ
MΩ
MΩ
MΩ
µs
Gain = 0.5x
Gain = 0.33x
Gain = 0.25x
1.627
1.626
1.625
2.593
Series Input
Resistance
Rsin
--
--
ACMPxL, Vref =1.024 V,
Gain = 1,
Overdrive = 100 mV
Low to High
High to Low
Low to High
3.647
--
--
2.829
2.808
5.127
5.143
µs
µs
Propagation Delay,
Response Time
PROP
ACMPxL,
Vref = 32 mV to 2048 mV,
Gain = 1,
High to Low
--
2.937
7.486
µs
Overdrive = 100 mV
G = 1
1
1
1
G = 0.5
G = 0.33
G = 0.25
0.496
0.331
0.248
0.5
0.504
0.337
0.253
G
Gain Error
0.334
0.25
Datasheet
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© 2021 Dialog Semiconductor
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
3.10 INTERNAL VREF CHARACTERISTICS
Table 17: Internal Vref Characteristics
Parameter Description
Conditions
Note
Min
Typ
Max
Unit
Vref
T = 25 °C
-0.2
--
0.2
%
Internal Vref
Accuracy
Accuracy at
and
VDD = 2.4 V to 5.5 V,
No loading
T = -40 °C to +85 °C
-0.7
--
0.7
%
Vref > 1216 mV
Loading
3.11 OUTPUT BUFFERS CHARACTERISTICS
Table 18: HD Buffer Electrical Characteristics at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter
Description
Conditions
Offset
Min
Typ
Max
Unit
VDDA = 5 V, VOUT = 0.5 V to
4 V, T = 25 °C
--
--
--
0.088
--
9.936
10.503
33.564
mV
mV
VOFFSET
Input Offset Voltage
VDDA = 5 V, VOUT = 0.5 V to
4 V, T = -40 °C to +85 °C
Offset Drift with
Temperature
VOUT = VDDA/2,
T = -40 °C to +85 °C
dVOFFSET/dt
1.033
µV/C
Output
VDDA = 5 V,
V
OUT = 2.048 V,
ΔVOUT(I)
Load Regulation
--
-0.146
0.718
mV
mV
mA
ILOAD = 0.5 mA to 2 mA,
T = 25 °C
VDDA = 2.5 V to 5 V,
V
ΔVOUT(U)
ISС
Line Regulation
--
--
0.803
--
3.781
25
OUT = 2.048 V, T = 25 °C
V
DDA = 2.4 V to 5.5 V,
Short Circuit Current
T = -40 °C to +85 °C
Shutdown Characteristics
RLOAD = 5 kΩ, T = 25 °C,
RLOAD = 5 kΩ, T = 25 °C
ton
toff
Buffer Turn-On Time
Buffer Turn-Off Time
--
--
--
42.583
--
µs
µs
0.076
Table 19: Vref0 Output Buffer at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter Description
Vref0 Buffer Output
Conditions
Note
Min
Typ
Max
Unit
T = 25 °C
Loading = 200 µA
-1
--
--
1
%
%
Accuracy,
Vref = 32 mV to
2048 mV, Buffer
Enabled
Loading = 1 mA
-5
5
Load Resistance = 1 MΩ
--
--
--
--
5
pF
pF
Vref0
Buffer
Accuracy
and
Load Resistance =
560 kΩ
10
Load Resistance =
100 kΩ
Loading
--
--
40
pF
Vref0 Buffer Output
Capacitance Loading
Load Resistance =
10 kΩ
--
--
--
--
--
--
80
pF
pF
pF
Load Resistance = 2 kΩ
120
150
Load Resistance = 1 kΩ,
Vref=32mV to1024mV
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
3.12 ANALOG TEMPERATURE SENSOR CHARACTERISTICS
Table 20: TS Output vs Temperature (Output Range 1)
VDD = 2.5 V
Typical, mV
VDD = 3.3 V
Typical, mV
VDD = 5.0 V
T, °C
Accuracy, %
±1.29
±1.31
±.1.33
±1.34
±1.34
±1.36
±1.39
±1.43
±1.48
±1.52
±1.58
±1.62
±1.67
±1.69
Accuracy, %
±1.28
±1.30
±1.32
±1.33
±1.34
±1.36
±1.37
±1.42
±1.46
±1.51
±1.55
±1.61
±1.65
±1.68
Typical, mV
998
Accuracy, %
±1.25
±1.28
±1.29
±1.31
±1.32
±1.33
±1.36
±1.40
±1.44
±1.48
±1.53
±1.59
±1.63
±1.66
-40
-30
-20
-10
0
1004
978
955
933
910
886
863
840
817
793
769
746
722
710
999
976
954
931
908
885
862
838
815
792
768
744
721
709
976
953
930
907
10
20
30
40
50
60
70
80
85
884
861
838
814
791
767
744
720
708
Table 21: TS Output vs Temperature (Output Range 2)
VDD = 2.5 V
T, °C
VDD = 3.3 V
VDD = 5.0 V
Typical, mV
1208
1181
1153
1126
1098
1070
1042
1014
986
Accuracy, %
±1.36
±1.37
±1.39
±1.42
±1.42
±1.44
±1.45
±1.49
±1.53
±1.58
±1.63
±1.68
±1.72
±1.76
Typical, mV
1206
1179
1151
1124
1096
1068
1040
1012
984
Accuracy, %
±1.35
±1.35
±1.37
±1.40
±1.40
±1.42
±1.44
±1.48
±1.52
±1.56
±1.62
±1.66
±1.71
±1.74
Typical, mV
1205
1178
1150
1123
1095
1067
1039
1011
983
Accuracy, %
±1.32
±1.33
±1.35
±1.38
±1.38
±1.41
±1.42
±1.46
±1.50
±1.54
±1.60
±1.64
±1.69
±1.71
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
85
957
956
955
929
927
926
900
898
898
872
870
869
857
855
855
Datasheet
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© 2021 Dialog Semiconductor
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
3.13 PROGRAMMABLE OPERATIONAL AMPLIFIER CHARACTERISTICS
Table 22: EC of OA, VDDA = 2.4 V to 5.5 V, VCM = VDDA/2, VOUT
≈
VDDA/2, RL = 100 kΩ to VDDA/2, CL = 50 pF, T = 25 °C
Parameter
Description
Conditions (Note 1)
Min
Typ
Max
Unit
Input Voltage Offset (without Customers Trimming, Included Factory Block Offset Trim)
VOFFSET
Input Offset Voltage
VCM = VDD/2
--
--
500
1
1000
5
µV
VCM = VDD/2,
T = -40 °C to +85 °C
µV/°C
Offset Drift with
Temperature
dVOFFSET/dt
VCM = GND,
T = -40 °C to +85 °C
--
1
5
µV/°C
Trimmed Input Offset (Customer Perspective after Using Digital Rheostats with Gain = 200x) (Note 2)
VDD = 3.3 V,
VCM = 0 V to VDD
VOFFSET
Input Offset Voltage
--
50
--
µV
Input Voltage Range
Input Common-Mode
Voltage Range
VDD
+ 0.2
VCMR
T = -40 °C to +85 °C
-0.2
80
--
110
90
95
90
V
GND + 0.8 V < VCM < VDD - 0.8 V, T
= -40 °C to +85 °C
--
--
--
--
dB
dB
dB
dB
Common-Mode
Rejection Ratio
CMRR
GND < VCM< GND+ 0.8 V or
VDD - 0.8 V < VCM < VDD
75
V
CM = VDD/2,
85
T = -40 °C to +85 °C
Power Supply Rejection
Ratio
PSRR
CS
VCM = GND,
T = -40 °C to +85 °C
80
Channel Separation
VDD = 5 V, f = 10 Hz
VDD = 5 V, f = 1 kHz
Input Current and Impedance
T = 25 °C
--
--
100
80
--
--
dB
dB
--
--
--
--
--
--
--
4
pA
pA
pA
pA
IB
Input Bias Current
Input Offset Current
T = +85 °C
125
T = 25 °C
1.804
32.864
IOFFSET
T = +85 °C
Common-Mode Input
Resistance
RCM
RDIFF
CCM
--
--
--
--
10^13
10^13
5
--
--
Ω
Ω
Differential Input
Resistance
Input Capacitance
Common-Mode
7
pF
pF
Input Capacitance
Differential
CDIFF
1.949
2.274
Open-Loop Gain
RLOAD = 1 MΩ,
GND + 0.1 V < VOUT < VDD - 0.1 V,
T = -40 °C to +85 °C
100
100
123.796
124.093
--
--
dB
dB
AOL
DC Open Loop Gain
RLOAD = 50 kΩ,
GND + 0.5 V < VOUT < VDD - 0.5 V
T = -40 °C to +85 °C
Output
Datasheet
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© 2021 Dialog Semiconductor
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 22: EC of OA, VDDA = 2.4 V to 5.5 V, VCM = VDDA/2, VOUT
≈
VDDA/2, RL = 100 kΩ to VDDA/2, CL = 50 pF, T = 25 °C
Parameter
Description
Conditions (Note 1)
Min
Typ
Max
Unit
RLOAD = 50 kΩ,
T = -40 °C to +85 °C
-6.7
--
--
mV
VOH
BW = 8.192 MHz,
RLOAD = 600 Ω,
-143
--
--
--
--
--
mV
mV
mV
T = -40 °C to +85 °C
Maximum Voltage
Swing
RLOAD = 50 kΩ,
T = -40 °C to +85 °C
4.8
101
VOL
BW = 8.192 MHz,
RLOAD = 600 Ω,
--
T = -40 °C to +85 °C
Linear Output Swing
Range
VOVR from Rail
RLOAD = 1 MΩ
GND +
100
VOSR
--
VDD - 100
mV
mA
mA
mA
mA
mA
mA
mA
BW = 128 kHz,
T = -40 °C to +85 °C
--
--
--
--
10.693
14.288
22.230
51.489
20.010
26.206
39.910
89.567
--
--
--
--
--
--
--
BW = 512 kHz,
T = -40 °C to +85 °C
ISC to GND
BW = 2.048 MHz,
T = -40 °C to +85 °C
BW = 8.192 MHz,
T = -40 °C to +85 °C
ISС
Short Circuit Current
BW = 128 kHz,
T = -40 °C to +85 °C
BW = 512 kHz,
T = -40 °C to +85 °C
ISC to VDD
BW = 2.048 MHz,
T = -40 °C to +85 °C
BW = 8.192 MHz,
T = -40 °C to +85 °C
--
--
mA
pF
CLOAD
Capacitive Load Drive
Supply Voltage
--
Power Supply
VDD
Guaranteed by PSRR Test
2.4
--
--
5.5
--
V
T = 25 °C,
VDDA = 2.5 V to 5.5 V
32.558
µA
Quiescent Current per
Amplifier,
BW = 128 kHz
T = -40 °C to +85 °C,
VDDA = 2.5 V to 5.5 V
--
--
--
--
--
--
--
32.160
87.576
--
--
--
--
--
--
--
µA
µA
µA
µA
µA
µA
µA
T = 25 °C,
VDDA = 2.5 V to 5.5 V
Quiescent Current per
Amplifier,
BW = 512 kHz
IQ
T = -40 °C to +85 °C,
VDDA = 2.5 V to 5.5 V
86.940
(including
charge pump
current
T = 25 °C,
VDDA = 2.5 V to 5.5 V
236.020
233.160
608.094
594.150
Quiescent Current per
Amplifier,
BW = 2.048 MHz
consumption)
T = -40 °C to +85 °C,
VDDA = 2.5 V to 5.5 V
T = 25 °C,
VDDA = 2.5 V to 5.5 V
Quiescent Current per
Amplifier,
BW = 8.192 MHz
T = -40 °C to +85 °C,
VDDA = 2.5 V to 5.5 V
Datasheet
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 22: EC of OA, VDDA = 2.4 V to 5.5 V, VCM = VDDA/2, VOUT
≈
VDDA/2, RL = 100 kΩ to VDDA/2, CL = 50 pF, T = 25 °C
Parameter
Description
Conditions (Note 1)
Min
Typ
Max
Unit
T = -40 °C to +85 °C,
VDDA = 2.5 V to 5.5 V
Full Shutdown
--
103.352
--
nA
IQ
Partial Shutdown
(Note 3),
BW = 128 kHz
(including
charge pump
current
--
--
T = 25 °C
14.916
14.916
--
--
µA
µA
consumption) Partial Shutdown
(Note 3),
T = 25 °C
BW = 8.192 MHz
Frequency Response
BW = 128 kHz
BW = 512 kHz
BW = 2.048 MHz
BW = 8.192 MHz
90
128
512
166
666
kHz
kHz
kHz
kHz
RLOAD = 10 kΩ,
CLOAD = 20 pF,
G = +1 V/V
358
Gain Bandwidth Product
GBW
PM
1434
5734
2048
8192
2662
10650
G = +1 V/V,
BW = 128 kHz → 8.192 MHz; RLOAD
Phase Margin
Slew Rate
44
70
--
degree
= 10 kΩ,
CLOAD = 20 pF
BW = 128 kHz,
T = -40 °C to +85 °C
--
--
--
--
--
0.091
0.380
1.834
6.310
500
--
--
--
--
--
V/µs
V/µs
V/µs
V/µs
µs
BW = 512 kHz,
T = -40 °C to +85 °C
RLOAD =50kΩ,
CLOAD = 85 pF
SR
BW = 2.048 MHz,
T = -40 °C to +85 °C
BW = 8.192 MHz,
T = -40 °C to +85 °C
Overload Recovery
Time
T = -40 °C to +85 °C
LOAD = 50 kΩ
tOR
R
Noise
f = 1 kHz,
BW = 128 kHz
--
--
--
--
1.3
0.2
0.7
0.1
--
--
--
--
%
%
%
AV = 1,
f = 1 kHz,
BW = 512 kHz
RLOAD = 50 kΩ,
Total Harmonic
Distortion
THD
VOUT(PP)
VDD/2
=
f = 1 kHz,
BW = 2.048 MHz
f = 1 kHz,
BW = 8.192 MHz
%
en
Input Voltage Noise
f = 0.1 to 10 Hz
f = 1 kHz
--
--
--
--
--
4
--
--
--
--
--
µVpp
BW = 128 kHz
BW = 512 kHz
BW = 2.048 MHz
BW = 8.192 MHz
130
125
120
75
nV/
Input Voltage Noise
Density
Vn
Hz
fA/
Input Current Noise
Density
In
f = 1 kHz
--
1
--
Hz
Shutdown Characteristics
Datasheet
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Revision 2.4
32 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 22: EC of OA, VDDA = 2.4 V to 5.5 V, VCM = VDDA/2, VOUT
≈
VDDA/2, RL = 100 kΩ to VDDA/2, CL = 50 pF, T = 25 °C
Parameter
Description
Conditions (Note 1)
Min
Typ
Max
Unit
VCM = VDDA/2,
RL = 50 kΩ
BW = 8.192
MHz,
--
2.121
5.363
µs
T = -40 °C to
+85 °C
VDDA > VCM
(VDDA - 1.3)
>
--
--
2.145
5.330
µs
µs
ton
Amplifier Turn-On Time
Amplifier Turn-Off Time
VCM = VDDA/2,
RL = 50 kΩ
25.458
43.158
BW = 128 kHz,
T = -40 °C to
+85 °C
VDDA > VCM
(VDDA - 1.3)
>
--
--
35.134
0.671
70.602
1.015
µs
µs
toff
--
Comparator Mode
VID = 100 mV, BW = 128 kHz
VID = 100 mV, BW = 512 kHz
--
--
15
--
--
µs
µs
3.5
Propagation Delay
Output High to Low
VID = 100 mV,
BW = 2.048 MHz
tPHL
--
--
1.2
4.2
--
--
µs
µs
VID = 100 mV,
BW = 8.192 MHz
VID = 100 mV, BW = 128 kHz
VID = 100 mV, BW = 512 kHz
--
--
14
--
--
µs
µs
3.5
Propagation Delay
Output Low to High
VID = 100 mV,
BW = 2.048 MHz
tPLH
--
--
1.2
4.2
--
--
µs
µs
V
ID = 100 mV,
BW = 8.192 MHz
3 Op Amp Instrumentation Amplifier Mode
Mismatch Between
Internal Resistors (R1,
R2, R3, R4)
RINT_TL
--
--
0.15
%
Note 1 AGND
= GND, unless otherwise noted
Note 2 Equivalent offset voltage of the amplifier after user’s trim using digital rheostat. Gain of the amplifier is G=200 and the
zero output voltage level Vzero = VDD/2 (See Section 10.2.1)
Note 3 Op amps analog supporting blocks are always turned on.
3.14 100K DIGITAL RHEOSTAT CHARACTERISTICS
Table 23: 100K Digital Rheostat EC at VA=VDD, VB=GND, T=-40°C to +85°C, VDD= 2.4V to 5.5V Unless Otherwise Noted
Parameter
Description
Conditions
Min
Typ
Max
Unit
Rheostat Pin Voltage
Range
Voltage between any (Aor B)
pins and AGND
VDR
AGND
--
VDDA
V
Digital Rheostat
Resistance
Full resistance with all
switches open (Note 1)
RDR
80
44.381
--
100
--
120
110
kΩ
Ω
Minimal Rheostat
Resistance
RDR_MIN
Code = 0x00
Mismatch between
rheostats
RMATCH
Code = 0x3FF, T = 25 °C
0.043
--
%
Number of taps
1024
Datasheet
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Revision 2.4
33 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 23: 100K Digital Rheostat EC at VA=VDD, VB=GND, T=-40°C to +85°C, VDD= 2.4V to 5.5V Unless Otherwise Noted
Parameter
Description
Conditions
Min
Typ
Max
Unit
Frequency applied on one
side of resistor chain and
-3 dB frequency measured at
the other side with full 100
KΩ, assume no additional
load
BWDTDR
Digital Rheostat Bandwidth
Step Resistance
--
50
--
kHz
RS
--
--
98.266
--
--
2
Ω
Max current through
Rheostat
IDR_MAX
T = 25 °C
mA
nV/√
Hz
ESW_N
Resistor Noise Voltage
RAB = 25 kΩ, f = 1 kHz
--
--
30
--
--
Chopper Comparator
Switching Frequency
fChACMP
30
kHz
µV
Chopper comparator offset
when Auto-Trim process is
active
VCh_offset
--
0
100
--
300
25
Counter Frequency
independent from the
Rheostat
The counter frequency is
determined by user selection
fDR_CLK
MHz
VA = 5 V, VB = 0 V, ±1 LSB
error band, Auto-Trim mode
--
--
--
--
10
1
kHz
kHz
Rheostat Switch Speed
(Note 2)
fDR_SWCH
VA = 5 V, VB = 0 V, ±1 LSB
error band, regular mode
Maximum Capacitance of
A, B pins Measured to
AGND
All switches are ON,
f = 200 kHz
СDR
--
33.461
--
pF
Includingactivechargepump
current consumption
ILKG
Leakage Current
Zero-Scale Error
--
--
--
--
--
--
--
--
1000
1.203
±1
nA
Error
ZScale
Code = 0x00
LSB
LSB
LSB
Integral
Non-linearity
INL
Differential
Non-linearity
DNL
±1
RLOAD <12.5 kΩ
--
--
--
--
240
120
60
--
--
--
--
kHz
kHz
kHz
kHz
RLOAD = 12.5 kΩ to 25 kΩ
RLOAD = 25 kΩ to 50 kΩ
RLOAD = 50 kΩ to 100 kΩ
Bandwidth -3 dB
(Load = 30 pF)
BWDTCAP
αR(T)
30
Resistance Temperature
Coefficient
ppm/
°C
VAB = const,
--
--
110
Potentiometer Mode
Integral
Non-linearity in
Potentiometer Mode
INLPOT
--
--
--
--
±1
±1
LSB
LSB
Differential
Non-linearity in
Potentiometer Mode
DNLPOT
Note 1 User can calculate actual Digital Rheostat value using calibration data from NVM (see Section 12.2).
Note 2 Includes internal timing. External circuit should be counted separately.
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
3.15 ANALOG SWITCHES CHARACTERISTICS
Table 24: Analog Switch0/Voltage Regulator EС at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter
Description
Conditions
Min
Typ
Max
Unit
Maximum Voltage At Pins
Voltage between any Analog
Switch pin to AGND
VAS
0
--
VDD + 0.3
V
Maximum Switching
Frequency
fMAX
RL = 50 kΩ
3
--
--
--
MHz
Ω
VDD = 3.3 V,
VIN < 1.2 V,
--
29.621
N-ch FET, T = 25 °C
RON
ON Resistance
VDD = 3.3 V,
VDD - 1.2 < VIN < VDD
P-ch FET, T = 25 °C
,
--
--
3.857
--
7.456
0.1
Ω
Switch OFF; from IN to OUT
VA = VDD or VB = VDD
IPWROFF
IPWRON
ISW_MAX
OFF Leakage Current
--
--
--
nA
µA
mA
ON Leakage Current
(Including Charge Pump
Current Consumption)
Switch ON,
quiescent current
consumption
--
Maximum ON-state Switch VA = VDD, load connected to
Current ground, VAB= 0.4 V
100
--
Table 25: Analog Switch1/Current Sink EС at T = -40 °C to +85 °C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter
Description
Conditions
Min
Typ
Max
Unit
Maximum Voltage At Pins
Voltage between any Analog
Switch pin to AGND
VAS
0
--
V
DD + 0.3
V
Maximum Switching
Frequency
fMAX
RL = 50 kΩ
3
--
--
--
MHz
Ω
V
DD = 3.3 V,
VIN < 1.2 V,
--
0.809
N-ch FET, T = 25 °C
RON
ON Resistance
VDD = 3.3 V,
VDD - 1.2 < VIN < VDD
P-ch FET, T = 25 °C
,
--
--
95.5
--
--
8.073
0.1
Ω
Switch OFF; from IN to OUT,
VA = VDD or VB = VDD
IPWROFF
IPWRON
ISW_MAX
OFF Leakage Current
nA
µA
mA
ON Leakage Current
(including charge pump
current consumption)
Switch ON
quiescent current
consumption
--
--
Maximum ON-state Switch VA = VDD, load connected to
100
--
--
Current
ground, VAB= 0.4 V
Datasheet
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
4
User Programmability
The SLG47004 is a user programmable device with Multiple-Time-Programmable (MTP) memory elements that are able to
configure the connection matrix and macrocells. A programming development kit allows the user the ability to create initial
devices. Once the design is finalized, the programming code (.gpx file) is forwarded to Dialog Semiconductor to integrate into a
production process.
Product
Definition
E-mail Product Idea, Definition, Drawing or
Customer creates their own design in
Schematic to
GreenPAK Designer
CMBUGreenPAK@diasemi.com
Dialog Semiconductor Applications
Engineer will review design specifications
with customer
Customer verifies GreenPAK in system
design
GreenPAK Design
approved
Samples, Design and Characterization
Report send to customer
GreenPAK Design
approved
Customers verifies GreenPAK design
GreenPAK Design
Approved in system test
Custom GreenPAK part enters production
Figure 2: Steps to Create a Custom GreenPAK Device
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
5
IO Pins
The SLG47004 has a total of 7 GPIO Pins which can function as either a user-defined Input or Output, as well as serve as a
special function (such as outputting the voltage reference) and 1 GPI Pin.
5.1 GPIO PINS
IO0, IO1, IO2, IO3, IO4, IO5, and IO6 serve as General Purpose IO Pins.
5.2 GPI PINS
I0 serve as General Purpose Input Pin.
5.3 PULL-UP/DOWN RESISTORS
All IO Pins have the option of user-selectable resistors that can be connected to the pin structure. The selectable values on these
resistors are 10 kΩ, 100 kΩ, and 1 MΩ. The internal resistors can be configured as either Pull-up or Pull-downs.
5.4 FAST PULL-UP/DOWN DURING POWER-UP
During power-up, IO Pull-up/down resistance will switch to 2.6 kΩ initially and then it will switch to normal setting value. This
function is enabled by register [1207].
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5.5 I2C MODE IO STRUCTURE
5.5.1 I2C Mode Structure (for SCL and SDA)
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1
01: Reserved
10: Low Voltage Digital In mode 1, lv_en = 1
11: Reserved
VDD
PAD
Non-Schmitt
Trigger Input
WOSMT_EN
Digital IN
VDD
Low Voltage
Input 1
LV_EN
I2C SDA (SCL) Signal
not available for direct user control
Figure 3: IO with I2C Mode IO Structure Diagram
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5.6 MATRIX OE IO STRUCTURE
Non-Schmitt
Trigger Input
Input Mode registers [1153:1152]
00: Digital In without Schmitt Trigger, wosmt_en = 1
WOSMT_EN
01: Digital In with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital In mode, lv_en = 1
11: analog IO mode
Schmitt
Trigger Input
Digital IN
Output Mode [1:0]
00: Push-Pull 1x mode, pp1x_en = 1
SMT_EN
01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1
10: NMOS 1x Open-Drain mode, od1x_en = 1
11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1
Low Voltage
Input
Note 1: Digital Out and OE are Matrix Output, Digital In is Matrix Input.
Note 2: Can be varied over PVT, for reference only.
LV_EN
Analog IO
Floating
s0
s1
s2
s3
VDD
s1
s0
172 Ω
(Note 2)
900 kΩ
Res_sel
[1:0]
90 kΩ
10 kΩ
VDD
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
Digital OUT
Digital OUT
OE
OE
OD1x_EN
PP1x_EN
VDD
PAD
VDD
Digital OUT
Digital OUT
OE
OE
OD2x_EN
PP2x_EN
Figure 4: Matrix OE IO Structure Diagram
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5.7 GPI STRUCTURE
5.7.1 GPI Structure (for I0)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1, OE=0
01: Digital In with Schmitt Trigger, smt_en = 1, OE = 0
10: Low Voltage Digital In mode, lv_en = 1, OE = 0
11: Reserved
WOSMT_EN
SMT_EN
OE
OE
Schmitt
Trigger Input
Digital IN
Note 1: OE cannot be selected by user.
Note 2: OE is Matrix output, Digital In is Matrix input.
Low Voltage
Input
LV_EN
OE
Floating
PAD
s0
s1
s2
s3
VDD
s1
s0
900 kΩ
Res_sel
[1:0]
90 kΩ
10 kΩ
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
Figure 5: IO0 GPI Structure Diagram
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5.8 IO PINS TYPICAL PERFORMANCE
Figure 6: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C
80
70
60
50
40
30
20
10
0
Open Drain 1x @ VDD = 5 V
Open Drain 1x @ VDD = 3.3 V
Open Drain 1x @ VDD = 2.5 V
Push-Pull 1x @ VDD = 5 V
Push-Pull 1x @ VDD = 3.3 V
Push-Pull 1x @ VDD = 2.5 V
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
VOL (V)
Figure 7: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range
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30
Open Drain 1x @ VDD = 5 V
25
Open Drain 1x @ VDD = 3.3 V
Open Drain 1x @ VDD = 2.5 V
Push-Pull 1x @ VDD = 5 V
20
15
10
5
Push-Pull 1x @ VDD = 3.3 V
Push-Pull 1x @ VDD = 2.5 V
0
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C
140
130
120
110
100
90
Open Drain 2x @ VDD = 5 V
Open Drain 2x @ VDD = 3.3 V
Open Drain 2x @ VDD = 2.5 V
Push-Pull 2x @ VDD = 5 V
Push-Pull 2x @ VDD = 3.3 V
Push-Pull 2x @ VDD = 2.5 V
80
70
60
50
40
30
20
10
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
VOL (V)
Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range
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with In-System Programmability and Advanced Analog Features
50
45
Open Drain 2x @ VDD = 5 V
Open Drain 2x @ VDD = 3.3 V
40
Open Drain 2x @ VDD = 2.5 V
Push-Pull 2x @ VDD = 5 V
35
Push-Pull 2x @ VDD = 3.3 V
Push-Pull 2x @ VDD = 2.5 V
30
25
20
15
10
5
0
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C
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with In-System Programmability and Advanced Analog Features
6
Connection Matrix
The Connection Matrix in the SLG47004 is used to create an internal routing for internal functional macrocells of the device
once it is programmed. The output of each functional macrocell within the SLG47004 has a specific digital bit code assigned to
it, that is either set to active "High" or inactive "Low", based on the design that is created. Once the 2048 register bits within the
SLG47004 are programmed, a fully custom circuit will be created.
The Connection Matrix has 64 inputs and 99 outputs. Each of the 64 inputs to the Connection Matrix is hard-wired to the digital
output of a particular source macrocell, including IOs, LUTs, analog comparators, other digital resources, such as VDD and GND.
The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines.
For a complete list of the SLG47004’s register table, see Section 21
.
Matrix Input Signal
N
Functions
GND
0
1
2
3
LUT2_0/DFF0 output
LUT2_1/DFF1 output
LUT2_2/DFF2 output
VDD
VDD
62
63
Matrix Inputs
N
0
1
2
99
Registers
registers [5:0]
registers [11:6]
registers [17:12]
registers [599:594]
Matrix OUT: IN0 of
LUT2_0 or Clock
Input of DFF0
Matrix OUT: IN1 of
LUT2_0 or Data
Input of DFF0
Matrix Out: IN0 of
LUT2_1 or Clock
Input of DFF1
Function
OP Vref ENABLE
Matrix Outputs
Figure 11: Connection Matrix
Function
Connection Matrix
IO13
IO12
LUT
IO12
IO13
IO14
LUT
IO14
Figure 12: Connection Matrix Example
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GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
6.1 MATRIX INPUT TABLE
Table 26: Matrix Input Table
Matrix Decode
Matrix Input
Matrix Input Signal Function
Number
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
GND
1
LUT2_0/DFF0 output
LUT2_1/DFF1 output
LUT2_2/DFF2 output
LUT2_3/PGen output
LUT3_0/DFF3 output
LUT3_1/DFF4 output
LUT3_2/DFF5 output
LUT3_3/DFF6 output
LUT3_4/DFF7 output
LUT3_5/DFF8 output
LUT3_6/DFF9 output
CNT_DLY0 output
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
MLT0_LUT4_1/DFF17_OUT
CNT_DLY1 output
MLT1_LUT3_7/DFF11_OUT
CNT_DLY2 output
MLT2_LUT3_8/DFF12_OUT
CNT_DLY3 output
MLT3_LUT3_9/DFF13_OUT
CNT_DLY4 output
MLT4_LUT3_10/DFF14_OUT
CNT_DLY5 output
MLT5_LUT3_11/DFF15_OUT
CNT_DLY6 output
MLT6_LUT3_12/DFF16_OUT
LUT3_13/Pipe Delay/RippleCNT_out0
Pipe Delay/RippleCNT_out1
Pipe Delay/RippleCNT_out2
LUT4_0/DFF10 output
Programmable Delay Edge Detect Output
Edge Detect Filter Output
I2C_virtual_0 Input
I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
I2C_virtual_5 Input
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 26: Matrix Input Table(Continued)
Matrix Decode
Matrix Input
Matrix Input Signal Function
Number
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
I2C_virtual_6 Input
I2C_virtual_7 Input
RH0 Idle/Active
RH1 Idle/Active
Output of Op Amp0 in ACMP mode
Output of Op Amp1 in ACMP mode
IO0 Digital Input
IO1 Digital Input
IO2 Digital Input
IO3 Digital Input
IO4 Digital Input
IO5 Digital Input
IO6 Digital Input
I0 Digital Input
Oscillator0 output 0
Oscillator1 output 0
Oscillator2 output
Chopper ACMP Out
ACMP0 Output (low speed)
ACMP1 Output (low speed)
Oscillator0 output 1
Oscillator1 output 1
POR OUT
VDD
VDD
VDD
6.2 MATRIX OUTPUT TABLE
Table 27: Matrix Output Table
Register Bit
Address
Matrix Output
Number
Matrix Output Signal Function
[5:0]
IN0 of LUT2_0 or Clock Input of DFF0
IN1 of LUT2_0 or Data Input of DFF0
IN0 of LUT2_1 or Clock Input of DFF1
IN1 of LUT2_1 or Data Input of DFF1
IN0 of LUT2_2 or Clock Input of DFF2
IN1 of LUT2_2 or Data Input of DFF2
IN0 of LUT2_3 or Clock Input of PGen
IN1 of LUT2_3 or nRST of PGen
0
1
2
3
4
5
6
7
8
[11:6]
[17:12]
[23:18]
[29:24]
[35:30]
[41:36]
[47:42]
[53:48]
IN0 of LUT3_0 or CLK Input of DFF3
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 27: Matrix Output Table(Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
[59:54]
[65:60]
IN1 of LUT3_0 or Data of DFF3
9
IN2 of LUT3_0 or nRST (nSET) of DFF3
IN0 of LUT3_1 or CLK Input of DFF4
IN1 of LUT3_1 or Data of DFF4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
[71:66]
[77:72]
[83:78]
IN2 of LUT3_1 or nRST (nSET) of DFF4
IN0 of LUT3_2 or CLK Input of DFF5
IN1 of LUT3_2 or Data of DFF5
[89:84]
[95:90]
[101:96]
[107:102]
[113:108]
[119:114]
[125:120]
[131:126]
[137:132]
[143:138]
[149:144]
[155:150]
[161:156]
[167:162]
[173:168]
IN2 of LUT3_2 or nRST(nSET) of DFF5
IN0 of LUT3_3 or CLK Input of DFF6
IN1 of LUT3_3 or Data of DFF6
IN2 of LUT3_3 or nRST (nSET) of DFF6
IN0 of LUT3_4 or CLK Input of DFF7
IN1 of LUT3_4 or Data of DFF7
IN2 of LUT3_4 or nRST (nSET) of DFF7
IN0 of LUT3_5 or CLK Input of DFF8
IN1 of LUT3_5 or Data of DFF8
IN2 of LUT3_5 or nRST (nSET) of DFF8
IN0 of LUT3_6 or CLK Input of DFF9
IN1 of LUT3_6 or CLK Input of DFF9
IN2 of LUT3_6 or nRST (nSET) of DFF9
IN0 of LUT3_7 or CLK Input of DFF11
Delay1 Input (or Counter1 nRST Input)
[179:174]
[185:180]
[191:186]
[197:192]
[203:198]
[209:204]
[215:210]
[221:216]
[227:222]
[233:228]
[239:234]
IN1 of LUT3_7 or nRST (nSET) of DFF11
Delay1 Input (or Counter1 nRST Input)
30
31
32
33
34
35
36
37
38
39
IN2 of LUT3_7 or Data of DFF11
Delay1 Input (or Counter1 nRST Input)
IN0 of LUT3_8 or CLK Input of DFF12
Delay2 Input (or Counter2 nRST Input)
IN1 of LUT3_8 or nRST (nSET) of DFF12
Delay2 Input (or Counter2 nRST Input)
IN2 of LUT3_8 or Data of DFF12
Delay2 Input (or Counter2 nRST Input)
IN0 of LUT3_9 or CLK Input of DFF13
Delay3 Input (or Counter3 nRST Input)
IN1 of LUT3_9 or nRST (nSET) of DFF13
Delay3 Input (or Counter3 nRST Input)
IN2 of LUT3_9 or Data of DFF13
Delay3 Input (or Counter3 nRST Input)
IN0 of LUT3_10 or CLK Input of DFF14
Delay4 Input (or Counter4 nRST Input)
IN1 of LUT3_10 or nRST (nSET) of DFF14
Delay4 Input (or Counter4 nRST Input)
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 27: Matrix Output Table(Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
IN2 of LUT3_10 or Data of DFF14
[245:240]
40
41
42
43
44
45
46
Delay4 Input (or Counter4 nRST Input)
IN0 of LUT3_11 or CLK Input of DFF15
[251:246]
Delay5 Input (or Counter5 nRST Input)
IN1 of LUT3_11 or nRST (nSET) of DFF15
[257:252]
Delay5 Input (or Counter5 nRST Input)
IN2 of LUT3_11 or nRST (nSET) of DFF15
[263:258]
Delay5 Input (or Counter5 nRST Input)
IN0 of LUT3_12 or CLK Input of DFF16
[269:264]
Delay6 Input (or Counter6 nRST Input)
IN1 of LUT3_12 or nRST (nSET) of DFF16
[275:270]
Delay6 Input (or Counter6 nRST Input)
IN2 of LUT3_12 or Data of DFF16
[281:276]
Delay6 Input (or Counter6 nRST Input)
[287:282]
[293:288]
[299:294]
[305:300]
[311:306]
[317:312]
[323:318]
IN0 of LUT3_13 or Input of Pipe Delay or UP signal of RIPP CNT
IN1 of LUT3_13 or nRST of Pipe Delay or nSet of RIPP CNT
IN2 of LUT3_13 or CLK of Pipe Delay_RIPP CNT
IN0 of LUT4_0 or CLK of DFF10
47
48
49
50
51
52
53
54
IN1 of LUT4_0 or Data of DFF10
IN2 of LUT4_0 or nRST (nSET) of DFF10
IN3 of LUT4_0
IN0 of LUT4_1 or CLK Input of DFF17
Delay0 Input (or Counter0 nRST Input)
[329:324]
[335:330]
IN1 of LUT4_1 or nRST of DFF17
Delay0 Input (or Counter0 nRST Input)
Delay/Counter0 External CLK source
55
56
IN2 of LUT4_1 or nSet of DFF17
Delay0 Input (or Counter0 nRST Input)
Delay/Counter0 External CLK source
KEEP Input of FSM0
[341:336]
IN3 of LUT4_1 or Data of DFF17
Delay0 Input (or Counter0 nRST Input)
UP Input of FSM0
57
[347:342]
[353:348]
[359:354]
[365:360]
[371:366]
[377:372]
[383:378]
[389:384]
[395:390]
[401:396]
[407:402]
[413:408]
Programmable delay/edge detect input
Filter/Edge detect input
IO0 DOUT
58
59
60
61
62
63
64
65
66
67
68
IO0 DOUT OE
IO1 DOUT
IO1 DOUT OE
IO2 DOUT
IO2 DOUT OE
IO3 DOUT
IO3 DOUT OE
IO4 DOUT
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 27: Matrix Output Table(Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
[419:414]
[425:420]
[431:426]
[437:432]
[443:438]
[449:444]
[455:450]
[461:456]
[467:462]
[473:468]
[479:474]
[485:480]
[491:486]
[497:492]
[503:498]
[509:504]
[515:510]
[521:516]
[527:522]
[533:528]
[539:534]
[545:540]
[551:546]
[557:552]
[563:558]
[569:564]
[575:570]
[581:576]
[587:582]
[593:588]
[599:594]
IO4 DOUT OE
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
IO5 DOUT
IO5 DOUT OE
IO6 DOUT
IO6 DOUT OE
Set of PT0 block
Clock of PT0 block
Reload of PT0 block
Program of PT0 block
Up/Down of PT0 block
Set of PT1 block
Clock of PT1 block
Reload of PT1 block
Program of PT1 block
Up/Down of PT1 block
FIFO Reset of PT blocks
Power Up of Chopper ACMP
Rheostats Charge Pump Enable
ASW0 enable/Half bridge Enable
ASW1 enable/Half bridge data
ACMP0 Power Up
ACMP1 Power Up
Oscillator0 Enable
Oscillator1 Enable
Oscillator2 Enable
VrefO, Temp sensor, VrefO Power Up
HDBUF Enable
Op Amp0 Power Up
Op Amp1 Power Up
Op Amp2 Power Up
Op amps Vref Enable
Note 1 For each Address, the two most significant bits are unused.
6.3 CONNECTION MATRIX VIRTUAL INPUTS
As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macrocells on the device. Eight
of the Connection Matrix inputs have the special characteristic that the state of these signal lines comes from a corresponding
data bit written as a register value via I2C. This gives the user the ability to write data via the serial channel, and have this
information translated into signals that can be driven into the Connection Matrix and from the Connection Matrix to the digital
inputs of other macrocells on the device. The I2C address for reading and writing these register values is at 0x7C (124).
An I2C write command to these register bits will set the signal values going into the Connection Matrix to the desired state. A
read command to these register bits will read either the original data values coming from the NVM memory bits (that were
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loaded during the initial device startup), or the values from a previous write command (if that has happened).
See Table 28.
Table 28: Connection Matrix Virtual Inputs
Matrix Input
Number
Register Bit
Addresses (d)
Matrix Input Signal Function
32
33
34
35
36
37
38
39
I2C_virtual_0 Input
I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
I2C_virtual_5 Input
I2C_virtual_6 Input
I2C_virtual_7 Input
[992]
[993]
[994]
[995]
[996]
[997]
[998]
[999]
6.4 CONNECTION MATRIX VIRTUAL OUTPUTS
The digital outputs of the various macrocells are routed to the Connection Matrix to enable interconnections to the inputs of other
macrocells in the device. At the same time, it is possible to read the state of each of the macrocell outputs as a register value via
I2C. This option, called Connection Matrix Virtual Outputs, allows the user to remotely read the values of each macrocell output.
The I2C addresses for reading these register values are bytes 0xC4 (196) to 0xCA (202). Write commands to these same register
values will be ignored (with the exception of the Virtual Input register bits at byte 0x7C (124)).
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7
Combination Function Macrocells
The SLG47004 has 13 combination function macrocells that can serve as more than one logic or timing function. In each case,
they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be
implemented in these macrocells:
Three macrocells that can serve as either 2-bit LUT or as D Flip-Flop
Seven macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input
One macrocell that can serve as either 3-bit LUT or as Pipe Delay/Ripple Counter
One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGen)
One macrocell that can serve as either 4-bit LUT or as D Flip-Flop with Set/Reset Input
Inputs/Outputs for the 13 combination function macrocells are configured from the connection matrix with specific logic functions
being defined by the state of configuration bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user-defined
function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
7.1 2-BIT LUT OR D FLIP-FLOP MACROCELLS
There is one macrocell that can serve as either 2-bit LUT or as D Flip-Flop. When used to implement LUT functions, the 2-bit
LUT takes in two input signals from the connection matrix and produces a single output, which goes back into the connection
matrix. When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and
clock (CLK) inputs for the Flip-Flop, with the output going back to the connection matrix.
The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:
DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change.
LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is
High).
register [1483] DFF or LATCH Select
IN1
register [1482] Output Select (Q or nQ)
S0
From Connection Matrix Output [1]
register [1481] DFF Initial Polarity Select
OUT
2-bit LUT0
0: 2-bit LUT0 IN1
1: DFF0 Data
S1
IN0
LUT Truth
Table
To Connection Matrix
Input [1]
S0
S1
4-bits NVM
registers [1483:1480]
0: 2-bit LUT0 Out
1: DFF0 Out
DFF/Latch
Registers
D
S0
S1
From Connection Matrix Output [0]
Q/nQ
DFF0
0: 2-bit LUT0 IN0
1: DFF0 CLK
CLK
1-bit NVM
register [1492]
Figure 13: 2-bit LUT0 or DFF0
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register [1487] DFF or LATCH Select
register [1486] Output Select (Q or nQ)
register [1485] DFF Initial Polarity Select
IN1
S0
From Connection Matrix Output [3]
OUT
2-bit LUT1
0: 2-bit LUT1 IN1
1: DFF1 Data
S1
IN0
LUT Truth
Table
To Connection Matrix
S0
Input [2]
4-bits NVM
registers [1487:1484]
S1
0: 2-bit LUT1 Out
1: DFF1 Out
DFF/Latch
Registers
D
S0
S1
From Connection Matrix Output [2]
Q/nQ
DFF1
0: 2-bit LUT1 IN0
1: DFF1 CLK
CLK
1-bit NVM
register [1493]
Figure 14: 2-bit LUT1 or DFF1
register [1491] DFF or LATCH Select
register [1490] Output Select (Q or nQ)
register [1489] DFF Initial Polarity Select
IN1
S0
S1
From Connection Matrix Output [5]
OUT
2-bit LUT2
0: 2-bit LUT2 IN1
1: DFF2 Data
IN0
LUT Truth
Table
To Connection Matrix
S0
Input [3]
4-bits NVM
registers [1491:1488]
S1
0: 2-bit LUT2 Out
1: DFF2 Out
DFF/Latch
Registers
D
S0
S1
From Connection Matrix Output [4]
Q/nQ
DFF2
0: 2-bit LUT2 IN0
1: DFF2 CLK
CLK
1-bit NVM
register [1494]
Figure 15: 2-bit LUT2 or DFF2
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7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT
Table 29: 2-bit LUT0 Truth Table
IN1
0
IN0
0
OUT
register [1480]
register [1481]
register [1482]
register [1483]
LSB
0
1
1
0
1
1
MSB
Table 30: 2-bit LUT1 Truth Table
IN1
0
IN0
0
OUT
register [1484]
register [1485]
register [1486]
register [1487]
LSB
0
1
1
0
1
1
MSB
Table 31: 2-bit LUT2 Truth Table
IN1
0
IN0
0
OUT
register [1488]
register [1489]
register [1490]
register [1491]
LSB
0
1
1
0
1
1
MSB
This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-Bit LUT0 is defined by registers [1483:1480]
2-Bit LUT1 is defined by registers [1487:1484]
2-Bit LUT2 is defined by registers [1491:1488]
Table 32 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the 2-bit LUT logic cells.
Table 32: 2-bit LUT Standard Digital Functions
Function
AND-2
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-2
OR-2
NOR-2
XOR-2
XNOR-2
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7.1.2 Initial Polarity Operations
VDD
Data
Clock
POR
Initial Polarity: High
Q with nReset (Case 1)
Initial Polarity: Low
Q with nReset (Case 1)
Figure 16: DFF Polarity Operations
7.2 2-BIT LUT OR PROGRAMMABLE PATTERN GENERATOR
The SLG47004 has one combination function macrocell that can serve as a logic or a timing function. This macrocell can serve
as a Look Up Table (LUT), or a Programmable Pattern Generator (PGen).
When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection matrix and produces a
single output, which goes back into the connection matrix. When used as a LUT to implement combinatorial logic functions, the
outputs of the LUT can be configured to any user defined function, including the following standard digital logic devices (AND,
NAND, OR, NOR, XOR, XNOR). The user can also define the combinatorial relationship between inputs and outputs to be any
selectable function.
It is possible to define the RST level for the PGen macrocell. There are both high level reset (RST) and a low level reset (nRST)
options available, which are selected by register [1517]. When operating as the Programmable Pattern Generator, the output of
the macrocell will clock out a sequence of two to sixteen bits that are user selectable in their bit values, and user selectable in
the number of bits (up to sixteen) that are output before the pattern repeats.
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From Connection Matrix Output [6]
From Connection Matrix Output [7]
In0
In1
OUT
2-bit LUT3
LUT Truth
Table
To Connection Matrix Input [4]
S0
S1
0: 2-bit LUT3 OUT
1: PGen OUT
registers [1515:1512]
Pattern
size
nRST
CLK
PGen
OUT
PGen
Data
register [1516]
registers [1511:1496]
Figure 17: 2-bit LUT3 or PGen
VDD
t
t
nRST
CLK
OUT
1
2
6
8
16 17
3
5
7
0
4
9
10 11
14 15
12 13
t
D7
D6
D5
D10
D8
D4
D3
D2
D1
D15
D0
D9
D0
D15
D14
D13
D12
D11
D0
t
Figure 18: PGen Timing Diagram
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7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT
Table 33: 2-bit LUT1 Truth Table
IN1
0
IN0
0
OUT
register [1512]
register [1513]
register [1514]
register [1515]
LSB
0
1
1
0
1
1
MSB
This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-Bit LUT3 is defined by [1515:1512]
Table 34 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the 2-bit LUT logic cells.
Table 34: 2-bit LUT Standard Digital Functions
Function
AND-2
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-2
OR-2
NOR-2
XOR-2
XNOR-2
7.3 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELLS
There are seven macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset inputs. When used to
implement LUT functions, the 3-bit LUTs each takes in three input signals from the connection matrix and produces a single
output, which goes back into the connection matrix. When used to implement D Flip-Flop function, the three input signals from
the connection matrix go to the data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output
going back to the connection matrix. It is possible to define the active level for the reset/set input of DFF/LATCH macrocell.
There are both active high level reset/set (RST/SET) and active low level reset/set (nRST/nSET) options available, which are
selected by register [1523].
The DFF3 operation will flow the functional description:
If register [1522] = 0, and the CLK is rising edge triggered, then Q = D, otherwise Q will not change.
If register [1522] = 1, then data from D is written into the DFF by the rising edge on CLK and output to Q by the falling edge on
CLK.
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register [1527] DFF or Latch Select
register [1526] Output Select (Q or nQ)
register [1525] DFF Initial Polarity Select
register [1524] DFF nRST or nSET Select
register [1523] Active level selection for
RST/SET
IN2
IN1
From Connection
Matrix Output [10]
S0
S1
register [1522] Q1 or Q2 Select
OUT
3-bit LUT0
IN0
LUT Truth
Table
From Connection
Matrix Output [9]
To Connection Matrix
S0
S1
Input [5]
S0
S1
8-bits NVM
registers [1527:1520]
From Connection
Matrix Output [8]
S0
S1
DFF/Latch
Registers
0
1
Q/nQ
DFF
DFF
D
D
Q
D
Q
nRST/
nSET
nRST/
CL
nSET
CL
nRST/nSET
CLK
register [1522]
1-bit NVM
register [1518]
Figure 19: 3-bit LUT0 or DFF3
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register [1535] DFF or LATCH Select
IN2
IN1
register [1534] Output Select (Q or nQ)
register [1533] DFF Initial Polarity Select
register [1532] DFF nRST or nSET Select
register [1531] Active level selection for
RST/SET
From Connection
Matrix Output [13]
S0
S1
OUT
3-bit LUT1
IN0
LUT Truth
Table
From Connection
Matrix Output [12]
To Connection Matrix
S0
S1
Input [6]
S0
8-bits NVM
registers [1535:1528]
S1
DFF/Latch
Registers
D
From Connection
Matrix Output [11]
S0
S1
nRST/nSET
CLK
DFF4
Q/nQ
1-bit NVM
register [1519]
Figure 20: 3-bit LUT1 or DFF4
register [791] DFF or LATCH Select
IN2
From Connection
Matrix Output [16]
S0
S1
register [790] Output Select (Q or nQ)
register [789] DFF Initial Polarity Select
register [788] DFF nRST or nSET Select
register [787] Active level selection for RST/SET
IN1
OUT
3-bit LUT2
IN0
LUT Truth
Table
From Connection
Matrix Output [15]
To Connection Matrix
S0
S1
S0
S1
Input [7]
8-bits NVM
registers [791:784]
DFF/Latch
Registers
D
From Connection
Matrix Output [14]
S0
S1
nRST/nSET
CLK
DFF5
Q/nQ
1-bit NVM
register [824]
Figure 21: 3-bit LUT2 or DFF5
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register [799] DFF or LATCH Select
register [798] Output Select (Q or nQ)
register [797] DFF Initial Polarity Select
register [796] DFF nRST or nSET Select
register [795] Active level selection for RST/SET
IN2
IN1
From Connection
Matrix Output [19]
S0
S1
OUT
3-bit LUT3
IN0
LUT Truth
Table
From Connection
Matrix Output [18]
To Connection Matrix
S0
S1
S0
S1
Input [8]
8-bits NVM
registers [799:792]
DFF
Registers
D
From Connection
Matrix Output [17]
S0
S1
nRST/nSET
CLK
DFF6
Q/nQ
1-bit NVM
register [825]
Figure 22: 3-bit LUT3 or DFF6
register [807] DFF or LATCH Select
register [806] Output Select (Q or nQ)
register [805] DFF Initial Polarity Select
register [804] DFF nRST or nSET Select
register [803] Active level selection for RST/SET
IN2
From Connection
Matrix Output [22]
S0
S1
IN1
OUT
3-bit LUT4
IN0
LUT Truth
Table
From Connection
Matrix Output [21]
To Connection Matrix
S0
S1
S0
S1
Input [9]
8-bits NVM
registers [807:800]
DFF/Latch
Registers
D
From Connection
Matrix Output [20]
S0
S1
nRST/nSET
CLK
DFF7
Q/nQ
1-bit NVM
registers [826]
Figure 23: 3-bit LUT4 or DFF7
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register [815] DFF or LATCH Select
register [814] Output Select (Q or nQ)
register [813] DFF Initial Polarity Select
register [812] DFF nRST or nSET Select
register [811] Active level selection for RST/SET
IN2
IN1
From Connection
Matrix Output [25]
S0
S1
OUT
3-bit LUT5
IN0
LUT Truth
Table
From Connection
Matrix Output [24]
To Connection Matrix
S0
S1
S0
S1
Input [10]
8-bits NVM
registers [815:808]
DFF
Registers
D
From Connection
Matrix Output [23]
S0
S1
nRST/nSET
CLK
DFF8
Q/nQ
1-bit NVM
register [827]
Figure 24: 3-bit LUT5 or DFF8
register [823] DFF or LATCH Select
register [822] Output Select (Q or nQ)
register [821] DFF Initial Polarity Select
register [820] DFF nRST or nSET Select
register [819] Active level selection for RST/SET
IN2
From Connection
Matrix Output [28]
S0
S1
IN1
OUT
3-bit LUT6
IN0
LUT Truth
Table
From Connection
Matrix Output [27]
To Connection Matrix
S0
S1
S0
S1
Input [11]
8-bits NVM
registers [823:816]
DFF
Registers
D
From Connection
Matrix Output [26]
S0
S1
nRST/nSET
CLK
DFF9
Q/nQ
1-bit NVM
register [828]
Figure 25: 3-bit LUT6 or DFF9
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7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs
Table 35: 3-bit LUT0 Truth Table
Table 39: 3-bit LUT4 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1520]
register [1521]
register [1522]
register [1523]
register [1524]
register [1525]
register [1526]
register [1527]
LSB
register [800]
register [801]
register [802]
register [803]
register [804]
register [805]
register [806]
register [807]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 36: 3-bit LUT1 Truth Table
Table 40: 3-bit LUT5 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1528]
register [1529]
register [1530]
register [1531]
register [1532]
register [1533]
register [1534]
register [1535]
register [808]
register [809]
register [810]
register [811]
register [812]
register [813]
register [814]
register [815]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 37: 3-bit LUT2 Truth Table
Table 41: 3-bit LUT6 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [784]
register [785]
register [786]
register [787]
register [788]
register [789]
register [790]
register [791]
register [816]
register [817]
register [818]
register [819]
register [820]
register [821]
register [822]
register [823]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
Table 38: 3-bit LUT3 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [792]
register [793]
register [794]
register [795]
register [796]
register [797]
register [798]
register [799]
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MSB
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Each macrocell, when programmed for a LUT function, uses an 8-bit register to define their output function:
3-Bit LUT0 is defined by registers [1527:1520]
3-Bit LUT1 is defined by registers [1535:1528]
3-Bit LUT2 is defined by registers [791:784]
3-Bit LUT3 is defined by registers [799:792]
3-Bit LUT4 is defined by registers [807:800]
3-Bit LUT5 is defined by registers [815:808]
3-Bit LUT6 is defined by registers [823:816]
Table 42 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the four 3-bit LUT logic cells.
Table 42: 3-bit LUT Standard Digital Functions
Function
AND-3
MSB
LSB
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-3
OR-3
NOR-3
XOR-3
XNOR-3
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7.3.2 Initial Polarity Operations
VDD
Data
Clock
POR
Initial Polarity: High
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Initial Polarity: Low
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Figure 26: DFF Polarity Operations with nReset
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VDD
Data
Clock
POR
Initial Polarity: High
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Initial Polarity: Low
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Figure 27: DFF Polarity Operations with nSet
7.4 4-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELL
There is one macrocell that can serve as either a 4-bit LUT or as a D Flip-Flop with Set/Reset inputs. When used to implement
LUT functions, the 4-bit LUT takes in four input signals from the connection matrix and produces a single output, which goes
back into the connection matrix. When used to implement D Flip-Flop function, the input signals from the connection matrix go to
the data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output going back to the connection
matrix.
If register [842] = 0, and the CLK is rising edge triggered, then Q = D, otherwise Q will not change.
If register [842] = 1, then data from D is written into the DFF by the rising edge on CLK and output to Q by the falling edge on
CLK. It is possible to define the active level for the reset/set input of DFF/LATCH macrocell. There are both active high level
reset/set (RST/SET) and active low level reset/set (nRST/nSET) options available, which are selected by register [843].
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From Connection
register [847] DFF or LATCH Select
S0
S1
Matrix Output [53]
register [846] Output Select (Q or nQ)
register [845] DFF Initial Polarity Select
register [844] DFF nRST or nSET Select
register [843]Active level selection for RST/SET
register [842] Q1 or Q2 Select
IN3
IN2
IN1
From Connection
Matrix Output [52]
S0
S1
OUT
4-bit LUT0
IN0
LUT Truth
Table
From Connection
Matrix Output [51]
To Connection Matrix
S0
S1
Input [29]
S0
16-bits NVM
registers [847:832]
S1
DFF/Latch
Registers
D
From Connection
Matrix Output [50]
S0
S1
nRST/nSET DFF10
RST/SET
Q/nQ
Q1/Q2
CLK
Select
register [842]
1-bit NVM
register [829]
Figure 28: 4-bit LUT0 or DFF10
7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT
Table 43: 4-bit LUT0 Truth Table
IN3
0
IN2
0
IN1
0
IN0
0
OUT
register [832]
register [833]
register [834]
register [835]
register [836]
register [837]
register [838]
register [839]
register [840]
register [841]
register [842]
register [843]
register [844]
register [845]
register [846]
register [847]
LSB
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
MSB
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This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:
4-Bit LUT0 is defined by registers [847:832]
Table 44: 4-bit LUT Standard Digital Functions
Function
AND-4
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-4
OR-4
NOR-4
XOR-4
XNOR-4
7.5 3-BIT LUT OR PIPE DELAY/RIPPLE COUNTER MACROCELL
There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay/Ripple Counter.
When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a
single output, which goes back into the connection matrix.
When used as a Pipe Delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK), and Reset (nRST). The Pipe
Delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF
cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell input (IN). Both of the two outputs (OUT0
and OUT1) provide user selectable options for 1 to 16 stages of delay. There are delay output points for each set of the OUT0
and OUT1 outputs to a 4-input mux that is controlled by registers [851:848] for OUT0 and registers [855:852] for OUT1.
The 4-input MUX is used to control the selection of the amount of delay.
The overall time of the delay is based on the clock used in the SLG47004 design. Each DFF cell has a time delay of the inverse
of the clock time (either external clock or the internal Oscillator within the SLG47004). The sum of the number of DFF cells used
will be the total time delay of the Pipe Delay logic cell. OUT1 Output can be inverted (as selected by register [859]).
In the Ripple Counter mode, there are 3 options for setting, which use 7 bits. There are 3 bits to set nSET value (SV) in range
from 0 to 7. It is a value, which will be set into the Ripple Counter outputs when nSET input goes LOW. End value (EV) will use
3 bits for setting outputs code, which will be last code in the cycle. After reaching the EV, the Ripple Counter goes to the first code
by the rising edge on CLK input. The Functionality mode option uses 1 bit. This setting defines how exactly Ripple Counter will
operate.
The user can select one of the functionality modes by register: RANGE or FULL. If the RANGE option is selected, the count starts
from SV. If UP input is LOW the count goes down: SV→EV→EV-1 to SV+1→SV, and others (if SV is smaller than EV), or SV→SV-
1 to EV+1→EV→SV (if SV is bigger than EV). If UP input is HIGH, count starts from SV up to EV, and others.
In the FULL range configuration the Ripple Counter functions as follows. If UP input is LOW, the count starts from SV and goes
down to 0. Then current counter value jumps to EV and goes down to 0, and others.
If UP input is HIGH, count goes up starting from SV. Then current counter value jumps to 0 and counts up to EV, and others. See
Ripple Counter functionality example in Figure 30.
Every step is executed by the rising edge on CLK input.
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registers [855:848]
From Connection
Matrix Output [47]
IN0
From Connection
Matrix Output [48]
IN1
IN2
OUT
3-bit LUT13
From Connection
Matrix Output [49]
registers [855:852]
Pipe Delay
register [859]
0
1
0
1
OUT2
OUT1
To Connection
Matrix Input[28]
register [858]
From Connection
Matrix Output [47]
IN
From Connection
Matrix Output [48]
nRST
16 Flip-Flops
0
1
OUT1
From Connection
Matrix Output [49]
CLK
To Connection
Matrix Input [27]
register [858]
OUT0
0
1
OUT0
To Connection
Matrix Input [26]
0
1
registers [851:848]
1 Pipe OUT
register [857]
Ripple Counter
3 Flip-Flops
UP
From Connection
Matrix Output [47]
UP/DOWN
Control
OUT0
D
Q
DFF1
CLK
From Connection
Matrix Output [49]
CL
nQ
nSET
From Connection
Matrix Output [48]
SET
OUT1
OUT2
Control
D
Q
DFF2
CL
nQ
Mode & SET/END
Value Control
D
Q
DFF3
nQ
CL
registers [854:848]
Figure 29: 3-bit LUT13/Pipe Delay/Ripple Counter
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Figure 30: Example: Ripple Counter Functionality
7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT
Table 45: 3-bit LUT13 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [848]
register [849]
register [850]
register [851]
register [852]
register [853]
register [854]
register [855]
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
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Each macrocell, when programmed for a LUT function, uses an 8-bit register to define their output function:
3-Bit LUT13 is defined by registers [855:848]
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8
Multi-Function Macrocells
The SLG47004 has seven Multi-Function macrocells that can serve as more than one logic or timing function. In each case, they
can serve as a LUT, DFF with flexible settings, or as CNT/DLY with multiple modes such as One Shot, Frequency Detect, Edge
Detect, and others. Also, the macrocell is capable to combine those functions: LUT/DFF connected to CNT/DLY or CNT/DLY
connected to LUT/DFF, see Figure 31.
See the list below for the functions that can be implemented in these macrocells:
Six macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays
One macrocell that can serve as a 4-bit LUT/D Flip-Flop and as 16-Bit Counter/Delay/FSM
To Connection Matrix
To Connection Matrix
From
From
Connection
Matrix
Connection
To Connection
Matrix
To Connection
Matrix
LUT
or
DFF
Matrix
LUT
or
DFF
CNT/DLY
CNT/DLY
Figure 31: Possible Connections Inside Multi-Function Macrocell
Inputs/Outputs for the seven Multi-Function macrocells are configured from the connection matrix with specific logic functions
being defined by the state of NVM bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined
function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
8.1 3-BIT LUT OR DFF/LATCH WITH 8-BIT COUNTER/DELAY MACROCELLS
There are six macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays.
When used to implement LUT functions, the 3-bit LUTs each takes in three input signals from the connection matrix and produces
a single output, which goes back into the connection matrix or can be connected to CNT/DLY's input.
When used to implement D Flip-Flop function, the three input signals from the connection matrix go to the data (D), clock (CLK),
and Reset/Set (nRST/nSET) inputs of the Flip-Flop, with the output going back to the connection matrix or to the CNT/DLY's input.
When used to implement Counter/Delays, each macrocell has a dedicated matrix input connection. For flexibility, each of these
macrocells has a large selection of internal and external clock sources, as well as the option to chain from the output of the
previous (N-1) CNT/DLY macrocell, to implement longer count/delay circuits. These macrocells can also operate in a One-Shot
mode, which will generate an output pulse of user-defined width. They can also operate in a Frequency Detection or Edge
Detection mode.
Counter/Delay macrocell has an initial value, which defines its initial value after SLG47004 is powered up. It is possible to select
initial Low or initial High, as well as initial value defined by a Delay In signal.
For example, in case initial LOW option is used, the rising edge delay will start operation.
For timing diagrams refer to Section 8.3.
Note: After two DFF – counters initialize with counter data = 0 after POR.
Initial state = 1 – counters initialize with counter data = 0 after POR.
Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.
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CNT5 and CNT6 current count value can be read via I2C. However, it is possible to change the counter data (value counter starts
operating from) for any macrocell using I2C write commands. In this mode, it is possible to load count data immediately (after two
DFF) or after counter ends counting. See Section 18.7.1 for further details.
8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams
register [1391] DFF or LATCH Select
register [1390] Output Select (Q or nQ)
From Connection
register [1389] (nRST or nSET) from
Matrix Output [31]
IN2
IN1
IN0
matrix Output
register [1388] DFF Initial Polarity Select
S0
S1
3-bit LUT7
S0
S1
OUT
LUT Truth
Table
From Connection
Matrix Output [30]
To Connection
S0
S0
S1
S0
S1
Matrix Input [15]
8-bits NVM
registers [1391:1384]
S1
DFF
Registers
D
From Connection
Matrix Output [29]
S0
S1
S0
S1
nRST/nSET DFF/
Q/nQ
LATCH11
CLK
register [1244]
LUT/DFF Sel
registers [1399:1392]
registers [1243:1240]
Mode Sel
CNT
Data
ext_CLK
To Connection
Matrix Input [14]
0
S0
OUT
CNT/DLY1
S0
S1
S2
S1
S2
S3
DLY_IN/CNT Reset
Config
Data
registers [1255:1245],
[1339:1338]
0
S3
Figure 32: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT7/DFF11, CNT/DLY1)
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register [1407] DFF or LATCH Select
register [1406] Output Select (Q or nQ)
register [1405] (nRST or nSET) from
matrix Output
From Connection
Matrix Output [34]
IN2
register [1404] DFF Initial Polarity Select
S0
S1
3-bit LUT8
S0
S1
OUT
IN1
IN0
LUT Truth
Table
From Connection
Matrix Output [33]
To Connection
S0
S0
S1
S0
S1
Matrix Input [17]
8-bits NVM
registers [1407:1400]
S1
DFF
Registers
D
From Connection
Matrix Output [32]
S0
S1
S0
S1
nRST/nSET
CLK
DFF/
Latch12
Q/nQ
register [1260]
LUT/DFF Sel
registers [1415:1408]
registers [1259:1256]
Mode Sel
CNT
Data
ext_CLK
To Connection
Matrix Input [16]
0
S0
OUT
CNT/DLY2
S0
S1
S2
S1
S2
S3
DLY_IN/CNT Reset
Config
Data
0
S3
registers [1271:1261], [1345:1344]
Figure 33: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF12, CNT/DLY2)
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register [1423] DFF or LATCH Select
register [1422] Output Select (Q or nQ)
register [1421] (nRST or nSET) from
matrix Output
From Connection
Matrix Output [37]
IN2
register [1420] DFF Initial Polarity Select
S0
S1
3-bit LUT9
S0
S1
OUT
IN1
IN0
LUT Truth
Table
From Connection
Matrix Output [36]
To Connection
S0
S0
S1
S0
S1
Matrix Input [19]
8-bits NVM
registers [1423:1416]
S1
DFF
Registers
D
From Connection
Matrix Output [35]
S0
S1
S0
S1
nRST/nSET
DFF/
Q/nQ
Latch13
CLK
register [1276]
LUT/DFF Sel
registers [1275:1272]
Mode Sel
registers [1431:1424]
CNT
Data
ext_CLK
To Connection
Matrix Input [18]
0
S0
OUT
CNT/DLY3
S0
S1
S2
S1
S2
S3
DLY_IN/CNT Reset
Config
Data
0
S3
registers [1287:1277], [1347:1346]
Figure 34: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF13, CNT/DLY3)
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register [1439] DFF or LATCH Select
register [1438] Output Select (Q or nQ)
register [1437] (nRST or nSET) from
matrix Output
From Connection
Matrix Output [40]
IN2
register [1436] DFF Initial Polarity Select
S0
3-bit LUT10
S0
OUT
IN1
S1
S1
LUT Truth
Table
IN0
From Connection
Matrix Output [39]
To Connection
S0
S0
S1
S0
S1
Matrix Input [21]
8-bits NVM
registers [1439:1432]
S1
DFF
Registers
D
From Connection
Matrix Output [38]
S0
S1
S0
S1
nRST/nSET
DFF/
Q/nQ
Latch14
CLK
register [1292]
LUT/DFF Sel
registers [1447:1440
registers [1291:1288]
Mode Sel
CNT
Data
ext_CLK
To Connection
Matrix Input [20]
0
S0
OUT
CNT/DLY4
DLY_IN/CNT Reset
S0
S1
S2
S1
S2
S3
Config
Data
0
S3
registers [1303:1293], [1349:1348]
Figure 35: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF14, CNT/DLY4)
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register [1455] DFF or LATCH Select
register [1454] Output Select (Q or nQ)
register [1453] (nRST or nSET) from
matrix Output
From Connection
Matrix Output [43]
register [1452] DFF Initial Polarity Select
IN2
S0
3-bit LUT11
S0
OUT
IN1
S1
S1
LUT Truth
Table
IN0
From Connection
Matrix Output [42]
To Connection
S0
S0
S1
S0
S1
Matrix Input [23]
8-bits NVM
registers [1455:1448]
S1
DFF
Registers
D
From Connection
Matrix Output [41]
S0
S1
S0
S1
nRST/nSET
DFF/
Q/nQ
Latch15
CLK
register [1308]
LUT/DFF Sel
registers [1307:1304]
Mode Sel
registers [1463:1456]
CNT
Data
ext_CLK
To Connection
Matrix Input [22]
0
S0
OUT
CNT/DLY5
DLY_IN/CNT Reset
S0
S1
S2
S1
S2
S3
Config
Data
0
S3
registers [1319:1309], [1351:1350]
Figure 36: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF15, CNT/DLY5)
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register [1471] DFF or LATCH Select
register [1470] Output Select (Q or nQ)
register [1469] (nRST or nSET) from
matrix Output
From Connection
Matrix Output [46]
register [1468] DFF Initial Polarity Select
IN2
S0
3-bit LUT12
S0
OUT
IN1
S1
S1
LUT Truth
Table
IN0
From Connection
Matrix Output [45]
To Connection
S0
S0
S1
S0
S1
Matrix Input [25]
8-bits NVM
registers [1471:1464]
S1
DFF
Registers
D
From Connection
Matrix Output [44]
S0
S1
S0
S1
nRST/nSET
DFF/
Q/nQ
Latch16
CLK
register [1324]
LUT/DFF Sel
registers [1479:1472]
registers [1323:1320]
Mode Sel
CNT
Data
ext_CLK
To Connection
Matrix Input [24]
0
S0
OUT
CNT/DLY6
DLY_IN/CNT Reset
S0
S1
S2
S1
S2
S3
Config
Data
0
S3
registers [1335:1325], [1341:1340]
Figure 37: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF16, CNT/DLY6)
As shown in Figure 32 to Figure 37 there is a possibility to use LUT/DFF and CNT/DLY simultaneously.
Note: It is not possible to use LUT and DFF at once, one of these macrocells must be selected.
Case 1. LUT/DFF in front of CNT/DLY. Three input signals from the connection matrix go to previously selected LUT or DFF's
inputs and produce a single output which goes to a CND/DLY input. In its turn Counter/Delay's output goes back to the matrix.
Case 2. CNT/DLY in front of LUT/DFF. Two input signals from the connection matrix go to CND/DLY's inputs (IN and CLK). Its
output signal can be connected to any input of previously selected LUT or DFF, after which the signal goes back to the matrix.
Case 3. Single LUT/DFF or CNT/DLY. Also, it is possible to use a standalone LUT/DFF or CNT/DLY. In this case, all inputs
and output of the macrocell are connected to the matrix.
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8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs
Table 46: 3-bit LUT7 Truth Table
Table 50: 3-bit LUT11 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1384]
register [1385]
register [1386]
register [1387]
register [1388]
register [1389]
register [1390]
register [1391]
LSB
register [1448]
register [1449]
register [1450]
register [1451]
register [1452]
register [1453]
register [1454]
register [1455]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 47: 3-bit LUT8 Truth Table
Table 51: 3-bit LUT12 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1400]
register [1401]
register [1402]
register [1403]
register [1404]
register [1405]
register [1406]
register [1407]
register [1464]
register [1465]
register [1466]
register [1467]
register [1468]
register [1469]
register [1470]
register [1471]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
Table 48: 3-bit LUT9 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [1416]
register [1417]
register [1418]
register [1419]
register [1420]
register [1421]
register [1422]
register [1423]
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MSB
LSB
Table 49: 3-bit LUT10 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [1432]
register [1433]
register [1434]
register [1435]
register [1436]
register [1437]
register [1438]
register [1439]
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MSB
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Each macrocell, when programmed for a LUT function, uses an 8-bit register to define their output function:
3-Bit LUT7 is defined by registers [1391:1384]
3-Bit LUT8 is defined by registers [1407:1400]
3-Bit LUT9 is defined by registers [1423:1416]
3-Bit LUT10 is defined by registers [1439:1432]
3-Bit LUT11 is defined by registers [1455:1448]
3-Bit LUT12 is defined by registers [1471:1464]
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8.2 4-BIT LUT OR DFF/LATCH WITH 16-BIT COUNTER/DELAY MACROCELL
There is one macrocell that can serve as either 4-bit LUT/D Flip-Flops or as 16-bit Counter/Delay.
When used to implement LUT function, the 4-bit LUT takes in four input signals from the Connection Matrix and produces a single
output, which goes back into the Connection Matrix.
When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and clock (CLK)
inputs for the Flip-Flop, with the output going back to the connection matrix.
When used to implement 16-Bit Counter/Delay function, two of the four input signals from the connection matrix go to the external
clock (EXT_CLK) and reset (DLY_IN/CNT Reset) for the Counter/Delay, with the output going back to the connection matrix.
This macrocell has an optional Finite State Machine (FSM) function. There are two additional matrix inputs for Up and Keep to
support FSM functionality
This macrocell can also operate in a one-shot mode, which will generate an output pulse of user-defined width.
This macrocell can also operate in a frequency detection or edge detection mode.
This macrocell can have its active count value read via I2C. See Section 18.7.1 for further details.
Note: After two DFF – counters initialize with counter data = 0 after POR.
Initial state = 1 – counters initialize with counter data = 0 after POR.
Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.
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8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram
From Connection
Matrix Output [57]
IN3
register [1367] DFF or LATCH Se-
S0
S1
lect
register [1366] DFF Output Select
(Q or nQ)
register [1365] DFF Initial Polarity
Select
S1
S0
S1
S0
IN2
IN1
From Connection
Matrix Output [56]
0
4-bit LUT1
S1
S0
S0
S1
S1
S0
0
OUT
IN0
LUT Truth
Table
From Connection
Matrix Output [55]
S1
S0
To Connection
S0
S0
S1
S1
S0
Matrix Input [13]
registers [1217:1216] =
00, 10, 11
16-bits NVM
registers [1367:1352]
1
S1
From Connection
Matrix Output [54]
DFF
D
S1
S0
Registers
S0
S1
S1
S0
nSET
Q/nQ
DFF17
1
nRST
CLK
LUT/DFF Sel
register [1220]
registers [1222:1221]
registers [1383:1368]
CNT
registers [1219:1216]
Mode Selection
0
S0
S1
S2
S3
Data
ext_CLK
CMO* [56]
CMO* [55]
S0
S1
To Connection
Matrix Input [12]
S0
0
0
S0
S1
S2
S3
CMO* [57]
CMO* [56]
CMO* [55]
CMO* [54]
S1
S2
S3
OUT
CNT/DLY0
DLY_IN/CNT Reset
CMO* [55]
S1
S0
From Connection
Matrix Output [56]
0
KEEP
UP
From Connection
Matrix Output [57]
FSM
S1
S0
Config
Data
0
Note: CMO - Connection Matrix Output
registers [1238:1223],
[1337:1336]
registers [1217:1216] = 01
Figure 38: 4-bit LUT1 or CNT/DLY0
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8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs
Table 52: 4-bit LUT1 Truth Table
IN3
0
IN2
0
IN1
0
IN0
0
OUT
register [1352]
register [1353]
register [1354]
register [1355]
register [1356]
register [1357]
register [1358]
register [1359]
register [1360]
register [1361]
register [1362]
register [1363]
register [1364]
register [1365]
register [1366]
register [1367]
LSB
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
MSB
This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:
4-Bit LUT1 is defined by registers [1367:1352]
Table 53: 4-bit LUT Standard Digital Functions
Function
AND-4
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-4
OR-4
NOR-4
XOR-4
XNOR-4
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8.3 CNT/DLY/FSM TIMING DIAGRAMS
8.3.1 Delay Mode CNT/DLY0 to CNT/DLY6
Delay In
Asynchronous delay variable
Asynchronous delay variable
OSC: force Power-On
(always running)
Delay Output
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
Delay In
offset
offset
OSC: auto Power-On
(powers up from delay in)
Delay Output
delay = offset + period x (counter data + 1)
See offset in table 3
delay = offset + period x (counter data + 1)
See offset in table 3
Figure 39: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3
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The macrocell shifts the respective edge to a set time and restarts by appropriate edge. It works as a filter if the input signal is
shorter than the delay time.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
Delay time
Delay Function
Rising Edge Detection
t
Delay Function
Falling Edge Detection
t
Delay Function
Both Edge Detection
t
Figure 40: Delay Mode Timing Diagram for Different Edge Select Modes
8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY6
RESET_IN
CLK
Counter OUT
4 CLK period pulse
Count start in first rising edge CLK
Figure 41: Counter Mode Timing Diagram without Two DFFs Synced Up
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RESET_IN
CLK
Counter OUT
4 CLK period pulse
Count start in 0 CLK after reset
Figure 42: Counter Mode Timing Diagram with Two DFFs Synced Up
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8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY6
This macrocell will generate a pulse whenever a selected edge is detected on its input. Register bits set the edge selection. The
pulse width is determined by counter data and clock selection properties.
The output pulse polarity (non-inverted or inverted) is selected by register bit. Any incoming edges will be ignored during the pulse
width generation. The following diagram shows one-shot function for non-inverted output.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
Delay time
One-Shot Function
Rising Edge Detection
t
One-Shot Function
Falling Edge Detection
t
One-Shot Function
Both Edge Detection
t
Figure 43: One-Shot Function Timing Diagram
This macrocell generates a high level pulse with a set width (defined by counter data) when detecting the respective edge. It does
not restart while pulse is high.
8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6
Rising Edge: The output goes high if the time between two successive edges is less than the delay. The output goes low if the
second rising edge has not come after the last rising edge in specified time.
Falling Edge: The output goes high if the time between two falling edges is less than the set time. The output goes low if the
second falling edge has not come after the last falling edge in specified time.
Both Edge: The output goes high if the time between the rising and falling edges is less than the set time, which is equivalent to
the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not come.
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Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Delay time
Frequency Detector Function
Rising Edge Detection
Frequency Detector Function
Falling Edge Detection
t
t
Frequency Detector Function
Both Edge Detection
Figure 44: Frequency Detection Mode Timing Diagram
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8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY6
The macrocell generates high level short pulse when detecting the respective edge. See Table 10.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Edge Detector Function
Rising Edge Detection
Edge Detector Function
Falling Edge Detection
t
t
Edge Detector Function
Both Edge Detection
Figure 45: Edge Detection Mode Timing Diagram
8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY6
In Delayed Edge Detection Mode, High-level short pulses are generated on the macrocell output after the configured delay time,
if the corresponding edge was detected on the input.
If the input signal is changed during the set delay time, the pulse will not be generated.
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Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Delayed Edge Detector
Function Rising
Edge Detection
Delayed Edge Detector
Function Falling
Edge Detection
t
t
Delayed Edge Detector
Function Both
Edge Detection
Figure 46: Delayed Edge Detection Mode Timing Diagram
8.3.7 CNT/FSM Mode CNT/DLY0
RESET IN
KEEP
COUNT END
CLK
3
2
1
0
3
2
1
0
3
2
1
3
2
1
0
0
Q
Note: Q = current counter value
Figure 47: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3
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SET IN
KEEP
COUNT END
CLK
2
1
0
3
2
1
0
3
3
2
1
2
1
0
3
3
Q
Note: Q = current counter value
Figure 48: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3
RESETI N
KEEP
COUNT END
CLK
65535
65533 65534
5
6
7
8
9
3
4
5
3
4
5
1
2
3
4
0
Q
Note: Q = current counter value
Figure 49: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3
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SET IN
KEEP
COUNT END
CLK
65533 65534 65535
8
9
10 11 12
3
4
5
3
4
5
4
5
6
7
3
Q
Note: Q = current counter value
Figure 50: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3
8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes
There is a difference in counter value for Counter and Delay/One-Shot/Frequency Detect modes. Compared to Counter mode,
in Delay/One-Shot/Frequency Detect modes the counter value is shifted for two rising edges of the clock signal. See Figure 51.
One-Shot/Freq. SET/Delay IN
CLK
CNT Out
0
3
2
1
0
CNT Data
3
2
DLY Out
Delay Data
3
3
2
1
3
3
3
One-Shot Out
One-Shot Data
3
3
2
3
3
1
3
Figure 51: Counter Value, Counter Data = 3
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8.4 WAKE AND SLEEP CONTROLLER
The SLG47004 has a Wake and Sleep (WS) function for ACMP. The macrocell CNT/DLY0 can be reconfigured for this purpose
registers [1224:1223] = 11 and register [1232] = 1. The WS serves for power saving, it allows to switch on and off selected ACMPs
on selected bit of 16-bit counter.
Note 1: BG/Analog_Good time is long and should be considered in the wake and sleep timing in case it dynamically powers on/off.
Note 2: Wake time should be long enough to make sure ACMP and Vref have enough time to get a sample before going to sleep.
Power Control
From Connection Matrix Output [91] for 2 kHz OSC0.
WS Controller
OSC0
CNT0_out
CNT
cnt_end
To Connection Matrix Input [12]
ck
CK_OSC
Divider
Analog Control Block
ACMPs WS EN [1:0]
register [612], register [634]
2
bg/regulator
pd
From Connection
Matrix Output [90:89]
WS_out
WS_PD
WS_PD
(from OSC PD)
ACMPs_PD
2
WS_out
WS_PD to WS out
state selection register [1233]
registers [1230:1227]
WS clock freq. selection
registers [1383:1368]
WS ratio control data
ACMPs
registers [633], [611]
WS mode: normal or short wake
ACMP0, ACMP1 OUT
2
+
-
0
1
Note: WS_PD is High at OSC0 power-down
2
To Connection
Matrix Input
[57:56]
ACMPs_PD
WS_out
nRST
BG/Analog_Good
Figure 52: Wake and Sleep Controller
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time between Reset goes low
and 1st WS clock rising edge
Force Wake
CNT_RST
(From Connection Matrix)
ACMP_PD is High
(From Connection Matrix)
CNT0_out
(To Connection Matrix)
WS_out
(internal signal)
Data is latched
BG/Analog_Good
(internal signal)
Sleep Mode
ACMP Latches Last Data
Normal ACMP
Operation
ACMP follows input
Sleep Mode
ACMP Latches New Data
Normal ACMP
Sleep Mode
ACMP Latches
New Data
Operation
ACMP follows input
BG/Analog
Startup time*
BG/Analog
Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.
Figure 53: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used
time between Reset goes low
and 1st WS clock rising edge
Force Wake
CNT_RST
(From Connection Matrix)
ACMP_PD is High
(From Connection Matrix)
CNT0_out
(To Connection Matrix)
WS_out
(internal signal)
Data is latched
Data is latched
BG/Analog_Good
(internal signal)
Sleep Mode
ACMP Latches Last Data
Sleep Mode
ACMP Latches New Data
Normal ACMP
Operation for short time
ACMP follows input
Sleep Mode
ACMP Latches
New Data
Normal ACMP
Operation for short time
ACMP follows input
BG/Analog
Startup time*
BG/Analog
Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.
Figure 54: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used
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time between Reset goes low
and 1st WS clock rising edge
Force Sleep
CNT_SET
(From Connection Matrix)
ACMP_PD is High
(From Connection Matrix)
CNT0_out
(To Connection Matrix)
WS_out
(internal signal)
Data is latched
BG/Analog_Good
(internal signal)
Sleep Mode
ACMP Latches Last Data
Normal ACMP
Operation
ACMP follows input
Sleep Mode
ACMP Latches New Data
BG/Analog
Startup time*
Note: CNT0_out is a delayed WS_out signal for 1 us to make sure the data is correct during LATCH.
Figure 55: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used
time between Reset goes low
and 1st WS clock rising edge
Force Sleep
CNT_RST
(From Connection Matrix)
ACMP_PD is High
(From Connection Matrix)
CNT0_out
(To Connection Matrix)
WS_out
(internal signal)
Data is latched
BG/Analog_Good
(internal signal)
Sleep Mode
Sleep Mode
ACMP Latches New Data
ACMP Latches Last Data
Normal ACMP
Operation for short time
ACMP follows input
BG/Analog
Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.
Figure 56: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Set is Used
Note: If low power BG is powered on/off by WS, the wake time should be longer than 2.1 ms. The BG/analog start up time will
take maximal 2 ms. If low power BG is always on, OSC0 period is longer than required wake time. The short wake mode can be
used to reduce the current consumption. The short wake mode is edge triggered, when the wake signal is latched by rising edge
and released the Power-On signal after the ACMP output data is latched. This allows to have a valid ACMP data for any type of
wake signal and have the optimized current consumption.
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To use any ACMP under WS controller, the following settings must be done:
CNT/DLY0 must be set to Wake and Sleep Controller function (for all ACMPs);
Register WS => enable (for each ACMP separately);
CNT/DLY0 set/reset input = 0 (for all ACMPs).
As the OSC any oscillator with any pre-divider can be used. The user can select a period of time while the ACMP is sleeping in
a range of 1 - 65535 clock cycles. Before they are sent to sleep their outputs are latched, so the ACMPs remain their state (High
or Low) while sleeping.
WS controller has the following settings:
Wake and Sleep Output State (High/Low)
If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = High, the
ACMP is continuously on.
If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = Low, the
ACMP is continuously off.
Both cases WS function is turned off.
Counter Data (Range: 1 to 65535)
User can select wake and sleep ratio of the ACMP; counter data = sleep time, one clock = wake time.
Q mode - defines the state of WS counter data when Set/Reset signal appears Reset - when active signal appears, the WS
counter will reset to zero and High level signal on its output will turn on the ACMPs. When Reset signal goes out, the WS
counter will go Low and turn off the ACMPs until the counter counts up to the end. Set - when active signal appears, the WS
counter will stop and Low level signal on its output will turn off the ACMPs. When Set signal goes out, the WS counter will go
on counting and High level signal will turn on the ACMPs while counter is counting up to the end.
Note: The OSC0 matrix power down to control ACMP WS is not supported for short wait time option.
Edge Select defines the edge for Q mode
High level Set/Reset - switches mode Set/Reset when level is High
Note: Q mode operates only in case of "High Level Set/Reset”.
Wake time selection - time required for wake signal to turn the ACMPs on
Normal Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on until
WS signal is Low again. Wake time is one clock period. It should be longer than BG turn on time and minimal required
comparing time of the ACMP.
Short Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on for 1 µs
and turn off regardless of WS signal. The WS signal width does not matter.
Keep - pauses counting while Keep = 1
Up - reverses counting
If Up = 1, CNT is counting up from user selected value to 65535.
If Up = 0, CNT is counting down from user selected value to 0.
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9
Analog Comparators
9.1 ANALOG COMPARATORS OVERVIEW
There are two Low Power Rail-to-Rail General Purpose Analog Comparators (ACMP) macrocells in the SLG47004. For the
ACMP macrocells to be used in a GreenPAK design, the power-up signals (ACMP0_L_pdb and ACMP1_L_pdb) need to be
active. By connecting to signals coming from the Connection Matrix, it is possible to have each ACMP be ON continuously, OFF
continuously, or switched on periodically, based on a digital signal coming from the Connection Matrix. When ACMP is powered
down, its output is low. Two General Purpose Analog Comparators are optimized for low power operation.
Each of the General Purpose ACMP cells has a positive input signal that can be provided by a variety of external sources, and
can also have a selectable gain stage (1x, 0.5x, 0.33x, 0.25x) before connection to the analog comparator. The gain divider is
unbuffered and has an input resistance of 2 MΩ (typ) for 0.5x, 0.33x, 0.25x, and 10 GΩ for 1x. Each of the General Purpose
ACMP macrocells has a negative input signal that is either created from an internal Vref or provided by any external source
(from external pins). Note that the external Vref signal is filtered with a 2nd order low pass filter with 8 kHz typical bandwidth, see
in Figure 57 and Figure 58.
Input bias current < 1 nA (typ).
PWR UP = 1 => ACMP is powered up.
PWR UP = 0 => ACMP is powered down.
Both General Purpose Analog Comparators have "Low Energy Power Up" setting (register [608] - AСMP0, register [630] -
AСMP1). When enabled, it allows reducing average power consumption during ACMP power up process. This setting changes
power up sequence of analog macrocells:
Low Energy Power Up register [608], register [630] = 0 - all analog macrocells associated with ACMP turns on simultaneously.
Low Energy Power Up register [608], register [630] = 1 - the first macrocell that begins to turn on is Bandgap. Other analog
macrocells begin to turn on only after BG_OK signal is valid. This option slightly increases general ACMP Power-On time, while
reducing the average current consumption.
During power-up, the ACMP output will remain LOW, and then becomes valid after power up signal goes high for ACMP0_L and
ACMP1_L (see parameter tstart in Table 16).
Each cell also has a flexible hysteresis selection, to offer hysteresis of 32 steps, but not more than Vref voltage. It means that
there are 6-bits to select Vref and independent 6-bits to select the hysteresis (no need to have an adder logic).
It’s possible to enable low pass filter at the Vref input. But it’s highly recommended to enable this LPF only when hysteresis
Vhys > 196 mV.
ACMP0_L IN+ options are OA0_out, GPIOx (PIN), VDD.
ACMP1_L IN+ options are OA1, GPIOx (PIN), ACMP0L_IN+, Temp Sensor OUT.
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9.1.1 ACMP0L Block Diagram
registers [629:624]
registers [623:618]
to ACMP1_L
6-bit
Hysteresis
Selection
registers [615:614]
OA0_Out
ACMP
Ready
00
01
10
GPIO
Selectable
Gain
+
-
To Connection
Matrix Input [56]
0
1
Internal VDD
pUp
Vref
Latch
Low Power
ACMP
registers [617:616]
register [612]
W/S Control
GPIO
1000000
register [613]
From Connection
Matrix Output [89]
0111111-
0000000
LPF
Vref
registers [629:624]
registers [623:618]
Figure 57: ACMP0L Block Diagram
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9.1.2 ACMP1L Block Diagram
registers [651:646]
registers [645:640]
6-bit
Hysteresis
Selection
registers [637:636]
OA1_Out
00
01
10
11
ACMP
Ready
GPIO
Selectable
Gain
+
-
From ACMP0_L_IN+
To Connection
Matrix Input [57]
0
1
pUp
Vref
Temp Sensor
Latch
Low Power
ACMP
registers [639:638]
register [634]
W/S Control
GPIO
1000000
register [635]
From Connection
Matrix Output [90]
0111111-
0000000
LPF
Vref
registers [651:646]
registers [645:640]
Figure 58: ACMP1L Block Diagram
9.2 CHOPPER ANALOG COMPARATOR
There is one Chopper Rail-to-Rail Analog Comparator (ACMP) macrocells in the SLG47004. It is possible to use Chopper
ACMP to do in system trim by changing the Rheostat resistance in Auto-Trim mode. It is also possible to use a Chopper ACMP
as a general purpose analog comparator.
The chopper ACMP power up signal is controlled either by internal Auto-Trim logic (Set 0/1 of Digital Rheostat 0/1) or by matrix
input.
The chopper ACMP is automatically powered on during the calibration time to control the up/down signal of the counter/rheostat,
when the Auto-Trim is enabled (register [909]= 0).
In order to use Chopper ACMP as a standalone comparator (Auto-Trim mode is disabled, register [909] = 1) user should provide
the clock signal to this macrocell. Clock source can be internal oscillators or any pulses from the connection matrix.
Note that clock frequency for the Chopper ACMP shouldn’t be greater than fChACMP. Please refer to Table 23.
Output of Chopper ACMP can be optionally inverted by register [882].
The matrix output [85] is used to control chopper ACMP power up signal for the general purpose usage, see Figure 59. It is
possible to use the chopper ACMP as a general purpose ACMP after Auto-Trim procedure is completed, since the power up
signal is a logic OR of the latched Set (Digital Rheostat 0/1) signal and matrix signal. If Auto-Trim (Set 0/1 of Digital Rheostat
0/1) is disabled and chopper ACMP channel is set to Auto (Channel 0/1), then ACMP output defaults to Channel 0 while
Channel 1 is ignored.
The power-up signals need to be active high in order to use the Chopper ACMP. By connecting to signals coming from the
Connection Matrix, it is possible to have ACMP be ON continuously, OFF continuously, or switched on periodically based on a
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digital signal coming from the Connection Matrix. When ACMP is powered down, its output is low.
There are no Gain and Hysteresis selection for chopper ACMP compared to the ACMP0L and ACMP1L.
It's possible to select different reference sources for Chopper ACMP. It can be:
external voltage from pin;
divided internal voltage from internal reference source (from 32 mV to 2048 mV);
divided internal reference voltage from HD Buffer (64 steps);
divided VDDA voltage (64 steps).
For more information see Section 15.
The positive input of the Chopper ACMP can be connected to the Op Amp0 out or Op Amp1 out or In Amp out, or to the external
PIN.
The inputs of Chopper ACMP can be reconfigured while operating in AutoTrim mode. There is one configuration of inputs
(Figure 59) for case when Set0 (Digital Rheostat 0) signal is latched, and another configuration of Chopper ACMP inputs when
Set1 (Digital Rheostat 1) signal is latched. For example, M1 MUX can be configured to operate with In Amp out when Set0
(Digital Rheostat 0) is latched and Chopper_ACMP+ pin when Set1 (Digital Rheostat 1) is latched. The same way, “-” input of
Chopper ACMP can be configured to work with any of possible inputs when Set0 (Digital Rheostat 0) or Set1 (Digital Rheostat
1) are latched.
Note that the default configuration is the configuration for Set0 (Digital Rheostat 0) signal. When Chopper ACMP operates as
separate ACMP and AutoTrim function is disabled, inputs of Chopper ACMP are defined by registers [893:892].
Figure 59: Chopper ACMP Block Diagram
9.3 ACMP SAMPLING MODE
Both General Purpose Analog Comparators (ACMPL0 and ACMPL1) have an optional sampling mode. In this mode, ACMP is
enabled for the shortest amount of time after rising edge at Power Up input to get a valid data. Then ACMP latches its value and
goes sleep again.
Registers [610], [632] enable sampling mode for two comparators.
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9.4 ACMP TYPICAL PERFORMANCE
12
10
8
High To Low, Overdrive = 10 mV
6
4
2
0
Low to High, Overdrive = 10 mV
High to Low, Overdrive = 100 mV
Low to High, Overdrive = 100 mV
0
512
1024
1536
2048
Vref (mV)
Figure 60: Propagation Delay vs. Vref for ACMPx at T = 25 °C, VDD = 2.4 V to 5.5 V, Hysteresis = 0
190
ACMPx (T = -40°C)
ACMPx (T = 25°C)
170
ACMPx (T = 85°C)
150
130
110
90
70
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 61: ACMPx Power-On Delay vs. VDD at BG - Forced
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6
4
2
0
-2
-4
-6
-8
32
480
1024
1600
2048
Vref (mV)
Figure 62: ACMPx Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, VDD = 2.4 V to 5.5 V, Gain = 1
500
450
400
350
300
250
200
150
100
50
0
-50
-100
-150
-200
-250
32
480
1024
1600
2048
Vref (mV)
Figure 63: Chopper ACMP Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, VDD = 2.4 V to 5.5 V, Gain = 1
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8
T = 85 °C
T = 25 °C
7.5
T = -40 °C
7
6.5
6
5.5
5
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
Figure 64: ACMPx Current Consumption vs. VDD
50
45
40
35
30
25
T = 85 °C
T = 25 °C
T = -40 °C
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
Figure 65: Chopper ACMP Current Consumption vs. VDD (with 2.048 kHz Clock)
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10 Programmable Operational Amplifiers
10.1 GENERAL DESCRIPTION
The SLG47004 contains three operational amplifiers with rail-to-rail input and output. Two of them (Programmable Op Amps)
have the additional functions of driving internal analog FETs (Voltage Regulator and Current Sink modes) and Comparator
mode. The third Internal Op Amp is an amplifier with internal resistors, and can be configured as a difference amplifier with Gain
= 1. All three op amps can function as instrumentation amplifiers. The structures of the op amps are shown in Figure 66 and
Figure 67.
Figure 66: Programmable Operational Amplifier OA0, OA1 Internal Circuit
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Figure 67: Internal Operational Amplifier Circuit
Each of the two Programmable Op Amp inputs has a hardware connection to the external pin and an optional connection to the
internal voltage reference source, which makes it possible to create precise voltage or current source. For more detailed
description of op amp Vref sources see Section 15. The output of the operational amplifier is hardwired to an external pin. This
output can also be connected to the Programmable Trim block of rheostat macrocell, ACMP non-inverting input (ACMP0_L+ for
OA0, ACMP1_L+ for OA1), or control the corresponding Analog Switch, depending on the mode of operation. Each
Programmable Op Amp can also be configured as an analog comparator, in which case its output signal is connected to the
Connection Matrix through a dedicated buffer.
Each Programmable Op Amp has a programmable bandwidth that can be set by two register bits. In addition, internal charge
pump setting for each Op Amp must be changed according to bandwidth selection, see Table 54.
The bandwidths may vary up to +/-30 % over PVT. Each operational amplifier is factory trimmed. This trimming is independent of
the trimming associated with the onboard digital rheostat (system calibration).
The Internal operational amplifier shares its inputs with the Programmable Op Amps outputs. The voltage reference for the
internal amplifier can be sourced from either the internal or external Vref. Note that if the internal Vref is used as a source for the
instrumentation amplifier Vref, the user can optionally connect this Vref to the output pin, or disconnect the Vref from output pin
and use this pin as GPIO.
Also, if the Internal Op Amp is inactive (In Amp Mode is disabled), the user can use the In Amp_Vref pin as GPIO. The In
Amp_Out pin can be configured as GPI.
Table 54: Op Amp Bandwidth Settings
Op Amp0
Op Amp1
Op Amp2 (Internal)
Op Amp
Bandwidth
Selection
Bandwidth
Selection
Charge Pump
Frequency
Bandwidth
Selection
Charge Pump
Frequency
Bandwidth
Selection
Charge Pump
Frequency
Register Bit →
128 kHz
745 744
955
0
954
0
747 746
963
0
962
0
749 748
971
0
970
0
0
0
0
0
0
0
512 kHz
0
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1
2.048 MHz
8.192 MHz
1
0
1
0
1
0
1
1
1
0
1
0
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10.2 MODES OF OPERATION
In order to use any of the op amp macrocells in the GreenPAK Designer, the power up signal (PWR_UP) must be set to logic
High. By default, all op amp macrocells are turned off after SLG47004 startup. During power-up, outputs of all op amps will
remain in a Hi-Z state and then become valid (see parameter ton in Table 22).
Operational amplifiers turn-on time can be decreased by setting register bits [759:757] to 1. In this case op amps analog
supporting blocks are always turned on. Note that current consumption of op amp will be increased when op amp is powered
down and bits [759:757] is 1 (see Section 3.13).
See the list below for the op amp operation modes:
Operational Amplifier mode;
Instrumentation Amplifier mode;
Analog Comparator mode;
Voltage Regulator mode;
Current Sink mode.
10.2.1 Operational Amplifier Mode
In this mode, the Programmable Op Amp operates as a conventional operational amplifier. Also, the Programmable Op Amp
can source the corresponding non-inverting ACMP input (see ACMP macrocell settings). The output of the Programmable Op
Amp macrocell is in a Hi-Z state while the macrocell is turned off.
Figure 68 shows the example of differential amplifier with input offset voltage compensation with help of digital rheostat and
programmable trim block. Zero input voltage equal to output voltage VOUT = VDD/2.
Figure 68: Example of Input Offset Voltage Compensation
10.2.2 Instrumentation Amplifier Mode
If this mode is active (Matrix Output [98] is High level), the two Programmable Op Amps and the single Internal Op Amp work
together in Instrumentation Amplifier configuration, shown in Figure 69. When power up signal is logic LOW the output of In Amp
is in Hi-Z state.
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Figure 69: Instrumentation Amplifier Structure
The absolute value of internal resistors R1, R2, R3, R4 is <RINT> kΩ ±20 %. The mismatch between resistors in one IC is
<RINT_TL> %. The resistors Rf and Rg are user defined external resistors. The output voltage VOUT of the instrumentation
amplifier shown in Figure 69 is
VOUT = (1 + 2Rf / Rg)(VIN+ - VIN-) + VREF
The user can trim both the gain and the offset error of the instrumentation amplifier using two of the Rheostats from the
SLG47004. Figure 70 shows the configuration of the instrumentation amplifier in this scenario.
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Figure 70: Instrumentation Operational Amplifier Configuration for Users Trim
Note that in Figure 70, the Demux connects to the Vref external input with an internal buffer (register [756] = 1). This allows us to
eliminate the influence of resistor divider Rdiv and Rheostat0 on instrumentation amplifier.
It is possible to use a built-in Auto-Trim function for either setting the zero point of the Wheatstone bridge sensor using the In
Amp or tuning a system output voltage to the desired level. However, the following limitations exist for using the built-in Auto-
Trim function to trim both total system offset and system gain errors:
- The Auto-Trim procedures of total offset compensation and system gain error must be done iteratively starting and finishing
with the total offset compensation: 1st iteration - offset compensation, 2nd iteration - gain trim, 3rd iteration - offset
compensation. Extra iterations can be added to achieve a better accuracy. The last iteration should be an offset
compensation.
- Total system offset (sensor offset + Op Amp1 offset + Op Amp2 offset) must not be greater than Vsensor_output_range/2.
It's possible to power external components like bridge or ADC from internal HD Buffer of SLG47004 to improve accuracy of
system.
10.2.3 Analog Comparator Mode
Both operational amplifiers have an Analog Comparator mode in which they work as conventional rail-to-rail comparators.
10.2.4 Voltage Regulator Mode
In this mode, the op amp output drives P-FET (part of Analog Switch). Note that FETs of Analog Switches have different
resistances. Analog Switch 0 has Rds_PMOS << Rds_NMOS, while Analog Switch 1 has Rds_NMOS << Rds_PMOS. That's
why it is recommended to implement voltage regulator mode using Analog Switch 0. In this mode the op amp output is High
when the macrocell is turned off. Figure 71 (A) shows the typical implementation of the voltage source function. Optionally, the
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user can use this mode to implement a constant current source with load connected to ground (Figure 71, B, C). Note that op
amp must operate in operational amplifier mode (register 750 = 0 for Op Amp0, register 751 = 0 for Op Amp1).
Figure 71: Typical Implementation of Voltage Regulator (A) and Current Sources (B, C)
Note that in this mode only an enhanced P channel FET of An_Sw_0 is used.
10.2.5 Current Sink Mode
Also, the op amp output can drive the N-FET (part of the Analog Switch) in order to implement a constant current sink. Note that
FETs of Analog Switches have different resistances. Analog Switch 0 has Rds_PMOS << Rds_NMOS, while Analog Switch 1
has Rds_NMOS << Rds_PMOS. That's why it is recommended to implement current sink mode using Analog Switch 1. In this
mode, the op amp output is LOW when the macrocell is turned off. Figure 72 (A) shows a typical implementation of this Current
Sink Function. Note that op amp must operate in operational amplifier mode (register 750 = 0 for Op Amp0, register 751 = 0 for
Op Amp1).
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Figure 72: Constant Current Sink
Note that in this mode only an enhanced N channel FET of An_Sw_1 is used.
10.3 OP AMPS TYPICAL PERFORMANCE
TA = 25 °C, VDDA = 5.0 V, VSS = GND, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, RL = 1 MΩ to VL, CL = 80 pF, unless otherwise
stated.
275
250
Opampx, 128 kHz, 2.4 V
225
Opampx, 128 kHz, 5.5 V
200
175
150
125
100
75
50
25
0
T (°C)
Figure 73: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 128 kHz
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250
Opampx, 512 kHz, 5.5 V
225
Opampx, 512 kHz, 2.4 V
200
175
150
125
100
75
50
25
0
T (°C)
Figure 74: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 512 kHz
225
200
Opampx, 2 MHz, 5.5 V
175
Opampx, 2 MHz, 2.4 V
150
125
100
75
50
25
0
T (°C)
Figure 75: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 2 MHz
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200
Opampx, 8 MHz, 2.4 V
Opampx, 8 MHz, 5.5 V
175
150
125
100
75
50
25
0
T (°C)
Figure 76: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 8 MHz
250
225
200
175
150
125
100
75
Internal OA, 128 kHz, 2.4 V
50
Internal OA, 128 kHz, 5.5 V
25
0
T (°C)
Figure 77: Internal Op Amp Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 128 kHz
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225
200
175
150
125
100
75
Internal OA, 512 kHz, 2.4 V
Internal OA, 512 kHz, 5.5 V
50
25
0
T (°C)
Figure 78: Internal Op Amp at Input CM Voltage = VDD/2, BW = 512 kHz
250
225
200
175
150
125
100
75
Internal OA, 2 MHz, 2.4 V
Internal OA2, 2 MHz, 5.5 V
50
25
0
T (°C)
Figure 79: Internal Op Amp at Input CM Voltage = VDD/2, BW = 2 MHz
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200
Internal OA, 8 MHz, 2.4 V
Internal OA, 8 MHz, 5.5 V
175
150
125
100
75
50
25
0
T (°C)
Figure 80: Internal Op Amp Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 8 MHz
110
100
90
80
70
60
50
40
OAx, 128 kHz, 2.4 V
30
OAx, 512 kHz, 2.4 V
OAx, 2 MHz, 2.4 V
OAx, 8 MHz, 2.4 V
20
10
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Input CM Voltage (V)
Figure 81: OpAmp0, 1 Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 2.4 V
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110
100
90
80
70
60
50
40
OAx, 128 kHz, 5.5 V
OAx, 512 kHz, 5.5 V
OAx, 2 MHz, 5.5 V
OAx, 8 MHz, 5.5 V
30
20
10
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
Input CM Voltage (V)
Figure 82: OpAmp0, 1 Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 5.5 V
130
120
110
100
90
80
70
60
50
Internal OA, 512 kHz, 2.4 V
40
Internal OA, 8 MHz, 2.4 V
Internal OA, 2 MHz, 2.4 V
Internal OA, 128 kHz, 2.4 V
30
20
10
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Input CM Voltage (V)
Figure 83: Internal OpAmp Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 2.4 V
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
130
120
110
100
90
80
70
60
50
Internal OA, 512 kHz, 5.5 V
40
Internal OA, 8 MHz, 5.5 V
Internal OA, 2 MHz, 5.5 V
Internal OA, 128 kHz, 5.5 V
30
20
10
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
Input CM Voltage (V)
Figure 84: Internal OpAmp Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 5.5 V
40
T = -40°C
39
T = 25°C
T = 85°C
38
37
36
35
34
33
32
31
30
2.5
2.8
3.1
3.4
3.7
4
4.3
4.6
4.9
5.2
5.5
VDD (V)
Figure 85: Quiescent Current vs. Power Supply Voltage for BW = 128 kHz
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
96
T = -40°C
T = 25°C
94
T = 85°C
92
90
88
86
84
82
2.5
2.8
3.1
3.4
3.7
4
4.3
4.6
4.9
5.2
5.5
VDD (V)
Figure 86: Quiescent Current vs. Power Supply Voltage for BW = 512 kHz
246
244
242
240
238
236
234
232
230
228
226
T = -40°C
T = 25°C
T = 85°C
2.5
2.8
3.1
3.4
3.7
4
4.3
4.6
4.9
5.2
5.5
VDD (V)
Figure 87: Quiescent Current vs. Power Supply Voltage for BW = 2 MHz
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
650
T = -40°C
T = 25°C
640
T = 85°C
630
620
610
600
590
580
570
2.5
2.8
3.1
3.4
3.7
4
4.3
4.6
4.9
5.2
5.5
VDD (V)
Figure 88: Quiescent Current vs. Power Supply Voltage or BW = 8 MHz
140
130
120
110
100
90
200
150
100
50
Gain, BW = 128 kHz, VDD = 2.4 V
Gain, BW = 128 kHz, VDD = 3.3 V
Gain, BW = 128 kHz, VDD = 5.5 V
Phase, BW = 128 kHz, VDD = 2.4 V
Phase, BW = 128 kHz, VDD = 3.3 V
Phase, BW = 128 kHz, VDD = 5.5 V
80
70
60
50
0
40
30
-50
-100
-150
-200
20
10
0
-10
-20
-30
-40
0.001
0.01
0.1
1
10
100
1000
10000
100000
1000000
10000000 100000000
Frequency (Hz)
Figure 89: OA0 Open Loop Gain and Phase vs. Frequency for BW = 128 kHz
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
140
200
150
100
50
130
120
110
100
90
Gain, BW = 512 kHz, VDD = 2.4 V
Gain, BW = 512 kHz, VDD = 3.3 V
Gain, BW = 512 kHz, VDD = 5.5 V
Phase, BW = 512 kHz, VDD = 2.4 V
Phase, BW = 512 kHz, VDD = 3.3 V
Phase, BW = 512 kHz, VDD = 5.5 V
80
70
60
50
0
40
30
-50
-100
-150
20
10
0
-10
-20
-30
-40
-200
0.001
0.01
0.1
1
10
100
1000
10000
100000
1000000
10000000
100000000
Frequency (Hz)
Figure 90: OA0 Open Loop Gain and Phase vs. Frequency for BW = 512 kHz
140
200
150
100
50
Gain, BW = 2 MHz, VDD = 2.4 V
Gain, BW = 2 MHz, VDD = 3.3 V
Gain, BW = 2 MHz, VDD = 5.5 V
Phase, BW = 2 MHz, VDD = 2.4 V
Phase, BW = 2 MHz, VDD = 3.3 V
Phase, BW = 2 MHz, VDD = 5.5 V
130
120
110
100
90
80
70
60
50
0
40
30
-50
-100
-150
-200
20
10
0
-10
-20
-30
-40
0.001
0.01
0.1
1
10
100
1000
10000
100000
1000000
10000000
Frequency (Hz)
Figure 91: OA0 Open Loop Gain and Phase vs. Frequency for BW = 2 MHz
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
140
200
150
100
50
Gain, BW = 8 MHz, VDD = 2.4 V
130
120
110
100
90
Gain, BW = 8 MHz, VDD = 3.3 V
Gain, BW = 8 MHz, VDD = 5.5 V
Phase, BW = 8 MHz, VDD = 2.4 V
Phase, BW = 8 MHz, VDD = 3.3 V
Phase, BW = 8 MHz, VDD = 5.5 V
80
70
60
50
0
40
30
-50
-100
-150
-200
20
10
0
-10
-20
-30
-40
0.001
0.01
0.1
1
10
100
1000
10000
100000
1000000
10000000
Frequency (Hz)
Figure 92: OA0 Open Loop Gain and Phase vs. Frequency for BW = 8 MHz
140
130
120
110
100
90
200
150
100
50
Gain, BW = 128 kHz, VDD = 2.4 V
Gain, BW = 128 kHz, VDD = 3.3 V
Gain, BW = 128 kHz, VDD = 5.5 V
Phase, BW = 128 kHz, VDD = 2.4 V
Phase, BW = 128 kHz, VDD = 3.3 V
Phase, BW = 128 kHz, VDD = 5.5 V
80
70
60
50
0
40
30
-50
-100
-150
-200
20
10
0
-10
-20
-30
-40
0.001
0.01
0.1
1
10
100
1000
10000
100000
1000000
10000000
Frequency (Hz)
Figure 93: OA1 Open Loop Gain and Phase vs. Frequency for BW = 128 kHz
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
140
200
Gain, BW = 512 kHz, VDD = 2.4 V
130
Gain, BW = 512 kHz, VDD = 3.3 V
120
Gain, BW = 512 kHz, VDD = 5.5 V
150
100
50
110
100
90
Phase, BW = 512 kHz, VDD = 2.4 V
Gain, BW = 512 kHz, VDD = 3.3 V
Gain, BW = 512 kHz, VDD = 5.5 V
80
70
60
50
0
40
30
-50
-100
-150
-200
20
10
0
-10
-20
-30
-40
0.001
0.01
0.1
1
10
100
1000
10000
100000
1000000
10000000
Frequency (Hz)
Figure 94: OA1 Open Loop Gain and Phase vs. Frequency for BW = 512 kHz
140
130
120
110
100
90
200
Gain, BW = 2 MHz, VDD = 2.4 V
Gain, BW = 2 MHz, VDD = 3.3 V
Gain, BW = 2 MHz, VDD = 5.5 V
Phase, BW = 2 MHz, VDD = 2.4 V
Phase, BW = 2 MHz, VDD = 3.3 V
Gain, BW = 2 MHz, VDD = 5.5 V
150
100
50
80
70
60
50
0
40
30
-50
-100
-150
-200
20
10
0
-10
-20
-30
-40
0.001
0.01
0.1
1
10
100
1000
10000
100000
1000000
10000000
Frequency (Hz)
Figure 95: OA1 Open Loop Gain and Phase vs. Frequency for BW = 2 MHz
Revision 2.4
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
140
200
150
100
50
Gain, BW = 8 MHz, VDD = 2.4 V
130
120
110
100
90
Gain, BW = 8 MHz, VDD = 3.3 V
Gain, BW = 8 MHz, VDD = 5.5 V
Phase, BW = 8 MHz, VDD = 2.4 V
Phase, BW = 8 MHz, VDD = 3.3 V
Phase, BW = 8 MHz, VDD = 5.5 V
80
70
60
50
0
40
30
-50
-100
-150
-200
20
10
0
-10
-20
-30
-40
0.001
0.01
0.1
1
10
100
1000
10000
100000
1000000
10000000
Frequency (Hz)
Figure 96: OA1 Open Loop Gain and Phase vs. Frequency for BW = 8 MHz
10
0
BW = 128 kHz
BW = 512 kHz
BW = 2 MHz
BW = 8 MHz
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0.01
0.10
1.00
10.00
100.00
1000.00
10000.00
f (kHz)
Figure 97: PSRR vs. Frequency VDD = 2.4 V to 5.5 V
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (2 s/div)
Figure 98: 0.1 Hz to 10 Hz Noise, BW = 128 kHz
Time (2 s/div)
Figure 99: 0.1 Hz to 10 Hz Noise, BW = 512 kHz
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (2 s/div)
Figure 100: 0.1 Hz to 10 Hz Noise, BW = 2 MHz
Time (2 s/div)
Figure 101: 0.1 Hz to 10 Hz Noise, BW = 2 MHz
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
0
-10
-20
BW = 128 kHz
BW = 512 kHz
-30
BW = 2 MHz
-40
BW = 8 MHz
-50
-60
-70
-80
-90
-100
-110
-120
-130
10
100
1 000
10 000
100 000
1 000 000
10 000 000
f (Hz)
Figure 102: Channel Separation vs. Frequency
700
BW = 128 kHz
BW = 512 kHz
BW = 2 MHz
BW = 8 MHz
600
500
400
300
200
100
0
10
100
1 000
10 000
100 000
1 000 000
f (Hz)
Figure 103: Op Ampx Noise Voltage Density vs. Frequency
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
85
80
75
70
65
60
55
128 kHz, 5.5 V, Falling
128 kHz, 5.5 V, Rising
128 kHz, 3.3 V, Falling
128 kHz, 3.3 V, Rising
128 kHz, 2.4 V, Falling
128 kHz, 2.4 V, Rising
50
T (°C)
Figure 104: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 128 kHz
340
320
300
280
260
240
220
512 kHz, 5.5 V, Falling
512 kHz, 5.5 V, Rising
512 kHz, 3.3 V, Falling
512 kHz, 3.3 V, Rising
512 kHz, 2.4 V, Falling
512 kHz, 2.4 V, Rising
T (°C)
Figure 105: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 512 kHz
Datasheet
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
2100
2 MHz, 5.5 V, Falling
2 MHz, 5.5 V, Rising
1900
2 MHz, 3.3 V, Rising
2 MHz, 2.4 V, Rising
2 MHz, 3.3 V, Falling
2 MHz, 2.4 V, Falling
1700
1500
1300
1100
900
700
T (°C)
Figure 106: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 2 MHz
5400
4900
4400
3900
3400
2900
2400
1900
1400
900
8 MHz, 5.5 V, Rising
8 MHz, 3.3 V, Rising
8 MHz, 2.4 V, Rising
8 MHz, 5.5 V, Falling
8 MHz, 2.4 V, Falling
8 MHz, 3.3 V, Falling
T (°C)
Figure 107: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 8 MHz
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (20 μs/div)
Figure 108: Small Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 128 kHz
Time (20 μs/div)
Figure 109: Small Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 512 kHz
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (10 μs/div)
Figure 110: Small Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 2 MHz
Time (10 μs/div)
Figure 111: Small Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 8 MHz
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (5 μs/div)
Figure 112: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 128 kHz
Time (5 μs/div)
Figure 113: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 512 kHz
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (5 μs/div)
Figure 114: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 2 MHz
Time (0.2 μs/div)
Figure 115: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 8 MHz
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (20 μs/div)
Figure 116: Large Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 80 pF, BW = 128 kHz
Time (20 μs/div)
Figure 117: Large Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 80 pF, BW = 512kHz
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (20 μs/div)
Figure 118: Large Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 80 pF, BW = 2 MHz
Time (20 μs/div)
Figure 119: Large Signal Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 80 pF, BW = 8 MHz
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (20 μs/div)
Figure 120: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 128 kHz
Time (20 μs/div)
Figure 121: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 512 kHz
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (5 μs/div)
Figure 122: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 2 MHz
Time (2.5 μs/div)
Figure 123: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 8 MHz
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (60 μs/div)
Figure 124: Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 128 kHz
Time (60 μs/div)
Figure 125: Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 512 kHz
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (30 μs/div)
Figure 126: Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 2 MHz
Time (15 μs/div)
Figure 127: Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 8 MHz
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (60 μs/div)
Figure 128: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 128 kHz
Time (60 μs/div)
Figure 129: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 512 kHz
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Time (30 μs/div)
Figure 130: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 2 MHz
Time (15 μs/div)
Figure 131: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 kΩ, CL = 60 pF, BW = 8 MHz
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
80
Overshoot (40 mV p-p)
70
Overshoot (100 mV p-p)
Undershoot (40 mV p-p)
60
Undershoot (100 mV p-p)
50
40
30
20
10
0
100
1000
10000
CLOAD (pF)
Figure 132: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 128 kHz
80
70
60
50
40
30
20
10
0
Overshoot (40 mV p-p)
Overshoot (100 mV p-p)
Undershoot (40 mV p-p)
Undershoot (100 mV p-p)
100
1000
10000
CLOAD (pF)
Figure 133: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 512 kHz
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
90
Overshoot (40 mV p-p)
80
Overshoot (100 mV p-p)
Undershoot (100 mV p-p)
Undershoot (40 mV p-p)
70
60
50
40
30
20
10
0
100
1000
10000
CLOAD (pF)
Figure 134: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 2 MHz
90
80
70
60
50
40
30
20
10
0
Undershoot (40 mV p-p)
Overshoot (40 mV p-p)
470
100
CLOAD (pF)
Figure 135: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 8 MHz
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Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
220
Output CM Voltage Low, Rload = 600 Ω, VDD = 5.5 V
210
Output CM Voltage Low, Rload = 600 Ω, VDD = 3.3 V
Output CM Voltage Low, Rload = 600 Ω, VDD = 2.4 V
200
190
180
170
160
150
140
130
120
110
100
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 136: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 128 kHz, RLOAD = 600 Ω
2.9
2.6
2.3
2
1.7
1.4
Output CM Voltage Low, Rload = 50 kΩ, VDD = 5.5 V
1.1
Output CM Voltage Low, Rload = 50 kΩ, VDD = 3.3 V
Output CM Voltage Low, Rload = 50 kΩ, VDD = 2.4 V
0.8
0.5
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 137: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 128 kHz, RLOAD = 50 kΩ
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
360
Output CM Voltage High, Rload = 600 Ω, VDD = 5.5 V
350
Output CM Voltage High, Rload = 600 Ω, VDD = 3.3 V
340
Output CM Voltage High, Rload = 600 Ω, VDD = 2.4 V
330
320
310
300
290
280
270
260
250
240
230
220
210
200
190
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 138: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 128 kHz, RLOAD = 600 Ω
5
4.5
4
3.5
Output CM Voltage High, Rload = 50 kΩ, VDD = 5.5 V
Output CM Voltage High, Rload = 50 kΩ, VDD = 2.4 V
3
Output CM Voltage High, Rload = 50 kΩ, VDD = 3.3 V
2.5
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 139: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 128 kHz, RLOAD = 50 kΩ
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180
Output CM Voltage Low, Rload = 600 Ω, VDD = 5.5 V
Output CM Voltage Low, Rload = 600 Ω, VDD = 3.3 V
170
Output CM Voltage Low, Rload = 600 Ω, VDD = 2.4 V
160
150
140
130
120
110
100
90
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 140: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 512 kHz, RLOAD = 50 kΩ
2.5
2
1.5
Output CM Voltage Low, Rload = 50 kΩ, VDD = 5.5 V
1
Output CM Voltage Low, Rload = 50 kΩ, VDD = 3.3 V
Output CM Voltage Low, Rload = 50 kΩ, VDD = 2.4 V
0.5
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 141: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 512 kHz, RLOAD = 50 kΩ
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GreenPAK Programmable Mixed-Signal Matrix
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290
Output CM Voltage High, Rload = 600 Ω, VDD = 5.5 V
Output CM Voltage High, Rload = 600 Ω, VDD = 3.3 V
270
Output CM Voltage High, Rload = 600 Ω, VDD = 2.4 V
250
230
210
190
170
150
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 142: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 512 kHz, RLOAD = 600 Ω
4.4
4.1
3.8
3.5
3.2
2.9
Output CM Voltage High, Rload = 50 kΩ, VDD = 5.5 V
2.6
Output CM Voltage High, Rload = 50 kΩ, VDD = 2.4 V
Output CM Voltage High, Rload = 50 kΩ, VDD = 3.3 V
2.3
2
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 143: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 512kHz, RLOAD = 50 kΩ
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GreenPAK Programmable Mixed-Signal Matrix
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140
Output CM Voltage Low, Rload = 600 Ω, VDD = 5.5 V
Output CM Voltage Low, Rload = 600 Ω, VDD = 3.3 V
130
Output CM Voltage Low, Rload = 600 Ω, VDD = 2.4 V
120
110
100
90
80
70
60
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 144: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 2 MHz, RLOAD = 600 Ω
2.5
2
1.5
1
Output CM Voltage Low, Rload = 50 kΩ, VDD = 5.5 V
Output CM Voltage Low, Rload = 50 kΩ, VDD = 3.3 V
0.5
Output CM Voltage Low, Rload = 50 kΩ, VDD = 2.4 V
0
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 145: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 2 MHz, RLOAD = 50 kΩ
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220
200
180
160
140
120
Output CM Voltage High, Rload = 600 Ω, VDD = 5.5 V
Output CM Voltage High, Rload = 600 Ω, VDD = 2.4 V
Output CM Voltage High, Rload = 600 Ω, VDD = 3.3 V
100
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 146: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 2 MHz, RLOAD = 600 Ω
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
Output CM Voltage High, Rload = 50 kΩ, VDD = 5.5 V
Output CM Voltage High, Rload = 50 kΩ, VDD = 2.4 V
1.8
Output CM Voltage High, Rload = 50 kΩ, VDD = 3.3 V
1.6
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 147: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 2 MHz, RLOAD = 50 kΩ
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100
Output CM Voltage Low, Rload = 600 Ω, VDD = 5.5 V
Output CM Voltage Low, Rload = 600 Ω, VDD = 3.3 V
Output CM Voltage Low, Rload = 600 Ω, VDD = 2.4 V
90
80
70
60
50
40
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 148: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 8MHz, RLOAD = 600 Ω
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
Output CM Voltage Low, Rload = 50 kΩ, VDD = 5.5 V
Output CM Voltage Low, Rload = 50 kΩ, VDD = 3.3 V
Output CM Voltage Low, Rload = 50 kΩ, VDD = 2.4 V
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 149: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 8 MHz, RLOAD = 50 kΩ
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130
Output CM Voltage High, Rload = 600 Ω, VDD = 5.5 V
Output CM Voltage High, Rload = 600 Ω, VDD = 3.3 V
120
Output CM Voltage High, Rload = 600 Ω, VDD = 2.4 V
110
100
90
80
70
60
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 150: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 8 MHz, RLOAD = 600 Ω
16
14
12
10
8
Output CM Voltage High, Rload = 50 kΩ, VDD = 5.5 V
Output CM Voltage High, Rload = 50 kΩ, VDD = 2.4 V
6
4
2
0
Output CM Voltage High, Rload = 50 kΩ, VDD = 3.3 V
-40
-30
-20
-10
0
10
20
T (°C)
30
40
50
60
70
80
Figure 151: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 8 MHz, RLOAD = 50 kΩ
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GreenPAK Programmable Mixed-Signal Matrix
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60
50
40
30
20
10
0
128 kHz, Rising
512 kHz, Rising
2 MHz, Rising
8 MHz, Rising
2.4
2.7
3.0
3.3
3.6
3.9
VDD (V)
4.2
4.5
4.8
5.1
5.4
Figure 152: Overload Recovery Time vs. Power Supply Voltage RL= 50 kΩ; G = 1 V/V, Rising
1.4
1.2
1
128 kHz, Falling
512 kHz, Falling
2 MHz, Falling
8 MHz, Falling
0.8
0.6
0.4
0.2
0
2.4
2.7
3.0
3.3
3.6
3.9
VDD (V)
4.2
4.5
4.8
5.1
5.4
Figure 153: Overload Recovery Time vs. Power Supply Voltage RL= 50 kΩ; G = 1 V/V, Falling
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Time (10 μs/div)
Figure 154: Output Response to Power Down Signal G = 1 V/V; RL = 50 kΩ; CL = 20 pF; VIN = VS/2, BW = 128 kHz
Time (2 μs/div)
Figure 155: Output Response to Power Down Signal G = 1 V/V; RL = 50 kΩ; CL = 20 pF; VIN = VS/2, BW = 512 kHz
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GreenPAK Programmable Mixed-Signal Matrix
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Time (1 μs/div)
Figure 156: Output Response to Power Down Signal G = 1 V/V; RL = 50 kΩ; CL = 20 pF; VIN = VS/2, BW = 2 MHz
Time (1 μs/div)
Figure 157: Output Response to Power Down Signal G = 1 V/V; RL = 50 kΩ; CL = 20 pF; VIN = VS/2, BW = 8 MHz
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GreenPAK Programmable Mixed-Signal Matrix
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40
Turn-On Time @ T = -40 °C
Turn-On Time @ T = 25 °C
Turn-On Time @ T = 85 °C
35
Turn-Off Time @ T = -40 °C
Turn-Off Time @ T = 25 °C
Turn-Off Time @ T = 85 °C
30
25
20
15
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 158: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 128 kHz
20
18
16
14
12
10
8
Turn-Off Time @ T = -40 °C
Turn-Off Time @ T = 25 °C
Turn-Off Time @ T = 85 °C
Turn-On Time @ T = -40 °C
Turn-On Time @ T = 25 °C
6
4
2
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 159: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 512 kHz
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18
16
14
12
10
Turn-Off Time @ T = -40 °C
Turn-Off Time @ T = 25 °C
Turn-Off Time @ T = 85 °C
Turn-On Time @ T = -40 °C
Turn-On Time @ T = 25 °C
Turn-On Time @ T = 85 °C
8
6
4
2
0
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 160: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 2 MHz
18
16
14
12
10
8
Turn-Off Time @ T = -40 °C
Turn-Off Time @ T = 25 °C
Turn-Off Time @ T = 85 °C
Turn-On Time @ T = -40 °C
Turn-On Time @ T = 25 °C
Turn-On Time @ T = 85 °C
6
4
2
0
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 161: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 8MHz
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600
500
400
300
200
100
0
BW = 8 MHz
BW = 2 MHz
BW = 512 kHz
BW = 128 kHz
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
Figure 162: Opamps Quiescent Current Consumption vs. VDD
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GreenPAK Programmable Mixed-Signal Matrix
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11 Analog Switch Macrocell
11.1 ANALOG SWITCH GENERAL DESCRIPTION
The SLG47004 contains two single-pole/single throw (SPST) normally open analog switches (AS). The structure of the Analog
Switches is shown in Figure 163 and Figure 164.
Each analog switch can be controlled from the following sources:
Connection matrix
Operational Amplifier macrocell.
Small NMOS (small PMOS) of Analog Switch must be enabled when macrocell is controlled by logic signal from connection
matrix. Otherwise, small NMOS (small PMOS) must be disabled when macrocell is controlled by op amp.
Table 55 and Table 56 show possible operation modes of analog switches.
Figure 163: Analog Switch 0 Control Circuit
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Figure 164: Analog Switch 1 Control Circuit
Table 55: Analog Switch 0 Modes of Operation
Half Bridge
Mode Enable
Matrix/Op
Amp Control
Small nMOS
Enable
Register [740] Register [738] Register [736]
Mode of Operation
Analog Switch mode with big pMOS only (control from connection
matrix)
0
0
0
Analog Switch mode with all FETs enabled (control from connection
matrix)
0
0
1
0
1
x
1
0
0
Voltage Regulator mode
Half Bridge mode with big pMOS only (control from connection ma-
trix)
Half Bridge mode with all FETs enabled (control from connection
matrix)
1
x
1
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Table 56: Analog Switch 1 Modes of Operation
Half Bridge
Mode Enable
Matrix/Op
Amp Control
Small pMOS
Enable
Register [740] Register [739] Register [737]
Mode of Operation
Analog Switch mode with big nMOS only (control from connection
matrix)
0
0
0
Analog Switch mode with all FETs enabled (control from connection
matrix)
0
0
1
0
1
x
1
0
0
Current Sink mode
Half Bridge mode with big nMOS only (control from connection ma-
trix)
Half Bridge mode with all FETs enabled (control from connection
matrix)
1
x
1
11.2 HALF BRIDGE MODE
Two switches can be externally connected in series to create a half bridge. Please refer to tables Table 55 and Table 56 to
enable half bridge mode. Additional logic will be connected to the analog switches to simplify control. Figure 165 shows the half
bridge structure with two analog switches.
Figure 165: Structure of Half Bridge
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11.3 ANALOG SWITCHES TYPICAL PERFORMANCE
70
60
AS0 VDD = 2.4 V
AS1 VDD = 2.4 V
50
40
30
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
VIN (V)
Figure 166: Typical RON vs. Input Voltage (Vi) for Vi = 0 to VDDA, LOAD = 1 mA, VDDA = 2.4 V
I
40
35
30
25
20
15
10
5
AS0 VDD = 5.5 V
AS1 VDD = 5.5 V
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VIN (V)
Figure 167: Typical RON vs. Input Voltage (Vi) for Vi = 0 to VDDA, LOAD = 1 mA, VDDA = 5.5 V
I
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240
AS0 (T = -40 °C)
AS1 (T = -40°C)
AS0 (T = 25 °C)
AS1 (T = 25 °C)
AS0 (T = 85 °C)
AS1 (T = 85 °C)
220
200
180
160
140
120
100
80
60
40
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 168: Turn-On Time vs. VDD at RLOAD = 100 Ω to GND, VIN = VDD/2
450
400
350
300
250
200
150
100
50
AS0 (T = -40 °C)
AS1 (T = -40°C)
AS0 (T = 25 °C)
AS1 (T = 25 °C)
AS0 (T = 85 °C)
AS1 (T = 85 °C)
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 169: Turn-Off Time vs. VDD at RLOAD = 100 Ω to GND, VIN = VDD/2
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GreenPAK Programmable Mixed-Signal Matrix
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12 Digital Rheostats and Programmable Trim Block
The SLG47004 contains two 10-bit Digital Rheostats. The structure of both macrocells is shown in Figure 170. The range of
digital code that corresponds to the rheostat resistance ranges from 0 to 1023 (1024 taps). Code 0 corresponds to the minimum
resistance between the RHx_A and RHx_B terminals. As the code value increases, the resistance between the RHx_A and
RHx_B terminals monotonically increases. Consequently, when the code value decreases, the resistance between the RH0_A
and RH0_B terminals decreases as well (see Section 12.2). The voltage on any rheostat pin can be in the range from AGND to
VDDA, as well as be dynamically changed during operation.
To guarantee proper operation of digital rheostats charge pump must be turned on (matrix input [86] must be logic High or
registers [912] = 1, [913] = 1). Optionally user can turn off rheostats charge pump to decrease energy consumption. But it's
strongly recommended to use the charge pump if VDD < 4.5 V.
It is possible to use the rheostat in the following different modes:
Changing the Rheostat value using the I2C interface;
Manually changing the rheostat value using clock and up/down signals, similar to the counter;
Using the Built-in Auto-Trim mode, where the rheostat value change is done using a special logic based on the signal from
the Chopper ACMP.
The Programmable Trim (PT) blocks of rheostats macrocell contain analog MUXs, digital MUXs, Chopper ACMP, and additional
logic. The two analog MUXs (M1 and M2) and the Chopper ACMP are both shared between the two rheostats. All analog and
digital MUXs are set by NVM bits and can be overwritten with I2C.
The M_CK0 and M_CK1 MUXs select the clock source from internal pre-dividers of the internal oscillators or from the
connection matrix. The internal clock sources for the rheostats are OSC0, OSC0/8, OSC0/64, OSC0/512, OSC0/4096,
OSC0/32768, OSC0/262144, OSC1, OSC1/8, OSC1/64, and OSC1/512. The PT blocks of the rheostat use the same clock
scheme as Counter/Delay Macrocells (refer to 16.5). M_CH0 and M_CH1 select the Chopper comparator or a matrix output as
the signal source for the main rheostat up/down counter direction. The output of the Chopper ACMP is connected with the
Up/Down inputs of the PT blocks by default. The output of the Chopper ACMP can be optionally inverted by setting register
[882] to “1”.
M1 MUX selects the input for the Chopper comparator to be connected either internally to one of 3 integrated op amps (Op
Amp0 out, Op Amp1 out, In Amp Out) or externally to a PIN. M2 MUX is simplified symbol of Chopper ACMP reference selection
blocks. The Chopper ACMP reference ("-" input) can be: analog signal from pin, divided internal Vref voltage (6-bit divider), or
divide VDDA voltage (6-bit divider). In Auto-Trim mode each of Rheostats has it own settings for Chopper ACMP inputs. For more
information about Chopper ACMP Vref see Section 9.2.
The power-up signal for the Chopper ACMP can be handled either by matrix output signal or Set0/Set1 signal from the PT
macrocell. In Auto-Trim mode (Auto_Cal _Dis_RHx NVM bit = 0) additional internal logic enables the clocking of the
corresponding PT macrocell counter and disables clocking when one of the stop conditions is reached. See a detailed
description in Section 12.4. In Figure 170 when Auto_Cal _Dis_RHx NVM bit = 0 (Auto-Trim mode is enabled), the clocking
pulses for the internal PT macrocell counter are under control of additional logic. When Auto_Cal _Dis_RHx NVM bit = 1 (Auto-
Trim mode is disabled), all additional logics (Set signal, internal Set signal, Idle/Active signal) operate the same way, but clock
pulses are always enabled and generated externally by the user. Calibration channel can be selected automatically (1st channel
is channel 0, second channel is channel 1) or can be set manually by registers [893:892].
The inputs of Chopper ACMP can be reconfigured while operating in Auto-Trim mode. There is one configuration of inputs (M1,
M2 configuration, Figure 170) for the case when Set0 signal is latched, and another configuration of M1, M2 MUXs when Set1
signal is latched. For example, M1 MUX can be configured to operate with In Amp out when Set0 is latched and
Chopper_ACMP+ pin when Set1 is latched. The same way, M2 can be configured to work with any of M2 inputs when Set0 or
Set1 are latched. Note that the default configuration is the configuration for Set0 signal. When Chopper ACMP operates as
separate ACMP and Auto-Trim function is disabled, M1 and M2 MUXs operates with configuration for Set0 signal.
Keep in mind that two Auto-Trim processes cannot be done simultaneously. When the Auto-Trim process for one rheostat is
active, all signals on the Set input for another rheostat will be ignored. See a detailed description in 12.4.1. The initial user
defined value of Digital Rheostat resistance can be programmed into the NVM. The initial value will be loaded during the Power-
On event and this value will be used as the initial rheostat resistance, as well as a starting point for count down or count up.
Both read and write operations are allowed for rheostat resistance value, stored in NVM. Also, both read and write operations
are allowed for current rheostat resistance value. RH0 read operation - registers [1561:1552], write operation - registers
[1545:1536]. RH1 read operation - registers [1689:1680], write operation - registers [1673:1664].
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Figure 170: Programmable Trim Blocks and Digital Rheostat’s Internal Circuit
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PT macrocell signals:
“Set”: external Set signal begins the Auto-Trim process when Auto_Cal _Dis_RHx bit is cleared (registers [901]). Otherwise,
this signal has no effect. The behavior of the PT macrocell in Auto-Trim mode is described below.
“Reload”: when Reload goes high the rheostat value stored in the MTP NVM will be loaded into the rheostat (Register and
Counter) overwriting any current setting. This signal is edge sensitive. It has no effect while the Auto-Trim procedure is active.
For detailed information see Section 12.3.
“Program”: when Program goes high the Internal Counter value of the rheostat will be programmed into the MTP overwriting
any current value in the NVM. This procedure can be done up to 1000 times. This signal is also edge sensitive. It has no
effect while the Auto-Trim procedure is active. For detailed information see 12.3. To enable "Program" signal from connection
matrix RH_PRB register must be cleared (RH_PRB [1796] = 0). If RH_PRB [1796] register is set to 1, the access to NVM is
disabled for "Program" signal. Refer to Section 19.6 for more details.
“Clock”: this input has the following options: the PT macrocell can be clocked internally or from matrix. When clocked
internally, the clock is automatically enabled/disabled by the Set input logic in Auto-Trim mode. The internal clock is
synchronized with the Chopper ACMP clock.
“Up/Down”: the rheostat counter counts up when the signal is High and down when the signal is Low.
“Idle/Active”: this is the connection matrix input, that is logic HIGH by default. It goes LOW with rising edge on SET input if
Auto-Trim mode is enabled (Auto_Cal _Dis_RHx NVM bit = 0). After the end of Auto-Trim procedure (one of stop conditions
occurs) this signal sets to logic HIGH again.
“FIFO nReset”: low level at this input clears internal FIFO buffer for commands Reload and Program for both rheostats. User
should provide high logic level at this input for the normal rheostat operation.
There is also an overflow protection option, for which the counter will stop counting up when the maximum value (0x3FF) is
reached or stop counting down when the minimum value (0x00) is reached. The digital rheostat is initialized/powered in the first
place. The rheostat value is Hi-Z (or highest resistance if it is impossible to disconnect the rheostat) during the Power-On
sequence.
12.1 POTENTIOMETER MODE
This mode allows two 2-pin rheostats to work as one 3-pin potentiometer. When this mode is active (register [917] = 1), user
changes the value of RH0 internal counter. In this mode, the value of RH1 counter is the inverted value of RH0 counter (Figure
171). Note that the RH0_B pin and the RH1_A pin must be connected externally. Also, note that the Auto-Trim function isn't
allowed in Potentiometer Mode.
Figure 171: Rheostats in Potentiometer Mode
12.2 CALCULATING ACTUAL RESISTANCE
In applications where the absolute rheostat resistance is critical, the user can calculate it using the rheostat tolerance data, the
minimum rheostat resistance, and the desired code.
The 16-bit tolerance data for both rheostats has been programmed into registers 0xE6 to 0xE9. These registers can be used to
calculate the total rheostat resistance. The 16th bit defines the sign (0 = +, 1 = -) of the tolerance. The other fifteen bits
correspond to the absolute value of the rheostat tolerances variation from 100 kΩ measured at 25 °C.
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B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Tolerance
Tolerance Sign
Magnitude
(0 : +) | (1 : -)
Figure 172: Rheostat Tolerance Registers
Note that the rheostat tolerance data is programmed into registers 0xE6 to 0xE9. To avoid losing this tolerance data, special
attention must be paid when erasing and reprogramming page 14 in the NVM.
The rheostat value at a given code depends on the total digital rheostat resistance. The equations below can be used to
calculate the rheostat resistance.
RCode = (RDR - RDR MIN) x (code/1023) + RDR MIN
RDR = 100 x 103 + (signRH_Tolerance x RRH_Tolerance
)
where:
Code - Rheostat Resistance at a Given Code;
R
RDR - Total Digital Rheostat Resistance;
RDR MIN - Minimum Rheostat Resistance;
code - Rheostat Position Ranging from 0x000 to 0x3FF;
signRH_Tolerance - the MSB of the Rheostat’s Tolerance Data;
RRH_Tolerance - the 15 LSBs of the Rheostat’s Tolerance Data.
For example, let's say that 0x2B67 has been written into the rheostat tolerance registers within the GreenPAK's NVM. B15
corresponds to a positive sign while B14:0 translates into a decimal value of 11111. RDR calculates to approximately 111,111 Ω
and can be used with the minimum rheostat resistance to calculate the resistance at a given code. Note that the minimum
rheostat resistance must be measured to obtain precise results, but a range is provided in Table 23.
12.3 DIGITAL RHEOSTAT VALUE SELF-PROGRAMMING INTO THE NVM
The current value of rheostat is stored in the Internal Counter. This value can be programmed into the MTP by setting logic
HIGH at "Program" input. In this case, SLG47004 will generate a specific memory control sequence to rewrite a new value into
the NVM. There is a separate NVM page that is dedicated for the Digital Rheostat value.
There is a dedicated bit RH_PRB, that enables/disables "Program" signal of PT block to change NVM rheostats resistance
values. If RH_PRB[1796] = 0, "Program" signal is enabled. If RH_PRB[1796] = 1, "Program" signal is disabled. Note that
RH_PRB bit has no effect on I2C access to NVM. To enable/disable I2C access to rheostat resistance value, stored in NVM,
user must change NPRB0, NPRB1 bits. Refer to Section 18.5.
SLG47004 can latch up to four "Program" and "Reload" signals of RH0 and RH1 (Reload RH0, Program RH0, Reload RH1,
Program RH1). The same signal can't be latched second time, until it is processed. All latched signals will be processed in the
order of arrival (FIFO buffer), since only one signal can access NVM at the same time. If Auto-Trim process of RH0 or RH1 is
active and one or more "Reload", "Program" signals for corresponding rheostat come, SLG47004 will wait until the end of Auto-
Trim process and then process will latch "Reload", "Program" signals. Set0 or Set1 signal can be latched at any time and
processed when rheostat clocking isn't disabled by "Program" or "Reload" signals.
User can clear the FIFO buffer by setting low logic level at FIFO nReset input of PT blocks.
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Figure 173: Flowchart of "Program" and "Reload" Signals
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Figure 174: Example of Latching and Processing "Program" and "Reload" Signals
Since the access to the MTP NVM is disabled during NVM self-programming procedure, the device will not acknowledge it via
I2C interface. This can be used to determine when the erase/programming cycle is completed (this feature can be used to
maximize bus throughput). ACK polling can be used in this case.
If the device is still busy during the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control
byte must be re-sent. Once the cycle is complete, then the device will return the ACK and the master can proceed with the next
Read or Write command.
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12.4 TRIMMING PROCESS USING PROGRAMMABLE TRIM BLOCK
There are several ways of implementing the trimming process using the PT block. One of the essential features of the PT
macrocell is the Auto-Trim function described below. It allows the user to design simple calibration circuits for a wide variety of
applications.
12.4.1 Trimming Process with Auto-Trim Option Enabled
For using the Auto-Trim function the following preliminary steps must be taken:
Clear Auto_Cal _Dis_RHx NVM bit (0 is default value). This enables Auto-Trim function.
Configure M1 MUX (registers [875:872]). It can be user system voltage feedback. If Auto-Trim function is used for two
rheostats, M1 MUX must be configured for both rheostats (for cases when Set0 is latched and when Set1 is latched).
Configure M2 MUX. It can be user desired set point threshold. If Auto-Trim function is used for two rheostats, M2 MUX must
be configured for both rheostats (for cases when Set0 is latched and when Set1 is latched). Remember, that M2 MUX is
simplified symbol of Chopper ACMP reference selection blocks.
Configure M_CH0 (M_CH1) MUX to work with Chopper ACMP (M_CH0,1 MUXs are configured to work with Chop ACMP by
default).
Configure inverting or non-inverting Chopper ACMP output (registers [923], [920] and [882]);
Select clock source (internal clock from internal pre-dividers or from connection matrix). Note that in Auto-Trim mode clock
source frequency for the PT Block is limited by the Chopper Comparator time response. Therefore, the clock source
frequency must not be greater than <fChACMP> kHz.
Start the Auto-Trim process by setting the Set0 (Set1) input of PT block to a High level. The Auto-Trim process stops if one of
three stop conditions occur:
1) 2nd time change on Up/Down input at the moment of rising edge on Clock input (see Figure 175).
2) the value of rheostat reaches its maximum (1023).
3) the value of rheostat reaches its minimum (0).
Stop conditions result in a change of the Idle/Active signal, which resets the internal Auto-Trim logic.
Note that the Set input is edge sensitive, but if the user keeps a High logic level at this input after reaching the set point, the
PT block will continue to operate and continue to switch rheostat around the set point.
To start new Auto-Trim process user should reapply a High level on Set input.
The detailed flow of Auto-Trim process is shown in Figure 175, Figure 176, Figure 177.
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Figure 175: Example of Auto-Trim Process for a Single Rheostat
The key events of the Auto-Trim process are the following (see Figure 175):
1. During the startup event the SLG47004 loads the rheostat value from NVM to Internal Counter. In this example this value is
512.
2. The Trim process starts with a rising edge on Set input. This Set signal is latched until the end of the Auto-Trim process. The
Set signal will enable the Chopper ACMP and the Vref, if they were not enabled earlier. After a ready signal from analog blocks
(BG_OK & Vref_OK), the clock pulses for the internal counter are enabled. The counter starts to count up or down depending on
the level at the Up/Down input. If user selected the “Internal Clock” option for Clock input, these clock pulses are generated
automatically during trim time. Each rising edge of the Clock pulse changes the value of the counter and, consequently, the
value of the rheostat.
3. There are three stop conditions for the Auto-Trim process:
1) A subsequent change on Up/Down input at the moment of rising edge on Clock input.
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2) The value of the rheostat reaches its maximum (1023).
3) The value of the rheostat reaches its minimum (0).
If the Set input signal is shorter than the trim time, the Auto-Trim process stops automatically after a stop condition occurs (event
3, Figure 175). However, if a stop condition comes and High logic level holds on the Set input, the rheostat value will be
switched near the set point until a Low level on the Set input occurs (event 7, Figure 175). Note that the Idle/Active signal
changes its level to High (Auto-Trim is done) even if the user keeps a High logic level at the Set input.
After the end of the Auto-Trim process, Chopper ACMP powers down and its output goes to a Low logic level.
4. After a rising edge at the “Reload” signal, the value from NVM is copied to the rheostat Internal Counter overwriting current
rheostat settings.
5. During this event user starts Auto-Trim process, but holds High logic level at Set input for a time longer than Auto-Trim
process.
6. A “Program” signal comes. The “Program” command is latched and will be executed at the end of the Auto-Trim process.
7. The Auto-Trim process stops when the signal at the Set input goes to Low level. Note that a logic High level at the Set input
was held longer than the time that was needed for the Auto-Trim process. At the end of the Auto-Trim process, the SLG47004
starts the NVM self-programming routine to copy the rheostat value from Reg LATCH to MPT NVM.
Figure 176 shows a similar Auto-Trim example. The only difference is that the user defined clock source as “External clock” from
connection matrix. The clock pulses are present at the Clock input all the time, but have effect (rheostat value changes) during
Trim time only. The stop condition for this case is the following: PT block reaches boundary value of 1023 and the logic level at
change Set input is Low.
Figure 176: Example of Auto-Trim Process with External Clock Signal
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Figure 177 shows Auto-Trim process flow for two rheostats.
Figure 177: Example of Auto-Trim Process for Two Rheostats
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12.4.2 I2C Controlled Trimming Process with Auto-Trim Option Enabled
It's possible to start the Auto-Trim process via I2C interface. In this case the user must configure the SLG47004 PT macrocell as
described in Section 12.4.1. To start the Auto-Trim process via I2C interface the user can use I2C virtual inputs.
Also, an external I2C master device can force the SLG47004 to reload the rheostat value from NVM ("Reload" command) or to
copy rheostat value to NVM ("Program" command) using I2C virtual inputs.
See Figure 178 for an example of the Auto-Trim process under external I2C master control.
Figure 178: Example of Auto-Trim Process via I2C
The key events of the Auto-Trim process under external I2C master control are as follows:
1. During the startup event the SLG47004 loads the rheostat value from the NVM to the Internal Counter. In the example this
value is 512.
2. I2C master sends the message to set High one of the I2C virtual inputs that is connected with Set input of the PT macrocell.
3. After the I2C message is received and processed, the I2C virtual input and the Set input will be at a High logic level. The Auto-
Trim process begins.
4. I2C master clears the virtual input and, consequently, the Set input. The Auto-Trim process goes on until a trim stop condition
occurs.
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5. The Auto-Trim process ends. The stop condition in this example is a 2nd change on Up/Down input at the moment of rising
edge on the Clock input and Low level at the Set input.
12.4.3 Changing Rheostat Value Directly via I2C
The user can perform their own trim algorithm setting the rheostat value directly via I2C interface. In the example below, a
microcontroller uses a user defined trim algorithm to change SLG47004‘s rheostat via I2C interface (Figure 179). Note that
during Auto-Trim process SLG47004 will return nACK, if master tries to get access (both read and write) to rheostats registers
via I2C.
Figure 179: Example of Hardware Configuration
Note that the PT Registers are allowed to read and write via communication interface, if not protected.
The preliminary configuration of system shown in Figure 179 is the following:
Auto_Cal _Dis_RHx bit is set to 1 (disable Auto-Trim mode);
M1 MUX (registers [875:872])) is configured to work with user system voltage feedback (pin Chop_ACMP+);
M2 MUX is configured to work with SLG47004 programmable Vref. Note that M2 MUX is simplified symbol of Chopper ACMP
reference selection blocks (see Section 9.2);
Chopper ACMP is powered up from connection matrix. Chopper ACMP out is connected to output pin;
No Clock source for PT block.
The example of a system trim via I2C is shown in the figure below. In this example the I2C master uses a simple approximation
algorithm for reaching the set point. Every next step the rheostat code is changed by ±(Previous rheostat code step value/2).
The sign depends on the Chopper ACMP output. The algorithm steps are as follows:
Set rheostat code to 1024/2 = 512;
Wait until the system settles down and check if Chopper ACMP output = 1, then Next_rheostat_code = 512 + (512/2). If
Chopper ACMP output = 0, then Next_rheostat_code = 512 - (512/2);
Repeat previous step until Next_rheostat_code = Prev_rheostat_code ± 1;
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Figure 180: Example of User Specific Trimming Process under I2C Master Control
The key events of a user specific trimming process under I2C master control are as follows:
1. During the startup event the SLG47004 loads the rheostat value from NVM to Internal Counter. In the example this value is
512.
2. I2C master writes a new value to the Rheostat’s Internal Counter according to Chopper ACMP output. Note that the minimum
time for changing the rheostat code depends on the time response of the user system.
3. After the trim process is completed, the I2C master sets the I2C virtual input to logic “1”. This input is connected to the
"Reload" signal of the PT macrocell. The rising edge on this input starts the NVM self-programming routine.
4. The I2C master clears the I2C virtual input.
Additionally, the I2C Master macrocell can use internal resources such as an ADC to read the system data, find the error, and
then adjust the Rheostat value. Also, it is possible to change the Rheostat value for different conditions. For example, the I2C
Master macrocell can change the Rheostat value based on the temperature change to reduce the system error.
12.5 USING CHOPPER ACMP
When the Auto-Trim Function is disabled, the Chopper comparator can be used as a standalone analog comparator. Inputs of
the Chopper ACMP are selected by the M1 and M2 analog MUXs. Output of the Chopper ACMP can be optionally inverted by
register [882]. This comparator output is the input [55] of the connection matrix. In case of a disabled Auto-Trim Function, the
power up source for the Chopper ACMP comes from connection matrix. Please refer to Section 9 for more details.
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0.2
VDD = 2.4 V
0.15
0.1
VDD = 5.5 V
0.05
0
-0.05
-0.1
-0.15
0
64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024
Code (Decimal)
Figure 181: DNL vs. Digital Code, Rheostat Mode (VAB = 1 V) at T = 25 °C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VDD = 2.4 V
VDD = 5.5 V
-0.1
-0.2
0
64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024
Code (Decimal)
Figure 182: INL vs. Digital Code, Rheostat Mode (VAB = 1 V) at T = 25 °C
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0.2
VDD = 2.4 V
0.15
0.1
VDD = 5.5 V
0.05
0
-0.05
-0.1
-0.15
0
64
128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024
Code (Decimal)
Figure 183: DNL vs. Digital Code, Potentiometer Mode (VAB = 1 V) at T = 25 °C
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VDD = 2.4 V
VDD = 5.5 V
0
64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024
Code (Decimal)
Figure 184: INL vs. Digital Code, Potentiometer Mode (VAB = 1 V) at T = 25 °C
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600
550
500
450
400
350
300
250
200
150
100
50
0
0
64
128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024
Code (Decimal)
Figure 185: (ΔRAB/RAB)/ΔTA Rheostat Mode Tempco
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VDD = 5.5 V
VDD = 2.4 V
T (°C)
Figure 186: RHx Zero Scale Error vs. Temperature (VIN = 1 V)
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Time (50 μs/div)
Figure 187: Transition Glitch in Worst Case (Code = 511 to Code = 512)
10
0
-10
-20
-30
-40
-50
10
100
1 000
10 000
100 000
1 000 000
10 000 000
f (Hz)
Figure 188: Gain vs. Frequency (Code = 512) at T = 25 °C, VDDA = 5 V
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6.0
UP
DOWN
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 189: RHx Settling Time vs. VDD at ILOAD = 1 mA, T = 25 °C
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13 Programmable Delay/Edge Detector
The SLG47004 has a programmable time delay logic cell available, that can generate a delay that is selectable from one of four
timings (time 2) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay
patterns, rising edge detection, falling edge detection, both edge detection, and both edge delay. These four patterns can be
further modified with the addition of delayed edge detection, which adds an extra unit of delay, as well as glitch rejection during
the delay period. See Figure 191 for further information.
Note: The input signal must be longer than the delay, otherwise it will be filtered out.
registers [865:864]
registers [867:866]
Delay Value Selection
Edge Mode Selection
To Connection
Matrix Input [30]
Programmable
From Connection Matrix Output [58]
IN
OUT
Delay
Figure 190: Programmable Delay
13.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT
width
width
IN
time1
Rising Edge Detector
time1
Falling Edge Detector
Edge Detector
Output
Both Edge Detector
Both Edge Delay
time2
time2
time1 is a fixed value
time2 delay value is selected via register
Figure 191: Edge Detector Output
Please refer to Table 11.
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14 Additional Logic Function. Deglitch Filter
The SLG47004 has one Deglitch Filter macrocell with inverter function that is connected directly to the Connection Matrix inputs
and outputs. In addition, this macrocell can be configured as an Edge Detector, with the following settings:
Rising Edge Detector
Falling Edge Detector
Both Edge Detector
Both Edge Delay
Filter
R
From Connection Matrix
Output [59]
0
1
C
0
1
To Connection Matrix
Input [31]
Edge
Detector
Logic
registers [871:870]
register [868]
register [869]
Figure 192: Deglitch Filter or Edge Detector
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15 Voltage Reference
15.1 VOLTAGE REFERENCE OVERVIEW
The SLG47004 has a Voltage Reference (Vref) Macrocell to provide reference to analog comparators and operational amplifiers.
The macrocell also has the option to output reference voltages on external pins (see Table 1). Vref0 and Vref1 share output buffers
with Temperature sensor. Note that user can use any of output buffers, but Temperature sensor is calibrated for Vref1 output
buffer. See Table 57 for the available selections for each analog comparator. Also, see Figure 193, Figure 194, and Figure 195,
which show the reference output structure.
Also there is a high drive voltage reference macrocell called HD Buffer. The purpose of this macrocell is to provide stable voltage
to the relatively high-power load (Please refer to the Table 18). HD Buffer has shared voltage reference source with the Op Amp0
Vref. User can select output voltage in the range from VDD/64 to VDD with a step VDD/64, or output voltage in a range from 32 mV
to 2.048 V with a step 32 mV (see Figure 195).
15.2 VREF SELECTION TABLE
Table 57: Vref Selection Table
SEL[5:0]
0
Vref
0.032
0.064
0.096
0.128
0.16
SEL[5:0]
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Vref
1.088
1.12
1
2
1.152
1.184
1.216
1.248
1.28
3
4
5
0.192
0.224
0.256
0.288
0.32
6
7
1.312
1.344
1.376
1.408
1.44
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
0.352
0.384
0.416
0.448
0.48
1.472
1.504
1.536
1.568
1.6
0.512
0.544
0.576
0.608
0.64
1.632
1.664
1.696
1.728
1.76
0.672
0.704
0.736
0.768
0.8
1.792
1.824
1.856
1.888
1.92
0.832
0.864
0.896
0.928
0.96
1.952
1.984
2.016
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Table 57: Vref Selection Table(Continued)
SEL[5:0]
Vref
SEL[5:0]
Vref
30
31
32
0.992
1.024
1.056
63
64
2.048
External
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15.3 VREF BLOCK DIAGRAM
Figure 193: Generalized Vref Structure
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Figure 194: ACMP0L, ACMP1L Voltage Reference Block Diagram
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Figure 195: HD Buffer and Chopper ACMP Reference Block Diagram
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Figure 196: Operational Amplifiers Voltage Reference Block Diagram
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15.4 VOLTAGE REFERENCE TYPICAL PERFORMANCE
r.
350
300
250
200
150
VDD = 5 V
100
VDD = 3.3 V
VDD = 2.5 V
50
0
0
1
2
3
4
5
I, mA
Figure 197: Typical Load Regulation, Vref = 320 mV, T = -40 °C to +85 °C, Buffer - Enable
700
600
500
400
300
200
VDD = 5 V
100
0
VDD = 3.3 V
VDD = 2.5 V
0
1
2
3
4
5
I, mA
Figure 198: Typical Load Regulation, Vref = 640 mV, T = -40 °C to +85 °C, Buffer - Enable
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1400
1200
1000
800
600
400
VDD = 5 V
VDD = 3.3 V
200
VDD = 2.5 V
0
0
1
2
3
4
5
I, mA
Figure 199: Typical Load Regulation, Vref = 1280 mV, T = -40 °C to +85 °C, Buffer - Enable
2100
1800
1500
1200
900
600
VDD = 5 V
VDD = 3.3 V
300
VDD = 2.5 V
0
0
1
2
3
4
5
I, mA
Figure 200: Typical Load Regulation, Vref = 2048 mV, T = -40 °C to +85 °C, Buffer - Enable
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0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
0
128
256
384
512
640
768
896 1024 1152 1280 1408 1536 1664 1792 1920 2048
Vref (mV)
Figure 201: Typical Input Offset Voltage vs. Vref at VDD = 2.4 V to 5.5 V, T = 25 °C, Buffer Disabled
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16 Clocking
16.1 OSC GENERAL DESCRIPTION
The SLG47004 has three internal oscillators to support a variety of applications:
Oscillator0 (2.048 kHz)
Oscillator1 (2.048 MHz)
Oscillator2 (25 MHz)
There are two divider stages for each oscillator that give the user flexibility for introducing clock signals to connection matrix, as
well as various other Macrocells. The pre-divider (first stage) for Oscillator allows the selection of /1, /2, /4, or /8 to divide down
frequency from the fundamental. The second stage divider has an input of frequency from the pre-divider, and outputs one of
eight different frequencies divided by /1, /2, /3, /4, /8, /12, /24, or /64 on Connection Matrix Input lines [52], [53], and [54]. Please
see Figure 205 for more details on the SLG47004 clock scheme.
Oscillator2 (25 MHz) has an additional function of 100 ns delayed startup, which can be enabled/disabled by register [713]. This
function is recommended to use when analog blocks are used along with the Oscillator.
The Matrix Power-down/Force On function allows switching off or force on the oscillator using an external pin. The Matrix Power-
down/Force On (Connection Matrix Output [91], [92], [93]) signal has the highest priority. The OSC operates according to the
Table 58.
Table 58: Oscillator Operation Mode Configuration Settings
Register:
OSC Enable
Signal from
CNT/DLY
Register:
Auto Power-
On or Force
On
OSC
Operation
Mode
External
Clock
Signal From Power-Down
POR
Connection
Matrix
or Force On
by Matrix In-
put
Selection
Macrocells
0
1
X
1
X
X
X
X
X
X
X
OFF
Internal OSC
is OFF,
X
logic is ON
1
1
1
0
0
0
1
1
0
0
1
X
X
X
1
X
X
X
OFF
ON
ON
ON
CNT/DLY
requires OSC
1
0
0
X
0
CNT/DLY
does not
OFF
1
0
0
X
0
require OSC
Note 1 The OSC will run only when any macrocell that uses OSC is powered on.
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16.2 OSCILLATOR0 (2.048 KHZ)
From Connection Matrix
Output [91]
Power-down/Force On
Matrix Output control register [721]
OSC Power Mode
register [720]
2.048 kHz Pre-divided Clock
PD/FORCE ON
registers [725:724]
OSC0
Auto Power-On
Force Power-On
(2.048 kHz) OUT
0
0
1
DIV /1 /2 /4 /8
0
1
Ext. Clock
Pre-divider
1
/ 2
/ 3
2
3
4
5
6
7
Ext. CLK Sel register [722]
To Connection Matrix
Input [52]
/ 4
OUT0
/ 8
OUT1
To Connection Matrix
Input [58]
/ 12
/ 24
/ 64
registers [728:726]
registers [733:731]
Second Stage
Divider
Figure 202: Oscillator0 Block Diagram
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16.3 OSCILLATOR1 (2.048 MHZ)
From Connection Matrix
Output [92]
Power-down/Force On
Matrix Output control register [689]
OSC Power Mode
register [688]
2.048 MHz Pre-divided Clock
PD/FORCE ON
registers [692:691]
OSC1
Auto Power-On
Force Power-On
(2.048 MHz)OUT
0
0
1
DIV /1 /2 /4 /8
0
1
Ext. Clock
Pre-divider
1
/ 2
/ 3
2
3
4
5
6
7
Ext. CLK Sel register [690]
To Connection Matrix
Input [53]
/ 4
OUT0
/ 8
OUT1
To Connection Matrix
Input [59]
/ 12
/ 24
/ 64
registers [695:693]
registers [703:701]
Second Stage
Divider
Figure 203: Oscillator1 Block Diagram
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16.4 OSCILLATOR2 (25 MHZ)
From Connection Matrix
Output [93]
Power-down/Force On
Matrix Output control register [705]
OSC Power Mode
register [704]
25 MHz Pre-divided Clock
PD/FORCE ON
registers [709:708]
OSC2
(25 MHz)
Auto Power-On
Force Power-On
OUT
0
0
1
Startup delay
DIV /1 /2 /4 /8
0
1
Pre-divider
register [713]
1
/ 2
/ 3
Ext. Clock
2
3
4
5
6
Ext. CLK Sel [706]
To Connection Matrix
Input [54]
/ 4
/ 8
/ 12
/ 24
/ 64
7
registers [712:710]
Second Stage
Divider
Figure 204: Oscillator2 Block Diagram
16.5 CNT/DLY CLOCK SCHEME
Each CNT/DLY within Multi-Function macrocell has its own additional clock divider connected to oscillators pre-divider. Available
dividers are:
OSC0/1, OSC0/8, OSC0/64, OSC0/512, OSC0/4096, OSC0/32768, OSC0/262144
OSC1/1, OSC1/8, OSC1/64, OSC1/512
OSC2/1, OSC2/4
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[3:0]
0
1
25 MHz Pre-divided clock
Div4
2
Div8
3
4
5
6
7
8
CNT/DLY/
ONESHOT/
FREQ_DET/
2.048 MHz Pre-divided clock
2.048 kHz Pre-divided clock
Div64
Div512
DLY_EDGE_DET
Div8
Div64
CNT overflow
Div512
9
Div4096
Div32768
Div262144
10
11
12
13
14
15
CNT (x-1) overflow
from Connection Matrix Out
(separate for each CNT/DLY macrocell)
CNT0/CNT1/CNT2/CNT3/CNT4/
CNT5/CNT6/RH0 CLK/RH1 CLK
none
Figure 205: Clock Scheme
16.6 EXTERNAL CLOCKING
The SLG47004 supports several ways to use an external, higher accuracy clock as a reference source for internal operations.
16.6.1 IO1 Source for Oscillator0 (2.048 kHz)
When register [722] is set to 1, an external clocking signal on IO0 will be routed in place of the internal oscillator derived 2.048 kHz
clock source. See Figure 202. The high and low limits for frequency that can be selected are 0 MHz and 10 MHz.
16.6.2 IO3 Source for Oscillator1 (2.048 MHz)
When register [690] is set to 1, an external clocking signal on IO1 will be routed in place of the internal oscillator derived 2.048 MHz
clock source. See Figure 203. The high and low limits for frequency that can be selected are 0 MHz and 10 MHz.
16.6.3 IO2 Source for Oscillator2 (25 MHz)
When register [706] is set to 1, an external clocking signal on IO2 will be routed in place of the internal oscillator derived 25 MHz
clock source. See Figure 204. The external frequency range is 0 MHz to 20 MHz at VDD = 2.4 V, 0 MHz to 30 MHz at VDD = 3.3 V,
0 MHz to 50 MHz at VDD = 5.0 V.
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16.7 OSCILLATORS POWER-ON DELAY
OSC enable
Power-On
Delay
CLK
Figure 206: Oscillator Startup Diagram
Note 1 OSC power mode: “Auto Power-On”.
Note 2 “OSC enable” signal appears when any macrocell that uses OSC is powered on
950
900
850
800
750
700
650
600
550
500
2.4
2.7
3
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 207: OSC0 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 2.048 kHz
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560
540
520
500
480
460
440
420
400
2.4
2.7
3
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 208: OSC1 Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC1 = 2.048 MHz
160
140
120
100
80
60
40
20
0
2.4
2.7
3
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 209: OSC2 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC2 = 25 MHz
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16.8 OSCILLATORS ACCURACY
Note: OSC power setting: Force Power-On; Clock to matrix input - enable; Bandgap: turn on by register - enable.
2.2
2.18
Fmax @ VDD = 2.5 V to 5 V
2.16
Ftyp @ VDD = 3.3 V
Fmin @ VDD = 2.5 V to 5 V
2.14
2.12
2.1
2.08
2.06
2.04
2.02
2
1.98
1.96
1.94
1.92
1.9
T (°C)
Figure 210: OSC0 Frequency vs. Temperature, OSC0 = 2.048 kHz
2.15
2.13
2.11
2.09
2.07
2.05
2.03
2.01
Fmax @ VDD = 2.5 V to 5 V
1.99
Ftyp @ VDD = 3.3 V
1.97
Fmin @ VDD = 2.5 V to 5.5 V
1.95
T (°C)
Figure 211: OSC1 Frequency vs. Temperature, OSC1 = 2.048 MHz
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26.1
25.9
25.7
Fmax @ VDD = 2.5 V to 5 V
25.5
Ftyp @ VDD = 3.3 V
25.3
Fmin @ VDD = 3.3 V
25.1
24.9
24.7
24.5
24.3
24.1
23.9
23.7
T (°C)
Figure 212: OSC2 Frequency vs. Temperature, OSC2 = 25 MHz
8
2.048 kHz Total Error @ VDD = 2.3 V to 5.5 V
7
6
5
4
3
2
1
25 MHz Total Error @ VDD = 2.3 V to 5.5 V
2.048 MHz Total Error @ VDD = 2.3 V to 5.5 V
T (°C)
Figure 213: Oscillators Total Error vs. Temperature
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Note: For more information see Section 3.8.
16.9 OSCILLATORS SETTLING TIME
488
487
486
485
484
0
1
2
3
4
Period
Figure 214: Oscillator0 Settling Time, VDD = 3.3 V, T = 25 °C, OSC0 = 2 kHz
510
500
490
480
470
460
450
0
1
2
3
4
5
6
Period
Figure 215: Oscillator1 Settling Time, VDD = 3.3 V, T = 25 °C, OSC1 = 2 MHz
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60
55
50
45
40
35
30
25
20
0
1
2
3
4
5
6
7
8
9
10
11
Period
Figure 216: Oscillator2 Settling Time, VDD = 3.3 V, T = 25 °C, OSC2 = 25 MHz (Normal Start)
160
140
120
100
80
60
40
20
0
1
2
3
4
5
6
7
8
Period
Figure 217: Oscillator2 Settling Time, VDD = 3.3 V, T = 25 °C, OSC2 = 25 MHz (Start with Delay)
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16.10 OSCILLATORS CURRENT CONSUMPTION
24
22
20
18
16
14
12
10
T = 85 °C
T = 25 °C
T = -40 °C
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
Figure 218: OSC1 Current Consumption vs. VDD (Pre-Divider = 1)
24
22
20
18
16
14
12
10
T = 85 °C
T = 25 °C
T = -40 °C
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
Figure 219: OSC1 Current Consumption vs. VDD (Pre-Divider = 4)
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24
22
20
18
16
14
12
10
T = 85 °C
T = 25 °C
T = -40 °C
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
Figure 220: OSC1 Current Consumption vs. VDD (Pre-Divider = 8)
80
75
70
65
60
55
50
45
40
35
T = 85 °C
T = 25 °C
T = -40 °C
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
Figure 221: OSC2 Current Consumption vs. VDD (Pre-Divider = 1)
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60
55
50
45
40
35
30
25
20
15
10
T = 85 °C
T = 25 °C
T = -40 °C
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
Figure 222: OSC2 Current Consumption vs. VDD (Pre-Divider = 4)
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55
50
45
40
35
30
25
T = 85 °C
T = 25 °C
T = -40 °C
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
Figure 223: OSC2 Current Consumption vs. VDD (Pre-Divider = 8)
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17 Power-On Reset
The SLG47004 has a Power-On Reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in
the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first
ramping to the device, and also while the VDD is falling during Power-down. To accomplish this goal, the POR drives a defined
sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of
the IOs.
17.1 GENERAL OPERATION
The SLG47004 is guaranteed to be powered down and non-operational when the VDD voltage (voltage on PIN13) is less than
Power-Off Threshold (see in Table 6), but not less than -0.6 V. Another essential condition for the chip to be powered down is that
no voltage higher (Note) than the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3 V, applying a voltage
higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior.
Note: There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes.
To start the POR sequence in the SLG47004, the voltage applied on the VDD should be higher than the Power-On Threshold
(Note). The full operational VDD range for the SLG47004 is 2.4 V to 5.5 V. This means that the VDD voltage must ramp up to the
operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power-On Threshold.
After the POR sequence has started, the SLG47004 will have a typical Startup Time (see in Table 6) to go through all the steps
in the sequence, and will be ready and completely operational after the POR sequence is complete.
Note: The Power-On Threshold is defined in Table 6.
To power down the chip, the VDD voltage should be lower than the operational and to guarantee that chip is powered down, it
should be less than Power-Off Threshold.
All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step
in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin
configuration at this point in time is defined by the design programmed into the chip. Also, as it was mentioned before, the voltage
on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.
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17.2 POR SEQUENCE
The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 224.
VDD
t
POR_NVM
(reset for NVM)
t
t
t
t
t
t
t
NVM_ready_out
POR_GPI
(reset for input enable,
Digital Rheostat (default value))
POR_LUT
(reset for LUT/FILTER)
POR_CORE
(reset for DLY/OSC/DFF
/LATCH/Pipe DLY/ACMP/
Edge Detector in Filter)
POR_OUT
(generate low to high to matrix)
POR_GPO
(reset for output enable)
Figure 224: POR Sequence
As can be seen from Figure 224 after the VDD has started ramping up and crossed the Power-On Threshold, first, the on-chip
NVM memory is reset. Next, the chip reads the data from NVM and transfers this information to a CMOS LATCH, that serves to
configure each macrocell, and the Connection Matrix, which routes signals between macrocells. The third stage causes the reset
of the input pins, and then enables them. At that time Digital Rheostats value is set to its default value. After that, the LUTs are
reset and become active. After LUTs, the Delay cells, OSCs, DFFs, LATCHES, and Pipe Delay are initialized. Only after all
macrocells are initialized, internal POR signal (POR macrocell output) goes from LOW to HIGH (POR_OUT in Figure 224). The
last portion of the device to be initialized is the output pins, which transition from high impedance to active at this point.
The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many
environmental factors, such as: slew rate, VDD value, temperature, and even will vary from chip to chip (process influence).
17.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE
To have a full picture of SLG47004 operation during powering and POR sequence refer to Figure 225, which describes the
macrocell output states during the POR sequence.
First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output pins which are in high
impedance state). On the next step, some of the macrocells start initialization: input pins output state becomes LOW; Digital
Rheostats value is set to its default value; LUTs also output LOW. After that input pins are enabled. Next, only LUTs are configured.
Then, all other macrocells are initialized. After macrocells are initialized, internal POR matrix signal switches from LOW to HIGH.
The last are output pins that become active and determined by the input signals.
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VDD
Guaranteed HIGH before POR_GPI
t
VDD _out
to matrix
Unpredictable
t
t
Input PIN _out
Unpredictable
Determined by External Signal
to matrix
Digital Rheostats
Resistance
Hi-Z
Default Value from NVM
t
LUT/FILTER_out
to matrix
Unpredictable
Unpredictable
Unpredictable
Unpredictable
Unpredictable
Determined by Input signals
Determined by input signals
t
t
t
t
t
t
OUT = IN without Delay
Programmable Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
Determined by initial state
DFF/LATCH/ACMP/Edge
Detector in Filter_out
to matrix
Determined by Input signals
Determined by input signals
OUT = IN without Delay
Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
POR_out
to matrix
Ext. GPO
Tri-state
Determined by input signals
Output State Unpredictable
Figure 225: Internal Macrocell States During POR Sequence
17.3.1 Initialization
All internal macrocells by default have initial low level. Starting from indicated power-up time of 1.6 V to 2.07 V, macrocells in
SLG47004 are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then
the reset signal is released for internal macrocells and they start to initialize according to the following sequence:
1. Input pins, Pull-up/down, Digital Rheostats, Op Amps.
2. LUTs.
3. DFFs, Delays/Counters, Pipe Delay, OSCs, ACMPs.
4. POR output to matrix.
5. Output pin corresponds to the internal logic.
The Vref output pin driving signal can precede POR output signal going high by 3 µs to 5 µs. The POR signal going high indicates
the mentioned power-up sequence is complete.
Note: The maximum voltage applied to any pin should not be higher than the VDD level. There are ESD Diodes between pin →
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VDD and pin → GND on each pin. Exceeding VDD results in leakage current on the input pin, and VDD will be pulled up, following
the voltage on the input pin.
17.3.2 Power-Down
VDD (V)
2 V
1.53 V
0.97 V
1 V Vref Out Signal
1 V
Time
Not guaranteed output state
Figure 226: Power-Down
During Power-down macrocells in SLG47004 are powered off after VDD falling down below Power-Off Threshold. Please note,
that during a slow rampdown outputs can possibly switch state.
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2
18 I C Serial Communications Macrocell
18.1 I2C SERIAL COMMUNICATIONS MACROCELL OVERVIEW
In the standard use case for the GreenPAK devices, the configuration choices made by the user are stored as bit settings in the
Non-Volatile Memory (NVM), and this information is transferred at startup time to volatile RAM registers that enable the
configuration of the macrocells. Other RAM registers in the device are responsible for setting the connections in the Connection
Matrix to route signals in the manner most appropriate for the user’s application.
The I2C Serial Communications Macrocell in this device allows an I2C bus Master to read and write this information via a serial
channel directly to the RAM registers, allowing the remote re-configuration of macrocells, and remote changes to signal chains
within the device.
The I2C bus Master is also able to read and write other register bits that are not associated with NVM memory. As an example,
the input lines to the Connection Matrix can be read as digital register bits. These are the signal outputs of each of the macrocells
in the device, giving the I2C bus Master the capability to remotely read the current value of any macrocell.
The user has the flexibility to control read access and write access via registers bits registers [1795:1792]. See Section 19 for
more details on I2C read/write memory protection.
18.2 I2C SERIAL COMMUNICATIONS DEVICE ADDRESSING
Each command to the I2C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are
shown in Figure 227.After the Start bit, the first four bits are a control code. Each bit in a control code can be sourced independently
from the register or by value defined externally by IO1, IO2, IO3, and IO4. The LSB of the control code is defined by the value of
IO1, while the MSB is defined by the value of IO4. The address source (either register bit or PIN) for each bit in the control code
is defined by registers [1019:1016]. This gives the user flexibility on the chip level addressing of this device and other devices on
the same I2C bus.The default control code is 0001. The Block Address is the next three bits (A10, A9, A8), which will define the
most significant bits in the addressing of the data to be read or written by the command. The last bit in the Control Byte is the R/W
bit, which selects whether a read command or write command is requested, with a “1” selecting for a Read command, and a “0”
selecting for a Write command. This Control Byte will be followed by an Acknowledge bit (ACK), which is sent by this device to
indicate successful communication of the Control Byte data.
In the I2C-bus specification and user manual there are two groups of eight addresses (0000 xxx and 1111 xxx) that are reserved
for the special functions, such as a system General Call address. If the user of this device choses to set the Control Code to either
“1111” or “0000” in a system with other slave device, please consult the I2C-bus specification and user manual to understand the
addressing and implementation of these special functions, to ensure reliable operation.
In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of
information, resulting in a total address space of 2K bytes. The valid addresses are shown in the memory map in Figure 237.
With the exception of the Current Address Read command, all commands will have the Control Byte followed by the Word
Address.
Start
bit
Acknowledge
bit
Control Byte
Word Address
A
10
A
9
A
8
A
7
A
0
S
X
X
X
X
R/W ACK
Control
Code
Block
Address
Read/Write bit
Figure 227: Basic Command Structure
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18.3 I2C SERIAL GENERAL TIMING
General timing characteristics for the I2C Serial Communications macrocell are shown in Figure 228. Timing specifications can
be found in the AC Characteristics, section 3.4.
tHIGH
tF
tR
tLOW
SCL
tSU STA
tHD DAT
tHD STA
tSU DAT
tSU STO
SDA IN
tBUF
tAA
tDH
SDA OUT
Figure 228: I2C General Timing Characteristics
18.4 I2C SERIAL COMMUNICATIONS COMMANDS
18.4.1 Byte Write Command
Following the Start condition from the Master, the Control Code [4 bits], the Block Address [3 bits], and the R/W bit (set to “0”) are
placed onto the I2C bus by the Master. After the SLG47004 sends an Acknowledge bit (ACK), the next byte transmitted by the
Master is the Word Address. The Block Address (A10, A9, A8), combined with the Word Address (A7 through A0), together set
the internal address pointer in the SLG47004, where the data byte is to be written. After the SLG47004 sends another
Acknowledge bit, the Master will transmit the data byte to be written into the addressed memory location. The SLG47004 again
provides an Acknowledge bit and then the Master generates a Stop condition. The internal write cycle for the data will take place
at the time that the SLG47004 generates the Acknowledge bit.
It is possible to latch all IOs during I2C write command to the register configuration data (block address A10, A9, A8 = 000),
register [985] = 1 - Enable. It means that IOs will remain their state until the write command is done.
Acknowledge
bit
Acknowledge
bit
Start
bit
Acknowledge
bit
Bus Activity
Control Byte
Word Address
Data
A
10
A
9
A
8
A
7
A
0
D
7
D
0
S
X
X
X
X
W
ACK
ACK
ACK
SDA LINE
P
Control
Code
Block
Address
Stop
bit
R/W bit = 0
Figure 229: Byte Write Command, R/W = 0
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18.4.2 Sequential Write Command
The write Control Byte, Word Address, and the first data byte are transmitted to the SLG47004 in the same way as in a Byte Write
command. However, instead of generating a Stop condition, the Bus Master continues to transmit data bytes to the SLG47004.
Each subsequent data byte will increment the internal address counter, and will be written into the next higher byte in the command
addressing. As in the case of the Byte Write command, the internal write cycle will take place at the time that the SLG47004
generates the Acknowledge bit.
Acknowledge
Acknowledge
bit
Start
bit
bit
Bus Activity
Data (n + 1)
Data (n + x)
Control Byte
Word Address (n)
Data (n)
A
10
A
9
A
8
ACK
ACK
P
SDA LINE
S
X
X
X
X
W
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
Write bit
Figure 230: Sequential Write Command
18.4.3 Current Address Read Command
The Current Address Read Command reads from the current pointer address location. The address pointer is incremented at the
first STOP bit following any write control byte. For example, if a Sequential Read command (which contains a write control byte)
reads data up to address n, the address pointer would get incremented to n + 1 upon the STOP of that command. Subsequently,
a Current Address Read that follows would start reading data at n + 1. The Current Address Read Command contains the Control
Byte sent by the Master, with the R/W bit = “1”. The SLG47004 will issue an Acknowledge bit, and then transmit eight data bits
for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition
Start
bit
Acknowledge
bit
Stop
bit
Bus Activity
Control Byte
Data (n)
A
10
A
9
A
8
S
X
X
X
X
R
ACK
SDA LINE
P
Control
Code
Block
Address
No Ack
bit
R/W bit = 1
Figure 231: Current Address Read Command, R/W = 1
18.4.4 Random Read Command
The Random Read command starts with a Control Byte (with R/W bit set to “0”, indicating a write command) and Word Address
to set the internal byte address, followed by a Start bit, and then the Control Byte for the read (exactly the same as the Byte Write
command). The Start bit in the middle of the command will halt the decoding of a Write command, but will set the internal address
counter in preparation for the second half of the command. After the Start bit, the Bus Master issues a second control byte with
the R/W bit set to “1”, after which the SLG47004 issues an Acknowledge bit followed by the requested eight data bits.
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Acknowledge
Stop
bit
Start
bit
bit
Bus Activity
Data (n)
Control Byte
Word Address (n)
Control Byte
A
10
A
9
A
8
A
10
A
9
A
8
S
ACK
X
X
X
X
R ACK
P
SDA LINE
S
X
X
X
X
W
ACK
Control
Code
Block
Address
Control
Code
Block
Address
No Ack
bit
Write bit
Read bit
Figure 232: Random Read Command
18.4.5 Sequential Read Command
The Sequential Read command is initiated in the same way as a Random Read command, except that once the SLG47004
transmits the first data byte, the Bus Master issues an Acknowledge bit as opposed to a Stop condition in a random read. The
Bus Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition.
Acknowledge
Start
bit
bit
Bus Activity
Data (n + 2)
Data (n + x)
Control Byte
Data (n)
Data (n + 1)
A
8
A
10
A
9
ACK
P
SDA LINE
S
X
X
X
X
R
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
No Ack
bit
Read bit
Figure 233: Sequential Read Command
18.4.6 I2C Serial Reset Command
If I2C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including
configuration of all macrocells and all connections provided by the Connection Matrix. This is implemented by setting register [984]
I2C reset bit to “1”, which causes the device to re-enable the Power-On Reset (POR) sequence, including the reload of all register
data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has taken place, the contents
of register [984] will be set to “0” automatically. The Figure 234 illustrates the sequence of events for this reset function.
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Acknowledge
bit
Acknowledge
bit
Start
bit
Acknowledge
bit
Bus Activity
Control Byte
Word Address
Data
A
10
A
9
A
8
A
7
A
0
D
7
D
0
S
X
X
X
X
W
ACK
ACK
ACK
SDA LINE
P
Internal Reset bit
Control
Code
Block
Address
Stop
bit
Not used, se
t to 0
Write bit
by I2C Stop Signal
Reset-bit register output
DFF output gated by stop signal
Internal POR for core only
Figure 234: Reset Command Timing
18.5 CHIP CONFIGURATION DATA PROTECTION
The SLG47004 utilizes a scheme that allows a portion or the entire Register and NVM to be inhibited from being read or
written/erased. There are two bytes that define the register and NVM access or change. The second byte NPR defines the chip
NVM data configuration read and write protection. The first byte RPR defines the register read and write protection. If desired,
the protection lock bit (PRL) can be set so that protection may no longer be modified, thereby making the current protection
scheme permanent. The status of the RPR and NPR can be determined by following a Random Read sequence. Changing the
state of the RPR and NPR is accomplished with a Byte Write sequence with the requirements outlined in this section.
Special care must be taken when NVM page 14 is rewritten (registers [1919:1792]). This page contains rheostats tolerance data
that can be permanently lost during write/erase operation.
The RPR register is located on H’E0 address, while NPR is located on H’E1 address.
The RPR format is shown in Table 59, and the RPR bit functions are included in Table 60.
Table 59: RPR Format
b7
b6
b5
b4
b3
b2
b1
b0
RPR
RH_PRB
RPRB3
RPRB2
RPRB1
RPRB0
* Becomes read only after PRL is high. The content is permanently locked for write and erase after PRL is high.
Table 60: RPR Bit Function Description
Bit
Name
Type
R/W*
R/W*
Description
0: Program signal from connection matrix is enabled
1: Program signal from connection matrix is disabled
4
RH_PRB
RPRB3
--
2k Register
Write
00: 2k register data is unprotected for write;
01: 2k register data is partly protected for write; Please refer to the Table 63.
10: 2k register data is fully protected for write.
3:2
Selection
Bits
RPRB2
R/W*
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Table 60: RPR Bit Function Description(Continued)
Bit
Name
2k Register
Type
Description
RPRB1
RPRB0
R/W*
00: 2k register data is unprotected for read;
01: 2k register data is partly protected for read; Please refer to the Table 63.
10: 2k register data is fully protected for read.
Read
Selection
Bits
1:0
R/W*
The NPR format is shown in Table 61, and the NPR bit functions are included in Table 62.
Table 61: NPR Format
b7
b6
b5
b4
b3
b2
b1
b0
NPR
Table 62: NPR Bit Function Description
NPRB1
NPRB0
Bit
Name
Type
Description
NPRB1
NPRB0
R/W*
00: 2k NVM Configuration data is unprotected for read and write/erase;
01: 2k NVM Configuration data is fully protected for read;
10: 2k NVM Configuration data is fully protected for write/erase;
11: 2k NVM Configuration data is fully protected for read and write/erase.
2k NVM
Configuration
Selection Bits
1:0
R/W*
* Becomes read only after PRL is high. The content is permanently locked for write and erase after PRL is high.
The protection selection bits allow different levels of protection of the register and NVM Memory Array.
There is a dedicated bit RH_PRB, that enables/disables "Program" signal of PT block to change NVM rheostats resistance values.
If RH_PRB [1796] = 0, "Program" signal is enabled. If RH_PRB [1796] = 1, "Program" signal is disabled. Note that RH_PRB bit
has no effect on I2C access to NVM. To enable/disable I2C access to rheostat resistance value, stored in NVM, user must change
NPRB0, NPRB1 bits.
The Protect Lock Bit (PRL) is used to permanently lock (for write and erase) the current state of the RPR and NPR,as well as
EEPROM protection. A Logic 0 indicates that the protection byte can be modified, whereas a Logic 1 indicates the byte has been
locked and can no longer be modified.
In this case it is impossible to erase the whole page E with protection bytes. The PRL is located at E4 address (register [1824]).
18.6 I2C SERIAL COMMAND REGISTER MAP
There are nine read/write protect modes for the design sequence from being corrupted or copied. See Table 63 for details.
Table 63: Read/Write Register Protection Options
Protection Modes Configuration
Partly
Lock
Read &
Lock
Lock
Read &
Partly
Lock
Partly
Lock
Read/
Write
Partly
Lock
Read
Partly
Lock
Write
Lock
Read/
Write
Configurations
Lock
Read
Lock
Write
Unlock
Register
Address
Test
Mode
Write
Write
00
00
01
00
00
01
01
01
01
10
10
01
10
00
00
10
10
10
RPR[1:0]
RPR[3:2]
2
I C Byte Write Bit
Masking
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
W
W
W
W
R
R
-
-
-
-
F6
(section 18.7.2)
2
I C Serial Reset
Command
7Bb'0
(section 18.4.6)
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Table 63: Read/Write Register Protection Options(Continued)
Protection Modes Configuration
Partly
Lock
Read &
Lock
Lock
Read &
Partly
Lock
Partly
Lock
Read/
Write
Partly
Lock
Read
Partly
Lock
Write
Lock
Read/
Write
Configurations
RPR[1:0]
Lock
Read
Lock
Write
Unlock
Register
Address
Test
Mode
Write
Write
00
00
01
00
00
01
01
01
01
10
10
01
10
00
00
10
10
10
RPR[3:2]
Outputs Latching
2
During I C Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
W
W
W
W
R
R
-
-
-
-
7Bb'1
7C
(section18.7)
Connection Matrix
Virtual Inputs
(section 6.3)
RH0_CNT Data
RH1_CNT Data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
W
W
W
W
R
R
-
-
R/W
R/W
C0,C1
D0,D1
Macrocells Output
Values (Connection
Matrix Inputs,
section
R
R
R
R
R
-
-
R
-
R
C4~CA
Counter Current
Value
R
R
R
R
R
-
-
R
-
R
CB~CE
RH0_CNT Value
RH1_CNT Value
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
C2,C3
D2,D3
Protection Mode
Selection
R/W
R/W
R
R
R
R
R
R
R
R
R/W
R
R
R7
R
R
R
E4'b0
(sections 18.6,
19.6)
7Fb'3~7F
b'0
2
I C Slave Address
R/W
R/W
R/W
R/W
R/W
R/W
Pin slave address
select
7Fb'7~7F
b'4
Service page lock
RH0 Tolerance Data
RH1 Tolerance Data
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
F3b'0
E6,E7
E8,E9
Protect Mode
Config
(RH_PRB,RPR,
NPR,WPR)
R/W*
W**
R/W*
W**
R/W*
W**
R/W*
W**
R/W*
W**
R/W*
W**
R/W*
W**
R/W*
W**
R/W*
W**
R/W*
W**
E0, E1, E2
E3
Page Erase byte
Macrocells Inputs
Configuration
00~4A
(4B rev)
(Connection Matrix
Outputs)
R/W
W
R
-
-
-
W
R
-
-
(section 6.2
)
Configuration Bits
for All Macrocells
(IOs, ACMPs,
Combination
Function
R/W
W
R
-
-
-
W
R
-
-
Macrocells, and
others)
R/W
W
Allow Read and Write Data
Allow Write Data Only
W**
Pages that can be erased are defined by NVM write protection
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R
-
Allow Read Data Only
The Data is protected for Read and Write
Note 1 R/W becomes read only if protection mode selection (lock bit) is set to 1.
Note 2 R/W Readable/writable depend on the "Trim mode enable" bit. If “Trim mode enable” bit value = 1, then trim bits are
enable.
It is possible to read some data from macrocells, such as counter current value, connection matrix, and connection matrix virtual
inputs. The I2C write will not have any impact on data in case data comes from macrocell output, except Connection Matrix Virtual
Inputs. The silicon identification service bits allow identifying silicon family, its revision, and others.
R/W* - Becomes read only after PRL is high.See Section 21 for detailed information on all registers.
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18.7 I2C ADDITIONAL OPTIONS
When Output latching during I2C write to the register configuration data (block address A10, A9, A8 = 000), registers [985] = 1
allows all PINs output value to be latched while register content is changing. It will protect the output change due to configuration
process during I2C write in case multiple register bytes are changed. Inputs and internal macrocells retain their status during I2C
write.
See Section 21 for detailed information on all registers.
18.7.1 Reading Counter Data via I2C
The current count value in three counters in the device can be read via I2C. The counters that have this additional functionality
are 16-bit CNT0, and 8-bit counters CNT2 and CNT4.
18.7.2 I2C Byte Write Bit Masking
The I2C macrocell inside SLG47004 supports masking of individual bits within a byte that is written to the RAM memory space.
This function is supported across the entire RAM memory space. To implement this function, the user performs a Byte Write
Command (see Section 18.4.1 for details) on the I2C Byte Write Mask Register (address 0F6H) with the desired bit mask pattern.
This sets a bit mask pattern for the target memory location that will take effect on the next Byte Write Command to this register
byte. Any bit in the mask that is set to “1” in the I2C Byte Write Mask Register will mask the effect of changing that particular bit
in the target register, during the next Byte Write Command. The contents of the I2C Byte Write Mask Register are reset (set to
00h) after valid Byte Write Command. If the next command received by the device is not a Byte Write Command, the effect of the
bit masking function will be aborted, and the I2C Byte Write Mask Register will be reset with no effect. Figure 235 shows an
example of this function.
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GreenPAK Programmable Mixed-Signal Matrix
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User Actions
Byte Write Command, Address = C9, Data = 11110000b [sets mask bits]
Byte Write Command, Address = 74h, Data = 10101010b [writes data with mask]
Memory Address 74h (original contents)
Mask to choose bit from new
write command
1
1
1
1
0
0
1
1
0
0
Mask to choose bit from
original register contents
Memory Address 74h (new data in write command)
0 1
1
0
1
0
0
0
Bit from new write command
Memory Address C9 (mask register)
1
1
1
0
0
0
Bit from original register
contents
Memory Address 74h (new contents after write command)
1
1
0
0
1
0
1
0
Figure 235: Example of I2C Byte Write Bit Masking
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19 Non-Volatile Memory
The SLG47004 provides 2,048 bits of Serial Electrically Erasable Configuration Register memory that is used for device
configuration, and 2,048 bits Programmable Read-Only Memory (emulated EEPROM). Each of these memory spaces is internally
organized as 16 pages of 16 bytes. The device features a Software Write Protection feature with five different programmable
levels of protection for the emulated EEPROM array. The protection settings of the device can be made permanent if desired.
The emulated EEPROM memory operates with a supply voltage ranging from 2.4 V to 5.5 V for Read and 2.5 V to 5.5 V for Write.
The emulated EEPROM inside the SLG47004 operates as a slave device and utilizes a simple I2C compatible 2-wire digital serial
interface to communicate with a host controller commonly referred to as the bus Master. The Master initiates and controls all read
and write operations to the Slave devices on the serial bus, and both the Master and the Slave devices can transmit and receive
data on the bus.
Key features:
Low-voltage Operation
for Read: VCC = 2.4 V to 5.5 V
for Write: VCC = 2.5 V to 5.5 V
I2C-Compatible (2-Wire) Serial Interface
100 kHz Standard Mode
400 kHz Fast Mode (FM)
Software Write Protection of the EEPROM Emulation Array
Five configuration options
Protection settings can be made permanent
Low Current Consumption
Read Current 0.5 mA max
Page Write Current 3.0 mA max
Chip Erase Current 3.0 mA max
Standby Current (1.0 μA max)
16-byte Page Write Mode
Self-timed Write/Erase Cycle (20 ms max)
Reliability
Endurance: 1,000 write cycles
Data retention: 10 years at 125 °C
19.1 SERIAL NVM WRITE OPERATIONS
Write access to the NVM is possible by setting A3, A2, A1, A0 to “0000”, which allows serial write data for a single page only.
Upon receipt of the proper Control Byte and Word Address bytes, the SLG47004 will send an ACK. The device will then be ready
to receive page data, which is 16 sequential writes of 8-bit data words. The SLG47004 will respond with an ACK after each data
word is received. The addressing device, such as a bus Master, must then terminate the write operation with a Stop condition
after all page data is written. At that time the device will enter an internally self-timed write cycle, which will be completed within
tWR (20 ms). While the data is being written into the NVM Memory Array, all inputs, outputs, internal logic, and I2C access to the
Register data will be operational/valid. Please refer to Figure 237 for the SLG47004 Memory Map.
Note: The 16 programmed bytes should be in the same page. Any I2C command that does not meet specific requirements will
be ignored and NVM will remain unprogrammed.
Note: Special care must be taken when NVM page 14 is rewritten (registers [1919:1792]). This page contains rheostats
tolerance data that can be permanently lost during write/erase operation.
SLG47004 will ignore the Serial NVM Write command in case the self-programming procedure for programming rheostat value
into the NVM is in progress. The SLG47004 will respond with NACK in this case. Please refer to the Acknowledge Polling
section for more details.
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Data “1” cannot be re-programmed as data “0” without erasure. Each byte can only be programmed one time without erasure.
Acknowledge
Acknowledge
bit
Start
bit
bit
Bus Activity
Data (n + 1)
Data (n + 15)
Control Byte
Word Address (n)
Data (n)
A
10
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
9
ACK
ACK
P
SDA LINE
S
X
X
X
X
W
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
R/W bit
Figure 236: Page Write Command
A10 will be ignored during communication to SLG47004.
A9 = 1 will enable access to the NVM.
A9 = 1 and A8 = 0 corresponds to the 2K bits chip configuration NVM data.
A9 = 1 and A8 = 1 corresponds to the 2K bits of emulated EEPROM data.
A3, A2, A1, and A0 should be 0000 for the page write operation.
In a single page, if the data written to any byte is 00H, the contents of the matching byte in NVM memory will not be altered.
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2
I C Block Address
Memory Space
Lowest I2C
Address = 000h
2 kbits Register Data Configuration
A10 = 0
A9 = 0
A9 = 0
A9 = 1
A9 = 1
A9 = X
A8 = 0
Not Used
A10 = 0
A10 = 0
A10 = 0
A10 = 1
A8 = 1
A8 = 0
A8 = 1
A8 = X
2 kbits NVM Data Configuration
2 kbits EEPROM
Not Used
Highest I2C
Address = 7FFh
Figure 237: I2C Block Addressing
19.2 SERIAL NVM READ OPERATIONS
There are three read operations:
Current Address Read
Random Address Read
Sequential Read
Please refer to the Section 18 for more details.
19.3 SERIAL NVM ERASE OPERATIONS
The erase scheme allows a portion or the entire emulated EEPROM including the 2K bits NVM chip configuration to be erased
by modifying the contents of the Erase Registers (ERSE <2:0>). Changing the state of the ERSE is accomplished with a Byte
Write sequence with the requirements outlined in this section.
The ERSE registers are located on byte E3h.
The ERSE format is shown in Table 64, and the ERSE bit functions are included in Table 65.
Table 64: Erase Register Bit Format
b7
b6
b5
b4
b3
b2
b1
b0
PageErase
Register
ERSE2
ERSE1
ERSE0
ERSEB4
ERSEB3
ERSEB2
ERSEB1
ERSEB0
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Table 65: Erase Register Bit Function Description
Bit
7
Name
Type
W
Description
ERSE2
ERSE1
ERSE0
000: erase disable
110: cause the NVM erase: full NVM (4k bits) erase for ERSCHIP = 1 if
DIS_ERSCHIP = 0 or page erase for
Erase
Enable
6
W
ERSCHIP = 0
5
W
4
ERSEB4
ERSEB3
ERSEB2
ERSEB1
ERSEB0
W
3
W
Page
Selection
for Erase
Define the page address, which will be erased:
ERSB4 = 0 corresponds to the Upper 2K NVM used for chip configuration;
ERSB4 = 1 corresponds to the 2-k emulated EEPROM
2
W
1
W
0
W
Upon receipt of the proper Device Address and Erase Registers Address, the SLG47004 will send an ACK. The device will then
be ready to receive Erase Registers data. The SLG47004 will respond with an ACK after Erase Registers data word is received.
The addressing device, such as a bus Master, must then terminate the write operation with a Stop condition. At that time the
device will enter an internally self-timed erase cycle, which will be completed within tER ms. While the data is being written into
the Memory Array, all inputs, outputs, internal logic, and I2C access to the Register data will be operational/valid.
After the erase has taken place, the contents of ERSE bits will be set to “0” automatically. The internal erase cycle will be triggered
at the time the Stop Bit in the I2C command is received.
19.4 ACKNOWLEDGE POLLING
An Acknowledge Polling routine can be implemented to optimize time sensitive applications that would prefer not to wait the fixed
maximum write cycle time (tWR) or erase maximum cycle time (tER). This method allows the application to know immediately when
the Serial EEPROM emulation write/erase cycle has completed, so a subsequent operation can be started. Once the internally
self-timed write/erase cycle has started, an Acknowledge Polling routine can be initiated. This involves repeatedly sending a Start
condition followed by a valid Device Address byte (NVM block address) with the R/W bit set at Logic 0. The device will not respond
with an ACK while the write cycle is ongoing. Once the internal write/erase cycle has completed, emulated EEPROM will respond
with an ACK, allowing a new read, erase, or write operation to be immediately initiated.
The same behavior will happen during the self-programming procedure when the rheostat value is written into the NVM.
The length of the self-timed write cycle (tWR) and self-timed erase cycle (tER) is defined as the amount of time from the Stop
condition that begins the internal write operation to the Start condition of the first Device Address byte that includes NVM address
(A9 = 1; A8 = X) sent to the SLG47004, that it subsequently responds to with an ACK.
19.5 LOW POWER STANDBY MODE
Emulated EEPROM inside the SLG47004 has a low power standby mode which is enabled when any one of the following occurs:
A valid power-up sequence is performed
A Stop condition is received by the devices unless it initiates an internal write/erase cycle
At the completion of an internal write/erase cycle
An unsuccessful match of the device type identifier or hardware address in the Device Address byte occurs
19.6 EMULATED EEPROM WRITE PROTECTION
The SLG47004 utilizes a software scheme that allows a portion or the entire emulated EEPROM to be inhibited from being written
or erased by modifying the contents of the Write Protection Register (WPR). If desired, the WPR can be set so that it may no
longer be modified/erased, thereby making the current protection scheme permanent. The status of the WPR can be determined
by following a Random Read sequence. Changing the state of the WPR is accomplished with a Byte Write sequence with the
requirements outlined in this section.
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SLG47004
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The WPR register is located at E2 Address.
The WPR format is shown in Table 66, and the WPR bit functions are included in Table 67.
Table 66: Write/Erase Protect Register Format
b7
b6
b5
b4
b3
b2
b1
b0
WPR
Table 67: Write/Erase Protect Register Bit Function Description
WPRE
WPB1
WPB0
Bit
Name
Write Protect
Register Enable
Type
R/W
R/W
Description
0: No Software Write Protection enabled (default)
1: Write Protection is set by the state of WPB [1:0] bits
2
WPRE
WPB1
00: Upper quarter of emulated EEPROM is write protected (default)
01: Upper half of emulated EEPROM is write protected
10: Upper 3/4 of emulated EEPROM is write protected.
11: Entire emulated EEPROM is write protected.
Write Protect
Block Bits
1:0
WPB0
R/W
Write Protect Enable (WPRE): The Write Protect Enable Bit is used to enable or disable the device Software Write/Erase Protect.
A Logic 0 in this position will disable Software Write/Erase Protection, and a Logic 1 will enable this function.
Write Protect Block Bits (WPB1:WPB0): The Write Protect Block bits allow four levels of protection of the Memory Array, provided
that the WPRE bit is a Logic 1. If the WPRE bit is a Logic 0, the state of the WPB1:0 bits have no impact on device protection.
Protect Lock Bit (PRL): The Protect Lock Bit is used to permanently lock the current state of the WPR, as well as RPR and NPR
(see Section 18.5). A Logic 0 indicates that the WPR, RPR, and NPR can be modified, whereas a Logic 1 indicates the WPR,
RPR, and NPR has been locked and can no longer be modified. The PRL register bit is located at register [1824] address.
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20 Analog Temperature Sensor
The SLG47004 has an Analog Temperature sensor (TS) with an output voltage linearly-proportional to the Centigrade
temperature. The TS cell shares buffer with Vref 0, so it is impossible to use both cells simultaneously, its output can be connected
directly to the IO0 or IO1 or the ACPM1_L positive input. Using buffer causes low-output impedance, linear output and makes
interfacing to readout or control circuitry especially easy. Vref0 and Vref1 share output buffers with Temperature sensor. Note,
that user can use any of output buffers, but Temperature sensor is calibrated for Vref1 output buffer. The TS is rated to operate
over a -40 °C to 85 °C temperature range. The error in the whole temperature range does not exceed ±1.76 %. For more details
refer to Section 3.12.
VTS1 = -2.3 x T + 907.4
VTS2 = -2.8 x T + 1095.4
where:
VTS1 (mV) - TS Output Voltage, range 1
VTS2 (mV) - TS Output Voltage, range 2
T (°C) - Temperature
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Figure 238: Analog Temperature Sensor Structure Diagram
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1.25
1.2
Output Range 2
Output Range 1
1.15
1.1
1.05
1
0.95
0.9
0.85
0.8
0.75
0.7
T (°C)
Figure 239: TS Output vs. Temperature, VDD = 3.3 V
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GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
21 Register Definitions
21.1 REGISTER MAP
Table 68: Register Map
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
Matrix Output
0
1
2
OUT0:
IN0 of LUT2_0 or Clock Input of DFF0
3
4
0
5
6
LUT2_0 & DFF0
7
8
OUT1:
IN1 of LUT2_0 or Data Input of DFF0
9
10
11
12
1
13
14
15
16
17
18
OUT2:
IN0 of LUT2_1 or Clock Input of DFF1
LUT2_1 & DFF1
19
20
2
OUT3:
IN1 of LUT2_1 or Data Input of DFF1
21
22
23
24
25
26
OUT4:
IN0 of LUT2_2 or Clock Input of DFF2
27
3
28
29
30
31
32
33
34
LUT2_2 & DFF2
OUT5:
IN1 of LUT2_2 or Data Input of DFF2
35
36
4
37
38
39
OUT6:
LUT2_3 & PGen
IN0 of LUT2_3 or Clock Input of PGen
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Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Byte
OUT6:
IN0 of LUT2_3 or Clock Input of PGen
5
LUT2_3 & PGen
OUT7:
IN1 of LUT2_3 or nRST of PGen
OUT8:
IN0 of LUT3_0 or CLK Input of DFF3
6
7
8
OUT9:
LUT3_0 & DFF3
IN1 of LUT3_0 or Data Input of DFF3
OUT10:
IN2 of LUT3_0 or nRST (nSET) of DFF3
OUT11:
IN0 of LUT3_1 or CLK Input of DFF4
OUT12:
LUT3_1 & DFF4
IN1 of LUT3_1 or Data Input of DFF4
9
OUT13:
IN2 of LUT3_1 or nRST (nSET) of DFF4
A
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Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
84
85
86
A
OUT14:
IN0 of LUT3_2 or CLK Input of DFF5
87
88
89
90
91
92
93
94
95
96
97
98
B
C
D
E
F
OUT15:
LUT3_2 & DFF5
IN1 of LUT3_2 or Data Input of DFF5
OUT16:
IN2 of LUT3_2 or nRST (nSET) of DFF5
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
OUT17:
IN0 of LUT3_3 or CLK Input of DFF6
OUT18:
LUT3_3 & DFF6
IN1 of LUT3_3 or Data Input of DFF6
OUT19:
IN2 of LUT3_3 or nRST (nSET) of DFF6
OUT20:
IN0 of LUT3_4 or CLK Input of DFF7
LUT3_4 & DFF7
OUT21:
IN1 of LUT3_4 or Data Input of DFF7
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Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
OUT21:
IN1 of LUT3_4 or Data Input of DFF7
10
LUT3_4 & DFF7
OUT22:
IN2 of LUT3_4 or nRST (nSET) of DFF7
11
12
13
OUT23:
IN0 of LUT3_5 or CLK Input of DFF8
OUT24:
LUT3_5 & DFF8
IN1 of LUT3_5 or Data Input of DFF8
OUT25:
IN2 of LUT3_5 or nRST (nSET) of DFF8
OUT26:
IN0 of LUT3_6 or CLK Input of DFF9
14
15
OUT27:
LUT3_6 & DFF9
IN1 of LUT3_6 or Data Input of DFF9
OUT28:
IN2 of LUT3_6 or nRST (nSET) of DFF9
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Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
15
OUT29:
IN0 of LUT3_7 or CLK Input of DFF11
Delay1 Input (or Counter1 nRST Input)
16
17
18
19
1A
OUT30:
Multi_function1
IN1 of LUT3_7 or nRST (nSET) of DFF11
Delay1 Input (or Counter1 nRST Input)
OUT31:
IN2 of LUT3_7 or Data of DFF11
Delay1 Input (or Counter1 nRST Input)
OUT32:
IN0 of LUT3_8 or CLK Input of DFF12
Delay2 Input (or Counter2 nRST Input)
OUT33:
Multi_function2
IN1 of LUT3_8 or nRST (nSET) of DFF12
Delay2 Input (or Counter2 nRST Input)
OUT34:
IN2 of LUT3_8 or Data of DFF12
Delay2 Input (or Counter2 nRST Input)
OUT35:
Multi_function3
IN0 of LUT3_9 or CLK Input of DFF13
Delay3 Input (or Counter3 nRST Input)
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Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
OUT36:
IN1 of LUT3_9 or nRST (nSET) of DFF13
Delay3 Input (or Counter3 nRST Input)
1B
Multi_function3
OUT37:
IN2 of LUT3_9 or Data of DFF13
Delay3 Input (or Counter3 nRST Input)
1C
1D
1E
1F
20
OUT38:
IN0 of LUT3_10 or CLK Input of DFF14
Delay4 Input (or Counter4 nRST Input)
OUT39:
Multi_function4
IN1 of LUT3_10 or nRST (nSET) of DFF14
Delay4 Input (or Counter4 nRST Input)
OUT40:
IN2 of LUT3_10 or Data of DFF14
Delay4 Input (or Counter4 nRST Input)
OUT41:
IN0 of LUT3_11 or CLK Input of DFF15
Delay5 Input (or Counter5 nRST Input)
OUT42:
Multi_function5
IN1 of LUT3_11 or nRST (nSET) of DFF15
Delay5 Input (or Counter5 nRST Input)
OUT43:
IN2 of LUT3_11 or Data of DFF15
Delay5 Input (or Counter5 nRST Input)
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Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
OUT44:
IN0 of LUT3_12 or CLK Input of DFF16
Delay6 Input (or Counter6 nRST Input)
21
OUT45:
Multi_function6
IN1 of LUT3_12 or nRST (nSET) of DFF16
Delay6 Input (or Counter6 nRST Input)
22
23
24
25
26
OUT46:
IN2 of LUT3_12 or Data of DFF16
Delay6 Input (or Counter6 nRST Input)
OUT47:
IN0 of LUT3_13 or Input of Pipe Delay or UP signal of
RIPP CNT
OUT48:
LUT3_13 & Pipe Delay (RIPP CNT)
IN1 of LUT3_13 or nRST of Pipe Delay or nSET of RIPP
CNT
OUT49:
IN2 of LUT3_13 or Clock of Pipe
Delay_RIPP CNT
OUT50:
IN0 of LUT4_0 or CLK Input of DFF10
LUT4_DFF10
OUT51:
IN1 of LUT4_0 or Data of DFF10
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Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
OUT52:
IN2 of LUT4_0 or nRST (nSET) of DFF10
27
LUT4_DFF10
OUT53:
IN3 of LUT4_0
28
29
2A
2B
2C
OUT54:
IN0 of LUT4_1 or CLK Input of DFF17
Delay0 Input (or Counter0 nRST Input)
OUT55:
IN1 of LUT4_1 or nRST of DFF17
Delay0 Input (or Counter0 nRST Input)
Delay/Counter0 External CLK source
Multi_function0
OUT56:
IN2 of LUT4_1 or nSET of DFF17
Delay0 Input (or Counter0 nRST Input)
Delay/Counter0 External CLK source
KEEP Input of FSM0
OUT57:
IN3 of LUT4_1 or Data of DFF17
Delay0 Input (or Counter0 nRST Input)
UP Input of FSM
Programmable delay
Filter/Edge detector
OUT58: Programmable delay/edge detect input
OUT59: Filter/Edge detect input
Datasheet
10-Mar-2021
Revision 2.4
232 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
OUT60: IO0 DOUT
2D
IO0
OUT61: IO0 DOUT OE
OUT62: IO1 DOUT
2E
2F
30
31
32
IO1
IO2
IO3
OUT63: IO1 DOUT OE
OUT64: IO2 DOUT
OUT65: IO2 DOUT OE
OUT66: IO3 DOUT
OUT67: IO3 DOUT OE
Datasheet
10-Mar-2021
Revision 2.4
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
OUT68: IO4 DOUT
33
IO4
OUT69: IO4 DOUT OE
OUT70: IO5 DOUT
34
35
36
37
38
IO5
OUT71: IO5 DOUT OE
OUT72: IO6 DOUT
IO6
OUT73: IO6 DOUT OE
OUT74:
set0 of Auto Calibration
Programmable Trim Block0
OUT75:
clock0 of Auto Calibration
Datasheet
10-Mar-2021
Revision 2.4
234 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
OUT76:
reload0 of Auto Calibration
39
Programmable Trim Block0
OUT77:
program0 of Auto Calibration
3A
3B
3C
3D
3E
OUT78:
Rheostat Counter0 up/down
0: down, 1: up. (register [920] = 0)
0: up, 1: down. (register [920] = 1)
Digital Rheostat
OUT79:
set1 of Auto Calibration
OUT80:
clock1 of Auto Calibration
Programmable Trim Block1
OUT81:
reload1 of Auto Calibration
OUT82:
program1 of Auto Calibration
OUT83:
Rheostat Counter1 up/down
0: down, 1: up. (register [923] = 0)
0: up, 1: down. (register [923] = 1)
Digital Rheostat
Datasheet
10-Mar-2021
Revision 2.4
235 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
OUT84:
FIFO Reset of PT blocks
FIFO nRST of the control logic of reload0/reload1/auto
program0/auto program1
3F
OUT85:
Chopper ACMP Power Up
Chopper ACMP
Digital Rheostat
Analog Switch0
Analog Switch1
ACMP0
40
41
42
43
44
OUT86:
Rheostat Charge pump enable
OUT87:
ASW0 enable/Half bridge enable
OUT88:
ASW1 enable/Half bridge data
OUT89:
ACMP0 Power Up
OUT90:
ACMP1 Power Up
ACMP1
OUT91:
OSC0 ENABLE
OSC0
Datasheet
10-Mar-2021
Revision 2.4
236 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
OUT92:
OSC1
OSC1 ENABLE
45
OUT93:
OSC2 ENABLE
OSC2
46
47
48
49
4A
OUT94:
Temperature Sensor
VREFO TEMPSEN/VREFO Power Up
OUT95:
HDBUF ENABLE
HDBUF
OUT96:
Op Amp0
Op Amp1
Op Amp2
Op amps
OP0(Op Amp ACMP0) Power Up
OUT97:
OP1(Op Amp ACMP1) Power Up
OUT98:
OP2 Power Up (In Amp Mode)
OUT99:
OP VREF ENABLE
Datasheet
10-Mar-2021
Revision 2.4
237 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
600
601
602
603
604
605
606
607
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
4B
ACMP0
ACMP Low Energy Power Up enable
(ACMP power after bg_ok)
608
1: enable
609
610
ACMP input path LPF enable
ACMP sampling mode enable
1: enable
1: enable
0: short time wake sleep enable
1: short time wake sleep disable
1: enable
611
612
613
614
ACMP short time wake sleep mode disable
ACMP wake sleep function enable
ACMP Vref path LPF enable
(when ACMP hysteresis > 196 mV)
4C
1: enable
00: 1
01: 0.5
10: 1/3
11: 1/4
00: OP0 output
01: from Pin
10: tie VDD
ACMP input divider selection
ACMP input mux selection
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
4D
4E
000000-111111:
ACMP Low to High Vref selection
ACMP High to Low Vref selection
32 mV ~2.048 V/step = 32 mV
000000-111111:
32 mV ~2.048 V/step = 32 mV
ACMP1
ACMP Low Energy Power Up enable
(ACMP power after bg_ok)
630
1: enable
4E
631
632
ACMP input path LPF enable
ACMP sampling mode enable
1: enable
1: enable
0: short time wake sleep enable
1: short time wake sleep disable
1: enable
633
634
635
636
ACMP short time wake sleep mode disable
ACMP wake sleep function enable
ACMP Vref path LPF enable
(when ACMP hysteresis > 196 mV)
4F
1: enable
00: 1
01: 0.5
10: 1/3
11: 1/4
ACMP input divider selection
637
Datasheet
10-Mar-2021
Revision 2.4
238 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
638
00: OP1 output
01: from Pin
4F
ACMP input mux selection
10: ACMP0 input mux output
11: VrefO1 Temp sensor output
639
640
641
642
643
644
645
646
647
648
649
650
651
000000-111111:
ACMP Low to High Vref selection
ACMP High to Low Vref selection
32 mV ~2.048 V/step = 32 mV
50
51
000000-111111:
32 mV ~2.048 V/step = 32 mV
Vref
652
653
654
655
656
657
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
51
0: ACMP0 VREF
1: Temp Sensor
658
VREFO0 input source selection
659
660
VREFO0 output buffer enable
VREFO0 register Power Up
1: enable
VREFO0 register power on signal
52
0: Power Up from reg
1: from matrix
no use
661
662
663
664
665
VREFO0 Power Up selection
Reserved
VREFO1's temp sensor to ACMP1 input path en- Temp Sensor output to ACMP1 enable
able
1: enable
0:1V; 1:1.2V
0: ACMP1 Vref
1: TS
VREFO1's temp sensor range selection
VREFO1 input source selection
666
667
VREFO1 output buffer enable
VREFO1 register Power Up
1: enable
VrefO1 register power on signal
53
0: Power Up from reg
1: from matrix
668
669
VREFO1 Power Up selection
ACMP Vrefs source selection
ACMP Vref gen source selection
(0: VBG, 1: VDD
)
670
671
672
673
674
ACMP0 external Vref enable
ACMP1 external Vref enable
Reserved
Reserved
Reserved
1:enable
1:enable
54
54
Datasheet
10-Mar-2021
Revision 2.4
239 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
675
676
677
678
679
680
681
682
683
684
685
686
687
Reserved
54
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
55
OSC1
when matrix output enable/pd control signal = 0:
0: auto on by delay cells
688
689
OSC1 turn on by register
1: always on
0: matrix down
1: matrix on
0: internal OSC1
1: external clock from PAD15
00: div 1
01: div 2
10: div 4
11: div8
OSC1 matrix power down or on select
OSC1 external clock source enable
690
691
OSC1 post divider ratio control
56
692
693
694
000: /1
001:/2
010:/4
011: /3
100: /8
101: /12
110: /24
111: /64
0: disable
1: enable
OSC1 matrix divider ratio control
OSC1 matrix out enable
695
696
697
698
699
Reserved
Reserved
Reserved
0: disable
1: enable
700
OSC1 2nd output to matrix enable
57
701
702
000: /1
001: /2
010: /4
011: /3
100: /8
101: /12
110: /24
111: /64
OSC1 2nd matrix divider ratio control
703
OSC2
Datasheet
10-Mar-2021
Revision 2.4
240 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
when matrix output enable/pd control signal = 0:
0: auto on by delay cells
1: always on
704
OSC2 turn on by register
0: matrix down
1: matrix on
0: internal OSC2
1: external clock from IO2
0: disable
1: enable
00: div 1
01: div 2
10: div 4
11: div8
705
706
OSC2 matrix power down or on select
OSC2 external clock source enable
OSC2 matrix out enable
58
707
708
OSC2 post divider ratio control
709
710
711
000: /1
001: /2
010: /4
011: /3
100: /8
101: /12
110: /24
111: /64
OSC2 matrix divider ratio control
OSC2 startup delay with 100ns
712
0: enable
1: disable
713
59
714
715
716
717
718
719
Reserved
Reserved
Reserved
Op Amp0 sr boost for OP 8 MHz
Op Amp1 sr boost for OP 8 MHz
Op Amp2 sr boost for OP 8 MHz
0: enable, 1: disable
0: enable, 1: disable
0: enable, 1: disable
OSC0
when matrix output enable/pd control signal = 0:
0: auto on by delay cells
1: always on
720
OSC0 turn on by register
0: matrix down
1: matrix on
0: internal OSC0
1: external clock from IO0
0: disable
1: enable
00: div 1
01: div 2
10: div 4
11: div8
721
722
OSC0 matrix power down or on select
OSC0 external clock source enable
OSC0 matrix out enable
5A
723
724
OSC0 post divider ratio control
725
726
727
000: /1
001: /2
010: /4
011: /3
100: /8
101: /12
110: /24
111: /64
OSC0 matrix divider ratio control
5B
728
Datasheet
10-Mar-2021
Revision 2.4
241 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
enable OSC0 output gating by wake_sleep signal
(note: the wake_sleep clock is separated path, so it
is not gated)
0: no gating
1: enable
729
0: disable
1: enable
730
OSC0 2nd output to matrix enable
731
732
000: /1
001: /2
010: /4
011: /3
100: /8
101: /12
110: /24
111: /64
5B
OSC0 2nd matrix divider ratio control
733
734
735
Reserved
Reserved
Analog Switch
0: small NMOS disable
736
ASW0 small NMOS enable selection
ASW1 small PMOS enable selection
ASW0 big PMOS control selection
ASW1 big NMOS control selection
ASW half bridge mode enable
1: small NMOS enable by matrix87
0: small PMOS disable
1: small PMOS enable by matrix88
0: control by matrix87
1:control by Op Amp0
0: control by matrix88
1:control by Op Amp1
0: analog switch mode
1: half bridge (enable from matrix87; data from matrix88)
00: bypass
01: 20ns
10: 100ns
11: 500ns
737
738
739
5C
740
741
ASW half bridge dead time select
Reserved
742
743
Op Amp0/1/2
744
00: 128 kHz
01: 512 kHz
10: 2 MHz
11: 8 MHz
00: 128 kHz
01: 512 kHz
10: 2 MHz
11: 8 MHz
00: 128 kHz
01: 512 kHz
10: 2 MHz
11: 8 MHz
Op Amp0 bandwidth selection
Op Amp1 bandwidth selection
Op Amp2 bandwidth selection
745
746
747
5D
748
749
0: Op amp mode
1: ACMP mode
0: Op amp mode
1: ACMP mode
750
751
ACMP/Op Amp0 mode
ACMP/Op Amp1 mode
0: Op amp input common voltage higher than VDD-1.5V,
enable CP
5E
752
Op Amp0 charge pump disable
1: Op amp input common voltage lower than VDD-1.5V,
disable CP
Datasheet
10-Mar-2021
Revision 2.4
242 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
0: Op amp input common voltage higher than VDD-1.5V,
enable CP;
753
754
Op Amp1 charge pump disable
Op Amp2 charge pump disable
1: Op amp input common voltage lower than VDD-1.5V,
disable CP
0: Op amp input common voltage higher than VDD-1.5V,
enable CP
1: Op amp input common voltage lower than VDD-1.5V,
disable CP
0: path on (for normal function)
1: path off (for trim function)
0: without buffer
1: with buffer
755
756
Path between Op Amp0/1 and Op Amp2
Op Amp2's Vref buffer bypass control
5E
0: on/off follows op amp
1: always on except input common voltage of op amp low-
er than VDD-1.5 V
0: on/off follows op amp
1: always on except input common voltage of op amp low-
er than VDD-1.5V
0: on/off follows op amp
1: always on except input common voltage of op amp low-
er than VDD-1.5V
757
758
759
Supporting blocks for Op Amp0 on/off
Supporting blocks for Op Amp1 on/off
Supporting blocks for Op Amp2 on/off
760
761
762
763
764
765
Op amp ACMP Vref0 output selection[0]
Op amp ACMP Vref0 output selection[1]
Op amp ACMP Vref0 output selection[2]
Op amp ACMP Vref0 output selection[3]
Op amp ACMP Vref0 output selection[4]
Op amp ACMP Vref0 output selection[5]
000000-111111: 32 mV ~2.048 V/step = 32 mV
5F
Op amp ACMP Vref0 register enable
(select by register [782])
0: dynamic on/off
1: Vref enable
766
767
768
769
770
771
772
773
Vref0 to op amp/ACMP input enable
Op amp ACMP Vref1 output selection[0]
Op amp ACMP Vref1 output selection[1]
Op amp ACMP Vref1 output selection[2]
Op amp ACMP Vref1 output selection[3]
Op amp ACMP Vref1 output selection[4]
Op amp ACMP Vref1 output selection[5]
0:disable; 1: enable
000000-111111: 32 mV ~2.048 V/step = 32 mV
60
Op amp ACMP Vref1 register enable
(select by register [783])
Vref1 to op amp/ACMP input enable
0: dynamic on/off
1: Vref enable
0:disable; 1: enable
0: Vref to ACMP negative input
1: Vref to ACMP positive input
774
775
776
Op amp ACMP Vref0 output selection
0: Vref to ACMP negative input
1: Vref to ACMP positive input
0: disable
1: enable
0: disable
1: enable
0: 2.048 V
1: VDD
0: 2.048 V
1: VDD
0: from register [766]
1: from matrix99
777
778
779
780
781
782
Op amp ACMP Vref1 output selection
Op amp Vref0 LPF enable
Op amp Vref1 LPF enable
61
Op amp ACMP Vref0 input voltage selection
Op amp ACMP Vref1 input voltage selection
Op amp ACMP vref0 enable selection
Datasheet
10-Mar-2021
Revision 2.4
243 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
0: from register [774]
1: from matrix99
61
783
Op amp ACMP vref1 enable selection
LUT3_2/DFF5
784
785
786
<2:0>: LUT3_2 <2:0>
<3>:LUT3_2 <3>/DFF5 Active level selection for
RST/SET
0: Active low level reset/set,
1: Active high level reset/set
787
<4>:LUT3_2<4>/DFF5
0: RSTB from Matrix Output,
1: SETB from Matrix Output
62
LUT3_2_DFF5 setting
788
<5>:LUT3_2 <5>/DFF5 Initial Polarity Select 0: Low, 1:
High
<6>:LUT3_2 <6>/DFF5 Output Select
0: Q output, 1: QB output
<7>:LUT3_2 <7>/DFF5 or Latch Select
0: DFF function, 1: Latch function
789
790
791
LUT3_3/DFF6
792
793
794
<2:0>: LUT3_3 <2:0>
<3>:LUT3_3 <3>/DFF6 Active level selection for
RST/SET
0: Active low level reset/set, 1: Active high level reset/set
795
<4>:LUT3_3<4>/DFF6
0: RSTB from Matrix Output, 1: SETB from Matrix
Output
LUT3_3_DFF6 setting
63
796
<5>:LUT3_3 <5>/DFF6 Initial Polarity Select
0: Low, 1: High
<6>:LUT3_3 <6>/DFF6 Output Select
0: Q output, 1: QB output
<7>:LUT3_3 <7>/DFF6 or Latch Select
0: DFF function, 1: Latch function
797
798
799
LUT3_4/DFF7
800
801
802
<2:0>: LUT3_4 <2:0>
<3>:LUT3_4 <3>/DFF7 Active level selection for
RST/SET
803
0: Active low level reset/set, 1: Active high level reset/set
<4>:LUT3_4<4>/DFF7
0: RSTB from Matrix Output, 1: SETB from Matrix Output
<5>:LUT3_4 <5>/DFF7 Initial Polarity Select
0: Low, 1: High
<6>:LUT3_4 <6>/DFF7 Output Select
0: Q output, 1: QB output
<7>:LUT3_4 <7>/DFF7 or Latch Select
0: DFF function, 1: Latch function
64
LUT3_4_DFF7 setting
LUT3_4_DFF7 setting
804
805
806
64
807
LUT3_5/DFF8
Datasheet
10-Mar-2021
Revision 2.4
244 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
808
809
<2:0>: LUT3_5 <2:0>
810
<3>:LUT3_5 <3>/DFF8 Active level selection for
RST/SET
0: Active low level reset/set, 1: Active high level reset/set
811
<4>:LUT3_5<4>/DFF8
65
LUT3_5_DFF8 setting
812
813
814
815
0: RSTB from Matrix Output, 1: SETB from Matrix Output
<5>:LUT3_5 <5>/DFF8 Initial Polarity Select 0: Low, 1:
High
<6>:LUT3_5 <6>/DFF8 Output Select
0: Q output, 1: QB output
<7>:LUT3_5 <7>/DFF8 or Latch Select
0: DFF function, 1: Latch function
LUT3_6/DFF9
816
817
818
<2:0>: LUT3_6 <2:0>
<3>:LUT3_6 <3>/DFF9 Active level selection for
RST/SET
0: Active low level reset/set, 1: Active high level reset/set
819
<4>:LUT3_6<4>/DFF9
0: RSTB from Matrix Output, 1: SETB from Matrix
Output
66
LUT3_6_DFF9 setting
820
<5>:LUT3_6 <5>/DFF9 Initial Polarity Select
0: Low, 1: High
<6>:LUT3_6 <6>/DFF9 Output Select
0: Q output, 1: QB output
<7>:LUT3_6 <7>/DFF9 or Latch Select
0: DFF function, 1: Latch function
0: LUT3_2
1: DFF5
0: LUT3_3
1: DFF6
0: LUT3_4
1: DFF7
0: LUT3_5
1: DFF8
0: LUT3_5
1: DFF8
821
822
823
824
825
826
827
828
829
LUT3_2 or DFF5 Select
LUT3_3 or DFF6 Select
LUT3_4 or DFF7 Select
LUT3_5 or DFF8 Select
LUT3_6 or DFF9 Select
LUT4_0 or DFF10 Select
67
0: LUT4_0
1: DFF10
830
831
Reserved
Reserved
LUT4_0/DFF10
Datasheet
10-Mar-2021
Revision 2.4
245 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
832
833
834
835
836
837
838
839
840
841
68
<9:0>: LUT4_0 <9:0>
<10>:LUT4_0 <10>/DFF10 stage selection
0: Q of first DFF; 1 Q of second DFF
LUT4_0_DFF10 setting
842
<11>:LUT4_0 <11>/DFF10 Active level selection for
RST/SET
0: Active low level reset/set, 1: Active high level reset/set
843
69
<12>:LUT4_0 <12>/DFF10
0: RSTB from Matrix Output, 1: SETB from Matrix Output
<13>:LUT4_0 <13> /DFF10 Initial Polarity Select
0: Low, 1: High
<14>:LUT4_0 <14>/DFF10 Output Select
0: Q output, 1: QB output
844
845
846
847
<15>:LUT4_0 <15>/DFF10 or Latch Select
0: DFF function, 1: Latch function
LUT3_13/Pipe Delay (RIPP CNT)
848
849
850
851
852
853
854
at LUT/pipe delay mode
bit<7:4>: LUT3_13 <7:4> / REG_S1<3:0> pipe delay out1
sel
bit<3:0>: LUT3_13 <3:0> / REG_S0<3:0> pipe delay out0
sel
6A
LUT value or pipe delay out sel or nSET/END value at RIPP CNT mode
bit<2:0> is the nSET value.
bit<5:3> is the END value
bit<6> is the range control:
0: full cycle, 1: range cycle
bit<7> No used
855
0: Active low level reset/set
1: Active high level reset/set
Out of LUT3_13 or Out0 of Pipe Delay/RIPP CNT 0: LUT3_13
856
857
858
859
Active level selection for RST/SET
Select
1: OUT0 of Pipe Delay or RIPP CNT
0: Pipe delay mode selection
1: Ripple Counter mode selection
0: Non-inverted
1: Inverted
PIPE_RIPP_CNT_S
6B
Pipe Delay OUT1 Polarity Select
860
861
862
863
Reserved
Reserved
Reserved
Reserved
Programmable Delay
Datasheet
10-Mar-2021
Revision 2.4
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
864
00: 125ns
01: 250ns
10: 375ns
11: 500ns
Delay Value Select for Programmable Delay &
Edge Detector
865
866
867
6C
00: Rising Edge Detector
Select the Edge Mode of Programmable Delay & 01: Falling Edge Detector
Edge Detector
10: Both Edge Detector
11: Both Edge Delay
Filter/Edge Detector
0: filter
1: edge detect
868
Filter or Edge Detector selection
0: output non-invert
1: output invert
00: Rising Edge Detect
01: Falling Edge Detect
10: Both Edge Detect
11: Both Edge DLY
869
870
Output Polarity Select
Select the edge mode
6C
871
Chopper ACMP
872
00: from In Amp out
Chopper ACMP positive input selection for calibra- 01: from Op Amp0 out
tion channel0
10: from Op Amp1 out
11: IO1
00: from In Amp out
873
874
Chopper ACMP positive input selection for calibra- 01: from Op Amp0 out
6D
tion channel1
10: from Op Amp1 out
11: IO1
875
876
877
878
879
880
881
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0: output non-invert
1: output invert
882
Output Polarity Select
883
884
885
886
887
888
6E
Reserved
Reserved
889
6F
890
891
Reserved
Reserved
Calibration
Datasheet
10-Mar-2021
Revision 2.4
247 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
0: calibration channel0
1: calibration channel1
0:calibration channel auto selection
1: from register [892]
892
893
auto calibration channel selection by register
auto calibration channel selection source selection
0: From Chopper ACMP
6F
894
895
RH_CNT1 clock source selection
RH_CNT0 clock source selection
(Chopper ACMP changes one time per rheostat clock)
1: from matrix directly
0: From Chopper ACMP
(Chopper ACMP changes one time per rheostat clock)
1: from matrix directly
896
897
898
0000: OSC1
0001:OSC1/8
0010:OSC1/64
0011: OSC1/512
0100: OSC0
0101:OSC0/8
Calibration0 clock divider
0110: OSC0/64
0111: OSC0/512
1000: OSC0/4096
1001: OSC0/32768
1010: OSC0/262144 1011/1100/1101/1110: GND
1111: EXTCLK
899
70
0: chopper ACMP
1: matrix83
0: auto calibration enable
1: disable
900
901
Up/down selection
auto_calibration disable
902
903
904
905
906
Reserved
Reserved
0000: OSC1
0001:OSC1/8
0010:OSC1/64
0011: OSC1/512
0100: OSC0
0101: OSC0/8
Calibration1 clock divider
0110: OSC0/64
0111: OSC0/512
1000: OSC0/4096
1001: OSC0/32768
1010: OSC0/262144 1011/1100/1101/1110: GND
1111: EXTCLK
907
71
0: chopper ACMP
1: matrix83
0: auto calibration enable
1: disable
908
909
Up/down selection
auto_calibration disable
910
911
Reserved
Reserved
Digital Rheostats
Datasheet
10-Mar-2021
Revision 2.4
248 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
0: control by matrix86
1: on
0: control by matrix86
1: on
0: from LPBG chopper OSC
1: from OSC1
912
913
914
915
916
POTCP0 turn on by register
POTCP1 turn on by register
POTCP0/1 clock source selection
POTCP0/1 clock source select from register
Reserved
0: by register [914]
1: calibration auto on
72
917
918
919
Reserved
Reserved
Reserved
0: default (up = 0 down mode, up = 1 up mode)
1: (up = 0 up mode, up = 1 down mode)
920
Polarity selection of RH_CNT0 UP signal
921
922
Reserved
Reserved
0: default (up = 0 down mode, up = 1 up mode)
1: (up = 0 up mode, up = 1 down mode)
923
Polarity selection of RH_CNT1 UP signal
73
924
925
926
927
Reserved
Reserved
Reserved
Reserved
HD Buffer
928
929
930
931
932
933
Chop ACMP Vref selection for calibration
channel 0
000000-111111: 1/64 ~ 64/64
(divider input select by register [946])
74
Chop ACMP calibration channel0 external Vref se- 0: external Vref (pin18)
934
lection
1: internal Vref
935
936
937
938
939
940
941
Reserved
000000-111111: 1/64 ~ 64/64
(divider input select by register [946])
Chop ACMP Vref selection for calibration channel 1
75
Chop ACMP calibration channel1 external Vref se- 0: external Vref (pin18)
942
943
lection
1: internal Vref
Reserved
Datasheet
10-Mar-2021
Revision 2.4
249 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
HD buffer register enable
(select by register [945])
0: disable
1: enable
0: from register [944]
1: from matrix95
944
945
HD buffer enable selection
0: from HD buffer output
1: from op amp Vref voltage (2.048/VDD selection register
in Vref block)
946
Chop ACMP Vref divider input selection
76
947
948
949
950
951
Reserved
Reserved
Reserved
Reserved
Reserved
CP OSC/Regulator
0: multiple OSC mode
1: single OSC mode
952
CPOSC single or multiple mode select
953
954
Reserved
00: 250 kHz
01: 1 MHz
10: 4 MHz
11: 8 MHz
CPOSC0 frequency select
955
77
956
Reserved
Reserved
957
958
959
960
961
962
Reserved
Reserved
Reserved
00: 250 kHz
01: 1 MHz
10: 4 MHz
11: 8 MHz
CPOSC1 frequency select
963
78
964
Reserved
Reserved
965
966
967
968
Reserved
Reserved
969
970
Reserved
00: 250 kHz
01: 1 MHz
10: 4 MHz
11: 8 MHz
CPOSC2 frequency select
971
79
972
973
974
975
Reserved
Reserved
Reserved
Datasheet
10-Mar-2021
Revision 2.4
250 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
976
00: none
01: internal Vref
10: Rheostat Vref
11: external Vref
Buffer Vref select
977
978
979
980
981
982
983
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7A
0: Keep existing condition
984
985
I2C soft reset
1: Reset execution, reload NVM to registers
0: disable
1: enable
IO latch enable during I2C write
986
987
Reserved
Reserved
7B
988
Reserved
989
Reserved
990
Reserved
991
992
993
994
995
996
997
998
Reserved
Matrix Input 32
Matrix Input 33
Matrix Input 34
Matrix Input 35
Matrix Input 36
Matrix Input 37
Matrix Input 38
Matrix Input 39
I2C_virtual_0 Input
I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
I2C_virtual_5 Input
I2C_virtual_6 Input
I2C_virtual_7 Input
7C
7D
7E
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
Reserved
Reserved
Datasheet
10-Mar-2021
Revision 2.4
251 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1016
1017
1018
1019
I2C slave address
0: from register [1016]
1: from PAD15
0: from register [1017]
1: from PAD16
0: from register [1018]
1: from PAD17
0: from register [1019]
1: from PAD18
1020
1021
1022
1023
slave address selection bit0
slave address selection bit1
slave address selection bit2
slave address selection bit3
7F
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
80
Reserved
Reserved
81
Reserved
Reserved
1039
1040
1041
1042
1043
1044
1045
1046
Reserved
82
Reserved
Reserved
1047
1048
1049
1050
1051
1052
1053
1054
Reserved
83
Reserved
Reserved
1055
Datasheet
10-Mar-2021
Revision 2.4
252 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
Reserved
84
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
85
86
87
88
Datasheet
10-Mar-2021
Revision 2.4
253 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
Reserved
89
Reserved
Reserved
Reserved
8A
8B
8C
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8D
8E
Reserved
Reserved
Datasheet
10-Mar-2021
Revision 2.4
254 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
8E
Reserved
8F
Reserved
Reserved
1151
SCL/SDA
1152
00: digital without Schmitt trigger
01: digital with Schmitt trigger
10: low voltage digital in
11: analog IO
input mode configuration
1153
90
1154
1155
Reserved
0: I2C fast mode +
I2C mode selection
1: I2C standard/fast mode
IO0
1156
1157
1158
1159
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
input mode configuration
output mode configuration
90
1160
1161
00: floating
01: 10k
Pull-up/down resistance selection
Pull-up/down selection
10: 100k
11: 1M
91
0: Pull-down
1: Pull-up
1162
IO1
1163
1164
1165
1166
1167
1168
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
00: floating
01: 10K
10: 100K
11: 1M
input mode configuration
output mode configuration
91
Pull-up/down resistance selection
Pull-up/down selection
92
0: Pull-down
1: Pull-up
1169
IO2
Datasheet
10-Mar-2021
Revision 2.4
255 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1170
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
00: floating
01: 10K
10: 100K
11: 1M
input mode configuration
output mode configuration
1171
1172
92
1173
1174
1175
Pull-up/down resistance selection
Pull-up/down selection
0: Pull-down
1: Pull-up
93
1176
IO3
1177
1178
1179
1180
1181
1182
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
00: floating
01: 10K
10: 100K
11: 1M
input mode configuration
output mode configuration
93
Pull-up/down resistance selection
Pull-up/down selection
0: Pull-down
1: Pull-up
1183
IO4
1184
1185
1186
1187
1188
1189
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
00: floating
01: 10K
10: 100K
11: 1M
input mode configuration
output mode configuration
94
Pull-up/down resistance selection
Pull-up/down selection
0: Pull-down
1: Pull-up
1190
IO5
Datasheet
10-Mar-2021
Revision 2.4
256 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
94
1191
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
00: floating
01: 10K
10: 100K
11: 1M
input mode configuration
1192
1193
1194
1195
1196
output mode configuration
95
Pull-up/down resistance selection
Pull-up/down selection
0: Pull-down
1: Pull-up
1197
IO6
1198
1199
1200
1201
1202
1203
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
00: floating
01: 10K
10: 100K
11: 1M
0: Pull-down
1: Pull-up
95
input mode configuration
output mode configuration
96
Pull-up/down resistance selection
Pull-up/down selection
1204
I0
1205
1206
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
input mode configuration
96
0: disable
1: enable
1207
IO fast Pull-up/down enable
1208
1209
1210
1211
1212
1213
1214
1215
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
97
Datasheet
10-Mar-2021
Revision 2.4
257 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1216
1217
1218
1219
mulit_function selection
dly2lut selection
Multi0 register configure
output selection of LUT4_1/DFF17:
0: LUT4_1
98
1220
1: DFF17
1221
1222
1223
external clock selection
00: DLY
01: one shoot
10: frequency detect
11: CNT register [1238] = 0
DLY/CNT0 Mode Selection
1224
1225
1226
00: both edge
01: falling edge
10: rising edge
11: High Level Reset (only in CNT mode)
DLY/CNT0 edge Mode Selection
1227
1228
1229
Clock source sel[3:0]
0000: 25M(OSC2)
0001: 25M/4
0010: 2M(OSC1)
0011: 2M/8
0100: 2M/64
99
0101: 2M/512
0110: 2K(OSC0)
0111: 2K/8
DLY/CNT0 Clock Source Select
1000: 2K/64
1001: 2K/512
1230
1010: 2K/4096
1011: 2K/32768
1100: 2K/262144
1101: CNT6_END
1110: External
1111: Not used
0: Reset to 0
1: Set to data
0: Default Mode,
1: Wake Sleep Mode
(registers [1224:1223] = 11)
1231
1232
FSM0 SET/RST Selection
wake sleep mode selection
0: low
1: high
0: bypass
1: after two DFF
0: bypass
1: after two DFF
0: bypass
1: after two DFF
1233
1234
1235
1236
1237
Wake sleep power down state selection
Keep signal sync selection
UP signal sync selection
9A
CNT0 CNT mode SYNC selection
CNT0 output pol selection
0: Default Output
1: Inverted Output
0: normal
1238
1239
CNT0 DLY EDET FUNCTION Selection
Reserved
1: DLY function edge detection (registers [1224:1223] =
00)
Datasheet
10-Mar-2021
Revision 2.4
258 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1240
1241
1242
1243
mulit_function selection
dly2lut selection
Multi1 register configure
output selection of LUT3_7/DFF11:
0: LUT3_7
1: DFF11
0: normal
1: DLY function edge detection
1244
1245
9B
CNT1 DLY EDET FUNCTION Selection
(registers [1251:1248] = 0000/0001/0010)
0: bypass
1: after two DFF
0: Default Output
1: Inverted Output
1246
1247
CNT1 CNT mode SYNC selection
CNT1 output pol selection
1248
1249
1250
0000: both edge Delay
0001: falling edge delay
0010: rising edge delay
0011: both edge One Shot
0100: falling edge One Shot
0101: rising edge One Shot
0110: both edge freq detect
0111: falling edge freq detect
1000: rising edge freq detect
1001: both edge detect
1010: falling edge detect
1011: rising edge detect
1100: both edge reset CNT
1101: falling edge reset CNT
1110: rising edge reset CNT
1111: high level reset CNT
CNT1 function and edge mode selection
1251
1252
1253
1254
Clock source sel[3:0]
0000: 25M(OSC2)
0001: 25M/4
9C
0010: 2M(OSC1)
0011: 2M/8
0100: 2M/64
0101: 2M/512
0110: 2K(OSC0)
0111: 2K/8
DLY/CNT1 Clock Source Select
1000: 2K/64
1001: 2K/512
1255
1010: 2K/4096
1011: 2K/32768
1100: 2K/262144
1101: CNT0_END
1110: External
1111: Not used
Datasheet
10-Mar-2021
Revision 2.4
259 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1256
1257
1258
1259
mulit_function selection
dly2lut selection
Multi2 register configure
output selection of LUT3_8/DFF12:
0: LUT3_8
1: DFF12
1260
1261
9D
0: normal
CNT2 DLY EDET FUNCTION Selection
1: DLY function edge detection (registers [1267:1264] =
0000/0001/0010)
0: bypass
1: after two DFF
0: Default Output
1: Inverted Output
1262
1263
CNT2 CNT mode SYNC selection
CNT2 output pol selection
1264
1265
1266
0000: both edge Delay
0001: falling edge delay
0010: rising edge delay
0011: both edge One Shot
0100: falling edge One Shot
0101: rising edge One Shot
0110: both edge freq detect
0111: falling edge freq detect
1000: rising edge freq detect
1001: both edge detect
1010: falling edge detect
1011: rising edge detect
1100: both edge reset CNT
1101: falling edge reset CNT
1110: rising edge reset CNT
111: high level reset CNT
9E
CNT2 function and edge mode selection
1267
1268
1269
1270
Clock source sel[3:0]
0000: 25M(OSC2)
0001: 25M/4
0010: 2M(OSC1)
0011: 2M/8
0100: 2M/64
0101: 2M/512
0110: 2K(OSC0)
0111: 2K/8
9E
DLY/CNT2 Clock Source Select
1000: 2K/64
1001: 2K/512
1271
1010: 2K/4096
1011: 2K/32768
1100: 2K/262144
1101: CNT1_END
1110: External
1111: Not used
Datasheet
10-Mar-2021
Revision 2.4
260 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1272
1273
1274
1275
mulit_function selection
dly2lut selection
Multi3 register configure
output selection of LUT3_9/DFF13:
0: LUT3_9
1: DFF13
1276
1277
9F
0: normal
CNT3 DLY EDET FUNCTION Selection
1: DLY function edge detection(registers [1283:1280] =
0000/0001/0010)
0: bypass;
1: after two DFF
0: Default Output,
1: Inverted Output
1278
1279
CNT3 CNT mode SYNC selection
CNT3 output pol selection
1280
1281
1282
0000: both edge Delay
0001: falling edge delay
0010: rising edge delay
0011: both edge One Shot
0100: falling edge One Shot
0101: rising edge One Shot
0110: both edge freq detect
0111: falling edge freq detect
1000: rising edge freq detect
1001: both edge detect
1010: falling edge detect
1011: rising edge detect
1100: both edge reset CNT
1101: falling edge reset CNT
1110: rising edge reset CNT
1111: high level reset CNT
CNT3 function and edge mode selection
1283
1284
1285
1286
Clock source sel[3:0]
0000: 25M(OSC2)
0001: 25M/4
A0
0010: 2M(OSC1)
0011: 2M/8
0100: 2M/64
0101: 2M/512
0110: 2K(OSC0)
0111: 2K/8
DLY/CNT3 Clock Source Select
1000: 2K/64
1001: 2K/512
1287
1010: 2K/4096
1011: 2K/32768
1100: 2K/262144
1101: CNT2_END
1110: External
1111: Not used
Datasheet
10-Mar-2021
Revision 2.4
261 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1288
1289
1290
1291
mulit_function selection
dly2lut selection
Multi4 register configure
output selection of LUT3_10/DFF14:
0: LUT3_10
1: DFF14
1292
1293
A1
0: normal
CNT4 DLY EDET FUNCTION Selection
1: DLY function edge detection (registers [1299:1296] =
0000/0001/0010)
0: bypass
1: after two DFF
0: Default Output
1: Inverted Output
1294
1295
CNT4 CNT mode SYNC selection
CNT4 output pol selection
1296
1297
1298
0000: both edge Delay
0001: falling edge delay
0010: rising edge delay
0011: both edge One Shot
0100: falling edge One Shot
0101: rising edge One Shot
0110: both edge freq detect;
0111: falling edge freq detect
1000: rising edge freq detect
1001: both edge detect
1010: falling edge detect
1011: rising edge detect
1100: both edge reset CNT
1101: falling edge reset CNT
1110: rising edge reset CNT
1111: high level reset CNT
CNT4 function and edge mode selection
1299
1300
1301
1302
Clock source sel[3:0]
0000: 25M(OSC2)
0001: 25M/4
A2
0010: 2M(OSC1)
0011: 2M/8
0100: 2M/64
0101: 2M/512
0110: 2K(OSC0)
0111: 2K/8
DLY/CNT4 Clock Source Select
1000: 2K/64
1001: 2K/512
1303
1010: 2K/4096
1011: 2K/32768
1100: 2K/262144
1101: CNT3_END
1110: External
1111: Not used
Datasheet
10-Mar-2021
Revision 2.4
262 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1304
1305
1306
1307
mulit_function selection
dly2lut selection
Multi5 register configure
output selection of LUT3_11/DFF15:
0: LUT3_11
1: DFF15
1308
1309
A3
0: normal
CNT5 DLY EDET FUNCTION Selection
1: DLY function edge detection (registers [1315:1312] =
0000/0001/0010)
0: bypass
1: after two DFF
0: Default Output
1: Inverted Output
1310
1311
CNT5 CNT mode SYNC selection
CNT5 output pol selection
1312
1313
1314
0000: both edge Delay
0001: falling edge delay
0010: rising edge delay
0011: both edge One Shot
0100: falling edge One Shot
0101: rising edge One Shot
0110: both edge freq detect
0111: falling edge freq detect
1000: rising edge freq detect
1001: both edge detect
1010: falling edge detect
1011: rising edge detect
1100: both edge reset CNT
1101: falling edge reset CNT
1110: rising edge reset CNT
1111: high level reset CNT
CNT5 function and edge mode selection
1315
1316
1317
1318
Clock source sel[3:0]
0000: 25M(OSC2)
0001: 25M/4
A4
0010: 2M(OSC1)
0011: 2M/8
0100: 2M/64
0101: 2M/512
0110: 2K(OSC0)
0111: 2K/8
DLY/CNT5 Clock Source Select
1000: 2K/64
1001: 2K/512
1319
1010: 2K/4096
1011: 2K/32768
1100: 2K/262144
1101: CNT4_END
1110: External
1111: Not used
Datasheet
10-Mar-2021
Revision 2.4
263 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1320
1321
1322
1323
mulit_function selection
dly2lut selection
Multi6 register configure
output selection of LUT3_12/DFF16:
0: LUT3_12
1: DFF16
1324
1325
A5
0: normal
CNT6 DLY EDET FUNCTION Selection
1: DLY function edge detection (registers [1331:1328] =
0000/0001/0010)
0: bypass
1: after two DFF
0: Default Output
1: Inverted Output
1326
1327
CNT6 CNT mode SYNC selection
CNT6 output pol selection
1328
1329
1330
0000: both edge Delay
0001: falling edge delay
0010: rising edge delay
0011: both edge One Shot
0100: falling edge One Shot
0101: rising edge One Shot
0110: both edge freq detect
0111: falling edge freq detect
1000: rising edge freq detect
1001: both edge detect
1010: falling edge detect
1011: rising edge detect
1100: both edge reset CNT
1101: falling edge reset CNT
1110: rising edge reset CNT
1111: high level reset CNT
CNT6 function and edge mode selection
1331
A6
1332
1333
1334
Clock source sel[3:0]
0000: 25M(OSC2)
0001: 25M/4
0010: 2M(OSC1)
0011: 2M/8
0100: 2M/64
0101: 2M/512
0110: 2K(OSC0)
0111: 2K/8
DLY/CNT6 Clock Source Select
1000: 2K/64
1001: 2K/512
1335
1010: 2K/4096
1011: 2K/32768
1100: 2K/262144
1101: CNT5_END
1110: External
1111: Not used
Datasheet
10-Mar-2021
Revision 2.4
264 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1336
00: bypass the initial
01: initial 0
CNT0 initial value selection
10: initial 1
1337
1338
11: initial 1
00:bypass the initial
01: initial 0
10: initial 1
11: initial 1
00: bypass the initial
01: initial 0
10: initial 1
CNT1 initial value selection
CNT6 initial value selection
1339
1340
1341
A7
11: initial 1
1342
1343
1344
Reserved
Reserved
00: bypass the initial
01: initial 0
CNT2 initial value selection
CNT3 initial value selection
10: initial 1
1345
1346
11: initial 1
00: bypass the initial
01: initial 0
10: initial 1
11: initial 1
00: bypass the initial
01: initial 0
10: initial 1
11: initial 1
00:bypass the initial
01: initial 0
1347
1348
1349
1350
1351
A8
CNT4 initial value selection
CNT5 initial value selection
10: initial 1
11: initial 1
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
A9
<12:0>:LUT4_1 <12:0>
Multi0_LUT4_DFF setting
AA
<13>:LUT4_1 <13>/DFF17
Initial Polarity Select 0: Low, 1: High
<14>:LUT4_1 <14>/DFF17 Output Select 0: Q output, 1:
QB output
<15>:LUT4_1 <15>/DFF17 or Latch Select 0: DFF func-
1365
1366
1367
tion, 1: Latch function
Datasheet
10-Mar-2021
Revision 2.4
265 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
AB
REG_CNT0_D<15:0>
Data[15:0]
AC
<3:0>:LUT3_7 <3:0>
<4>:LUT3_7 <4>/DFF11 Initial Polarity Select
0: Low, 1: High
<5>:LUT3_7 <5>/DFF11
0: RSTB from Matrix Output, 1: SETB from Matrix Output
<6>:LUT3_7 <6>/DFF11 Output Select
0: Q output, 1: QB output
<7>:LUT3_7 <7>/DFF11 or Latch Select
0: DFF function, 1: Latch function
1388
1389
1390
1391
AD
Multi1_LUT3_DFF setting
Multi1_CNT1
1392
1393
1394
1395
1396
AE
REG_CNT1_D<7:0>
Data[7:0]
1397
1398
1399
1400
1401
1402
1403
<3:0>:LUT3_8 <3:0>
<4>:LUT3_8 <4>/DFF12 Initial Polarity Select
0: Low, 1: High
<5>:LUT3_8 <5>/DFF12
0: RSTB from Matrix Output, 1: SETB from Matrix Output
<6>:LUT3_8 <6>/DFF12 Output Select
0: Q output, 1: QB output
1404
AF
Multi2_LUT3_DFF setting
1405
1406
1407
<7>:LUT3_8 <7>/DFF12 or Latch Select
0: DFF function, 1: Latch function
Datasheet
10-Mar-2021
Revision 2.4
266 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
B0
REG_CNT2_D<7:0>
Data[7:0]
<3:0>:LUT3_9 <3:0>
<4>:LUT3_9 <4>/DFF13 Initial Polarity Select
0: Low, 1: High
<5>:LUT3_9 <5>/DFF13
0: RSTB from Matrix Output, 1: SETB from Matrix Output
<6>:LUT3_9 <6>/DFF13 Output Select
0: Q output, 1: QB output
1420
1421
1422
1423
B1
B2
B3
B4
Multi3_LUT3_DFF setting
<7>:LUT3_9 <7>/DFF13 or Latch Select
0: DFF function, 1: Latch function
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
REG_CNT3_D<7:0>
Data[7:0]
<3:0>:LUT3_10 <3:0>
<4>:LUT3_10 <4>/DFF14 Initial Polarity Select
0: Low, 1: High
<5>:LUT3_10 <5>/DFF14
0: RSTB from Matrix Output, 1: SETB from Matrix Output
<6>:LUT3_10 <6>/DFF14 Output Select
0: Q output, 1: QB output
1436
1437
1438
1439
Multi4_LUT3_DFF setting
<7>:LUT3_10 <7>/DFF14 or Latch Select
0: DFF function, 1: Latch function
1440
1441
1442
1443
1444
1445
1446
1447
REG_CNT4_D<7:0>
Data[7:0]
Datasheet
10-Mar-2021
Revision 2.4
267 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1448
1449
1450
1451
<3:0>:LUT3_11<3:0>
<4>:LUT3_11<4>/DFF15 Initial Polarity Select
0: Low, 1: High
<5>:LUT3_11 <5>/DFF15
0: RSTB from Matrix Output, 1: SETB from Matrix Output
<6>:LUT3_11 <6>/DFF15 Output Select
0: Q output, 1: QB output
1452
1453
1454
1455
B5
Multi5_LUT3_DFF setting
<7>:LUT3_11 <7>/DFF15 or Latch Select
0: DFF function, 1: Latch function
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
B6
B7
B8
REG_CNT5_D<7:0>
Multi6_LUT3_DFF setting
REG_CNT6_D<7:0>
Data[7:0]
<3:0>:LUT3_12 <3:0>
<4>:LUT3_12 <4>/DFF16 Initial Polarity Select
0: Low, 1: High
<5>:LUT3_12 <5>/DFF16
0: RSTB from Matrix Output, 1: SETB from Matrix Output
<6>:LUT3_12 <6>/DFF16 Output Select
0: Q output, 1: QB output
1468
1469
1470
1471
<7>:LUT3_12 <7>/DFF16 or Latch Select
0: DFF function, 1: Latch function
1472
1473
1474
1475
1476
1477
1478
1479
Data[7:0]
Datasheet
10-Mar-2021
Revision 2.4
268 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1480
<0>:LUT2_0 <0>
<1>:LUT2_0 <1>/DFF0 Initial Polarity Select
0: Low, 1: High
<2>:LUT2_0 <2>/DFF0 Output Select
0: Q output, 1: QB output
1481
1482
LUT2_0/DFF0 setting
<3>:LUT2_0 <3>/DFF0 or Latch Select
0: DFF function, 1: Latch function
<0>:LUT2_0 <0>
<1>:LUT2_0 <1>/DFF0 Initial Polarity Select
0: Low, 1: High
1483
1484
1485
B9
LUT2_1/DFF1 setting
LUT2_2/DFF2 setting
<2>:LUT2_0 <2>/DFF0 Output Select
0: Q output, 1: QB output
<3>:LUT2_0 <3>/DFF0 or Latch Select
0: DFF function, 1: Latch function
<0>:LUT2_0 <0>
<1>:LUT2_0 <1>/DFF0 Initial Polarity Select
0: Low, 1: High
<2>:LUT2_0 <2>/DFF0 Output Select
0: Q output, 1: QB output
<3>:LUT2_0 <3>/DFF0 or Latch Select
0: DFF function, 1: Latch function
0: LUT2_0
1: DFF0
0: LUT2_1
1: DFF1
1486
1487
1488
1489
1490
1491
1492
1493
1494
BA
LUT2_0 or DFF0 Select
LUT2_1 or DFF1 Select
0: LUT2_2
1: DFF2
LUT2_2 or DFF2 Select
Reserved
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
BB
PGen data
PGen Data[15:0]
BC
Datasheet
10-Mar-2021
Revision 2.4
269 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1512
1513
1514
1515
LUT2_3<3:0> or PGen 4bit counter
data<3:0>
LUT2_3_VAL or PGen_data
0: LUT2_3
1: PGen
0: Active low level reset/set
1: Active high level reset/set
0: LUT3_0
1: DFF3
0: LUT3_1
1: DFF4
1516
1517
1518
1519
LUT2_3 or PGen Select
BD
Active level selection for RST/SET
LUT3_0 or DFF3 Select
LUT3_1 or DFF4 Select
1520
1521
<1:0>: LUT3_0 <1:0>
<2>:LUT3_0 <2>/DFF3 stage selection
0: Q of first DFF; 1 Q of second DFF
1522
<3>:LUT3_0 <3>/DFF3 Active level selection for
RST/SET
1523
0: Active low level reset/set, 1: Active high level
reset/set
BE
LUT3_0_DFF3 setting
<4>:LUT3_0 <4>/DFF3
0: RSTB from Matrix Output, 1: SETB from Matrix
Output
1524
<5>:LUT3_0 <5>/DFF3 Initial Polarity Select
0: Low, 1: High
<6>:LUT3_0 <6>/DFF3 Output Select
0: Q output, 1: QB output
<7>:LUT3_0 <7>/DFF3 or Latch Select
0: DFF function, 1: Latch function
1525
1526
1527
1528
1529
1530
<2:0>: LUT3_1 <2:0>
<3>:LUT3_1 <3>/DFF4 Active level selection for
RST/SET
1531
1532
0: Active low level reset/set, 1: Active high level
reset/set
<4>:LUT3_1 <4>/DFF4
0: RSTB from Matrix Output, 1: SETB from Matrix
Output
BF
LUT3_1_DFF4 setting
<5>:LUT3_1 <5>/DFF4 Initial Polarity Select
0: Low, 1: High
<6>:LUT3_1 <6>/DFF4 Output Select
0: Q output, 1: QB output
<7>:LUT3_1 <7>/DFF4 or Latch Select
0: DFF function, 1: Latch function
1533
1534
1535
Datasheet
10-Mar-2021
Revision 2.4
270 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
C0
0000000000: 0
~
1111111111:100k
Rheostat0 data selection
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
C1
C2
C3
C4
C5
Rheostat0 current value (read only)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Matrix Input 0
Matrix Input 1
Matrix Input 2
Matrix Input 3
Matrix Input 4
Matrix Input 5
Matrix Input 6
Matrix Input 7
Matrix Input 8
Matrix Input 9
Matrix Input 10
Matrix Input 11
Matrix Input 12
Matrix Input 13
Matrix Input 14
Matrix Input 15
Datasheet
10-Mar-2021
Revision 2.4
271 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
Matrix Input 16
Matrix Input 17
Matrix Input 18
Matrix Input 19
Matrix Input 20
Matrix Input 21
Matrix Input 22
Matrix Input 23
Matrix Input 24
Matrix Input 25
Matrix Input 26
Matrix Input 27
Matrix Input 28
Matrix Input 29
Matrix Input 30
Matrix Input 31
Matrix Input 40
Matrix Input 41
Matrix Input 42
Matrix Input 43
Matrix Input 44
Matrix Input 45
Matrix Input 46
Matrix Input 47
Matrix Input 48
Matrix Input 49
Matrix Input 50
Matrix Input 51
Matrix Input 52
Matrix Input 53
Matrix Input 54
Matrix Input 55
Matrix Input 56
Matrix Input 57
Matrix Input 58
Matrix Input 59
Matrix Input 60
Matrix Input 61
Matrix Input 62
Matrix Input 63
C6
C7
C8
C9
CA
Datasheet
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Revision 2.4
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
CB
CNT0_Q
CC
CD
CE
CF
CNT5_Q
CNT6_Q
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Datasheet
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
D0
0000000000: 0
~
1111111111:100k
Rheostat1 data selection
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D1
D2
D3
D4
D5
Rheostat1 current value (read only)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Datasheet
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D6
D7
D8
D9
DA
DB
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1760
1761
1762
1763
1764
1765
1766
1767
1768
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ID[24]: Reserved
DC
ReservedforNVMPower-UpCheckPatternStatus (A55A
match from Flag)
1769
ID[25]: Reserved
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
ID[27:26]: Reserved for Silicon Identification
Service Bits (metal hard code)
DD
Reserved
Reserved
DE
DF
Reserved
00: 2k register data is unprotected for read
01: 2k register data is partly protected for read
10: 2k register data is fully protected for read
11: reserved
00: 2k register data is unprotected for write
01: 2k register data is partly protected for write
10: 2k register data is fully protected for write
11: reserved
RPR<1:0>
(2k register read selection bits)
1793
1794
1795
RPR<3:2>
(2k register write selection bits)
E0
0: Rheostat Program Input from matrix enabled
1: Rheostat Program Input from matrix disabled
1796
RH_PRB
1797
1798
1799
Reserved
Reserved
Reserved
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1800
00:2kNVM Configurationdatais unprotectedforreadand
write/erase
01: 2k NVM Configuration data is fully protected for read
10: 2k NVM Configuration data is fully protected for
write/erase
NPR<1:0>
(2k NVM configuration selection bits)
1801
1802
11: 2k NVM Configuration data is fully protected for read
and write/erase
00: Rheosta0 NVM Configuration data is unprotected for
read and write/erase
01: Rheosta0 NVM Configuration data is fully protected
for read
NPR<3:2>
(Rheostat0 NVM configuration selection bits)
10: Rheosta0 NVM Configuration data is fully protected
for write/erase
1803
1804
1805
E1
11: Rheosta0 NVM Configuration data is fully protected
for read and write/erase
00: Rheosta1 NVM Configuration data is unprotected for
read and write/erase
01: Rheosta1 NVM Configuration data is fully protected
for read
NPR<5:4>
(Rheostat1 NVM configuration selection bits)
10: Rheosta1 NVM Configuration data is fully protected
for write/erase
11: Rheosta1 NVM Configuration data is fully protected
for read and write/erase
1806
1807
1808
Reserved
Reserved
00: Upper 1/4 (page16~19) of EEPROM is write protected
(default)
01: Upper 2/4 (page16~23) of EEPROM is write protected
10: Upper 3/4 (page16~27) of EEPROM is write protected
11: Entire (page16~31) EEPROM is write protected
WPR<1:0>
(EEPROM Write protect block bits
range: page31~16)
1809
WPRE
0: No Software Write Protection enabled (default)
1: Write Protection is set by the state of the WPR<1:0> bits
1810
(EEPROM Write protect register enable)
E2
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
Reserved
Reserved
Reserved
Reserved
Reserved
Define the page address which will be erased
ERSE<4> = 0 corresponds to the upper 2k NVM used for
chip configuration
ERSE<4:0>
(Page selection for erase)
ERSE<4> = 1 corresponds to the 2k
EEPROM
E3
000/001/010/011/100/101/111: erase disable
110: cause the NVM erase: full NVM (4k bits) erase for
ERSCHIP = 1 if
DIS_ERSCHIP=0 or page erase for
ERSCHIP=0.
0: RPR/WPR/NPR setting can be changed
1: RPR/WPR/NPR setting cannot be changed
ERSE <2:0>
(Erase enable)
1823
1824
PRL
(Protection lock)
1825
1826
1827
1828
1829
1830
1831
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
E4
Datasheet
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Revision 2.4
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
E5
Reserved
Rheostat0 tolerance data <0>
Rheostat0 tolerance data <1>
Rheostat0 tolerance data <2>
Rheostat0 tolerance data <3>
Rheostat0 tolerance data <4>
Rheostat0 tolerance data <5>
Rheostat0 tolerance data <6>
Rheostat0 tolerance data <7>
Rheostat0 tolerance data <8>
Rheostat0 tolerance data <9>
Rheostat0 tolerance data <10>
Rheostat0 tolerance data <11>
Rheostat0 tolerance data <12>
Rheostat0 tolerance data <13>
Rheostat0 tolerance data <14>
E6
E7
E8
0: “+”
1: "-"
1855
Sign of Rheostat0 tolerance data
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
Rheostat1 tolerance data <0>
Rheostat1 tolerance data <1>
Rheostat1 tolerance data <2>
Rheostat1 tolerance data <3>
Rheostat1 tolerance data <4>
Rheostat1 tolerance data <5>
Rheostat1 tolerance data <6>
Rheostat1 tolerance data <7>
Rheostat1 tolerance data <8>
Rheostat1 tolerance data <9>
Rheostat1 tolerance data <10>
Rheostat1 tolerance data <11>
Rheostat1 tolerance data <12>
Rheostat1 tolerance data <13>
Rheostat1 tolerance data <14>
E9
EA
0: "+";
1: "-"
1871
Sign of Rheostat1 tolerance data
1872
1873
1874
1875
Reserved
Datasheet
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Revision 2.4
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1876
1877
1878
1879
1880
1881
1882
1883
1884
EA
Reserved
Reserved
Reserved
Reserved
EB
1885
1886
Reserved
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EC
ED
EE
EF
Datasheet
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
F0
Reserved
F1
Reserved
F2
Reserved
0: Service page can be changed
1: Service page is locked
0: chopper enable
1: chopper off
1944
1945
Service page lock bit
BG Chopper off
1946
1947
Reserved
Reserved
F3
0: power on
1: power off
1948
BG register power down
1949
1950
1951
1952
1953
Reserved
Reserved
Reserved
Reserved
Reserved
1954
Reserved
1955
1956
1957
1958
1959
Reserved
Reserved
Reserved
Reserved
Reserved
F4
Datasheet
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
F5
0: overwrite;
1: mask the bit which set to high
F6
F7
F8
F9
I2C write mask bits
Reserved
Reserved
Reserved
Reserved
Datasheet
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Revision 2.4
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
2000
2001
2002
2003
2004
Reserved
FA
2005
2006
2007
Reserved
Reserved
Reserved
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
Reserved
FB
FC
FD
FE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Datasheet
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Revision 2.4
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Register
Bit
Byte
2040
2041
2042
2043
2044
2045
2046
2047
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FF
Datasheet
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
22 Package Top Marking System Definition
22.1 STQFN-24L 3 MM X 3 MM X 0.55 MM, 0.4P FCD PACKAGE
Part Code
PPPPP
Date Code
WWNNN S/N Code
Assembly House Code +
Revision Code
Pin 1
Identifier
ARR
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
23 Package Information
23.1 PACKAGE OUTLINES FOR STQFN 24L 3 MM X 3 MM X 0.55 MM 0.4P GREEN PACKAGE
JEDEC MO-220
Bottom View
Top View
Side View
23.2 STQFN HANDLING
Be sure to handle STQFN package only in a clean, ESD-safe environment. Tweezers or vacuum pick-up tools are suitable for
handling. Do not handle STQFN package with fingers as this can contaminate the package pins and interface with solder reflow.
23.3 SOLDERING INFORMATION
Please see IPC/JEDEC J-STD-020: for relevant soldering information. More information can be found at www.jedec.org.
Datasheet
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
24 Ordering Information
Part Number
Type
SLG47004V
24-pin STQFN
24-pin STQFN - Tape and Reel (5k units)
SLG47004VTR
24.1 TAPE AND REEL SPECIFICATIONS
Max Units
per Reel per Box
Leader (min)
Length
Trailer (min)
Nominal
Package Size
(mm)
Reel &
Hub Size
(mm)
Tape
Width Pitch
(mm) (mm)
Part
Package # of
Length
Type
Pins
Pockets
Pockets
(mm)
(mm)
STQFN 24L
3 mm x3mm
0.4P FC
24
3 x 3 x 0.55
5.000
10.000 330 / 100
42
336
42
336
12
8
Green
24.2 CARRIER TAPE DRAWING AND DIMENSIONS
Index Hole Index Hole
PocketBTMPocketBTM Pocket Index Hole Pocket Index Hole
to Tape
Edge
to Pocket Tape Width
Center
(mm)
Length
(mm)
Width
(mm)
Depth
(mm)
Pitch
(mm)
Pitch
(mm)
Diameter
(mm)
Package
Type
(mm)
(mm)
A0
B0
K0
P0
P1
D0
E
F
W
STQFN 24L
3 mm x3mm
0.4P FC
3.3
3.3
0.8
4
8
1.55
1.75
5.5
12
Green
Notes:
1. 10 SPROCKET HOLE PITCH CUMULATIVE TOLERANCE ±0.2
2. POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED AS TRUE POSITION OF POCKET, NOT POCKET HOLE
3. A0 AND B0 ARE CALCULATED ON A PLANE AT A DISTANCE “R” ABOVE THE BOTTOM OF THE POCKET.
Note: Orientation in carrier: Pin1 is at upper left corner (Quadrant1).
Datasheet
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
25 Layout Guidelines
SLG47004 has two analog supply pins and two ground pins: VDD, VDDA, GND and AGND. Separating analog supply voltage
from digital one helps to minimize noise generated by the digital part of IC.
Analog supply voltage domain: operational amplifiers, charge pumps for op amps, charge pumps for Oscillators, bias generators
and regulators for op amps, digital rheostats, Chopper ACMP, HD Buffer, Vref of op amp and HD Buffer, Low Power Bandgap.
Digital supply voltage domain: ACMPs, Vref of ACMPs, Vref output buffers, Oscillator 0, Oscillator 1, Oscillator 2, I2C macrocell,
NVM logic, Multi-function and Combination Function macrocells.
Analog and digital grounds must be connected together on the PCB board. The place of connection depends on users
schematic. For application cases with low digital current of SLG47004, both AGND and GND should be connected to analog
ground plane.
25.1 STQFN 24L 3 MM X 3 MM X 0.55 MM 0.4P GREEN PACKAGE
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Glossary
A
ACK
Acknowledge bit
ACMP
ACMPH
ACMPL
AS
Analog Comparator
Analog Comparator High Speed
Analog Comparator Low Power
Analog Switch
B
BG
Bandgap
C
CLK
CMO
CNT
Clock
Connection matrix output
Counter
D
DFF
DLY
DNL
DR
D Flip-Flop
Delay
Differential Non-Linearity
Digital Rheostat
E
EC
Electrical Characteristics
Erase Enable
ERSE
ERSR
ESD
EV
Erase Register
Electrostatic discharge
End Value
F
FSM
Finite State Machine
G
GPI
GPIO
GPO
General Purpose Input
General Purpose Input/Output
General Purpose Output
I
IN
Input
In Amp
DNL
Instrumentation Amplifier
Differential Non-Linearity
Datasheet
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SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
INL
IO
Integral Non-Linearity
Input/Output
L
LPF
LSB
LUT
LV
Low Pass Filter
Least Significant Bit
Look Up Table
Low Voltage
M
MSB
MTP
MUX
Most Significant Bit
Multiple-Time-Programmable
Multiplexer
N
NPR
nRST
NVM
Non-Volatile Memory Read/Write/Erase Protection
Reset
Non-Volatile Memory
O
OA
Operational Amplifier
Open-Drain
OD
OE
Output Enable
Operational Amplifier
Oscillator
Op Amp
OSC
OUT
Output
P
PD
Power-down
PGen
POR
PP
Pattern Generator
Power-On Reset
Push-Pull
PRL
PT
Protect Lock Bit
Programmable Trim
Power
PWR
P DLY
Programmable Delay
R
RPR
RPRB
RPRL
Register Read/Write Protection
Register Read/Write Protection Bit
Register Protection Read/Write/Erase Lock
Datasheet
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
R/W
Read/Write
S
SCL
SDA
SLA
SMT
SPST
SV
I2C Clock Input
I2C Data Input/Output
Slave Address
With Schmitt Trigger
Single-pole/Single throw
nSET Value
T
TS
Temperature Sensor
Voltage Reference
V
Vref
W
WOSMT
WPB
WPR
WPRE
WS
Without Schmitt Trigger
Write Protect Bit
Write Protection Register
Write Protect Enable
Wake and Sleep Controller
Datasheet
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Revision History
Revision
Date
Description
Updated Carrier Tape Drawing and Dimensions
Added Vref Performance: Typical Input Offset Voltage vs. Vref
2.4
10-Mar-2021
Updated Tape and Reel Specification
Added Op Amps, Analog Switches, Rheostats, OSCs, ACMPs, TS, Vref Typical Performance
Updated Thermal Resistance parameter in Absolute Maximum Ratings Table
Updated Op Amp Typical Performance
2.3
2-Mar-2021
Updated 100K Digital Rheostat EC
Updated table Read/Write Register Protection Options
Updated Analog Switch Spec Conditions
Fixed typos
2.2
3-Dec-2020
2.1
2.0
13-Nov-2020 Removed TSSOP Package
9-Nov-2020 Preliminary version
Datasheet
10-Mar-2021
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CFR0011-120-00
SLG47004
Preliminary
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
Status Definitions
Revision Datasheet Status
Product Status
Definition
1.<n>
Target
Development
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
2.<n>
Preliminary
Qualification
Production
This datasheet contains the specifications and preliminary characterization
data for products in pre-production. Specifications may be changed at any
time without notice in order to improve the design.
3.<n>
4.<n>
Final
This datasheet contains the final specifications for products in volume
production. The specifications may be changed at any time in order to
improve the design, manufacturing and supply. Major specification
changes are communicated via Customer Product Notifications. Datasheet
changes are communicated via www.dialog-semiconductor.com.
Obsolete
Archived
This datasheet contains the specifications for discontinued products. The
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Datasheet
10-Mar-2021
Revision 2.4
292 of 292
© 2021 Dialog Semiconductor
CFR0011-120-00
相关型号：
SLG47004VTR
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
DIALOG
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