SLG47105V [DIALOG]
GreenPAK Programmable Mixed-Signal Matrix with High Voltage Features;
| 型号： | SLG47105V |
| 厂家： | 
Dialog Semiconductor |
| 描述： | GreenPAK Programmable Mixed-Signal Matrix with High Voltage Features |
| 文件： | 总253页 (文件大小：3559K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
General Description
The SLG47105 provides a small, low power component for commonly used Mixed-Signal and Bridge functions. The user
creates their circuit design by programming the one time programmable (OTP) Non-Volatile Memory (NVM) to configure the
interconnect logic, the IO Pins, the High Voltage Pins, and the macrocells of the SLG47105.
Configurable PWM macrocells in combination with Special High Voltage outputs will be useful for a motor drive or load drive
applications. High Voltage pins allow to design smart level translators or to drive the high voltage high current load.
Key Features
Two Power Supply Inputs:
Four Selectable DFF/LATCH/3-bit LUTs + 8-bit Delay/
Counters
One Selectable DFF/LATCH/4-bit LUT + 16-bit Delay/
Counter
2.5 V (±8 %) to 5.0 V (±10 %) VDD
3.3 V (±9 %) to 12.0 V (±10 %) VDD2
Four High Voltage High Current Drive GPOs
Dual/Single Full Bridge Motor Driver Option
Twelve Combination Function Macrocells
Quad/Dual/Single Half Bridge Driver Option
Three Selectable DFF/LATCH or 2-bit LUTs
One Selectable Programmable Pattern Generator or
2-bit LUT
Six Selectable DFF/LATCH or 3-bit LUTs
One Selectable Pipe Delay or Ripple Counter or 3-bit
LUT
SLEEP Function
Low RDS ON High Side + Low Side resistance = 0.4 Ω
2 A Peak, 1.5 A RMS per Full Bridge (at VDD2 = 5 V,
T = 25 °C) (Note 1)
4 A Peak, 3 A RMS per two Full Bridge connected in
parallel (at VDD2 = 5 V, T = 25 °C) (Note 1)
2 A Peak, 1.5 A RMS per Half Bridge GPO
(at VDD2 = 5 V, T = 25 °C) (Note 1)
One Selectable DFF/LATСH or 4-bit LUT
Two PWM Macrocells
Flexible 8-bit/7-bit PWM Mode with the Duty Cycle
Control
16 Preset Duty Cycle Registers Switching Mode for
PWM Sine or Other Waveforms (Note 2)
Integrated Protections:
- Over Current Protection (OCP)
- Short Circuit Protection
- Under-Voltage Lockout (UVLO)
- Thermal Shutdown (TSD)
Serial Communications
I2C Protocol Interface
SENSE_A, SENSE_B Inputs that are connected to the
Programmable Delay with Edge Detector Output
Additional Logic Function – One Deglitch Filter with Edge
Detectors
Two Oscillators (OSC)
Current Comparators for Current Control
Fault Signal Indicator individual per Full Bridge:
- OCP
- UVLO
- TSD
2.048 kHz Oscillator
25 MHz Oscillator
Differential Amplifier with Integrator and Comparator for
Motor Speed Control Function
Analog Temperature Sensor with ACMP Connected Out-
put
POR
One Time Programmable Memory
Operating Temperature Range: -40 °C to 85 °C
RoHS Compliant/Halogen-Free
20-pin STQFN: 2 mm x 3 mm x 0.55 mm, 0.4 mm pitch
Two Current Sense Comparators with Dynamical Vref
Mode
Two High-Speed General Purpose ACMPs
Modes: UVLO, OCP, TSD, Voltage Monitor, Current
Monitor
One Voltage Reference (Vref) Output
Five Multi-Function Macrocells
Applications
Smart Locks
Toys
Personal Computers and Servers
Consumer Electronics
Motor Drivers
HV MOSFET Drivers
Video Security Cameras
LED Matrix Dimmers
Note 1 Power dissipation and thermal limits must be observed. See Section 3.3
Note 2 For all PWM features see Section 13.
Datasheet
31-Aug-2021
Revision 3.4
1 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Contents
General Description.................................................................................................................................................................1
Key Features.............................................................................................................................................................................1
Applications..............................................................................................................................................................................1
1 Block Diagram ....................................................................................................................................................................10
2 Pinout ..................................................................................................................................................................................11
2.1 Pin Configuration - STQFN- 20L ..........................................................................................................................11
3 Characteristics ...................................................................................................................................................................13
3.1 Absolute Maximum Ratings .................................................................................................................................13
3.2 Electrostatic Discharge Ratings ...........................................................................................................................13
3.3 Recommended Operating Conditions ..................................................................................................................14
3.4 Thermal Information .............................................................................................................................................14
3.5 Electrical Characteristics ......................................................................................................................................14
3.6 I2C Pins Electrical Characteristics ........................................................................................................................19
3.7 Macrocells Current Consumption .........................................................................................................................22
3.8 HV Output Electrical Characteristic ......................................................................................................................23
3.9 Protection Circuits Electrical Characteristic .........................................................................................................27
3.10 Timing Characteristics ........................................................................................................................................28
3.11 Counter/Delay Characteristics ...........................................................................................................................30
3.12 Oscillator Characteristics ...................................................................................................................................30
3.13 Current Sense Comparator Characteristics .......................................................................................................31
3.14 Differential Amplifier with Integrator and Comparator Characteristics ..............................................................33
3.15 ACMP Characteristics ........................................................................................................................................34
3.16 Analog Temperature Sensor Characteristics .....................................................................................................36
4 User Programmability ........................................................................................................................................................38
5 System Overview ...............................................................................................................................................................39
5.1 GPIO Pins ............................................................................................................................................................39
5.2 High Voltage Output Pins .....................................................................................................................................39
5.3 Connection Matrix ................................................................................................................................................39
5.4 Two Current Sense Comparators ........................................................................................................................39
5.5 Differential Amplifier with Integrator and Comparator ..........................................................................................39
5.6 Two general purpose analog comparators ...........................................................................................................39
5.7 Voltage reference .................................................................................................................................................39
5.8 Twelve Combination Function Macrocells ............................................................................................................39
5.9 Five Multi-Function Macrocells .............................................................................................................................39
5.10 Two PWM Macrocells ........................................................................................................................................39
5.11 Serial Communication ........................................................................................................................................40
5.12 Programmable Delay .........................................................................................................................................40
5.13 Additional Logic Function ...................................................................................................................................40
5.14 Two Oscillators ...................................................................................................................................................40
5.15 Dual VDD .....................................................................................................................................................................................................40
6 Input/Output Pins ...............................................................................................................................................................41
6.1 GPIO Pins ............................................................................................................................................................41
6.2 GPI Pin .................................................................................................................................................................41
6.3 HV GPO Pins .......................................................................................................................................................41
6.4 Pull-Up/Down Resistors .......................................................................................................................................41
6.5 Fast Pull-Up/Down during Power-Up ...................................................................................................................41
6.6 ESD Protection .....................................................................................................................................................41
6.7 GPI IO Structure (for VDD Group) .........................................................................................................................42
6.8 I2C Mode IO Structure (for VDD Group) ................................................................................................................43
6.9 Matrix OE IO Structure (for VDD Group) ...............................................................................................................45
6.10 GPO Matrix OE Structure (For VDD2 Group) ......................................................................................................46
6.11 IO Typical Performance .....................................................................................................................................48
7 High Voltage Output Modes ..............................................................................................................................................51
7.1 Full Bridge Mode ..................................................................................................................................................53
Datasheet
31-Aug-2021
Revision 3.4
2 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
7.2 Half Bridge mode .................................................................................................................................................56
7.3 Pre-Driver Mode ...................................................................................................................................................57
7.4 Parallel Connection of HV GPO ...........................................................................................................................57
7.5 Protection Circuits ................................................................................................................................................58
7.6 PWM Voltage Control ...........................................................................................................................................59
7.7 High Voltage Outputs Typical Performance .........................................................................................................60
8 Differential Amplifier with Integrator and Comparator ...................................................................................................70
8.1 Differential Amplifier with Integrator Block Diagram .............................................................................................71
8.2 Differential Amplifier Load Regulation ..................................................................................................................71
9 Current Sense Comparator ...............................................................................................................................................73
9.1 Current Sense Comparator0 Block Diagram ........................................................................................................73
9.2 Current Sense Comparator1 Block Diagram ........................................................................................................74
9.3 Current Regulation ...............................................................................................................................................74
9.4 Current Sense Comparator Typical Performance ................................................................................................75
10 Connection Matrix ............................................................................................................................................................77
10.1 Matrix Input Table .............................................................................................................................................78
10.2 Matrix Output Table ............................................................................................................................................80
10.3 Connection Matrix Virtual Inputs ........................................................................................................................82
10.4 Connection Matrix Virtual Outputs .....................................................................................................................83
11 Combination Function Macrocells ..................................................................................................................................84
11.1 2-bit LUT or D Flip-Flop Macrocells ...................................................................................................................84
11.2 2-bit LUT or Programmable Pattern Generator ..................................................................................................87
11.3 3-bit LUT or D Flip-Flop with Set/Reset Macrocells ...........................................................................................89
11.4 3-bit LUT or D Flip-Flop with Set/Reset Macrocell or PWM Chopper ................................................................96
11.5 3-bit LUT or Pipe Delay/Ripple Counter Macrocell ..........................................................................................103
11.6 4-bit LUT or D Flip-Flop Macrocell ...................................................................................................................106
12 Multi-Function Macrocells .............................................................................................................................................109
12.1 3-bit LUT or DFF/LATCH with 8-bit Counter/Delay Macrocells ........................................................................110
12.2 4-bit LUT or DFF/LATCH with 16-bit Counter/Delay Macrocell ........................................................................116
12.3 CNT/DLY/FSM Timing Diagrams .....................................................................................................................119
12.4 Wake and Sleep Controller ..............................................................................................................................128
13 Pulse Width Modulator Macrocell (PWM) .....................................................................................................................133
13.1 8-bit/7-bit PWM Configurations ........................................................................................................................133
13.2 PWM Inputs ......................................................................................................................................................133
13.3 PWM Outputs ...................................................................................................................................................133
13.4 I2C/Matrix/Auto dynamically changeable Duty Cycle and Period .....................................................................134
13.5 I2C PWM Duty Cycle read/write .......................................................................................................................134
13.6 Flexible OSC-integrated Divider .......................................................................................................................134
13.7 Inverted Output option ......................................................................................................................................134
13.8 Changeable dead band option for OUT+ and OUT- ........................................................................................134
13.9 Initial PWM value .............................................................................................................................................136
13.10 Sync On/Off setting for Power-Down signal ...................................................................................................136
13.11 Regular/Preset Registers Mode .....................................................................................................................140
13.12 PWM Continuous/Autostop mode ..................................................................................................................141
13.13 Internal Oscillator Auto Disable Mode ............................................................................................................141
13.14 Phase Correct PWM Mode ............................................................................................................................144
13.15 PWM Period Output .......................................................................................................................................144
13.16 PWM Block Diagrams ....................................................................................................................................145
13.17 PWM Register Settings ..................................................................................................................................146
14 Analog Comparators .....................................................................................................................................................150
14.1 ACMP0H Block Diagram ..................................................................................................................................151
14.2 ACMP1H Block Diagram ..................................................................................................................................152
14.3 ACMP Typical Performance .............................................................................................................................153
15 Programmable Delay/Edge Detector ............................................................................................................................156
15.1 Programmable Delay Timing Diagram - Edge Detector OUTPUT ...................................................................156
16 Additional Logic Function. Deglitch Filter ...................................................................................................................157
17 Voltage Reference ..........................................................................................................................................................158
Datasheet
31-Aug-2021
Revision 3.4
3 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
17.1 Voltage Reference Overview ...........................................................................................................................158
17.2 Vref Selection Table .........................................................................................................................................158
17.3 Mode Selection ................................................................................................................................................159
17.4 Vref Block Diagram ..........................................................................................................................................160
17.5 Vref Load Regulation .......................................................................................................................................161
18 Clocking ..........................................................................................................................................................................163
18.1 OSC General description .................................................................................................................................163
18.2 Oscillator0 (2.048 kHz) .....................................................................................................................................164
18.3 Oscillator1 (25 MHz) ........................................................................................................................................164
18.4 CNT/DLY Clock Scheme ..................................................................................................................................165
18.5 PWM Clock Scheme ........................................................................................................................................165
18.6 External Clocking .............................................................................................................................................166
18.7 Oscillators Power-On Delay .............................................................................................................................167
18.8 Oscillators Accuracy .........................................................................................................................................168
18.9 Oscillators Settling Time ..................................................................................................................................170
18.10 Oscillators Current Consumption ...................................................................................................................171
19 Low Power Bandgap (LP_BG) .......................................................................................................................................175
20 Power-On Reset ..............................................................................................................................................................176
20.1 General Operation ............................................................................................................................................176
20.2 POR Sequence ................................................................................................................................................177
20.3 Macrocells Output States During POR Sequence ...........................................................................................178
21 I2C Serial Communications Macrocell ..........................................................................................................................180
21.1 I2C Serial Communications Macrocell Overview ..............................................................................................180
21.2 I2C Serial Communications Device Addressing ...............................................................................................180
21.3 I2C Serial General Timing ................................................................................................................................181
21.4 I2C Serial Communications Commands ...........................................................................................................181
21.5 I2C Serial Command Register Map ..................................................................................................................184
22 Analog Temperature Sensor .........................................................................................................................................188
23 Register Definitions .......................................................................................................................................................190
23.1 Register Map ....................................................................................................................................................190
24 Package Top Marking Definitions .................................................................................................................................241
24.1 STQFN 20L 2 mm x 3 mm 0.4P FCD Green ...................................................................................................241
25 Package Information ......................................................................................................................................................242
25.1 Package Outlines for STQFN 20L 2 mm x 3 mm 0.4P FCD Green Package ..................................................242
25.2 Moisture Sensitivity Level .................................................................................................................................243
25.3 Soldering Information .......................................................................................................................................243
26 Ordering Information .....................................................................................................................................................243
26.1 Tape and Reel Specifications ..........................................................................................................................243
26.2 Carrier Tape Drawing and Dimensions ............................................................................................................243
27 Thermal Guidelines ........................................................................................................................................................245
28 Layout consideration .....................................................................................................................................................246
29 Layout Guidelines ..........................................................................................................................................................248
29.1 STQFN 20L 2 mm x 3.0 mm x 0.55 mm 0.4P FCD Package ...........................................................................248
Glossary................................................................................................................................................................................249
Revision History...................................................................................................................................................................252
Datasheet
31-Aug-2021
Revision 3.4
4 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Figures
Figure 1: Block Diagram...........................................................................................................................................................10
Figure 2: Steps to Create a Custom GreenPAK Device...........................................................................................................38
Figure 3: GPI Structure Diagram..............................................................................................................................................42
Figure 4: GPIO with I2C Mode Structure Diagram ...................................................................................................................43
Figure 5: GPIO Matrix OE IO Structure Diagram .....................................................................................................................45
Figure 6: HV GPO Matrix OE IO Structure Diagram (for HV GPOs 0 and 1)...........................................................................46
Figure 7: HV GPO Matrix OE IO Structure Diagram (for HV GPOs 2 and 3)...........................................................................47
Figure 8: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C.......................................................48
Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range......................48
Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C .......................................49
Figure 11: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range....................49
Figure 12: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C .......................................50
Figure 13: HV OUT Block Diagram..........................................................................................................................................52
Figure 14: Full Bridge Mode Operation....................................................................................................................................53
Figure 15: Drive and Decay Modes..........................................................................................................................................55
Figure 16: Half Bridge Mode Operation....................................................................................................................................56
Figure 17: Parallel Connection of HV GPOs for Full Bridge Mode...........................................................................................57
Figure 18: Overcurrent Protection Operation...........................................................................................................................59
Figure 19: Full Bridge Typical Drain-Source High Side On-Resistance vs. Load Current at VDD = 5.5 V, VDD2 = 5 V............60
Figure 20: Full Bridge Typical Drain-Source Low Side On-Resistance vs. Load Current at VDD = 5.5 V, VDD2 = 5 V ............60
Figure 21: Full Bridge Typical Drain-Source High Side On-Resistance vs. Temperature at ILOAD = 0.5 A, VDD = 2.3 V ........61
Figure 22: Full Bridge Typical Drain-Source High Side On-Resistance vs. Temperature at ILOAD = 0.5 A, VDD = 5.5 V ........61
Figure 23: Full Bridge Typical Drain-Source Low Side On-Resistance vs. Temperature at ILOAD = 0.5 A, VDD = 2.3 V .........62
Figure 24: Full Bridge Typical Drain-Source Low Side On-Resistance vs. Temperature at ILOAD = 0.5 A, VDD = 5.5 V .........62
Figure 25: Full Bridge Typical Drain-Source On-Resistance vs. VDD2 at VDD = 5.5 V, ILOAD = 0.1 A......................................63
Figure 26: Half Bridge Under-voltage Lockout Value vs. Temperature at VDD = 3.3 V............................................................63
Figure 27: Full Bridge High Side OCP Threshold Distribution at VDD=2.3V to 5.5V, VDD2=3V to 13.2V, TJ=-40 °C to 150°C 64
Figure 28: Full Bridge Low Side OCP Threshold Distribution at VDD=2.3V to 5.5V, VDD2= 3V to 13.2V, TJ= -40°C to 150°C 64
Figure 29: Full Bridge OCP Threshold vs. VDD2 at VDD = 5.5 V...............................................................................................65
Figure 30: Half Bridge Dead Band Time vs. VDD2 at VDD = 2.3 V to 5.5 V, f = 50 kHz for Pre-Driver Mode ...........................65
Figure 31: Half Bridge Dead Band Time vs. VDD2 at VDD = 2.3 V to 5.5 V, f = 50 kHz for Regular Mode ...............................66
Figure 32: Half Bridge Output Transition Time vs. VDD2 at VDD = 2.3 V to 5.5 V, f = 50 kHz for Pre-Driver Mode..................66
Figure 33: Half Bridge Output Transition Time vs. VDD2 at VDD = 2.3 V to 5.5 V, f = 50 kHz for Regular Mode......................67
Figure 34: One Half Bridge IDD2 vs. VDD2 at VDD = 5.5 V ........................................................................................................67
Figure 35: All Four Half Bridges IDD2 vs. VDD2 at VDD = 5.5 V.................................................................................................68
Figure 36: Two Full Bridges + One CCMP IDD2 vs. VDD2 at VDD = 5.5 V ................................................................................68
Figure 37: One Full Bridge + Integrator + PWM + OSC1 IDD2 vs. VDD2 at VDD = 5.5 V ..........................................................69
Figure 38: Differential Amplifier with Integrator Block Diagram................................................................................................71
Figure 39: Typical Load Regulation at VOUT = 4.096 V, VDD = 2.3 V to 5.5 V, VDD2 = 5 V .....................................................71
Figure 40: Typical Load Regulation at VOUT = 4.096 V, VDD = 2.3 V to 5.5 V, VDD2 = 9 V .....................................................72
Figure 41: Current Sense Comparator0 Block Diagram...........................................................................................................73
Figure 42: Current Sense Comparator1 Block Diagram...........................................................................................................74
Figure 43: Input Offset Voltage Error vs. Vref for CCMPx (including Amplifier Offset and ACMP Offset) ...............................75
Figure 44: Typical Propagation Delay vs. Vref for CCMPx at T = 25 °C, at VDD = 2.3 V to 5.5 V, Gain = 4............................75
Figure 45: CCMPx Power-On Delay vs. VDD (BG is Forced On).............................................................................................76
Figure 46: Connection Matrix...................................................................................................................................................77
Figure 47: Connection Matrix Example....................................................................................................................................77
Figure 48: 2-bit LUT0 or DFF0.................................................................................................................................................84
Figure 49: 2-bit LUT1 or DFF1.................................................................................................................................................85
Figure 50: 2-bit LUT2 or DFF2.................................................................................................................................................85
Figure 51: DFF Polarity Operations..........................................................................................................................................87
Figure 52: 2-bit LUT3 or PGen.................................................................................................................................................88
Figure 53: PGen Timing Diagram.............................................................................................................................................88
Figure 54: 3-bit LUT0 or DFF3.................................................................................................................................................90
Figure 55: 3-bit LUT3 or DFF6.................................................................................................................................................91
Datasheet
31-Aug-2021
Revision 3.4
5 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Figure 56: 3-bit LUT4 or DFF7.................................................................................................................................................91
Figure 57: 3-bit LUT5 or DFF8.................................................................................................................................................92
Figure 58: DFF Polarity Operations with nReset......................................................................................................................94
Figure 59: DFF Polarity Operations with nSet..........................................................................................................................95
Figure 60: 3-bit LUT1 or DFF4.................................................................................................................................................96
Figure 61: 3-bit LUT2 or DFF5.................................................................................................................................................96
Figure 62: PWM Chopper Circuit Example ..............................................................................................................................98
Figure 63: PWM Chopper Interconnection...............................................................................................................................98
Figure 64: PWM Chopper. Overcurrent Timing Diagram.........................................................................................................99
Figure 65: PWM Chopper. Overcurrent Start During Blanking Time........................................................................................99
Figure 66: PWM Chopper. PWM Duty Cycle is Less than Blanking Time ...............................................................................99
Figure 67: PWM Chopper. 0% Duty Cycle.............................................................................................................................100
Figure 68: PWM Chopper. Overcurrent when 100 % Duty Cycle ..........................................................................................100
Figure 69: DFF Polarity Operations with nReset....................................................................................................................101
Figure 70: DFF Polarity Operations with nSet........................................................................................................................102
Figure 71: 3-bit LUT6/Pipe Delay/Ripple Counter..................................................................................................................104
Figure 72: Example of Ripple Counter Functionality..............................................................................................................105
Figure 73: 4-bit LUT0 or DFF9...............................................................................................................................................107
Figure 74: Possible Connections Inside Multi-Function Macrocell.........................................................................................109
Figure 75: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT7/DFF10, CNT/DLY1) .................................................111
Figure 76: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF11, CNT/DLY2) .................................................112
Figure 77: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF12, CNT/DLY3) .................................................113
Figure 78: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF13, CNT/DLY4) ...............................................114
Figure 79: 16-bit Multi-Function Macrocell Block Diagram (4-bit LUT1/DFF14, CNT/DLY/FSM0).........................................117
Figure 80: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3 ......................................................................119
Figure 81: Delay Mode Timing Diagram for Different Edge Select Modes.............................................................................120
Figure 82: Counter Mode Timing Diagram without Two DFFs Synced Up ............................................................................120
Figure 83: Counter Mode Timing Diagram with Two DFFs Synced Up .................................................................................121
Figure 84: One-Shot Function Timing Diagram......................................................................................................................122
Figure 85: Frequency Detection Mode Timing Diagram.........................................................................................................123
Figure 86: Edge Detection Mode Timing Diagram.................................................................................................................124
Figure 87: Delayed Edge Detection Mode Timing Diagram...................................................................................................125
Figure 88: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3...126
Figure 89: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3 .......126
Figure 90: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3...127
Figure 91: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator Is Forced On, UP = 1) for Counter Data = 3.......127
Figure 92: Counter Value, Counter Data = 3..........................................................................................................................128
Figure 93: Wake/Sleep Controller..........................................................................................................................................129
Figure 94: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used ........................................................129
Figure 95: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used ...........................................................130
Figure 96: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used ............................................................130
Figure 97: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Set is Used ...............................................................131
Figure 98: PWM Output Waveforms and Test Circuit Example for Driving NMOS FETs ......................................................135
Figure 99: PWM Output Waveforms and Test Circuit Example for Driving NMOS and PMOS FETs....................................135
Figure 100: PWM Output Waveforms for Phase Correct PWM Mode ...................................................................................136
Figure 101: Power-Down with SYNC On/Off = 1 and Dead Band = 0 CLK ...........................................................................137
Figure 102: Power-Down with SYNC On/Off = 1 and Dead Band = 1 to 3 CLK ....................................................................138
Figure 103: Power-Down with SYNC On/Off = 0 and Dead Band = 0 CLK ...........................................................................139
Figure 104: Power-Down with SYNC On/Off = 0 and Dead Band = 1 to 3 CLK ....................................................................140
Figure 105: Example of PWM Auto Oscillator Control ...........................................................................................................143
Figure 106: Phase Correct PWM Mode .................................................................................................................................144
Figure 107: PWM Period Waveform.......................................................................................................................................144
Figure 108: PWM0 Functional Diagram.................................................................................................................................145
Figure 109: PWM1 Functional Diagram.................................................................................................................................146
Figure 110: ACMP0H Block Diagram.....................................................................................................................................151
Figure 111: ACMP1H Block Diagram.....................................................................................................................................152
Figure 112: ACMPxH Input Offset Voltage vs. Vref at VDD = 2.3 V to 5.5 V, T = -40 °C to 85 °C .........................................153
Datasheet
31-Aug-2021
Revision 3.4
6 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Figure 113: Propagation Delay vs. Vref for ACMPxH at T = 25 °C, at VDD = 2.3 V to 5.5 V, Gain = 1, Hysteresis = 0.........153
Figure 114: ACMPxH Power-On Delay vs. VDD....................................................................................................................................................154
Figure 115: ACMPxH Current Consumption vs. VDD at Vref = 32 mV...................................................................................154
Figure 116: ACMPxH Current Consumption vs. VDD at Vref = 1024 mV...............................................................................155
Figure 117: ACMPxH Current Consumption vs. VDD at Vref = 2016 mV...............................................................................155
Figure 118: Programmable Delay ..........................................................................................................................................156
Figure 119: Edge Detector Output.........................................................................................................................................156
Figure 120: Deglitch Filter/Edge Detector..............................................................................................................................157
Figure 121: Voltage Reference Block Diagram......................................................................................................................160
Figure 122: Typical Load Regulation, Vref = 320 mV, T = -40 °C to +85 °C, Buffer - Enabled..............................................161
Figure 123: Typical Load Regulation, Vref = 640 mV, T = -40 °C to +85 °C, Buffer - Enabled..............................................161
Figure 124: Typical Load Regulation, Vref = 1280 mV, T = -40 °C to +85 °C, Buffer - Enabled............................................162
Figure 125: Typical Load Regulation, Vref = 2016 mV, T = -40 °C to +85 °C, Buffer - Enabled............................................162
Figure 126: Oscillator0 Block Diagram...................................................................................................................................164
Figure 127: Oscillator1 Block Diagram...................................................................................................................................164
Figure 128: Clock Scheme.....................................................................................................................................................165
Figure 129: PWM Clock Scheme...........................................................................................................................................165
Figure 130: Oscillator Startup Diagram..................................................................................................................................167
Figure 131: Oscillator0 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 2.048 kHz .............................................167
Figure 132: Oscillator1 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC1 = 25 MHz .................................................168
Figure 133: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz..............................................................................168
Figure 134: Oscillator1 Frequency vs. Temperature, OSC1 = 25 MHz .................................................................................169
Figure 135: Oscillators Total Error vs. Temperature..............................................................................................................169
Figure 136: Oscillator0 Settling Time, VDD = 3.3 V, T = 25 °C, OSC0 = 2 kHz .....................................................................170
Figure 137: Oscillator1 Settling Time, VDD = 3.3 V, T = 25 °C, OSC1 = 25 MHz (Normal Start)...........................................170
Figure 138: Oscillator1 Settling Time, VDD = 3.3 V, T = 25 °C, OSC1 = 25 MHz (Start with Delay)......................................171
Figure 139: OSC0 Current Consumption vs. VDD (All Pre-Dividers)......................................................................................171
Figure 140: OSC1 Current Consumption vs. VDD (Pre-Divider = 1).......................................................................................172
Figure 141: OSC1 Current Consumption vs. VDD (Pre-Divider = 2).......................................................................................172
Figure 142: OSC1 Current Consumption vs. VDD (Pre-Divider = 4).......................................................................................173
Figure 143: OSC1 Current Consumption vs. VDD (Pre-Divider = 8).......................................................................................173
Figure 144: OSC1 Current Consumption vs. VDD (Pre-Divider = 12).....................................................................................174
Figure 145: POR Sequence...................................................................................................................................................177
Figure 146: Internal Macrocell States During POR Sequence...............................................................................................178
Figure 147: Power-Down .......................................................................................................................................................179
Figure 148: Basic Command Structure..................................................................................................................................181
Figure 149: I2C General Timing Characteristics ....................................................................................................................181
Figure 150: Byte Write Command, R/W = 0...........................................................................................................................182
Figure 151: Sequential Write Command................................................................................................................................182
Figure 152: Current Address Read Command, R/W = 1 .......................................................................................................183
Figure 153: Random Read Command...................................................................................................................................183
Figure 154: Sequential Read Command................................................................................................................................183
Figure 155: Reset Command Timing .....................................................................................................................................185
Figure 156: Example of I2C Byte Write Bit Masking ..............................................................................................................187
Figure 157: Analog Temperature Sensor Structure Diagram.................................................................................................188
Figure 158: TS Output vs. Temperature, VDD = 2.3 V to 5.5 V..............................................................................................189
Figure 159: STQFN 20L 2x3mm 0.4P FCD Package ............................................................................................................242
Figure 160: Die Temperature when HV OUTs are Active.......................................................................................................245
Figure 161: Typical Application Circuit ...................................................................................................................................246
Figure 162: PCB Layout Example..........................................................................................................................................247
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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Tables
Table 1: Pin Description...........................................................................................................................................................11
Table 2: Pin Type Definitions ...................................................................................................................................................12
Table 3: Absolute Maximum Ratings........................................................................................................................................13
Table 4: Electrostatic Discharge Ratings .................................................................................................................................13
Table 5: Recommended Operating Conditions........................................................................................................................14
Table 6: Recommended Operating Conditions........................................................................................................................14
Table 7: EC at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted...............................................................14
Table 8: EC of the I2C Pins for Digital Input Mode at T = -40 °C to +150 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted.19
Table 9: EC of the I2C Pins for Low-Level Input Mode at T= -40°C to +150°C, VDD = 2.3V to 5.5V Unless Otherwise Noted20
Table 10: I2C Pins Timing Characteristics, DI Mode, T = -40 °C to +150 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted.20
Table 11: I2C Pins Timing Characteristics, DILV Mode, T = -40°C to +150°C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted21
Table 12: Typical Current Estimated for Each Macrocell at T = 25 °C.....................................................................................22
Table 13: HV Output Electrical Characteristic (Full Bridge or Half Bridge Modes)...................................................................23
Table 14: HV Output Electrical Characteristic (Pre-driver Mode).............................................................................................25
Table 15: Protection Circuits....................................................................................................................................................27
Table 16: Typical Startup Estimated for Chip at T = 25 °C ......................................................................................................28
Table 17: Typical Delay Estimated for Each Macrocell at T = 25 °C........................................................................................28
Table 18: Programmable Delay Expected Typical Delays and Widths at T = 25 °C................................................................29
Table 19: Typical Filter Rejection Pulse Width at T = 25 °C ....................................................................................................29
Table 20: LP_BG Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V.......................................................................30
Table 21: Typical Counter/Delay Offset at T = 25 C ................................................................................................................30
Table 22: OSC0 Frequency Limits, VDD = 2.3 V to 5.5 V.........................................................................................................30
Table 23: OSC1 Frequency Limits, VDD = 2.3 V to 5.5 V.........................................................................................................30
Table 24: Oscillators Power-On Delay at T = 25 °C, OSC Power Setting: "Auto Power-On" ..................................................31
Table 25: Current Sense Comparator Specifications at T = -40 °C to +85 °C, VDD = 2.3 to 5.5 V Unless Otherwise Noted...31
Table 26: Differential Amplifier Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted..........33
Table 27: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted................................34
Table 28: TS Output vs Temperature (Output Range 1) ..........................................................................................................36
Table 29: TS Output vs Temperature (Output Range 2) ..........................................................................................................36
Table 30: ESD Resistors Value................................................................................................................................................41
Table 31: GPIO2 Mode Selection.............................................................................................................................................44
Table 32: GPIO3 Mode Selection.............................................................................................................................................44
Table 33: HV OUT CTRL0 Full Bridge Logic for IN-IN Mode...................................................................................................53
Table 34: HV OUT CTRL1 Full Bridge Logic for IN-IN Mode...................................................................................................53
Table 35: HV OUT CTRL0 Full Bridge Logic for PH-EN Mode................................................................................................54
Table 36: HV OUT CTRL1 Full Bridge Logic for PH-EN Mode................................................................................................54
Table 37: PWM Control of Motor Speed (IN-IN Mode).............................................................................................................54
Table 38: PWM Control of Motor Speed (PH-EN Mode)..........................................................................................................54
Table 39: HV_GPO0_HD Half Bridge Logic.............................................................................................................................56
Table 40: HV_GPO1_HD Half Bridge Logic.............................................................................................................................56
Table 41: HV_GPO2_HD Half Bridge Logic.............................................................................................................................56
Table 42: HV_GPO3_HD Half Bridge Logic.............................................................................................................................57
Table 43: Matrix Input Table.....................................................................................................................................................78
Table 44: Matrix Output Table..................................................................................................................................................80
Table 45: Connection Matrix Virtual Inputs ..............................................................................................................................83
Table 46: 2-bit LUT0 Truth Table.............................................................................................................................................86
Table 47: 2-bit LUT1 Truth Table.............................................................................................................................................86
Table 48: 2-bit LUT2 Truth Table.............................................................................................................................................86
Table 49: 2-bit LUT Standard Digital Functions .......................................................................................................................86
Table 50: 2-bit LUT1 Truth Table.............................................................................................................................................89
Table 51: 2-bit LUT Standard Digital Functions .......................................................................................................................89
Table 52: 3-bit LUT0 Truth Table.............................................................................................................................................93
Table 53: 3-bit LUT4 Truth Table.............................................................................................................................................93
Table 54: 3-bit LUT3 Truth Table.............................................................................................................................................93
Table 55: 3-bit LUT5 Truth Table.............................................................................................................................................93
Table 56: 3-bit LUT Standard Digital Functions .......................................................................................................................93
Table 57: 3-bit LUT1 Truth Table.............................................................................................................................................97
Table 58: 3-bit LUT2 Truth Table.............................................................................................................................................97
Table 59: 3-bit LUT Standard Digital Functions .......................................................................................................................97
Table 60: 3-bit LUT6 Truth Table...........................................................................................................................................106
Table 61: 4-bit LUT0 Truth Table...........................................................................................................................................108
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 62: 4-bit LUT Standard Digital Functions .....................................................................................................................108
Table 63: 3-bit LUT7 Truth Table...........................................................................................................................................115
Table 64: 3-bit LUT9 Truth Table...........................................................................................................................................115
Table 65: 3-bit LUT8 Truth Table...........................................................................................................................................115
Table 66: 3-bit LUT10 Truth Table.........................................................................................................................................115
Table 67: 4-bit LUT1 Truth Table...........................................................................................................................................118
Table 68: 4-bit LUT Standard Digital Functions .....................................................................................................................118
Table 69: Regular/Preset Mode Registers.............................................................................................................................141
Table 70: Conditions for Disabling/Enabling an Internal Oscillator ........................................................................................141
Table 71: PWM0 Register Settings........................................................................................................................................146
Table 72: PWM1 Register Settings........................................................................................................................................147
Table 73: Vref Selection Table...............................................................................................................................................158
Table 74: Mode Selection Table.............................................................................................................................................159
Table 75: Oscillator Operation Mode Configuration Settings.................................................................................................163
Table 76: Read/Write Protection Options...............................................................................................................................184
Table 77: Register Map..........................................................................................................................................................190
Table 78: MSL Classification..................................................................................................................................................243
Table 79: Ordering Information ..............................................................................................................................................243
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GreenPAK Programmable Mixed-Signal Matrix with High
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1
Block Diagram
Filter
I2C Serial
Multi-Function Macrocells
VDD
GPI
VDD2_A
OTP
POR
with Edge
Detector
Communication
3-bit
LUT3_7/
3-bit
LUT3_8/
DFF10+8bit
CNT/DLY1
DFF11+8bit
CNT/DLY2
Programmable
Delay with
Edge Detector
VDD2_B
Temperature
Sensor
Oscillators
3-bit
3-bit
LUT3_9/
LUT3_10/
DFF13+8bit
CNT/DLY4
DFF12+8bit
CNT/DLY3
2.048kHz
25MHz
SENSE_A
SENSE_B
High Speed Analog
GPIO0
GPIO1
4-bit
LUT4_1 /
DFF14+16bit
CNT/DLY0
PWM Macrocells
ACMP0H
ACMP1H
8-bit
PWM1
8-bit
PWM0
Charge
Pump
HV_GPO0_HD
OCP
LS
LS
LS
LS
SCL/
GPIO2
High
Speed
Vref
Combination Function Macrocells
Charge
Pump
HV_GPO1_HD
OCP
SDA/
GPIO3
2-bit
LUT2_0
or DFF0
2-bit
LUT2_1
or DFF1
2-bit
LUT2_2
or DFF2
HV GPO Control
Analog
GPIO4
GPIO5
Charge
Pump
HV_GPO2_HD
OCP
Current
Sense
Comp0
2-bit
LUT2_3
or PGen
3-bit
LUT3_0
or DFF3
3-bit LUT3_1
or DFF4/
PWM Chop0
Charge
Pump
HV_GPO3_HD
OCP
Diff Amp +
Integrator
3-bit
LUT3_4
or DFF7
3-bit
LUT3_3
or DFF6
3-bit LUT3_2
or DFF5/
PWM Chop1
GPIO6
GND
Current
Sense
Comp1
GND_HV
GND_HV
3-bit
LUT3_6
or PD/
4-bit
LUT4_0
or DFF9
3-bit
LUT3_5
or DFF8
Ripple CNT
Figure 1: Block Diagram
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GreenPAK Programmable Mixed-Signal Matrix with High
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2
Pinout
2.1 PIN CONFIGURATION - STQFN- 20L
Table 1: Pin Description
Pin # Signal Name Pin Functions
1
2
VDD
Power Supply 2.5 V – 5.0 V
Matrix OE GPIO, Vref OUT, Diff Amp Vset Input,
TS _OUT
GPIO0
3
4
GPI
GPI, EXT_Vref0, SLA_0
Analog Ground
18 17
20 19
GND_HV
SDA/GPIO3
SCL/GPIO2
GPIO1
VDD
GPIO0
1
2
3
16
15
14
Winding A Sense, relate to HV_GPO0_HD,
HV_GPO1_HD
5
SENSE_A
GND
6
7
8
9
V
High Voltage Power Supply 3.3 V - 12.0 V (Note )
DD2_A
GPI
HV_GPO0_HD HV_GPO_HD
HV_GPO1_HD HV_GPO_HD
HV_GPO2_HD HV_GPO_HD
GND_HV
GND_HV
SENSE_A
VDD2_A
13 GND_HV
4
5
12
SENSE_B
10 HV_GPO3_HD HV_GPO_HD
6
11
11
12
13
14
V
High Voltage Power Supply 3.3 V - 12.0 V (Note )
DD2_B
VDD2_B
Winding B Sense, relate to HV_GPO2_HD,
HV_GPO3_HD
7
8
9
10
SENSE_B
GND_HV
GPIO1
Analog Ground
Matrix OE GPIO, SLA_1, EXT_CLK for OSC0 or
Current Sense CMP0 EXT_Vref
15
16
SCL/GPIO2 SCL, GPIO
SDA/GPIO3 SDA, GPIO
Matrix OE GPIO, EXT_Vref1, SLA_2, EXT_CLK
for OSC1 or Current Sense CMP1 EXT_Vref
17
GPIO4
18
19
20
GND
General Ground
GPIO5
GPIO6
Matrix OE GPIO, ACMP0_H
STQFN-20L
(Top View)
Matrix OE GPIO, SLA_3, ACMP1_H
Legend:
ACMP: Analog Comparator
CMP: Comparator
Diff Amp: Differential Amplifier
GPI: General Purpose Input
GPO: General Purpose Output
GPIO: General Purpose Input/Output
HD: High Current Drive
HV: High Voltage
SCL: I2C Clock Input
SDA: I2C Data Input/Output
SLA_x: Slave Address
Vrefx: Voltage Reference Output
TS_OUT: Temperature Sensor Output
EXT: External
CLK: Clock
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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Table 2: Pin Type Definitions
Pin Type
VDD
Description
Power Supply
GPIO
General Purpose Input/Output
General Purpose Input
High Voltage General Purpose Output High Current Drive
I2C Serial Clock Input
GPI
HV_GPO_HD
SCL
SDA
I2C Serial Data Input/Output
GND
General Ground
GND_X
SENSE_X
VDD2_X
Analog Ground
Current Sense Pin
High Voltage Power Supply
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GreenPAK Programmable Mixed-Signal Matrix with High
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3
Characteristics
3.1 ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability.
Table 3: Absolute Maximum Ratings
Parameter
Description
Condition
Min
-0.3
Max
7.0
Unit
V
Supply voltage on VDD relative to GND
Supply voltage on VDD2 relative to GND
DC Input Voltage
-0.3
18
V
GND - 0.5 V
V
DD + 0.5 V
V
(Through VDD or
GND pin) for VDD
group
Maximum VDD Average or DC Current
--
--
120
mA
mA
(Through each
VDD2_A, VDD2_B,
SENSE_A or
Maximum VDD2 or Sense Average or DC
Current
2000
SENSE_B pin)
Push-Pull 1x
--
--
--
--
--
--
--
--
11
16
Maximum Average
Through VDD Group
pins
Push-Pull 2x
OD 1x
or
TJ = -40 °C to 85 °C
TJ = -40 °C to 150 °C
mA
DC Current (VDD
power supply)
11
OD 2x
21
Push-Pull 1x
Push-Pull 2x
OD 1x
3.8
7.6
3.8
7.6
Maximum Average
or
DC Current (VDD
power supply)
Through VDD Group
pins
mA
mA
OD 2x
Maximum Average
or DC Current
(VDD2 power
Push-Pull/
Half Bridge
Through VDD2 High
Current Group pins
--
1500
supply)
Internally
limited by
OCP
Maximum pulsed current sink/sourced
per HV HD pin
Pulsewidth<0.5ms;
duty cycle < 2 %
--
mA
mA
Through VDD Group
pin
Current at Input Pin
-0.1
1.0
Input Leakage Current (Absolute Value)
Storage Temperature Range
Junction Temperature
--
-65
--
1000
150
nA
°C
°C
150
Moisture Sensitivity Level
1
3.2 ELECTROSTATIC DISCHARGE RATINGS
Table 4: Electrostatic Discharge Ratings
Parameter
Min
4000
1300
Max
--
Unit
V
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
--
V
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GreenPAK Programmable Mixed-Signal Matrix with High
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3.3 RECOMMENDED OPERATING CONDITIONS
Table 5: Recommended Operating Conditions
Parameter
Condition
Min
2.3
3.0
-40
-40
Typ
3.3
12.0
25
Max
5.5
13.2
85
Unit
V
Supply Voltage (VDD
)
High Supply Voltage (VDD2
)
V
Operating Ambient Temperature (TA)
Junction Temperature Range (TJ)
Capacitor Value at VDD
°C
°C
µF
(Note )
--
150
--
0.1
Allowable Input Voltage at
Analog Pins
VDD or VDD2
(Note 1)
Analog Input Common Mode Range
0
--
V
Note 1 VDD for GPI, GPIO4, GPIO5, GPIO6 and VDD2 for HV GPO0 and HV GPO1
3.4 THERMAL INFORMATION
Table 6: Recommended Operating Conditions
Parame-
ter
Description
Condition
Min
Typ
Max
Unit
θJA
Thermal Resistance
4L JEDEC PCB
--
--
65
°C/W
4L JEDEC PCB with a thermal vias
that connect thermal pad through all
layers of the PCB
θJA
Thermal Resistance
--
--
46
°C/W
Junction-to-case (top)
Thermal Resistance
θJC(top)
θJB
--
--
23.50
25.51
--
--
°C/W
°C/W
Junction-to-board
Thermal Resistance
Junction-to-case (top)
ψJC(top) Characterization
--
--
6.80
--
--
°C/W
°C/W
Parameter
Junction-to-board
Characterization
Parameter
ψJB
24.44
3.5 ELECTRICAL CHARACTERISTICS
Table 7: EC at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Parameter Description
Condition
Min
Typ
Max
Unit
0.7x
VDD
VDD
0.3
+
Logic Input (Note 1)
--
V
HIGH-Level Input Voltage for
VDD group (Note 3)
0.8x
VDD
VDD
0.3
+
VIH
Logic Input with Schmitt Trigger
Low-Level Logic Input (Note 1)
Logic Input (Note 1)
--
--
--
--
--
V
V
V
V
V
VDD
0.3
+
1.25
GND-
0.3
0.3x
VDD
LOW-Level Input Voltage for
GND-
0.3
0.2x
VDD
VIL
Logic Input with Schmitt Trigger
Low-Level Logic Input (Note 1)
V
DD group (Note 3)
GND-
0.3
0.5
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GreenPAK Programmable Mixed-Signal Matrix with High
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Table 7: EC at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 1x Drive,
VDD = 2.5 V ± 8 %, IOH = 1 mA
2.07
--
--
V
Push-Pull, 1x Drive,
VDD = 3.3 V ± 10 %, IOH = 3 mA
2.54
3.95
2.13
2.69
4.11
2.05
2.49
3.90
2.12
2.67
4.09
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Push-Pull, 1x Drive,
VDD = 5 V ± 10 %, IOH = 5 mA
HIGH-Level Output Voltage
for VDD Group
TJ = -40 °C to 85 °C
Push-Pull, 2x Drive,
VDD = 2.5 V ± 8 %, IOH = 1 mA
--
Push-Pull, 2x Drive,
VDD = 3.3 V ± 10 %, IOH = 3 mA
--
Push-Pull, 2x Drive,
VDD = 5 V ± 10 %, IOH = 5 mA
--
VOH
Push-Pull, 1x Drive,
--
V
DD = 2.5 V ± 8 %, IOH = 1 mA
Push-Pull, 1x Drive,
DD = 3.3 V ± 10 %, IOH = 3 mA
--
V
HIGH-Level Output Voltage
for VDD Group
Push-Pull, 1x Drive,
VDD = 5 V ± 10 %, IOH = 5 mA
--
TJ = -40 °C to 150 °C
Push-Pull, 2x Drive,
VDD = 2.5 V ± 8 %, IOH = 1 mA
--
Push-Pull, 2x Drive,
--
V
DD = 3.3 V ± 10 %, IOH = 3 mA
Push-Pull, 2x Drive,
VDD = 5 V ± 10 %, IOH = 5 mA
--
Push-Pull, 1x Drive,
VDD = 2.5 V ± 8 %, IOL= 1 mA
0.08
0.18
0.21
0.04
0.09
0.11
0.030
0.068
0.083
0.014
Push-Pull, 1x Drive,
--
V
DD = 3.3 V ± 10 %, IOL = 3 mA
Push-Pull, 1x Drive,
VDD = 5 V ± 10 %, IOL= 5 mA
--
Push-Pull, 2x Drive,
VDD = 2.5 V ± 8 %, IOL = 1 mA
--
Push-Pull, 2x Drive,
VDD = 3.3 V ± 10 %, IOL= 3 mA
--
LOW-Level Output Voltage
for VDD Group
VOL
Push-Pull, 2x Drive,
VDD = 5 V ± 10 %, IOL = 5 mA
TJ = -40 °C to 85 °C
--
NMOS OD, 1x Drive,
VDD = 2.5 V ± 8 %, IOL = 1 mA
--
NMOS OD, 1x Drive,
VDD = 3.3 V ± 10 %, IOL = 3 mA
--
NMOS OD, 1x Drive,
VDD = 5 V ± 10 %, IOL = 5 mA
--
NMOS OD, 2x Drive,
VDD = 2.5 V ± 8 %, IOL = 1 mA
--
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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Table 7: EC at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
NMOS OD, 2x Drive,
VDD = 3.3 V ± 10 %, IOL = 3 mA
--
--
0.035
V
LOW-Level Output Voltage
for VDD Group
TJ = -40 °C to 85 °C
NMOS OD, 2x Drive,
VDD = 5 V ± 10 %, IOL = 5 mA
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0.083
0.09
0.21
0.26
0.04
0.11
0.13
0.035
0.082
0.100
0.017
0.042
0.052
--
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Push-Pull, 1x Drive,
VDD = 2.5 V ± 8 %, IOL= 1 mA
--
Push-Pull, 1x Drive,
VDD = 3.3 V ± 10 %, IOL = 3 mA
--
Push-Pull, 1x Drive,
VDD = 5 V ± 10 %, IOL= 5 mA
--
Push-Pull, 2x Drive,
VDD = 2.5 V ± 8 %, IOL = 1 mA
--
Push-Pull, 2x Drive,
VDD = 3.3 V ± 10 %, IOL= 3 mA
--
VOL
Push-Pull, 2x Drive,
--
LOW-Level Output Voltage
for VDD Group
TJ = -40 °C to 150 °C
V
DD = 5 V ± 10 %, IOL = 5 mA
NMOS OD, 1x Drive,
VDD = 2.5 V ± 8 %, IOL = 1 mA
--
NMOS OD, 1x Drive,
VDD = 3.3 V ± 10 %, IOL = 3 mA
--
NMOS OD, 1x Drive,
--
V
DD = 5 V ± 10 %, IOL = 5 mA
NMOS OD, 2x Drive,
VDD = 2.5 V ± 8 %, IOL = 1 mA
--
--
NMOS OD, 2x Drive,
VDD = 3.3 V ± 10 %, IOL = 3 mA
NMOS OD, 2x Drive,
--
V
DD = 5 V ± 10 %, IOL = 5 mA
Push-Pull, VDD2 = 5 V ± 10 %,
IOH2 = 10 mA
4.496
8.097
10.797
--
HIGH-Level Output Voltage
for VDD2 High Current Group
Push-Pull, VDD2 = 9 V ± 10 %,
IOH2 = 10 mA
VOH2
--
Push-Pull, VDD2 = 12 V ± 10 %,
IOH2 = 10 mA
--
Push-Pull, VDD2 = 5 V ± 10 %,
IOL2 = 10 mA
0.004
0.004
0.004
LOW-Level Output Voltage
Push-Pull, VDD2 = 9 V ± 10 %,
VOL2
--
for VDD2 High Current Group IOL2 = 10 mA
Push-Pull, VDD2 = 12 V ± 10 %,
IOL2 = 10 mA
--
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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Table 7: EC at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 1x Drive,
VDD = 2.5 V ± 8 %, VOH = VDD - 0.2
1.43
--
--
mA
Push-Pull, 1x Drive,
VDD = 3.3 V ± 10 %, VOH = 2.4 V
4.80
18.60
2.87
9.56
36.83
1.27
4.35
16.70
2.52
8.57
32.99
1.92
6.18
8.98
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
HIGH-Level Output Pulse
Current (Note 2)
Push-Pull, 1x Drive,
VDD = 5 V ± 10 %, VOH = 2.4 V
Voltage for VDD Group,
TJ = -40 °C to 85 °C
Push-Pull, 2x Drive,
VDD = 2.5 V ± 8 %, VOH = VDD - 0.2
Push-Pull, 2x Drive,
VDD = 3.3 V ± 10 %, VOH = 2.4 V
Push-Pull, 2x Drive,
VDD = 5 V ± 10 %, VOH = 2.4 V
IOH
Push-Pull, 1x Drive,
VDD = 2.5 V ± 8 %, VOH = VDD - 0.2
Push-Pull, 1x Drive,
V
DD = 3.3 V ± 10 %, VOH = 2.4 V
HIGH-Level Output Pulse
Current (Note 2)
Push-Pull, 1x Drive,
VDD = 5 V ± 10 %, VOH = 2.4 V
Voltage for VDD Group,
TJ = -40 °C to 150 °C
Push-Pull, 2x Drive,
VDD = 2.5 V ± 8 %, VOH = VDD - 0.2
Push-Pull, 2x Drive,
V
DD = 3.3 V ± 10 %, VOH = 2.4 V
Push-Pull, 2x Drive,
VDD = 5 V ± 10 %, VOH = 2.4 V
Push-Pull, 1x Drive, VDD = 2.5 V ± 8 %,
VOL = 0.15 V
LOW-Level Output Pulse
Current (Note 2)
Push-Pull, 1x Drive, VDD = 3.3 V ± 10 %,
VOL = 0.4 V
IOL
Voltage for VDD Group,
TJ = -40 °C to 85 °C
Push-Pull, 1x Drive, VDD = 5.0 V ± 10 %,
V
OL = 0.4 V
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GreenPAK Programmable Mixed-Signal Matrix with High
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Table 7: EC at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 2x Drive, VDD = 2.5 V ± 8 %,
VOL = 0.15 V
3.82
--
--
mA
Push-Pull, 2x Drive, VDD = 3.3 V ± 10 %,
VOL = 0.4 V
12.25
17.67
4.71
--
--
--
--
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
nA
Push-Pull, 2x Drive, VDD = 5.0 V ± 10 %,
VOL = 0.4 V
NMOS OD, 1x Drive, VDD = 2.5 V ± 8 %,
VOL = 0.15 V
--
--
LOW-Level Output Pulse
Current (Note 2)
NMOS OD, 1x Drive, VDD = 3.3 V ± 10%,
VOL = 0.4 V
15.16
21.84
9.24
--
--
Voltage for VDD Group,
TJ = -40 °C to 85 °C
NMOS OD, 1x Drive, VDD = 5.0 V ± 10%,
VOL = 0.4 V
--
--
NMOS OD, 2x Drive, VDD = 2.5 V ± 8 %,
VOL = 0.15 V
--
--
NMOS OD, 2x Drive, VDD = 3.3 V ± 10%,
29.51
41.90
1.63
--
--
V
OL = 0.4 V
NMOS OD, 2x Drive, VDD = 5.0 V ± 10%,
VOL = 0.4 V
--
--
Push-Pull, 1x Drive, VDD = 2.5 V ± 8 %,
VOL = 0.15 V
--
--
Push-Pull, 1x Drive, VDD = 3.3 V ± 10%,
VOL = 0.4 V
5.23
--
--
IOL
Push-Pull, 1x Drive, VDD = 5.0 V ± 10%,
7.52
--
--
V
OL = 0.4 V
Push-Pull, 2x Drive, VDD = 2.5 V ± 8 %,
VOL = 0.15 V
3.22
--
--
Push-Pull, 2x Drive, VDD = 3.3 V ± 10%,
VOL = 0.4 V
10.34
14.78
3.99
--
--
LOW-Level Output Pulse
Current (Note 2)
Push-Pull, 2x Drive, VDD = 5.0 V ± 10%,
--
--
V
OL = 0.4 V
Voltage for VDD Group,
TJ = -40 °C to 150 °C
NMOS OD, 1x Drive, VDD = 2.5 V ± 8 %,
VOL = 0.15 V
--
--
NMOS OD, 1x Drive, VDD = 3.3 V ± 10%,
VOL = 0.4 V
12.77
18.26
7.83
--
--
NMOS OD, 1x Drive, VDD = 5.0 V ± 10%,
VOL = 0.4 V
--
--
NMOS OD, 2x Drive, VDD = 2.5 V ± 8 %,
VOL = 0.15 V
--
--
NMOS OD, 2x Drive, VDD = 3.3 V ± 10%,
VOL = 0.4 V
24.94
35.03
--
--
--
NMOS OD, 2x Drive, VDD = 5.0 V ± 10%,
VOL = 0.4 V
--
--
All macrocells are in SLEEP
For VDD2 <= 5.0V
mode including charge pumps UVLO disabled
Isleep
--
219
2.16
1.83
VDD Level Required to Start Up the Chip,
TJ = -40 °C to 150 °C
PONTHR
Power-On Threshold
1.80
1.98
1.55
V
VDD Level Required to Switch Off the
Chip, TJ = -40 °C to 150 °C
POFFTHR Power-Off Threshold
1.33
V
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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Table 7: EC at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
1 M for Pull-up: VIN = GND;
for Pull-down: VIN = DVDD
0.79
0.98
1.25
MΩ
Pull-up or Pull-down
Resistance
TJ = -40 °C to 85°C
100 k for Pull-up: VIN = GND;
for Pull-down: VIN = DVDD
87.1
8.2
100.4
11.1
0.98
100
116
13.6
1.25
120
kΩ
kΩ
10 k For Pull-up: VIN = GND;
for Pull-down: VIN = DVDD
RPULL
1 M for Pull-up: VIN = GND;
for Pull-down: VIN = DVDD
0.79
80
MΩ
kΩ
Pull-up or Pull-down
Resistance
TJ = -40 °C to 150 °C
100 k for Pull-up: VIN = GND;
for Pull-down: VIN = DVDD
10 k For Pull-up: VIN = GND;
for Pull-down: VIN = DVDD
8.2
--
11.1
2.5
13.6
--
kΩ
CIN
Input Capacitance
pF
Note 1 No hysteresis.
Note 2 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
Note 3 ESD resistor should be taken into consideration when using pull-up/pull-down resistors. It may affect VIH and VIL. See
sections 6.6 to 6.9.
3.6 I2C PINS ELECTRICAL CHARACTERISTICS
Table 8: EC of the I2C Pins for Digital Input Mode at T = -40 °C to +150 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Fast-Mode
Fast-Mode Plus
Parameter Description
Condition
Unit
Min
Max
Min
Max
LOW-level Input
Voltage
VIL
-0.5
0.3xVDD
-0.5
0.3xVDD
V
V
V
HIGH-level Input
Voltage
VIH
0.7xVDD
0.05xVDD
5.5
--
0.7xVDD
5.5
--
Hysteresis of Schmitt
Trigger Inputs
VHYS
0.05xVDD
(Open-Drain) at 3 mA sink
current
VDD > 2 V
LOW-Level Output
Voltage 1
VOL1
0
0
0.4
0
0
0.4
V
V
(Open-Drain) at 2 mA sink
current
VDD ≤ 2 V
LOW-Level Output
Voltage 2
VOL2
0.2xVDD
0.2xVDD
VOL = 0.4 V
VOL = 0.6 V
3
6
--
--
20
--
--
--
mA
mA
LOW-Level Output
Current
IOL
Output Fall Time from
VIHmin to VILmax
(Note 1)
14x
(VDD/5.5 V)
14x
(VDD/5.5 V)
tof
250
120
ns
PulseWidthofSpikes
that must be
suppressed by the
Input Filter
tSP
0
50
0
50
ns
Input Current each IO
Pin
Ii
0.1xVDD < VI < 0.9xVDDmax
-10
--
+10
10
-10
--
+10
10
µA
Capacitance for each
IO Pin
Ci
pF
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GreenPAK Programmable Mixed-Signal Matrix with High
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Table 8: EC of the I2C Pins for Digital Input Mode at T = -40 °C to +150 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Fast-Mode
Min Max
Note 1 Does not meet standard I2C specifications: tof = 20x(VDD/5.5 V) (min).
Note 2 For Fast-mode Plus SDA pin must be configured as 3.2x Open-Drain, see register [837] in Section 23.
Fast-Mode Plus
Parameter Description
Condition
Unit
Min Max
Table 9: EC of the I2C Pins for Low-Level Input Mode at T= -40°C to +150°C, VDD = 2.3V to 5.5V Unless Otherwise Noted
Fast-Mode
Parame-
Description
Condition
Unit
ter
Min
-0.5
1.2
Max
0.5
VIL
LOW-level Input Voltage
HIGH-level Input Voltage
V
V
VIH
5.5
Hysteresis of Schmitt Trigger
Inputs
VHYS
VOL1
VOL2
0.05xVDD
--
V
V
V
(Open-Drain) at 3 mA sink current
LOW-Level Output Voltage 1
LOW-Level Output Voltage 2
0
0
0.4
V
DD > 2 V
(Open-Drain) at 2 mA sink current
VDD ≤ 2 V
0.2xVDD
VOL = 0.4 V
VOL = 0.6 V
3
6
--
--
mA
mA
IOL
LOW-Level Output Current
Output Fall Time from VIHmin to
14x
(VDD/5.5 V)
tof
250
50
ns
ns
V
ILmax (Note 1)
Pulse Width of Spikes that must
be suppressed by the Input Filter
tSP
0
Ii
Input Current each IO Pin
0.1xVDD < VI < 0.9xVDDmax
-10
--
+10
10
µA
Ci
Capacitance for each IO Pin
pF
Note 1 Does not meet standard I2C specifications: tof = 20x(VDD/5.5 V) (min)
Table 10: I2C Pins Timing Characteristics, DI Mode, T = -40 °C to +150 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Speed
Parameter Description
Condition
400 kHz
1 MHz
Unit
Min
--
Typ
--
Max
400
--
Min
--
Typ
--
Max
1000 kHz
FSCL
tLOW
tHIGH
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
1300
600
--
500
260
--
--
--
ns
ns
--
--
--
Input Filter Spike Suppression
(SCL, SDA)
tI
--
--
--
--
--
50
900
--
--
--
--
--
--
50
450
--
ns
ns
ns
tAA
tBUF
Clock Low to Data OUT Valid
Bus Free Time between Stop
and Start
1300
500
tHD_STA
tSU_STA
tHD_DAT
tSU_DAT
tR
Start Hold Time
Start Set-up Time
Data Hold Time
Data Set-up Time
Inputs Rise Time
600
600
0
--
--
--
--
--
--
--
260
260
0
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
--
--
100
--
--
50
--
--
300
120
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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Table 10: I2C Pins Timing Characteristics, DI Mode, T = -40 °C to +150 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Speed
Parameter Description
Condition
400 kHz
1 MHz
Unit
Min
--
Typ
--
Max
300
--
Min
--
Typ
--
Max
120
--
tF
Inputs Fall Time
ns
ns
ns
tSU_STO
Stop Set-up Time
600
50
--
260
50
--
tDH
Data OUT Hold Time
--
--
--
--
Note 1: Please follow official I2C spec UM10204
Table 11: I2C Pins Timing Characteristics, DILV Mode, T = -40°C to +150°C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Speed
Parameter
Description
Condition
400 kHz
Unit
Min
--
Typ
--
Max
400
--
FSCL
tLOW
tHIGH
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
kHz
ns
1300
600
--
--
--
ns
Input Filter Spike Suppression (SCL,
SDA)
tI
--
--
50
ns
tAA
tBUF
Clock Low to Data OUT Valid
Bus Free Time between Stop and Start
Start Hold Time
--
1300
600
600
327
443
--
--
--
--
--
--
--
--
--
--
--
900
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHD_STA
tSU_STA
tHD_DAT
tSU_DAT
tR
--
Start Set-up Time
--
Data Hold Time (Note 1)
Data Set-up Time (Note 1)
Inputs Rise Time
--
--
300
300
--
tF
Inputs Fall Time
--
tSU_STO
tDH
Stop Set-up Time
600
Data OUT Hold Time
50
--
Note 1 Does not meet standard I2C specifications: tHD_DAT = 0 ns (min), tSU_DAT = 100 ns (min) for Fast-mode
Note 2: Please follow official I2C spec UM10204
Note 3: When SCL Input is in Low-Level Logic mode max frequency is 400kHz
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GreenPAK Programmable Mixed-Signal Matrix with High
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3.7 MACROCELLS CURRENT CONSUMPTION
Table 12: Typical Current Estimated for Each Macrocell at T = 25 °C
Parameter Description Note
Chip Quiescent (Pdet + OTP st-by)
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
Unit
0.038
0.040
0.047
µA
Chip Quiescent and LPBG (LPBG + Pdet
+ OTP st-by + I2C en + leakages),
UVLO disabled
0.57
0.59
0.63
µA
µA
µA
Chip Quiescent and LPBG (LPBG + Pdet
+ OTP st-by + I2C en + leakages),
UVLO_A enabled
18.06
18.17
18.16
18.14
18.45
18.44
Chip Quiescent and LPBG (LPBG + Pdet
+ OTP st-by + I2C en + leakages),
UVLO_B enabled
Chip Quiescent and LPBG (LPBG + Pdet
+ OTP st-by + I2C en + leakages),
UVLO_A and UVLO B enabled
20.98
21.6
21.14
21.7
21.53
22.1
µA
µA
Vref (LPBG + Vref_mux +
Vref_OUT_BUF)
OSC1 25 MHz, Pre-divider = 1
OSC1 25 MHz, Pre-divider = 2
OSC1 25 MHz, Pre-divider = 4
OSC1 25 MHz, Pre-divider = 8
OSC1 25 MHz, Pre-divider = 12
OSC0 2.048 kHz, Pre-divider = 1
OSC0 2.048 kHz, Pre-divider = 4
OSC0 2.048 kHz, Pre-divider = 8
IO with 1x push-pull + 4 pF (2.048 kHz)
62.37
47.41
40.14
36.28
35.21
0.35
79.3
59.3
49.4
44.2
42.8
0.35
0.35
0.35
0.16
126.74
94.93
79.02
70.81
68.41
0.37
µA
µA
µA
µA
µA
µA
µA
µA
µA
0.34
0.37
IDD
Current
0.34
0.37
0.13
0.22
Temperature Sensor (LPBG + Vref_mux
+ Vref_OUT_BUF + I_TS)
23
22
23
µA
µA
µA
µA
One ACMPxH
(includes internal Vref) (Note 1)
36.1
21.5
56.8
36.5
22.0
57.6
37.8
23.2
59.9
One ACMPxH
(includes external Vref) (Note 1)
Two ACMPxH
(includes internal Vref) (Note 1)
Two ACMPxH
(includes external Vref) (Note 1)
38.1
39.2
42.5
µA
µA
Any Half Bridge, VDD2 = 5 V
164.7
193.7
270.2
All Four Half Bridges
(or Two Full Bridges),
VDD2 = 5 V
341.3
375.1
464.1
µA
One Full Bridge + Integrator + PWM +
OSC1, VDD2 = 5 V
476.4
361.3
419.9
596.6
394.1
453.5
886.2
480.7
542.5
µA
µA
µA
Two Full Bridges + one CCMP (any Vref,
any Gain), VDD2 = 5 V
Two Full Bridges + two CCMP (any Vref,
any Gain), VDD2 = 5 V
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GreenPAK Programmable Mixed-Signal Matrix with High
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Table 12: Typical Current Estimated for Each Macrocell at T = 25 °C(Continued)
Parameter Description Note
Any Half Bridge, VDD2 = 5 V
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
Unit
164.3
162.0
160.6
µA
All Four Half Bridges
(or Two Full Bridges),
VDD2 = 5 V
348.1
338.9
332.4
µA
One Full Bridge + Integrator + PWM +
OSC1
406.9
327.7
348.1
2.1
402.7
319.4
338.9
2.1
402.3
313.6
332.4
2.1
µA
µA
µA
µA
µA
Two Full Bridges + one CCMP (any Vref,
any Gain), VDD2 = 5 V
IDD2
Current
Two Full Bridges + two CCMP (any Vref,
any Gain), VDD2 = 5 V
Under-voltage Lockout A or B Enabled,
VDD2 = 5 V
Under-voltage LockoutAand B Enabled,
4.17
4.17
4.17
V
DD2 = 5 V
Note 1 Numbers for ACMPs are averaged from different Vref since different Vref has different current
Note 2 VDD2 = VDD_A = VDD_B
3.8 HV OUTPUT ELECTRICAL CHARACTERISTIC
Table 13: HV Output Electrical Characteristic (Full Bridge or Half Bridge Modes)
Parameter
Description
Condition
Min
Typ
Max
Unit
VDD2 = 5 V, 16 Ω to GND,
10 % to 90 % VDD2
TJ = -40 °C to 150 °C
,
tR
Rise time HV OUT
80
116
200
200
ns
ns
VDD2 = 5 V, 16 Ω to GND,
90 % to 10 % VDD2
TJ = -40 °C to 85 °C
,
80
80
115
115
tF
Fall time HV OUT
VDD2 = 5 V, 16 Ω to GND,
90 % to 10 % VDD2
,
225
ns
TJ = -40 °C to 150 °C
VDD2 = 3 V,
TJ = -40 °C to 150 °C
--
--
--
337
75
--
--
ns
ns
Dead band time of
HV_GPOx_HD in Pre-
driver mode (not for Driv-
er mode)
(Break before making
For Full Bridge and Half
Bridge mode)
VDD2 = 5 V,
TJ = -40 °C to 150 °C
tDEAD
VDD2 = 13.2 V,
TJ = -40 °C to 150 °C
91
--
;
ns
Dead band time, gener-
ated by PWM block
PWM_tDEAD
Configured in PWM block
0; 1·Tclk; 2·Tclk; 3·Tclk
Clktime
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GreenPAK Programmable Mixed-Signal Matrix with High
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Table 13: HV Output Electrical Characteristic (Full Bridge or Half Bridge Modes)(Continued)
Parameter
Description
Condition
Min
Typ
Max
Unit
VDD2 = 13.2 V, Io = 500 mA,
TJ = 25 ºC
--
170
--
mΩ
VDD2 = 13.2 V, Io = 500 mA,
TJ = 150 ºC
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
170
--
295
--
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
VDD2 = 9.0 V, Io = 500 mA,
TJ = 25ºC
VDD2 = 9.0 V, Io = 500 mA,
TJ = 150 ºC
HS FET on resistance
(SENSE_A, SENSE_B,
GND_HV and GND Pins
are connected together)
295
--
VDD2 = 5.0 V, Io = 500 mA,
TJ = 25 ºC
176
--
VDD2 = 5.0 V, Io = 500 mA,
TJ = 150ºC
304
--
VDD2 = 3.0 V, Io = 500 mA,
TJ = 25ºC
255
--
VDD2 = 3.0 V, Io = 500 mA,
TJ = 150ºC
426
--
RDS(ON)
VDD2 = 13.2 V, Io = 500 mA,
TJ = 25ºC
182
--
VDD2 = 13.2 V, Io = 500 mA,
TJ = 150ºC
332
--
VDD2 = 9.0 V, Io = 500 mA,
TJ = 25ºC
182
--
VDD2 = 9.0 V, Io = 500 mA,
TJ = 150ºC
LS FET on resistance
(SENSE_A, SENSE_B,
332
--
GND_HV and GND Pins VDD2 = 5.0 V, Io = 500 mA,
185
--
are connected together)
TJ = 25ºC
VDD2 = 5.0 V, Io = 500 mA,
TJ = 150ºC
338
--
VDD2 = 3.0 V, Io = 500 mA,
TJ = 25ºC
232
--
VDD2 = 3.0 V, Io = 500 mA,
TJ = 150ºC
414
GPO0_HD, GPO1_HD (Note 1),
VDD2 = 5.0 V,
23.2
23.2
--
--
--
--
--
32.9
35.2
0.2
µA
µA
µA
µA
TJ = -40 °C to 85 °C,
Sleep Mode
GPO0_HD, GPO1_HD (Note 1),
VDD2 = 5.0 V,
TJ = -40 °C to 150 °C,
Sleep Mode
IOFF
Off-state leakage current
GPO2_HD, GPO3_HD,
VDD2 = 5.0 V,
TJ = -40 °C to 85 °C,
Sleep Mode
GPO2_HD, GPO3_HD,
VDD2 = 5.0 V,
TJ = -40 °C to 150 °C,
--
1.5
Sleep Mode
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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Table 13: HV Output Electrical Characteristic (Full Bridge or Half Bridge Modes)(Continued)
Parameter
Description
Condition
Min
Typ
Max
Unit
VDD2 = 5.0 V,
TJ = -40 °C to 150 °C,
Static (PWM is off), including the
charge pump OSC
--
--
250
µA
SingleHVDriverCurrent
Consumption (including
support circuits),
VDD2 = 5.0 V,
without output load
--
344
625
µA
TJ = -40 °C to 150 °C,
IDD2
Switching (PWM = 250 kHz)
All HV Drivers On
Current Consumption
(including support cir-
cuits), without output
load
VDD2 = 5.0 V,
TJ = -40 °C to 150 °C,
Static (PWM is off), including the
charge pump OSC
100
--
--
800
134
µA
µs
HV SLEEP OUT high to output
transition, BG is always on,
Another pins SLEEP - disable
tWAKE
Wake-up time
82.3
Note 1 There is a resistive voltage divider in front of Diff Amplifier that is connected to GPO0_HD and GPO1_HD.
Table 14: HV Output Electrical Characteristic (Pre-driver Mode)
Parameter
Description
Conditions
Min
Typ
Max
Unit
VDD2 = 5 V, 16 Ω to GND,
10 % to 90 % VDD2
TJ = -40 °C to 85 °C
,
10
13
21
ns
tR
Rise time HV OUT
VDD2 = 5 V, 16 Ω to GND,
10 % to 90 % VDD2
TJ = -40 °C to 150 °C
,
10
8
13
11
11
22
23
25
ns
ns
ns
VDD2 = 5 V, 16 Ω to GND,
10 % to 90 % VDD2
,
TJ = -40 °C to 85 °C
tF
Fall time HV OUT
VDD2 = 5 V, 16 Ω to GND,
10 % to 90 % VDD2
,
8
TJ = -40 °C to 150°C
VDD2 = 3 V,
TJ = -40 °C to 150 °C
--
--
--
55
23
22
--
--
ns
ns
ns
Dead band time of
HV_GPOx_HD in Pre-
driver mode (not for Driv-
er mode)
(Break before making
For Full Bridge and Half
Bridge mode)
VDD2 = 5 V,
TJ = -40 °C to 150 °C
tDEAD
VDD2 = 13.2 V,
TJ = -40 °C to 150 °C
--
;
Clk
time
PWM_tDEAD
PWM dead band time
Configured in PWM block
0; 1·Tclk; 2·Tclk; 3·Tclk
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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Table 14: HV Output Electrical Characteristic (Pre-driver Mode) (Continued)
Parameter
Description
Conditions
Min
Typ
Max
Unit
VDD2 = 13.2 V, Io = 500 mA,
TJ = 25 ºC
--
171
--
mΩ
VDD2 = 13.2 V, Io = 500 mA,
TJ = 150 ºC
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
171
--
295
--
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
VDD2 = 9.0 V, Io = 500 mA,
TJ = 25 ºC
VDD2 = 9.0 V, Io = 500 mA,
TJ = 150 ºC
HS FET on resistance
(SENSE_A, SENSE_B,
295
--
GND_HV and GND Pins VDD2 = 5.0 V, Io = 500 mA,
177
--
are connected together)
TJ = 25 ºC
VDD2 = 5.0 V, Io = 500 mA,
TJ = 150 ºC
305
--
VDD2 = 3.0 V, Io = 500 mA,
TJ = 25 ºC
256
--
VDD2 = 3.0 V, Io = 500 mA,
TJ = 150 ºC
426
--
RDS(ON)
VDD2 = 13.2 V, Io = 500 mA,
TJ = 25 ºC
182
--
VDD2 = 13.2 V, Io = 500 mA,
TJ = 150 ºC
332
--
VDD2 = 9.0 V, Io = 500 mA,
TJ = 25 ºC
182
--
VDD2 = 9.0 V, Io = 500 mA,
TJ = 150 ºC
LS FET on resistance
(SENSE_A, SENSE_B,
331
--
GND_HV and GND Pins VDD2 = 5.0 V, Io = 500 mA,
185
--
are connected together)
TJ = 25 ºC
VDD2 = 5.0 V, Io = 500 mA,
TJ = 150 ºC
338
--
VDD2 = 3.0 V, Io = 500 mA,
TJ = 25 ºC
232
--
VDD2 = 3.0 V, Io = 500 mA,
TJ = 150 ºC
414
GPO0_HD, GPO1_HD (Note 1),
VDD2 = 5.0 V,
23.2
23.2
--
--
--
--
--
32.9
35.2
0.2
µA
µA
µA
µA
TJ = -40 °C to 85 °C,
Sleep Mode
GPO0_HD, GPO1_HD (Note 1),
VDD2 = 5.0 V,
TJ = -40 °C to 150 °C,
Sleep Mode
IOFF
Off-state leakage current
GPO2_HD, GPO3_HD,
VDD2 = 5.0 V,
TJ = -40 °C to 85 °C,
Sleep Mode
GPO2_HD, GPO3_HD,
VDD2 = 5.0 V,
TJ = -40 °C to 150 °C,
--
1.5
Sleep Mode
Datasheet
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 14: HV Output Electrical Characteristic (Pre-driver Mode) (Continued)
Parameter
Description
Conditions
Min
Typ
Max
Unit
VDD2 = 5.0 V,
TJ = -40 °C to 150 °C,
PWM is off, including the charge
pump OSC
--
--
200
µA
Charge Pump consump-
tion current (from VDD1
Pin or VDD2 Pin)
IDD2
VDD2 = 5.0 V,
TJ = -40 °C to 150 °C,
PWM = 250 kHz
100
--
--
800
134
µA
µs
HV SLEEP OUT high to output
transition, BG is always on,
Another pins SLEEP - disable
tWAKE
Wake-up time
82.3
Note 1 There is a resistive voltage divider in front of Diff Amplifier that is connected to GPO0_HD and GPO1_HD.
3.9 PROTECTION CIRCUITS ELECTRICAL CHARACTERISTIC
Table 15: Protection Circuits
Parameter
Description
Conditions
Min
Typ
Max
Unit
Overcurrent protection
threshold
IOCP
Per any HS or LS FET
--
2.18
--
A
VDD = 5 V, VDD2 = 5 V,
T = 25 ºC, Deglitch = Enable,
High Side
--
--
2.497
1.232
--
--
µs
µs
tOCP1
OCP deglitch time (Note 1)
VDD = 5 V, VDD2 = 5 V,
T = 25 ºC, Deglitch = Enable,
Low Side
Delay = 492 µs
Delay = 656 µs
Delay = 824 µs
Delay = 988 µs
Delay = 1152 µs
Delay = 1316 µs
Delay = 1480 µs
Delay = 1640µs
--
--
--
--
--
--
--
--
491
655
--
--
--
--
--
--
--
--
µs
µs
µs
µs
µs
µs
µs
µs
818
982
tOCP2
OCP retry time (Note 2)
1146
1309
1473
1637
Recover from
Under-voltage lockout
At rising edge of VDD2
At falling edge of VDD2
Junction temperature TJ
--
--
--
--
2.90
2.77
159
V
V
VUVLO
(Note 3)
Under-voltage lockout
Thermal shutdown tem-
perature
TTSD
135
141
°C
Thermal shutdown hyster-
esis
THYST
--
16
--
°C
Note 1: OCP deglitch time option can be enabled by register [873] and register [875] separately for each Full Bridge. The High
Side FETs doesn't have OCP deglitch time if the current through the FET is higher than IOCP level during enable time.This is
done to avoid huge currents during retry when the short is persist on the output.
Note 2: OCP retry time can be selected separately for each HV OUT: HV GPO0 - registers[780:778], HV GPO1 -
registers[788:786], HV GPO2 - registers[796:794], HV GPO3 - registers[804:802]. For more information check the Section 7.5.3.
Note 3: UVLO Function can be enabled separately for VDD2_A by register [864] and VDD2_B by register [865]. For more
information see Section 7.5.5.
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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3.10 TIMING CHARACTERISTICS
Table 16: Typical Startup Estimated for Chip at T = 25 °C
Parameter
Description
Conditions
Min
Typ
Max
Unit
From VDD rising past
PONTHR
TSU
Chip Startup Time
--
1
2
ms
Table 17: Typical Delay Estimated for Each Macrocell at T = 25 °C
VDD = 2.5 V
VDD = 3.3 V
VDD = 5 V
Parameter Description Note
Unit
Rising Falling Rising Falling Rising Falling
25
25
tpd
tpd
Delay
Delay
16
18
12
13
ns
ns
Digital Input to PP 1x
Digital Input with Schmitt Trigger
to PP 1x
25
26
17
19
14
14
Low Voltage Digital Input to
PP 1x
25
22
tpd
Delay
247
24
17
15
157
17
13
11
83
13
ns
ns
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tw
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Width
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Digital Input to PP 2x
Digital Input to NMOS 1x
Digital Input to NMOS 2x
1x3-State Hi-Z to 0
1x3-State Hi-Z to 1
2x3-State Hi-Z to 0
2x3-State Hi-Z to 1
OE Hi-Z to 0
--
--
23
23
--
--
17
16
--
--
13
12
ns
ns
--
24
--
23
--
--
17
--
17
--
--
12
--
12
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23
--
16
--
11
--
23
--
16
--
12
--
23
--
17
--
12
--
24
22
24
72
17
19
20
24
24
18
--
17
15
15
51
11
13
13
17
18
12
--
12
10
10
35
8
OE Hi-Z to 1
24
25
71
17
19
19
24
26
18
20
--
17
17
50
12
13
12
17
15
13
14
--
11
11
34
8
DFF
LATCH
CTN/DLY
2-bit LUT
8
9
3-bit LUT
9
9
4-bit LUT
12
10
8
12
11
9
Pipe Delay nRESET OUT Q, nQ
Pipe Delay OUT0 Q, nQ
PGEN CLK
--
10
--
PGEN nRESET Zto0
PGEN nRESET Zto1
Edge detect
21
256
18
275
180
--
13
180
12
190
118
--
9
255
19
274
209
191
180
--
179
12
191
137
123
119
--
125
8
125
8
tpd
tpd
tpd
tpd
tpd
tpd
tpd
Edge detect
132
75
--
133
82
73
75
--
Edge detect Delayed
Filter nQ
Filter nQ First spark
Filter Q
209
191
--
136
123
--
81
73
--
Filter Q First spark
Inverter Filter nQ First spark
165
107
68
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 17: Typical Delay Estimated for Each Macrocell at T = 25 °C(Continued)
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
164
25
29
33
25
25
25
25
23
22
25
23
22
--
--
107
17
29
23
17
17
16
16
15
14
16
15
14
--
--
68
11
13
15
11
11
11
11
11
10
11
10
10
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Inverter Filter Q First spark
Ripple CNT CLK UP Q1
Ripple CNT CLK UP Q2
Ripple CNT CLK UP Q3
Ripple CNT CLK DOWN Q1
Ripple CNT CLK DOWN Q2
Ripple CNT CLK DOWN Q3
Ripple CNT nSET UP Q1
Ripple CNT nSET UP Q2
Ripple CNT nSET UP Q3
Ripple CNT nSET DOWN Q1
Ripple CNT nSET DOWN Q2
Ripple CNT nSET DOWN Q3
PWM CHOPPER BLANK
PWM OUT- nQ1
23
22
22
24
29
36
41
42
46
41
40
40
37
25
--
16
16
16
17
20
25
29
29
31
28
27
27
25
17
--
11
11
11
11
13
16
19
19
21
19
18
18
17
11
--
--
--
--
24
21
--
16
14
--
11
9
PWM0 OUT- Q1
--
--
--
PWM0 OUT+ nQ1
22
15
--
10
PWM0 OUT+ Q1
Table 18: Programmable Delay Expected Typical Delays and Widths at T = 25 °C
Parameter
tw
Description
Note
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V Unit
Pulse Width, 1 cell mode: (any) edge detect, edge detect output
Pulse Width, 2 cell mode: (any) edge detect, edge detect output
Pulse Width, 3 cell mode: (any) edge detect, edge detect output
Pulse Width, 4 cell mode: (any) edge detect, edge detect output
234
464
695
926
18
162
321
481
641
12
113
222
334
445
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw
tw
tw
time1
time1
time1
time1
time2
time2
time2
time2
Delay, 1 cell
Delay, 2 cell
Delay, 3 cell
Delay, 4 cell
Delay, 1 cell
Delay, 2 cell
Delay, 3 cell
Delay, 4 cell
mode: (any) edge detect, edge detect output
mode: (any) edge detect, edge detect output
mode: (any) edge detect, edge detect output
mode: (any) edge detect, edge detect output
mode: both edge delay, edge detect output
mode: both edge delay, edge detect output
mode: both edge delay, edge detect output
mode: both edge delay, edge detect output
18
12
8
18
12
8
18
12
8
249
476
704
933
173
329
488
647
120
229
339
450
Table 19: Typical Filter Rejection Pulse Width at T = 25 °C
Parameter
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
< 180 < 118 < 71
Unit
Filtered Pulse Width
ns
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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Table 20: LP_BG Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V
Parameter
Description
Conditions
Min
--
Typ
--
Max
2.5
--
Unit
ms
LP_BG Start-Up Time
LP_BG Icc
--
555
nA
3.11 COUNTER/DELAY CHARACTERISTICS
Table 21: Typical Counter/Delay Offset at T = 25 C
Parameter
OSC Freq
25 MHz
OSC Power-On VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
Unit
ns
Power-On time
auto
auto
134
496
127
443
125
398
Power-On time
2.048 kHz
25 MHz
µs
Frequency settling time
Frequency settling time
Variable (CLK period)
Variable (CLK period)
auto
850
1100
1200
900
ns
2.048 kHz
25 MHz
auto
900
950
µs
forced
forced
39-42
476-495
39-42
476-495
39-42
476-495
ns
2.048 kHz
µs
Typical Propagation Delay
(non-delayed edge)
25 MHz
either
39
26
17
ns
3.12 OSCILLATOR CHARACTERISTICS
Table 22: OSC0 Frequency Limits, VDD = 2.3 V to 5.5 V
Junction Temperature Range
-40 °C to +85 °C -40 °C to +125 °C
Min. Max. Error,
+25 °C
-40 °C to +150 °C
OSC
Min.
Value
Max.
Value
Error,
%
Min.
Max.
Error,
%
Min.
Max.
Error,
Value
Value
%
Value
Value
Value
Value
%
2.048
kHz
OSC0
+1.12
-1.61
+4.35
+4.35
-7.17
+4.35
2.015
kHz
2.071
kHz
1.901
kHz
2.137
kHz
1.901
kHz
2.137
kHz
1.720
kHz
2.137
kHz
-7.17
-16.01
Table 23: OSC1 Frequency Limits, VDD = 2.3 V to 5.5 V
Junction Temperature Range
-40 °C to +85 °C
+25 °C
-40 °C to +150 °C
Minimum Maximum
OSC
Minimum Maximum
Minimum Maximum
Error, %
Error, %
Error, %
Value
Value
Value
Value
Value
Value
+1.20
-1.56
+3.78
-3.66
+3.78
-5.76
25 MHz
OSC1
24.610
MHz
25.300
MHz
24.084
MHz
25.944
MHz
23.560
MHz
25.944
MHz
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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3.12.1 OSC Power-On Delay
Table 24: Oscillators Power-On Delay at T = 25 °C, OSC Power Setting: "Auto Power-On"
OSC1 25 MHz
Power Supply
Range
OSC0 2.048 kHz
OSC1 25 MHz
Start with Delay
Typical
Maximum
Value, µs
Typical
Maximum
Value, ns
Typical
Maximum
Value, ns
(VDD) V
Value, µs
Value, ns
Value, ns
2.30
2.50
3.30
5.00
5.50
521
660
622
539
469
452
50
44
29
18
17
59
50
34
32
31
138
148
143
137
137
137
496
134
443
127
398
125
385
125
3.13 CURRENT SENSE COMPARATOR CHARACTERISTICS
Table 25: Current Sense Comparator Specifications at T = -40 °C to +85 °C, VDD = 2.3 to 5.5 V Unless Otherwise Noted
Parameter
Description
Note
Conditions
Min
Typ
Max
Unit
Per Full Bridge
SENSE_x Pin
(LS FET only)
Current limit input
range
IFET*RSENSE
RCurrCMP
50
--
500
mV
120 mV input
504 mV input
120 mV input
504 mV input
120 mV input
504 mV input
60 mV input
252 mV input
60 mV input
252 mV input
60 mV input
252 mV input
-3.1
-0.9
-4.5
-1.2
-4.5
-1.2
-5.1
-1.6
-7.5
-2.0
-7.5
-2.2
--
--
--
--
--
--
--
--
--
--
--
--
+3.9
+1.0
+4.7
+1.2
+5.6
+1.4
+7.7
+1.8
+8.8
+2.1
+10.4
+2.5
%
%
%
%
%
%
%
%
%
%
%
%
TJ = 25 °C
TJ = -40 °C to
85 °C
Current Sense
accuracy
Iaccur
TJ = -40 °C to
150 °C
TJ = 25 °C
TJ = -40 °C to
85 °C
Current Sense
accuracy
Iaccur
TJ = -40 °C to
150 °C
Current Sense
CMP Power-
On delay
Current Sense CMP
Startup Time
tstart
TJ = -40 °C to 85 °C
--
6.7
12.1
µs
Datasheet
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 25: Current Sense Comparator Specifications at T = -40 °C to +85 °C, VDD = 2.3 to 5.5 V Unless Otherwise Noted
Parameter
Description
Note
Conditions
Min
Typ
Max
Unit
Low to High,
TJ = -40 °C to 85 °C,
Vref = 1024 mV,
Overdrive = 100 mV
--
0.5
0.9
µs
Low to High,
TJ = -40 °C to 85 °C,
Vref = 1024 mV,
Overdrive = 10 mV
--
--
--
--
--
--
--
--
--
--
0.9
0.5
1
2.5
1.0
3.7
0.9
5.6
1.0
7.0
0.9
2.6
1.0
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Low to High,
TJ = -40 °C to 85 °C,
Vref = 480 mV to 2016 mV,
Overdrive = 100 mV
Low to High,
TJ = -40 °C to 85 °C,
Vref = 480 mV to 2016 mV,
Overdrive = 10 mV
High to Low,
TJ = -40 °C to 85 °C,
Vref = 1024 mV,
Overdrive = 100 mV
0.6
1.8
0.6
1.8
0.5
1.0
0.6
High to Low,
Propagation Delay,
Response Time
TJ = -40 °C to 85 °C,
Vref = 1024 mV,
Overdrive = 10 mV
PROP
High to Low,
TJ = -40 °C to 85 °C,
Vref = 480 mV to 2016 mV,
Overdrive = 100 mV
High to Low,
TJ = -40 °C to 85 °C,
Vref = 480 mV to 2016 mV,
Overdrive = 10 mV
Low to High,
TJ = -40 °C to 150 °C,
Vref = 1024 mV,
Overdrive = 100 mV
Low to High,
TJ = -40 °C to 150 °C,
Vref = 1024 mV,
Overdrive = 10 mV
Low to High,
TJ = -40 °C to 150 °C,
Vref = 480 mV to 2016 mV,
Overdrive = 100 mV
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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Table 25: Current Sense Comparator Specifications at T = -40 °C to +85 °C, VDD = 2.3 to 5.5 V Unless Otherwise Noted
Parameter
Description
Note
Conditions
Min
Typ
Max
Unit
Low to High,
TJ = -40 °C to 150 °C,
Vref = 480 mV to 2016 mV,
Overdrive = 10 mV
--
1.0
3.7
µs
High to Low,
TJ = -40 °C to 150 °C,
Vref = 1024 mV,
Overdrive = 100 mV
--
--
--
--
0.6
1.9
0.6
1.9
1.0
5.6
1.1
7.9
µs
µs
µs
µs
High to Low,
Propagation Delay,
Response Time
TJ = -40 °C to 150 °C,
Vref = 1024 mV,
Overdrive = 10 mV
PROP
High to Low,
TJ = -40 °C to 150 °C,
Vref = 480 mV to 2016 mV,
Overdrive = 100 mV
High to Low,
TJ = -40 °C to 150 °C,
Vref = 480 mV to 2016 mV,
Overdrive = 10 mV
3.14 DIFFERENTIAL AMPLIFIER WITH INTEGRATOR AND COMPARATOR CHARACTERISTICS
Table 26: Differential Amplifier Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Parameter
Description
Conditions
Min
Typ
Max
Unit
VDD2 = 5 V to 13.2 V, VOUT = 4.096 V,
ILoad = 0.5 A, TJ = 25 °C
--
±0.8
--
%
VDD2 = 9 V to 13.2 V, VOUT = 8.064 V,
ILoad = 0.5 A, TJ = 25 °C
--
--
--
--
--
±1.2
±0.8
±1.2
±0.8
±1.2
--
--
--
--
--
%
%
%
%
%
VDD2 = 5 V to 13.2 V, VOUT = 4.096 V,
ILoad = 0.5 A, TJ = -40 °C to 85 °C
∆VLINe
Line Regulation
VDD2 = 9 V to 13.2 V, VOUT = 8.064 V,
ILoad = 0.5 A, TJ = -40 °C to 85 °C
VDD2 = 5 V to 13.2 V, VOUT = 4.096 V,
ILoad = 0.5 A, TJ = -40 °C to 150 °C
V
DD2 = 9 V to 13.2 V, VOUT = 8.064 V,
ILoad = 0.5 A, TJ = -40 °C to 150 °C
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GreenPAK Programmable Mixed-Signal Matrix with High
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Table 26: Differential Amplifier Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Parameter
∆VLOAD
fINT
Description
Conditions
Min
Typ
Max
Unit
VDD2 = 5 V, VOUT = 4.096 V,
ILOAD = 200 mA to 500 mA,
TJ = 25 °C
--
±1.8
--
%
VDD2 = 9 V, VOUT = 4.096 V,
I
LOAD = 200 mA to 900 mA,
--
--
--
--
±2.1
±1.8
±2.1
±1.8
--
--
--
--
%
%
%
%
TJ = 25 °C
VDD2 = 5 V, VOUT = 4.096 V,
I
LOAD = 200 mA to 500 mA,
TJ = -40 °C to 85 °C
DD2 = 9 V, VOUT = 4.096 V,
Load Regulation
V
ILOAD = 200 mA to 900 mA,
TJ = -40 °C to 85 °C
VDD2 = 5 V, VOUT = 4.096 V,
ILOAD = 200 mA to 500 mA,
TJ = -40 °C to 150 °C
VDD2 = 9 V, VOUT = 4.096 V,
ILOAD = 200 mA to 900 mA,
TJ = -40 °C to 150 °C
--
±2.1
--
--
--
%
Integrated Frequency
44
kHz
3.15 ACMP CHARACTERISTICS
Table 27: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Parameter Description
Note
Condition
Min
0
Typ
--
Max
Unit
V
Positive Input
Negative Input
VDD
VDD
ACMP Input Voltage
VACMP
Range
0
--
V
ACMPxH Vhys = 0 mV,
Gain = 1,
Vref = 32 mV to 2016 mV
-8
-9.8
--
--
--
--
6.5
7.2
32
mV
mV
µs
TJ = -40 °C to 85 °C
TJ = -40 °C to 150 °C
TJ = -40 °C to 85 °C
TJ = -40 °C to 150 °C
ACMP Input Offset
(Note 2)
Voffset
ACMPxH Power-On delay,
ACMP Startup Time Minimal required wake
tstart
time for the "Wake and
SLEEP function"
--
--
32.7
µs
VHYS = 32 mV
30
62
--
--
--
--
--
35
66
mV
mV
mV
mV
mV
VHYS = 64 mV
ACMPxH
TJ = -40 °C to 85 °C
TJ = -40 °C to 150 °C
VHYS = 192 mV
187
29
197
36
Built-in Hysteresis
(Note 1) (Note 2)
VHYS
VHYS = 32 mV
VHYS = 64 mV
61
67
VHYS = 192 mV
Gain = 1x
186
--
--
10
--
198
--
mV
GΩ
MΩ
MΩ
MΩ
Gain = 0.5x
Series Input
1.7
1.7
1.7
2.4
2.4
2.4
Rsin
Resistance
Gain = 0.33x
--
Gain = 0.25x
--
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GreenPAK Programmable Mixed-Signal Matrix with High
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Table 27: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Note
Condition
Min
Typ
Max
Unit
ACMPxH, Vref =1.024 V,
Gain = 1,
Overdrive = 100 mV
Low to High,
TJ = -40 °C to 85 °C
--
0.51
1.51
µs
High to Low,
TJ = -40 °C to 85 °C
--
--
--
--
--
--
--
0.51
0.53
0.52
0.51
0.51
0.53
0.52
0.79
1.51
1.11
1.51
0.80
1.51
1.18
µs
µs
µs
µs
µs
µs
µs
Low to High,
TJ = -40 °C to 85 °C
ACMPxH, Vref =
0.032 V to 2.016 V,
Gain = 1,
High to Low,
TJ = -40 °C to 85 °C
Overdrive = 100 mV
Propagation Delay,
PROP
Response Time
Low to High,
TJ = -40 °C to 150 °C
ACMPxH, Vref =
1.024 V,
Gain = 1,
High to Low,
TJ = -40 °C to 150 °C
Overdrive = 100 mV
Low to High,
TJ = -40 °C to 150 °C
ACMPxH, Vref =
0.032 V to 2.016 V,
Gain = 1,
High to Low,
TJ = -40 °C to 150 °C
Overdrive = 100 mV
G = 1
1
1
1
G = 0.5
G = 0.33
G = 0.25
G = 1
0.487
0.320
0.244
1
0.500
0.334
0.250
1
0.519
0.346
0.260
1
TJ = -40 °C to 85 °C
Gain Error (including
threshold and
internal Vref error)
G
G = 0.5
G = 0.33
G = 0.25
0.485
0.320
0.244
0.500
0.334
0.250
0.519
0.346
0.260
TJ = -40 °C to 150 °C
TJ = 25 °C
-0.50
--
--
--
+0.50
+1.64
9.6
%
%
Internal Vref
accuracy
Vrefaccuracy
Vref ≥ 1.216 V
TJ = -40 °C to 150 °C -1.64
-17.1
Vref output buffer
offset (when
connected to the
output Pin)
mV
TJ = 25 °C
Vrefbuf_offset
Vref = 32 mV to 2016 mV
TJ = -40 °C to 150 °C -18.0
--
11.1
mV
1 MΩ
--
--
--
--
--
--
--
--
--
--
5
pF
pF
pF
pF
pF
560 kΩ
100 kΩ
10 kΩ
2 kΩ
10
Vref Output Buffer
Capacitance
Loading
40
Resistance Load in
Condition cell
CVREF
80
120
1 kΩ, Vref: 32 mV to
1024 mV
--
--
150
pF
Note 1 VIL = Vin - VHYS, VIH = Vin.
Note 2 ESD resistor should be taken into consideration when using pull-up/pull-down resistors. It may affect VIH and VIL. See
sections 6.6 to 6.9.
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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3.16 ANALOG TEMPERATURE SENSOR CHARACTERISTICS
Table 28: TS Output vs Temperature (Output Range 1)
VDD = 2.5 V
Typical, mV
VDD = 3.3 V
Typical, mV
VDD = 4.5 V to 5.5 V
Typical, mV
T, °C
Accuracy, %
±1.7
±1.5
±1.4
±1.2
±1.2
±1.1
±1.3
±1.3
±1.4
±1.5
±1.6
±1.6
±1.7
±1.7
±1.7
±1.7
±1.7
±1.7
±1.7
±1.6
±1.6
±1.6
±2.0
Accuracy, %
±1.7
±1.5
±1.4
±1.2
±1.2
±1.1
±1.2
±1.2
±1.3
±1.4
±1.5
±1.5
±1.6
±1.6
±1.6
±1.6
±1.6
±1.6
±1.6
±1.5
±1.6
±1.6
±2.0
Accuracy, %
±1.6
±1.5
±1.3
±1.2
±1.1
±1.1
±1.2
±1.2
±1.3
±1.4
±1.5
±1.6
±1.6
±1.7
±1.6
±1.7
±1.7
±1.7
±1.6
±1.6
±1.6
±1.5
±1.9
-40
-30
-20
-10
0
998.9
976.9
954.3
931.7
908.9
908.9
862.9
851.0
839.4
816.2
792.8
769.1
745.1
721.1
708.8
696.8
672.4
648.0
623.5
611.0
598.5
573.5
549.1
998.8
976.8
954.2
931.6
908.7
885.7
862.8
850.9
839.3
816.1
792.6
768.9
744.9
721.0
708.7
696.6
672.3
647.9
623.3
610.8
598.3
573.4
548.9
998.9
976.9
954.4
931.8
909.0
886.0
863.0
851.2
839.6
816.4
793.0
769.3
745.3
721.4
709.1
697.1
672.8
648.4
623.9
611.4
598.9
574.0
549.6
10
20
25
30
40
50
60
70
80
85
90
100
110
120
125
130
140
150
Table 29: TS Output vs Temperature (Output Range 2)
VDD = 2.5 V
T, °C
VDD = 3.3 V
VDD = 5 V
Typical, mV
1206.1
1179.5
1152.2
1124.9
1097.3
1069.6
1041.8
1027.5
1013.5
985.4
Accuracy, %
±1.7
Typical, mV
1205.9
1179.3
1152.1
1124.7
1097.2
1069.4
1041.6
1027.3
1013.3
985.2
Accuracy, %
±1.7
Typical, mV
1206.0
1179.5
1152.2
1124.9
1097.4
1069.7
1041.9
1027.7
1027.7
985.6
Accuracy, %
±1.6
-40
-30
-20
-10
0
±1.5
±1.5
±1.5
±1.4
±1.4
±1.3
±1.2
±1.2
±1.2
±1.2
±1.1
±1.1
10
20
25
30
40
50
60
70
±1.1
±1.1
±1.1
±1.2
±1.2
±1.2
±1.3
±1.2
±1.2
±1.3
±1.3
±1.3
±1.5
±1.4
±1.4
957.1
±1.5
956.9
±1.5
957.3
±1.5
928.5
±1.6
928.3
±1.5
928.7
±1.6
899.5
±1.6
899.3
±1.6
899.7
±1.6
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 29: TS Output vs Temperature (Output Range 2)(Continued)
VDD = 2.5 V
VDD = 3.3 V
VDD = 5 V
T, °C
Typical, mV
Accuracy, %
±1.7
Typical, mV
Accuracy, %
±1.6
Typical, mV
Accuracy, %
±1.6
80
85
870.6
855.7
841.2
811.8
782.3
752.7
737.6
722.5
692.5
663.0
870.4
855.6
841.0
811.7
782.1
752.5
737.5
722.3
692.3
662.8
870.9
856.1
841.5
812.2
782.7
753.2
738.1
723.0
693.0
663.5
±1.7
±1.6
±1.6
90
±1.7
±1.6
±1.7
100
110
120
125
130
140
150
±1.7
±1.6
±1.7
±1.7
±1.6
±1.7
±1.7
±1.6
±1.7
±1.6
±1.5
±1.6
±1.6
±1.5
±1.6
±1.5
±1.5
±1.5
±1.9
±1.9
±1.8
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SLG47105
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4
User Programmability
The SLG47105 is a user programmable device with one time programmable (OTP) memory elements that are able to configure
the connection matrix and macrocells. A programming development kit allows the user the ability to create initial devices. Once
the design is finalized, the programming code (.hvp file) is forwarded to Dialog Semiconductor to integrate into a production
process.
Product
Definition
E-mail Product Idea, Definition, Drawing or
Customer creates their own design in
Schematic to
GreenPAK Designer
CMBUGreenPAK@diasemi.com
Dialog Semiconductor Applications
Engineer will review design specifications
with customer
Customer verifies GreenPAK in system
design
GreenPAK Design
approved
Samples, Design and Characterization
Report send to customer
GreenPAK Design
approved
Customers verifies GreenPAK design
GreenPAK Design
approved in system test
Custom GreenPAK part enters production
Figure 2: Steps to Create a Custom GreenPAK Device
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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5
System Overview
5.1 GPIO PINS
Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
NMOS Open-Drain Outputs
Push-Pull Outputs
Analog IO
10 kΩ/100 kΩ/1 MΩ Pull-up/Pull-down resistors
GPIO with OE can be configured as bidirectional IO or three-state output
5.2 HIGH VOLTAGE OUTPUT PINS
High voltage digital output in Push-Pull, Open-Drain configurations or Full Bridge logic
Build-in Overcurrent and Short Circuit protection
Configurable Dead Band Time
Sleep mode to save energy
Advanced Voltage Control and Current Control
5.3 CONNECTION MATRIX
Digital matrix for circuit connections based on user design
5.4 TWO CURRENT SENSE COMPARATORS
SENSE_x pin that is connected to a positive input of Sense Comparator for Advanced Current Control
Separate Selectable Vref: 6-bit selection
Static or Dynamic Vref selection
Configurable Gain: 4x or 8x
5.5 DIFFERENTIAL AMPLIFIER WITH INTEGRATOR AND COMPARATOR
Low Quiescent Current
Provide constant motor speed for variable VDD2
Connected to HV GPO0 and HV GPO1
5.6 TWO GENERAL PURPOSE ANALOG COMPARATORS
Wide Vref Selector: 32 mV to 2016 mV, with 32 mV step
Selectable hysteresis: 2-bit selection
Configurable Gain (resistor divider) 1x; 0.5x; 0.33x; 0.25x
Different input sources: PINs, VDD or Temp sense
5.7 VOLTAGE REFERENCE
Used for references on Analog Comparators
Can be driven to external pin
5.8 TWELVE COMBINATION FUNCTION MACROCELLS
Three Selectable DFF/LATCH or 2-bit LUTs
One Selectable Programmable Pattern Generator or 2-bit LUT
Six Selectable DFF/LATCH with Set/Reset input or 3-bit LUTs
One Selectable Pipe Delay or Ripple Counter or 3-bit LUT
One Selectable DFF/LATCH with Set/Reset input or 4-bit LUT
5.9 FIVE MULTI-FUNCTION MACROCELLS
Four Selectable DFF/LATCH/3-bit LUTs + 8-bit Delay/Counters
One Selectable DFF/LATCH/4-bit LUT + 16-bit Delay/Counter
5.10 TWO PWM MACROCELLS
Flexible 8-bit or 7-bit PWM mode with the Duty Cycle control
True 0 % and 100 % Duty Cycle
Regular or 16 Preset Registers mode
Autostop mode
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GreenPAK Programmable Mixed-Signal Matrix with High
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Phase correct mode
Selectable separate Dead Band Time
Glitch Safety
5.11 SERIAL COMMUNICATION
I2C Interface
5.12 PROGRAMMABLE DELAY
125 ns/250 ns/375 ns/500 ns @ 3.3 V
Includes Edge Detection function
5.13 ADDITIONAL LOGIC FUNCTION
One Deglitch filter macrocell
Includes Edge Detection function
5.14 TWO OSCILLATORS
2.048 kHz
25 MHz
5.15 DUAL VDD
General Power Supply VDD in range 2.5 V to 5.0 V
Second Power Supply VDD2 in range 3.3 V to 12.0 V (Note )
Two GPIOs groups: VDD GPIOs Group, VDD2 GPOs Group
Note VDD2_A Pin should be used necessarily if VDD2 is used. Using VDD2_B without using VDD2_A is unacceptable, because
internal high voltage circuit part is supplied by VDD2_A Pin. Therefore, HV_GPO0_HD and HV_GPO1_HD should be used firstly.
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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6
Input/Output Pins
6.1 GPIO PINS
The SLG47105 has a total of 7 GPIO, 1 GPI, and 4 HV GPO Pins, which can function as either a user-defined Input or Output,
as well as serving as a special function (such as outputting the voltage reference).
6.2 GPI PIN
GPI serves as General Purpose Input Pin of VDD Group.
6.3 HV GPO PINS
HV GPO0, HV GPO1, HV GPO2, HV GPO3 serve as High Voltage General Purpose Output Pins of VDD2 Group.
6.4 PULL-UP/DOWN RESISTORS
All IO Pins of VDD Group have the option for user selectable resistors connected to the input structure. The selectable values on
these resistors are 10 kΩ, 100 kΩ, and 1 MΩ. The internal resistors can be configured as either Pull-up or Pull-downs.
6.5 FAST PULL-UP/DOWN DURING POWER-UP
During power-up, IO Pull-up/down resistance will switch to 2.6 kΩ initially and then it will switch to the normal setting value. This
function is enabled by register [754].
6.6 ESD PROTECTION
Every pin has the ESD protection circuit built-in, see Figure 3, Figure 4, Figure 5. In addition to the ESD diodes, when
configured as inputs, all pins have a series resistor which decreases the exceeding input current to a safe level. For the value of
the resistors refer to Table 30. It should be noted, this additional input resistance will affect the input thresholds (VIH and VIL)
when using pull-up/pull-down resistors.
Table 30: ESD Resistors Value
Pin
Value, Ohm
200
GPIO0
GPI
200
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
1060
200
200
1060
1060
1060
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6.7 GPI IO STRUCTURE (FOR VDD GROUP)
6.7.1 GPI IO Structure
Non-Schmitt
Trigger Input
WOSMT_EN
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1
01: Digital In with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital In mode, lv_en = 1
11: Analog IO mode
Schmitt
Trigger Input
Digital IN
Note 1: Can be varied over PVT, for reference only.
Note 2: Should be taken into consideration when using pull-up/pull-down resistors.
SMT_EN
May affect VIH and VIL
.
Low Voltage
Input
LV_EN
Analog IO
Floating
s0
s1
s2
s3
VDD
s1
s0
200 Ω
(Note 1, 2)
900 kΩ
90 kΩ
10 kΩ
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
PAD
Figure 3: GPI Structure Diagram
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GreenPAK Programmable Mixed-Signal Matrix with High
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6.8 I2C MODE IO STRUCTURE (FOR VDD GROUP)
6.8.1 I2C Mode IO Structure (for SCL/GPIO2 and SDA/GPIO3, Register OE)
Input Mode [1:0]
00: Digital Input without Schmitt Trigger, WOSMT_EN = 1
01: Digital Input with Schmitt Trigger, SMT_EN = 1
10: Low Voltage, Digital Input, LV_EN = 1
11: Reserved
Non-Schmitt
Trigger Input
Note 1: It is possible to apply an input voltage higher than VDD to GPIO2 and
GPIO3. However, this voltage should not exceed 5.5 V.
Note 2: GPIO2 and GPIO3 don‘t support Push-Pull and PMOS Open-Drain
modes.
WOSMT_EN
SMT_EN
Note 3: When an internal Pull-up/down is used, the input voltage can‘t be higher
than VDD
.
Schmitt
Trigger Input
Note 4: OE goes HIGH only when I2C_EN signal = 0 and register [831] = 1
(for GPIO2)/register[837] = 1 (for GPIO3).
Digital IN
Note 5: When OE is HIGH, Input Mode[1:0] = 11 must be selected.
Note 6: When I2C_EN signal = 1, fast+ mode (3.2x OD for SDA) can be select-
ed by register [830] = 0 and standard/fast mode (0.8x OD for SDA) can be se-
lected by register [830] = 1.
Low Voltage
Input
Note 7: When OE is HIGH, only OD 3.2x option is active.
Note 8: When I2C_EN signal = 1, internal Pull-Up/Down Resistors would be al-
ways floating.
LV_EN
Note 9: Can be varied over PVT, for reference only.
Note 10: Should be taken into consideration when using pull-up/pull-down re-
sistors. May affect VIH and VIL
.
Floating
s0
VDD
s1
s2
s3
s1
s0
900 kΩ
90 kΩ
10 kΩ
200 Ω
(Note 9, 10)
I2C_EN
Pull-up_EN
I2C_EN
OE
s1
s0
Res_sel [1:0]
register [831] for GPIO2 and
register [837] for GPIO3
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
OD 0.8x
Digital OUT
OE
I2C_EN
s1
s0
register [830]
OD 2.4x
I2C_EN
I2C Digital OUT
I2C_EN
OD 0.8x
PAD
Figure 4: GPIO with I2C Mode Structure Diagram
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GreenPAK Programmable Mixed-Signal Matrix with High
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Table 31: GPIO2 Mode Selection
Register [2032]
Register [831]
Register [830]
GPIO2 Mode
I2C SCL
0
1
1
x
0
1
x
x
x
GPI, depends on registers [826:825]
GPO, 3.4x OD only
Table 32: GPIO3 Mode Selection
Register [2032]
Register [837]
Register [830]
GPIO3 Mode
I2C SDA, fast+
I2C SDA, standard/fast
GPI, depends on registers [833:832]
GPO, 3.4x OD only
0
0
1
1
x
x
0
1
0
1
x
x
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GreenPAK Programmable Mixed-Signal Matrix with High
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6.9 MATRIX OE IO STRUCTURE (FOR VDD GROUP)
6.9.1 Matrix OE IO Structure (for GPIOs 0, 1, 4, 5, 6)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, WOSMT_EN = 1, OE = 0
01: Digital In with Schmitt Trigger, SMT_EN = 1, OE = 0
10: Low Voltage Digital In mode, LV_EN = 1, OE = 0
WOSMT_EN
OE
OE
11: Analog IO mode
Schmitt
Trigger Input
Output Mode [1:0]
00: Push-Pull 1x mode, PP1x_EN = 1, OE = 1
01: Push-Pull 2x mode, PP2x_EN = 1, PP1x_EN = 1, OE = 1
10: NMOS 1x Open-DRAIN mode, OD1x_EN = 1, OE = 1
11: NMOS 2x Open-DRAIN mode, OD2x_EN = 1, OD1x_EN = 1, OE = 1
Digital IN
SMT_EN
Low Voltage
Input
Note 1: Digital OUT and OE are Matrix Output, Digital In is Matrix Input.
Note 2: Can be variated over PTV, for reference only.
Note 3: Should be taken into consideration when using pull-up/pull-down
resistors. May affect VIH and VIL
Note 4: 200 Ohm for GPIO0, 1060 Ohm for GPIOs 1, 4, 5, and 6.
.
LV_EN
OE
Analog IO
Floating
s0
s1
s2
s3
VDD
s1
s0
(Note 2, 3, 4)
900 kΩ
90 kΩ
10 kΩ
VDD
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
Digital OUT
Digital OUT
OE
OE
OD1x_EN
PP1x_EN
VDD
PAD
VDD
Digital OUT
Digital OUT
OE
OE
OD2x_EN
PP2x_EN
Figure 5: GPIO Matrix OE IO Structure Diagram
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GreenPAK Programmable Mixed-Signal Matrix with High
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6.10 GPO MATRIX OE STRUCTURE (FOR VDD2 GROUP)
Using SLEEP mode to minimize supply current should be sufficient under normal operation.
Outputs HV GPO0, HV GPO1, HV GPO2, HV GPO3 have individual HV_SLEEP Input signal. If Sleep Input is active, Charge
Pumps are disabled, and Full Bridge FETs are set to Hi-Z state.
6.10.1 GPO with Matrix OE Structure (for HV GPOs 0 and 1)
Output Mode registers [777:776] for HV_GPO_0, registers [785:784] for HV_GPO_1:
00: Hi-Z mode (High Impedance)
01: NMOS 1x LOW SIDE Open-DRAIN mode (Open-DRAIN LOW side On)
10: NMOS 1x HIGH SIDE Open-DRAIN mode (Open-DRAIN HIGH side On)
11: Push-Pull 1x mode (Open-DRAIN HIGH and LOW sides On)
HV GPO SLEEP
VDD2_A
Charge Pump
Open-DRAIN HIGH side
register [777] for HV_GPO0
register [785] for HV_GPO1
Level Shifter
PAD
Open-DRAIN LOW side
Digital OUT
register [776] for HV_GPO0
from matrix
register [784] for HV_GPO1
OE
current_sense_a
SENSE_A
GND
GND_HV
GND_HV
GND_HV
Figure 6: HV GPO Matrix OE IO Structure Diagram (for HV GPOs 0 and 1)
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GreenPAK Programmable Mixed-Signal Matrix with High
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6.10.2 GPO with Matrix OE Structure (for HV GPOs 2 and 3)
Output Mode registers [793:792] for HV_GPO_2, registers [801:800] for HV_GPO_3:
00: Hi-Z mode (High Impedance)
01: NMOS 1x LOW SIDE Open-DRAIN mode (Open-DRAIN LOW side On)
10: NMOS 1x HIGH SIDE Open-DRAIN mode (Open-DRAIN HIGH side On)
11: Push-Pull 1x mode (Open-DRAIN HIGH and LOW sides On)
HV GPO SLEEP
VDD2_B
Charge Pump
Open-DRAIN HIGH side
register [793] for HV_GPO2
register [801] for HV_GPO3
Level Shifter
PAD
Open-DRAIN LOW side
register [792] for HV_GPO2
register [800] for HV_GPO3
Digital OUT
from matrix
OE
current_sense_b
SENSE_B
GND
GND_HV
GND_HV
GND_HV
Figure 7: HV GPO Matrix OE IO Structure Diagram (for HV GPOs 2 and 3)
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GreenPAK Programmable Mixed-Signal Matrix with High
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6.11 IO TYPICAL PERFORMANCE
Figure 8: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C
80
70
60
50
40
30
20
10
0
Open Drain 1x @ VDD = 5 V
Open Drain 1x @ VDD = 3.3 V
Open Drain 1x @ VDD = 2.5 V
Push-Pull 1x @ VDD = 5 V
Push-Pull 1x @ VDD = 3.3 V
Push-Pull 1x @ VDD = 2.5 V
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
VOL (V)
Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range
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GreenPAK Programmable Mixed-Signal Matrix with High
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30
Open Drain 1x @ VDD = 5 V
25
Open Drain 1x @ VDD = 3.3 V
Open Drain 1x @ VDD = 2.5 V
Push-Pull 1x @ VDD = 5 V
20
15
10
5
Push-Pull 1x @ VDD = 3.3 V
Push-Pull 1x @ VDD = 2.5 V
0
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C
160
Open Drain 2x @ VDD = 5 V
Open Drain 2x @ VDD = 3.3 V
Open Drain 2x @ VDD = 2.5 V
Push-Pull 2x @ VDD = 5 V
Push-Pull 2x @ VDD = 3.3 V
Push-Pull 2x @ VDD = 2.5 V
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
VOL (V)
Figure 11: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range
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GreenPAK Programmable Mixed-Signal Matrix with High
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50
45
Open Drain 2x @ VDD = 5 V
Open Drain 2x @ VDD = 3.3 V
40
Open Drain 2x @ VDD = 2.5 V
Push-Pull 2x @ VDD = 5 V
35
Push-Pull 2x @ VDD = 3.3 V
Push-Pull 2x @ VDD = 2.5 V
30
25
20
15
10
5
0
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
Figure 12: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C
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GreenPAK Programmable Mixed-Signal Matrix with High
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7
High Voltage Output Modes
The device integrates four High Drive Half bridges, PWM voltage regulation method, current regulation circuitry, and protection
circuits, including dead band circuit.
HV GPOs work as power pins, so if two bridges open simultaneously for any reason, for example, timing desynchronization, it
will result in cross-conduction (shoot-through) between the two bridges and damage the chip. To avoid this, tDEAD is entered
between switching on upper and lower power transistors. During output state transition from LOW to HIGH, the lower NMOS
turns off and only after tDEAD the upper NMOS turns on. While tDEAD the pin is in Hi-Z state. The same process is applied when
transiting from HIGH to LOW. tDEAD is different for DRIVER and PREDRIVER modes.
The user can select Modes of HV Outputs:
Full Bridge Mode;
Half Bridge Mode;
Pre-Driver Mode.
PWM Voltage regulation is useful for designs where there is a need to maintain constant motor speed with changeable power
supply level. When the High VDD2 is decreasing (battery discharging), it's possible to increase PWM duty cycle, and when the
High VDD2 is increasing (battery charging) it's possible to decrease PWM duty cycle. It's possible to turn off the PWM and HV
GPO for battery saving when the motor is idle, and others.
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GreenPAK Programmable Mixed-Signal Matrix with High
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Pre-Driver Mode
register [781]
From HV GPO0 Sleep
Connection Matrix Output [23]
to integrator_switch_input
TSD
HVDD
OCP
from HV GPO0 OE
Connection Matrix
Output[13]
0
1
CHARGE
PUMP
HV_GPO0_HD
OE1
from HV GPO0 Output
Connection Matrix
Output[12]
PIN LOGIC
IN1/EN
0
1
Decay
Mode IN
OCP
OUT1
Fault_1A
TSD
Stepper
Motor
DCM
HVDD
OCP
FULL BRIDGE
LOGIC
0
1
register [874]
Full Bridge Logic Mode: IN-IN/PH-EN
CHARGE
PUMP
OUT2
PIN LOGIC
0
1
HV_GPO1_HD
SENSE_A
IN2/PH
OE2
from HV GPO1 Output
Connection Matrix Output[14]
OCP
Fault_2A
from HV GPO1 OE
Connection Matrix Output[15]
register [782]
Full Bridge Mode
current_sense_a
to Fault_A Connection Matrix Input [50]
from HV GPO1 Sleep
Connection Matrix Output[24]
TSD
Pre-Driver Mode
register [797]
From HV GPO2 Sleep
Connection Matrix Output [25]
TSD
HVDD
OCP
from HV GPO2 OE
Connection Matrix Output[17]
0
1
CHARGE
PUMP
HV_GPO2_HD
OE1
PIN LOGIC
IN1/EN
from HV GPO2 Output
Connection Matrix Output[16]
0
1
Decay
Mode IN
OCP
OUT1
Fault_1B
TSD
DCM
HVDD
OCP
FULL BRIDGE
LOGIC
0
1
register [876]
Full Bridge Logic
Mode: IN-IN/PH-EN
CHARGE
PUMP
OUT2
PIN LOGIC
0
1
HV_GPO3_HD
SENSE_B
IN2/PH
OE2
from HV GPO3 Output
Connection Matrix Output[18]
OCP
Fault_2B
from HV GPO3 OE
Connection Matrix Output[19]
register [798]
Full Bridge Mode
current_sense_b
to Fault_B Connection Matrix Input [51]
from HV GPO3 Sleep
Connection Matrix Output[26]
Figure 13: HV OUT Block Diagram
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GreenPAK Programmable Mixed-Signal Matrix with High
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7.1 FULL BRIDGE MODE
Full Bridge mode is selected by setting register [782] and register [798] to 1 for HV_GPO0/HV_GPO1 and HV_GPO2/HV_GPO3
respectively. In this mode, HV GPO0 functions in couple with HV GPO1 and HV GPO2 functions in couple with HV GPO3. This
mode is useful for driving up to two DC motors with the ability to change the motors rotation direction. Also, this mode can be
used to drive one Stepper Motor as shown in Figure 14.
HV_GPO0_HD
HV_GPO0_HD
Stepper
HV_GPO1_HD
Motor
HV_GPO2_HD
HV_GPO1_HD
HV_GPO3_HD
Figure 14: Full Bridge Mode Operation
OE inputs of high voltage pins aren't used in Full-Bridge mode except HV GPO0 OE input and HV GPO2 OE input in PH-EN
sub-mode, where these inputs are used to select Decay Mode for each of Full Bridges.
Note : All 4 Sleep pins in this mode are active separately.
Other inputs and outputs operate depending on Control_Sel register [874] and register [876] for HV_GPO0/HV_GPO1 and
HV_GPO2/HV_GPO3 respectively as shown in Table 33 to Table 36.
Table 33: HV OUT CTRL0 Full Bridge Logic for IN-IN Mode
HV_GPO0_HD
(Pin 7)
HV_GPO1_HD
(Pin 8)
Sleep_x
IN0
IN1
Function
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
Hi-Z
Hi-Z
L
Hi-Z
Hi-Z
H
Off (Coast)
Coast
Reverse
Forward
Brake
H
L
L
L
Table 34: HV OUT CTRL1 Full Bridge Logic for IN-IN Mode
HV_GPO2_HD
(Pin 9)
HV_GPO3_HD
(Pin 10)
Sleep_x
IN0
IN1
Function
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
Hi-Z
Hi-Z
L
Hi-Z
Hi-Z
H
Off (Coast)
Coast
Reverse
Forward
Brake
H
L
L
L
Note 1 Sleep 0 and Sleep 1 should be connected together in Full Bridge Mode for each HV OUT CTRL block
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GreenPAK Programmable Mixed-Signal Matrix with High
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.
Table 35: HV OUT CTRL0 Full Bridge Logic for PH-EN Mode
HV_GPO0_HD HV_GPO1_HD
Sleep_x
Decay
EN
PH
Function
(Pin 7)
Hi-Z
Hi-Z
L
(Pin 8)
Hi-Z
Hi-Z
L
1
0
0
0
0
X
X
0
0
1
1
X
X
X
0
Off (Coast)
Coast
0 (Fast Decay)
1 (Slow Decay)
Brake
X
X
H
L
Forward
Reverse
1
L
H
.
Table 36: HV OUT CTRL1 Full Bridge Logic for PH-EN Mode
HV_GPO2_HD HV_GPO3_HD
Sleep_x
Decay
EN
PH
Function
(Pin 9)
Hi-Z
Hi-Z
L
(Pin 10)
1
0
0
0
0
X
X
0
0
1
1
X
X
X
0
Hi-Z
Hi-Z
L
Off (Coast)
Coast
0 (Fast Decay)
1 (Slow Decay)
Brake
X
X
H
L
Forward
Reverse
1
L
H
HV GPO0, HV GPO1, HV GPO2, and HV GPO3 are tri-state Pins, which can't be pulled up/down internally.
The HV GPOs can be used to control the motor speed with the help of PWM technique. Fast decay mode causes a rapid
reduction in inductive current and allows the motor to coast toward zero velocity. Slow decay mode leads to a slower reduction
in inductive current, but produces rapid deceleration.
For IN-IN mode, to drive DC motor in fast-decay mode, the PWM signal should be applied to one of IN0 or IN1 inputs, while the
other is held in the logic LOW state. To use slow-decay mode, one of IN0 or IN1 inputs should be sourced by PWM signal, while
the opposite pin is held in the logic HIGH state.
Table 37: PWM Control of Motor Speed (IN-IN Mode)
Function
IN0
PWM
1
IN1
0
Forward PWM, fast decay
Forward PWM, slow decay
Reverse PWM, fast decay
Reverse PWM, slow decay
PWM
PWM
1
0
PWM
PH-EN mode is convenient for Full Bridge control by internal PWM macrocell, because PWM signal is connected to EN input
only. In this case there is no need to use an additional MUXs. Rotation direction is changed by PH input.
Table 38: PWM Control of Motor Speed (PH-EN Mode)
Function
EN
PH
0
Decay
Forward PWM, fast decay
Reverse PWM, fast decay
Forward PWM, slow decay
Reverse PWM, slow decay
PWM
PWM
PWM
PWM
0
0
1
1
1
0
1
Figure 15 shows the current paths in a different drive and decay modes.
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GreenPAK Programmable Mixed-Signal Matrix with High
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HVDD
HVDD
HV_GPO1_HD HV_GPO0_HD
HV_GPO1_HD
HV_GPO0_HD
PWR_GND
PWR_GND
FORWARD
REVERSE
HVDD
HVDD
HV_GPO0_HD
HV_GPO1_HD HV_GPO0_HD
HV_GPO1_HD
PWR_GND
PWR_GND
SLOW DECAY
FORWARD FAST DECAY
Figure 15: Drive and Decay Modes
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7.2 HALF BRIDGE MODE
Half Bridge Mode is selected by setting register [782] and register [798] to 0 for HV_GPO0/HV_GPO1 and HV_GPO2/
HV_GPO3 respectively. This mode is the default mode for HV GPO pins. In this mode, there is a possibility to drive up to four
motors spinning in one direction.
HV_GPO0_HD
DCM
Figure 16: Half Bridge Mode Operation
In Half Bridge mode HV GPO will work as shown in Table 39 to Table 42.
Table 39: HV_GPO0_HD Half Bridge Logic
HV_GPO0_HD
Function
Sleep0
OE0
IN0
(PIN 7)
Hi-Z
Hi-Z
L
Off
1
0
0
0
X
0
1
1
X
X
0
1
Off (Coast)
Brake
Forward
H
Table 40: HV_GPO1_HD Half Bridge Logic
HV_GPO1_HD
(PIN 8)
Function
Sleep1
OE1
IN1
Off
1
0
0
0
X
0
1
1
X
X
0
1
Hi-Z
Hi-Z
L
Off (Coast)
Brake
Forward
H
Table 41: HV_GPO2_HD Half Bridge Logic
HV_GPO2_HD
(PIN 9)
Function
Sleep0
OE0
IN0
Off
1
0
0
X
0
1
X
X
0
Hi-Z
Hi-Z
L
Off (Coast)
Brake
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GreenPAK Programmable Mixed-Signal Matrix with High
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Table 41: HV_GPO2_HD Half Bridge Logic
HV_GPO2_HD
(PIN 9)
Function
Sleep0
OE0
IN0
Forward
0
1
1
H
Table 42: HV_GPO3_HD Half Bridge Logic
HV_GPO3_HD
(PIN 10)
Function
Sleep1
OE1
IN1
Off
1
0
0
0
X
0
1
1
X
X
0
1
Hi-Z
Hi-Z
L
Off (Coast)
Brake
Forward
H
Note: All 4 Sleep inputs in this mode are active separately
7.3 PRE-DRIVER MODE
This mode is activated by setting register [781] and register [797] to 1 for HV_GPO0/HV_GPO1 and HV_GPO2/HV_GPO3
respectively. The difference of this mode is that the rise time tR and fall time tF of High Drive HV GPO MOSFETs are much
smaller than in regular mode. This allows using SLG47105 as a driver for external transistors.
When this mode is active, user can configure HV GPO to work in Full Bridge or Half Bridge Modes, as well as in regular mode
(Pre-Driver Mode is disabled, registers [781] / [797] = 0).
7.4 PARALLEL CONNECTION OF HV GPO
The user can connect outputs in parallel to increase current rating. Note that this mode has no special register for activation.
To work in parallel Full Bridge Mode, the user must connect HV_GPO0_HD with HV_GPO2_HD and HV_GPO1_HD with
HV_GPO3_HD. Figure 17 shows a simplified schematic of DC motor connected to parallel Full Bridge of SLG47105.
Note that user can configure HV GPO outputs in Half Bridge Mode and connect them in parallel. In this case, user must take
care of HV GPO control to prevent short circuit.
HV_GPO0_HD
HV_GPO2_HD
DCM
HV_GPO1_HD
HV_GPO3_HD
Figure 17: Parallel Connection of HV GPOs for Full Bridge Mode
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GreenPAK Programmable Mixed-Signal Matrix with High
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7.5 PROTECTION CIRCUITS
7.5.1 General FAULT signals
The SLG47105 has five FAULT signals. Two of them are FAULT_A and FAULT_B. They are the general signals which consist of
all available FAULT signals for both VDD2_A and VDD2_B separately.
FAULT_A:
Over-current Protection OCP_A
Thermal Shutdown
Under-voltage Lockout
FAULT_B:
Over-current Protection OCP_B
Thermal Shutdown
Under-voltage Lockout
For more information on each of FAULT signals see Section 7.5.3 (Over-current Protection), Section 7.5.4 (Thermal Shutdown),
and Section 7.5.5 (Under-voltage Lockout).
7.5.2 Advanced Current Control
A current control circuit is provided to regulate the system in the event of an overcurrent condition, for example, an abnormal
mechanical load of DC motor. This circuit can be used for implementing constant current closed loop systems or for current
limitation.
The current is sensed by external sense resistors connected to SENSE_A and SENSE_B Pins. Two current comparators are
used to convert these currents to logic level. Using a current comparator with PWM block, output current can be dynamically
changed. For example, for a stepper motor for micro stepping it is possible to set 16 values for sinusoidal current limit form.
7.5.3 Over-Current Protection (OCP)
Each of FETs has an analog current limit circuit for turning off FETs when the current exceeds the threshold. When the
overcurrent (IOCP) persists for longer than the tOCP1 time, the FETs in the Half Bridge are disabled, and FAULT signal to matrix
driven high. tOCP1 time is optional. It can be enabled by register [873] for HV GPO0/1 and by register [875] for HV GPO2/3.
When this option is disabled, OCP circuit reacts immediately without deglitch time. The FETs will be disabled along tOCP2 time
when the current decreases to a normal value. tOCP2 could be changed by setting the registers (HV GPO0 - registers[780:778],
HV GPO1 - registers[788:786], HV GPO2 - registers[796:794], HV GPO3 - registers[804:802]). Overcurrent conditions are
detected for both high- and low-side FETs. There are special type of matrix input FAULTs, first one is personal matrix input [60]
for OCP_FAULT_A and another one is personal matrix input [61] for OCP_FAULT_B.
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GreenPAK Programmable Mixed-Signal Matrix with High
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Short Circuit
Short Circuit Removed
Current per
IOCP
HV OUT
t
t
t
tOCP1
Fault_X
tOCP2
HV OUTx
Hi-Z
Hi-Z
Hi-Z
ON
ON
Figure 18: Overcurrent Protection Operation
7.5.4 Thermal Shutdown (TSD) and Thermal Considerations
If the die temperature exceeds safe limits TSD, all output FETs in each Full/Half Bridge are disabled. After the die temperature
has fallen to a safe level, operation automatically resumes. Note that TSD is active only during HV GPOs are wake. When all HV
GPOs are in Power-down, TSD function is inactive. The SLG47105 has a special package optimized for better heat dissipation.
All HV output pins and central plates should be thermally connected to copper traces or pads on the PCB for better heat
dissipation. It is recommended to use thermal vias under the Ground and VDD plates for the better thermal characteristic.
TSD_FAULT signal is connected to Matrix Input [62]. TSD_FAULT signal is also present in FAULT_A and FAULT_B signals.
7.5.5 Under-Voltage Lockout (UVLO)
When the voltage on the pin VDD2 is less than the VUVLO, then the HV_GPOx outputs are disabled, Fault_A and Fault_B outputs
are driven HIGH. When the voltage rises to the minimal VDD2 voltage, then the Fault outputs is driven LOW and work is
restored.
UVLO can be enabled separately for VDD2_A and VDD2_B by register [864]/[865].
7.6 PWM VOLTAGE CONTROL
The SLG47105 provides the ability to control the voltage applied to the motor winding. This feature allows achieving constant
motor speed during supply voltage variations.
To use this function, the user needs to enable Full Bridge mode and use the integrator on first Full Bridge, which consists of
HV_GPO0_HD and HV_GPO1_HD Pins. The integrator output is connected to the positive input of separate Analog
Comparator. Also, Vref value on the negative comparator input must be selected. The integrator monitors the voltage difference
between HV_GPO0_HD and HV_GPO1_HD Pins of Full Bridge and integrates it to get an average voltage value.
The outputs of the comparator must be connected to the PWM block with or without an additional logic circuit. If the average
output voltage is lower than Vref, the duty cycle of the PWM output needs to increase; if the average output value is higher than
Vref, the duty cycle needs to decrease; when the average output value is equal to Comparator threshold, PWM duty cycle is
kept by EQUAL output.
Note that if the desired output voltage (reference of ACMP) is greater than the supply voltage, the device will operate at 100 %
duty cycle and the voltage regulation feature will be disabled. In this mode the device behaves as a conventional Full Bridge
driver.
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GreenPAK Programmable Mixed-Signal Matrix with High
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7.7 HIGH VOLTAGE OUTPUTS TYPICAL PERFORMANCE
290
270
T = 150 °C
T = 25 °C
T = 85 °C
T = -40 °C
250
230
210
190
170
150
130
I (A)
Figure 19: Full Bridge Typical Drain-Source High Side On-Resistance vs. Load Current at VDD = 5.5 V, VDD2 = 5 V
290
270
T = 150 °C
T = 25 °C
T = 85 °C
T = -40 °C
250
230
210
190
170
150
130
I (A)
Figure 20: Full Bridge Typical Drain-Source Low Side On-Resistance vs. Load Current at VDD = 5.5 V, VDD2 = 5 V
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GreenPAK Programmable Mixed-Signal Matrix with High
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370
350
VDD2 = 3 V
330
310
290
270
250
230
210
190
170
150
130
VDD2 = 5 V
VDD2 = 9 V
VDD2 = 13.2 V
T (°C)
Figure 21: Full Bridge Typical Drain-Source High Side On-Resistance vs. Temperature at ILOAD = 0.5 A, VDD = 2.3 V
370
350
VDD2 = 3 V
330
310
290
270
250
230
210
190
170
150
130
VDD2 = 5 V
VDD2 = 9 V
VDD2 = 13.2 V
T (°C)
Figure 22: Full Bridge Typical Drain-Source High Side On-Resistance vs. Temperature at ILOAD = 0.5 A, VDD = 5.5 V
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370
350
VDD2 = 3 V
330
310
290
270
250
230
210
190
170
150
130
VDD2 = 5 V
VDD2 = 9 V
VDD2 = 13.2 V
T (°C)
Figure 23: Full Bridge Typical Drain-Source Low Side On-Resistance vs. Temperature at ILOAD = 0.5 A, VDD = 2.3 V
370
350
VDD2 = 3 V
330
310
290
270
250
230
210
190
170
150
130
VDD2 = 5 V
VDD2 = 9 V
VDD2 = 13.2 V
T (°C)
Figure 24: Full Bridge Typical Drain-Source Low Side On-Resistance vs. Temperature at ILOAD = 0.5 A, VDD = 5.5 V
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0.4
High Side @ Tj = 150 °C
Low Side @ Tj = 150 °C
Low Side @ Tj = 85 °C
Low Side @ Tj = 25 °C
Low Side @ Tj = -40 °C
High Side @ Tj = 85 °C
0.35
High Side @ Tj = 25 °C
High Side @ Tj = -40 °C
0.3
0.25
0.2
0.15
0.1
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10 10.5 11 11.5 12 12.5 13
VDD2 (V)
Figure 25: Full Bridge Typical Drain-Source On-Resistance vs. VDD2 at VDD = 5.5 V, ILOAD = 0.1 A
2.8
2.78
2.76
2.74
Fault A, Upper Limit
Fault B, Upper Limit
2.72
Fault A, Lower Limit
2.7
Fault B, Lower Limit
2.68
2.66
2.64
2.62
2.6
T (°C)
Figure 26: Half Bridge Under-voltage Lockout Value vs. Temperature at VDD = 3.3 V
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7%
6%
5%
4%
3%
2%
1%
0%
OCP threshold (A)
Figure 27: Full Bridge High Side OCP Threshold Distribution at VDD=2.3V to 5.5V, VDD2=3V to 13.2V, TJ=-40 °C to 150°C
7%
6%
5%
4%
3%
2%
1%
0%
OCP threshold (A)
Figure 28: Full Bridge Low Side OCP Threshold Distribution at VDD=2.3V to 5.5V, VDD2= 3V to 13.2V, TJ= -40°C to 150°C
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2.4
2.35
2.3
2.25
2.2
2.15
2.1
2.05
Low Side @ Tj = -40 °C
High Side @ Tj = -40 °C
Low Side @ Tj = 85 °C
Low Side @ Tj = 150 °C
High Side @ Tj = 150 °C
Low Side @ Tj = 25 °C
High Side @ Tj = 25 °C
High Side @ Tj = 85 °C
2
1.95
1.9
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
VDD2 (V)
Figure 29: Full Bridge OCP Threshold vs. VDD2 at VDD = 5.5 V
8
8.5
9
9.5 10 10.5 11 11.5 12 12.5 13
68
Tj = 150 °C, Rising
Tj = 25 °C, Rising
Tj = 150 °C, Falling
Tj = 25 °C, Falling
Tj = 85 °C, Rising
Tj = -40 °C, Rising
Tj = 85 °C, Falling
Tj = -40 °C, Falling
63
58
53
48
43
38
33
28
23
18
13
8
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10 10.5 11 11.5 12 12.5 13
VDD2 (V)
Figure 30: Half Bridge Dead Band Time vs. VDD2 at VDD = 2.3 V to 5.5 V, f = 50 kHz for Pre-Driver Mode
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390
Tj = 150 °C, Rising
Tj = 25 °C, Rising
Tj = 150 °C, Falling
Tj = 25 °C, Falling
Tj = 85 °C, Rising
Tj = -40 °C, Rising
Tj = 85 °C, Falling
Tj = -40 °C, Falling
370
350
330
310
290
270
250
230
210
190
170
150
130
110
90
70
50
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10 10.5 11 11.5 12 12.5 13
VDD2 (V)
Figure 31: Half Bridge Dead Band Time vs. VDD2 at VDD = 2.3 V to 5.5 V, f = 50 kHz for Regular Mode
18
Tj = 150 °C, Rising
Tj = 25 °C, Rising
Tj = 150 °C, Falling
Tj = 25 °C, Falling
Tj = 85 °C, Rising
Tj = -40 °C, Rising
Tj = 85 °C, Falling
Tj = -40 °C, Falling
17
16
15
14
13
12
11
10
9
8
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10 10.5 11 11.5 12 12.5 13
VDD2 (V)
Figure 32: Half Bridge Output Transition Time vs. VDD2 at VDD = 2.3 V to 5.5 V, f = 50 kHz for Pre-Driver Mode
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170
165
160
155
150
145
140
135
130
125
120
115
110
105
100
Tj = 150 °C, Rising
Tj = 25 °C, Rising
Tj = 150 °C, Falling
Tj = 25 °C, Falling
Tj = 85 °C, Rising
Tj = -40 °C, Rising
Tj = 85 °C, Falling
Tj = -40 °C, Falling
95
90
85
80
75
70
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10 10.5 11 11.5 12 12.5 13
VDD2 (V)
Figure 33: Half Bridge Output Transition Time vs. VDD2 at VDD = 2.3 V to 5.5 V, f = 50 kHz for Regular Mode
360
340
320
Tj = 150 °C
300
Tj = 85 °C
280
Tj = 25 °C
Tj = -40 °C
260
240
220
200
180
160
140
120
100
80
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10 10.5 11 11.5 12 12.5 13
VDD2 (V)
Figure 34: One Half Bridge IDD2 vs. VDD2 at VDD = 5.5 V
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850
800
750
Tj = 150 °C
700
650
600
550
500
450
400
350
300
250
200
Tj = 85 °C
Tj = 25 °C
Tj = -40 °C
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10 10.5 11 11.5 12 12.5 13
VDD2 (V)
Figure 35: All Four Half Bridges IDD2 vs. VDD2 at VDD = 5.5 V
800
700
600
500
400
300
200
Tj = 150 °C
Tj = 85 °C
Tj = 25 °C
Tj = -40 °C
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10 10.5 11 11.5 12 12.5 13
VDD2 (V)
Figure 36: Two Full Bridges + One CCMP IDD2 vs. VDD2 at VDD = 5.5 V
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750
700
650
600
550
500
450
400
350
300
Tj = 150 °C
Tj = 85 °C
Tj = 25 °C
Tj = -40 °C
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10 10.5 11 11.5 12 12.5 13
VDD2 (V)
Figure 37: One Full Bridge + Integrator + PWM + OSC1 IDD2 vs. VDD2 at VDD = 5.5 V
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8
Differential Amplifier with Integrator and Comparator
Differential Amplifier with Integrator and Analog Comparator is connected to HV_GPO0_HD and HV_GPO1_HD (first Full
Bridge). This macrocell is useful when there is a need to keep the constant voltage at Full Bridge load. Differential Amplifier with
Integrator and Comparator has dedicated power-up input control (Connection Matrix output). During LOW on power-up input the
Differential Amplifier with Integrator and Comparator is in power down state and its outputs are latched in previous state.
"Upward" output of macrocell is active LOW when Average Voltage Difference on Full Bridge (integrated Voltage) is higher than
upper Vref of Comparator (including Differential Amplifier influence). "Upward" output can be optionally inverted by setting
register [753] to 0.
"Equal" output is active HIGH when integrated Voltage is equal to Comparator Threshold.
The inputs of the Differential Amplifier can be:
-HV_GPO0_HD or HV_GPO1_HD outputs for non-inverting ("+") input;
-HV_GPO1_HD or HV_GPO0_HD outputs for inverting ("-") input.
The internal multiplexer connects HV_GPOx_HD Pins to Differential Amplifier inputs in right combination automatically,
depending on Full Bridge logic inputs current state (in Full Bridge Mode only).
The Comparator IN- voltage source is internal 32 mV - 2016 mV with 32 mV step or external voltage (GPIO0). There is 0.25x
Gain divider after Differential Amplifier.
The Differential Amplifier operation conditions:
PWM0 is enabled
HV OUT CRTL0 is configured in Full Bridge mode
PWM frequency 44 kHz or higher to make sure that Integrator operates correctly.
The integrated DC voltage level is applied to the comparator negative input. The comparator outputs are used to control the
PWM duty cycle. In this case, a closed loop system controls the PWM duty cycle to ensure the constant average output voltage
level.
Note that PWM duty cycle CNT CLK requires the rate of update at latest two PWM period cycles or more.
Differential Amplifier with Integrator and Analog Comparator macrocell operates synchronously to PWM0 macrocell. So, to use
Differential Amplifier with Integrator and Analog Comparator it is necessary to enable PWM0 macrocell and Oscillator, used by
this PWM macrocell.
It's recommended not to use Hi-Z state of HV_GPO0_HD and HV_GPO1_HD Pins when working with Differential Amplifier with
Integrator and Comparator macrocell. Hi-Z state can decrease the accuracy of Differential Amplifier and may cause thermal shut
down due to current flow through the diodes in the HV outputs, when Hi-Z state is enabled.
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8.1 DIFFERENTIAL AMPLIFIER WITH INTEGRATOR BLOCK DIAGRAM
Auto Switch
Logic
Internal
Vref
000000-
111110
Ext. VREF
(GPIO0)
111111
invert UPWARD
register[753]
Vref
registers [669:664
]
Diff. Amp
from HV GPO0 HD
from HV GPO1 HD
0
1
to Diff. Amp+Integrator
UPWARD Matrix Input [44]
0
1
/4
Integrator
powerUp
ACMP
powerUp
to Diff. Amp+Integrator
EQUAL Matrix Input [45]
0
1
powerUp
Diff_Amp+Integrator_En
Matrix Output [94]
Figure 38: Differential Amplifier with Integrator Block Diagram
8.2 DIFFERENTIAL AMPLIFIER LOAD REGULATION
4.1
4.08
4.06
4.04
4.02
4
3.98
3.96
3.94
Tj = 150 °C, PWM f = 49 kHz
Tj = 85 °C, PWM f = 49 kHz
Tj = -40 °C, PWM f = 49 kHz
Tj = 85 °C, PWM f = 196 kHz
Tj = -40 °C, PWM f = 196 kHz
3.92
Tj = 25 °C, PWM f = 49 kHz
Tj = 150 °C, PWM f = 196 kHz
3.9
Tj = 25 °C, PWM f = 196 kHz
3.88
0.2
0.3
0.4
0.5
I (A)
Figure 39: Typical Load Regulation at VOUT = 4.096 V, VDD = 2.3 V to 5.5 V, VDD2 = 5 V
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4.08
4.04
4
3.96
3.92
3.88
3.84
3.8
Tj = 150 °C, PWM f = 49 kHz
Tj = 25 °C, PWM f = 49 kHz
Tj = 150 °C, PWM f = 196 kHz
Tj = 25 °C, PWM f = 196 kHz
Tj = 85 °C, PWM f = 49 kHz
Tj = -40 °C, PWM f = 49 kHz
Tj = 85 °C, PWM f = 196 kHz
Tj = -40 °C, PWM f = 196 kHz
3.76
3.72
3.68
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
I (A)
Figure 40: Typical Load Regulation at VOUT = 4.096 V, VDD = 2.3 V to 5.5 V, VDD2 = 9 V
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9
Current Sense Comparator
There are two Current Sense Comparator macrocells in the SLG47105.
Each of the Current CMP macrocells has a positive input signal that is connected to SENSE_x pins through Selectable Gain
block. The options for Selectable Gain are 4x or 8x.
Each of the Current CMP macrocells has a negative input signal that can be connected to static or dynamic variable Vref. The
static Vref value is selected via registers. The dynamically changed Vref values are selected with the help of one of the PWM
blocks, different for each Current Sense Comparator. In this case, 6-bit Vref is selected by 6 Low Significant bits of Synchro
Buffer, which is a part of the PWM block (detailed in Section 13). For example, the Current Sense Comparator Vref can be
changed "on the flight" from 16-bytes Register File, which is connected to the Synchro Buffer by PWM block settings, and where
user-defined Vref values are stored. The Vref values are switched Up or Down depending on the level of PWM macrocell Up/
Down input, each pulse on DUTY_CYCLE_CLK input.
Note 1: The PWM block can be active when 16-bytes Register File is used by Current Sense Comparator.
Note 2: The Vref can be changed in a range from 32 mV to 2016 mV with 32 mV step.
During power-up, the Current Sense Comparator output will remain LOW, and then become valid 12.5 μs (max) after power-up
signal goes high.
Current Sense Comparator0 IN+ is connected with SENSE_A pin through Selectable Gain0.
Current Sense Comparator1 IN+ is connected with SENSE_B pin through Selectable Gain1.
9.1 CURRENT SENSE COMPARATOR0 BLOCK DIAGRAM
register [866]
CCMP0
Ready
Current CMP0
current_sense_a
Selectable
Gain0
to Connection
4x/8x
Matrix Input [48]
0
1
PU
Internal Vref
0.032V-2.016V
Or Ext Vref
000000-
111111
Static Current
Sense0 threshold
registers [701:696]
0
1
invert current CMP0 Out
register [867]
Dynamic from PWM0
CCMP0 nDisable
register [870]
Current Closed
Loop mode register [702]
from HV GPO0 Sleep
Connection Matrix Output[23]
from HV GPO1 Sleep
Connection Matrix Output[24]
Figure 41: Current Sense Comparator0 Block Diagram
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GreenPAK Programmable Mixed-Signal Matrix with High
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9.2 CURRENT SENSE COMPARATOR1 BLOCK DIAGRAM
register [868]
CCMP1
Ready
Current CMP1
current_sense_b
Selectable
to Connection
Matrix Input [49]
Gain0
4x/8x
0
1
PU
Internal Vref
000000-
0.032V-2.016V
Or Ext Vref
111111
Static Current
Sense1 threshold
registers [709:704]
0
invert current CMP1 Out
register [869]
Dynamic from PWM1
Current Closed
Loop mode register [710]
1
CCMP1 nDisable
register [871]
from HV GPO2 Sleep
Connection Matrix Output[25]
from HV GPO3 Sleep
Connection Matrix Output[26]
Figure 42: Current Sense Comparator1 Block Diagram
9.3 CURRENT REGULATION
To use the Current Regulation, it is necessary to connect sense-resistors between SENSE_x pins and ground. The resistor
value is calculated by the formula:
Vref[n]
I[n] = -------------------------------------
Rsense × Gain
Where:
I[n]- Load Current (through controlled winding or resistive load) for selected Vref[n]
Vref - reference voltage of Current Sense Comparator, constant value, external source, or selectable value from Register File
RSENSE - resistance of the sense resistor
GAIN - selectable gain (4x or 8x, selectable by the register)
The reference voltage can be set statically or dynamically. For static reference voltage setting it is required to calculate RSENSE
for selected reference voltage and desired motor current.
For dynamic reference voltage setting it is required to calculate RSENSE for the maximal user-defined reference voltage and
maximal current via motor winding.
16 values in the Reg File can be used to determine the shape of motor current, for example, sin current for the stepper motor.
DUTY_CYCLE_CLK input of PWM macrocell is used to switch to the next Vref value, and UP/DOWN input of PWM macrocell
selects the direction of Vref change (next or previous Vref value). For more detailed description of Reg File see Section 13.
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GreenPAK Programmable Mixed-Signal Matrix with High
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9.4 CURRENT SENSE COMPARATOR TYPICAL PERFORMANCE
40
30
Upper Limit
Lower Limit
20
10
0
480
1024
1568
-10
-20
-30
Vref (mV)
T = -40 °C to 150 °C, VDD = 2.3 V to 5.5 V, Gain = 4
Figure 43: Input Offset Voltage Error vs. Vref for CCMPx (including Amplifier Offset and ACMP Offset)
0.7
0.6
0.5
0.4
High To Low, Overdrive = 10 mV
0.3
Low to High, Overdrive = 10 mV
High to Low, Overdrive = 100 mV
0.2
Low to High, Overdrive = 100 mV
0.1
0
480
992
1504
2016
Vref (mV)
Figure 44: Typical Propagation Delay vs. Vref for CCMPx at T = 25 °C, at VDD = 2.3 V to 5.5 V, Gain = 4
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GreenPAK Programmable Mixed-Signal Matrix with High
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10
9
8
7
6
Tj = -40 °C
Tj = 25 °C
Tj = 85 °C
Tj = 150 °C
5
4
3
2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VDD (V)
Figure 45: CCMPx Power-On Delay vs. VDD (BG is Forced On)
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10 Connection Matrix
The Connection Matrix in the SLG47105 is used to create the internal routing for internal functional macrocells of the device once
it is programmed. The registers are programmed from the one time programmable (OTP) NVM cell during Test Mode Operation.
The output of each functional macrocell within the SLG47105 has a specific digital bit code assigned to it, that is either set to
active “High”, or inactive “Low”, based on the design that is created. Once the 2048 register bits within the SLG47105 are
programmed, a fully custom circuit will be created.
The Connection Matrix has 64 inputs and 96 outputs. Each of the 64 inputs to the Connection Matrix is hard-wired to the digital
output of a particular source macrocell, including IO pins, LUTs, analog comparators, other digital resources, such as VDD and
GND. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines.
For a complete list of the SLG47105’s register table, see Section 23.
Matrix Input Signal
N
Functions
GND
0
1
2
3
LUT2_0/DFF OUT
LUT2_1/DFF OUT
LUT2_2/DFF OUT
TSD_FAULT
VDD
62
63
Matrix Inputs
0
1
2
94
N
Registers
registers [5:0]
registers [11:6]
registers [17:12]
registers [569:564]
Diff_Amp_Intergator_EN
GPIO0
Digital Output
GPIO0
Digital Output OE
GPIO1
Digital Output
Function
Matrix Outputs
Figure 46: Connection Matrix
Function
Connection Matrix
GPIO0
GPIO1
LUT
GPIO0
GPIO1
GPIO4
LUT
GPIO4
Figure 47: Connection Matrix Example
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GreenPAK Programmable Mixed-Signal Matrix with High
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10.1 MATRIX INPUT TABLE
Table 43: Matrix Input Table
Matrix Decode
Matrix Input
Matrix Input Signal Function
Number
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
GND
1
LUT2_0/DFF0 output
2
LUT2_1/DFF1 output
3
LUT2_2/DFF2 output
4
LUT2_3/PGen output
5
LUT3_0/DFF3 output
6
LUT3_1/DFF4/Chopper0 output
LUT3_2/DFF5/Chopper1 output
LUT3_3/DFF6 output
7
8
9
LUT3_4/DFF7 output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
LUT3_5/DFF8 output
LUT4_0/DFF9 output
LUT3_6/PD/RIPP CNT output0
LUT3_6/PD/RIPP CNT output1
LUT3_6/PD/RIPP CNT output2
PROG_DLY_EDET_OUT
MULTFUNC_8BIT_1: DLY_CNT_OUT
MULTFUNC_8BIT_2: DLY_CNT_OUT
MULTFUNC_8BIT_3: DLY_CNT_OUT
MULTFUNC_8BIT_4: DLY_CNT_OUT
MULTFUNC_8BIT_1: LUT3_DFF_OUT
MULTFUNC_8BIT_2: LUT3_DFF_OUT
MULTFUNC_8BIT_3: LUT3_DFF_OUT
MULTFUNC_8BIT_4: LUT3_DFF_OUT
MULTFUNC_16BIT_0: DLY_CNT_OUT
MULTFUNC_16BIT_0: LUT4_DFF_OUT
GPIO0 Digital Input
GPI Digital Input
GPIO1 Digital Input
GPIO4 Digital Input
GPIO5 Digital Input
GPIO6 Digital Input
GPIO2 digital input or I2C_virtual_0 Input
GPIO3 digital input or I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
I2C_virtual_5 Input
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GreenPAK Programmable Mixed-Signal Matrix with High
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Table 43: Matrix Input Table(Continued)
Matrix Decode
Matrix Input
Matrix Input Signal Function
Number
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
I2C_virtual_6 Input
I2C_virtual_7 Input
PWM0_OUT+
PWM0_OUT-
PWM1_OUT+
PWM1_OUT-
Diff. Amp +Integrator UPWARD
Diff. Amp +Integrator EQUAL
ACMP0H_OUT
ACMP1H_OUT
CurrentSenseComp0_OUT
CurrentSenseComp1_OUT
Fault_A
Fault_B
EDET_FILTER_OUT
Oscillator1 (25 MHz) output
Flex-Divider output
Oscillator0 (2.048 kHz) output 0
Oscillator0 (2.048 kHz) output 1
POR OUT
PWM0_PERIOD
PWM1_PERIOD
OCP_FAULT_A
OCP_FAULT_B
TSD_FAULT
VDD
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GreenPAK Programmable Mixed-Signal Matrix with High
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10.2 MATRIX OUTPUT TABLE
Table 44: Matrix Output Table
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
[5:0]
GPIO0 Digital Output
0
[11:6]
GPIO0 Digital Output OE
GPIO1 Digital Output
1
[17:12]
2
[23:18]
GPIO1 Digital Output OE
GPIO2 Digital Output
3
[29:24]
4
[35:30]
GPIO3 Digital Output
5
[41:36]
GPIO4 Digital Output
6
[47:42]
GPIO4 Digital Output OE
GPIO5 Digital Output
7
[53:48]
8
[59:54]
GPIO5 Digital Output OE
GPIO6 Digital Output
9
[65:60]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
[71:66]
GPIO6 Digital Output OE
HV GPO0 Digital Output
HV GPO0 Digital Output OE
HV GPO1 Digital Output
HV GPO1 Digital Output OE
HV GPO2 Digital Output
HV GPO2 Digital Output OE
HV GPO3 Digital Output
HV GPO3 Digital Output OE
Reserved
[77:72]
[83:78]
[89:84]
[95:90]
[101:96]
[107:102]
[113:108]
[119:114]
[125:120]
[131:126]
[137:132]
[143:138]
[149:144]
[155:150]
[161:156]
[167:162]
[173:168]
[179:174]
[185:180]
[191:186]
[197:192]
[203:198]
[209:204]
[215:210]
[221:216]
[227:222]
Reserved
Reserved
HV GPO0 SLEEP
HV GPO1 SLEEP
HV GPO2 SLEEP
HV GPO3 SLEEP
IN0 of LUT2_0 or Clock Input of DFF0
IN1 of LUT2_0 or Data Input of DFF0
IN0 of LUT2_3 or Clock Input of PGen
IN1 of LUT2_3 or nRST of PGen
IN0 of LUT2_1 or Clock Input of DFF1
IN1 of LUT2_1 or Data Input of DFF1
IN0 of LUT2_2 or Clock Input of DFF2
IN1 of LUT2_2 or Data Input of DFF2
IN0 of LUT3_0 or Clock Input of DFF3
IN1 of LUT3_0 or Data Input of DFF3
IN2 of LUT3_0 or nRST(nSET) of DFF3
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Table 44: Matrix Output Table(Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
[233:228]
[239:234]
[245:240]
[251:246]
[257:252]
[263:258]
[269:264]
[275:270]
[281:276]
[287:282]
[293:288]
[299:294]
[305:300]
[311:306]
[317:312]
[323:318]
[329:324]
[335:330]
[341:336]
[347:342]
[353:348]
[359:354]
IN0 of LUT3_1 or Clock Input of DFF4
IN1 of LUT3_1 or Data Input of DFF4
IN2 of LUT3_1 or nRST(nSET) of DFF4
IN0 of LUT3_2 or Clock Input of DFF5
IN1 of LUT3_2 or Data Input of DFF5
IN2 of LUT3_2 or nRST(nSET) of DFF5
IN0 of LUT3_3 or Clock Input of DFF6
IN1 of LUT3_3 or Data Input of DFF6
IN2 of LUT3_3 or nRST(nSET) of DFF6
IN0 of LUT3_4 or Clock Input of DFF7
IN1 of LUT3_4 or Data Input of DFF7
IN2 of LUT3_4 or nRST(nSET) of DFF7
IN0 of LUT3_5 or Clock Input of DFF8
IN1 of LUT3_5 or Data Input of DFF8
IN2 of LUT3_5 or nRST(nSET) of DFF8
IN0 of LUT3_6 or Input of Pipe Delay or UP Signal of RIPP CNT
IN1 of LUT3_6 or nRST of Pipe Delay or nSET of RIPP CNT
IN2 of LUT3_6 or Clock of Pipe/RIPP_CNT
IN0 of LUT4_0 or Clock Input of DFF9
IN1 of LUT4_0 or Data Input of DFF9
IN2 of LUT4_0 or nRST(nSET) of DFF9
IN3 of LUT4_0
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
MULTFUNC_8BIT_1: IN0 of LUT3_7 or Clock Input of DFF10,
Delay1 Input (or Counter1 nRST Input)
[365:360]
[371:366]
[377:372]
[383:378]
[389:384]
[395:390]
[401:396]
[407:402]
[413:408]
[419:414]
MULTFUNC_8BIT_1: IN1 of LUT3_7 or nRST (nSET) of DFF10,
Delay1 Input (or Counter1 nRST Input) or Delay/Counter1 External Clock Source
61
62
63
64
65
66
67
68
69
MULTFUNC_8BIT_1: IN2 of LUT3_7 or Data Input of DFF10,
Delay1 Input (or Counter1 nRST Input)
MULTFUNC_8BIT_2: IN0 of LUT3_8 or Clock Input of DFF11,
Delay2 Input (or Counter2 nRST Input)
MULTFUNC_8BIT_2: IN1 of LUT3_8 or nRST (nSET) of DFF11,
Delay2 Input (or Counter2 nRST Input) or Delay/Counter2 External Clock Source
MULTFUNC_8BIT_2: IN2 of LUT3_8 or Data Input of DFF11,
Delay2 Input (or Counter2 nRST Input)
MULTFUNC_8BIT_3: IN0 of LUT3_9 or Clock Input of DFF12,
Delay3 Input (or Counter3 nRST Input)
MULTFUNC_8BIT_3: IN1 of LUT3_9 or nRST (nSET) of DFF12,
Delay3 Input (or Counter3 nRST Input) or Delay/Counter3 External Clock Source
MULTFUNC_8BIT_3: IN2 of LUT3_9 or Data Input of DFF12,
Delay3 Input (or Counter3 nRST Input)
MULTFUNC_8BIT_4: IN0 of LUT3_10 or Clock Input of DFF13,
Delay4 Input (or Counter4 nRST Input)
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Table 44: Matrix Output Table(Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
MULTFUNC_8BIT_4: IN1 of LUT3_10 or nRST (nSET) of DFF13;
[425:420]
70
71
72
73
74
75
Delay4 Input (or Counter4 nRST Input) or Delay/Counter4 External Clock Source
MULTFUNC_8BIT_4: IN2 of LUT3_10 or Data Input of DFF13;
Delay4 Input (or Counter4 nRST Input)
[431:426]
MULTFUNC_16BIT_0: IN0 of LUT4_1 or Clock Input of DFF14; Delay0 Input (or Count-
er0 RST/SET Input)
[437:432]
MULTFUNC_16BIT_0: IN1 of LUT4_1 or nRST of DFF14;
[443:438]
Delay0 Input (or Counter0 nRST Input) or Delay/Counter0 External Clock Source
MULTFUNC_16BIT_0: IN2 of LUT4_1 or nSET of DFF14 or KEEP Input of FSM0 or
External Clock Input of Delay0 (or Counter0)
[449:444]
MULTFUNC_16BIT_0: IN3 of LUT4_1 or Data Input of DFF14;
[455:450]
Delay0 Input (or Counter0 nRST Input) or UP Input of FSM0
[461:456]
[467:462]
[473:468]
[479:474]
[485:480]
[491:486]
[497:492]
[503:498]
[509:504]
[515:510]
[521:516]
[527:522]
[533:528]
[539:534]
[545:540]
[551:546]
[557:552]
[563:558]
[569:564]
[575:570]
PWM0_UP/DOWN
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
PWM0_KEEP/STOP
PWM0_DUTY_CYCLE_CNT
PWM0_EXT_CLK
PWM0_RESET/SET
PWM1_UP/DOWN
PWM1_KEEP/STOP
PWM1_DUTY_CYCLE_CNT
PWM1_EXT_CLK
PWM1_RESET/SET
pd of ACMP0H from the matrix
pd of ACMP1H from the matrix
Filter/Edge detect input
Programmable delay/edge detect input
OSC0 ENABLE from matrix
OSC1 ENABLE from matrix
Temp sensor PD from matrix
BG Power-down from the matrix
Diff_Amp_Integrator_En
Reserved
10.3 CONNECTION MATRIX VIRTUAL INPUTS
As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macrocells on the device. Eight
of the Connection Matrix inputs have the special characteristic that the state of these signal lines comes from a corresponding
data bit written as a register value via I2C. This gives the user the ability to write data via the serial channel, and have this
information translated into signals that can be driven into the Connection Matrix and from the Connection Matrix to the digital
inputs of other macrocells on the device. The I2C address for reading and writing these register values is at 0x4C (76).
An I2C write command to these register bits will set the signal values going into the Connection Matrix to the desired state. A read
command to these register bits will read either the original data values coming from the NVM memory bits (that were loaded during
the initial device startup) or the values from a previous write command (if that has happened).
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GreenPAK Programmable Mixed-Signal Matrix with High
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Table 45: Connection Matrix Virtual Inputs
Matrix Input
Register Bit
Addresses (d)
Matrix Input Signal Function
Number
32
33
34
35
36
37
38
39
I2C_virtual_0 Input
I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
I2C_virtual_5 Input
I2C_virtual_6 Input
I2C_virtual_7 Input
[608]
[609]
[610]
[611]
[612]
[613]
[614]
[615]
10.4 CONNECTION MATRIX VIRTUAL OUTPUTS
The digital outputs of the various macrocells are routed to the Connection Matrix to enable interconnections to the inputs of other
macrocells in the device. At the same time it is possible to read the state of each of the macrocell outputs as a register value via
I2C. This option, called Connection Matrix Virtual Outputs, allows the user to remotely read the values of each macrocell output.
The I2C addresses for reading these register values are registers [639:576]. Write commands to the same register values will be
ignored (with the exception of the Virtual Input register bits at registers [615:608]).
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11 Combination Function Macrocells
The SLG47105 has 12 combination function macrocells that can serve more than one logic or timing function. In each case, they
can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be
implemented in these macrocells.
Three macrocells that can serve as either 2-bit LUT or as D Flip-Flop
Four macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input
Two macrocells that can serve as either 3-bit LUTs, as D Flip-Flops with Set/Reset Input or as PWM Choppers
One macrocell that can serve as either 3-bit LUT or as Pipe Delay/Ripple Counter
One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGen)
One macrocell that can serve as either 4-bit LUT or as D Flip-Flop with Set/Reset Input
Inputs/Outputs for the 12 combination function macrocells are configured from the connection matrix with specific logic functions
being defined by the state of configuration bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined
function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
11.1 2-BIT LUT OR D FLIP-FLOP MACROCELLS
There are three macrocells that can serve as either 2-bit LUT or as D Flip-Flop. When used to implement LUT functions, the 2-
bit LUT takes in two input signals from the connection matrix and produces a single output, which goes back into the connection
matrix. When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and
clock (CLK) inputs for the Flip-Flop, with the output going back to the connection matrix.
The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:
DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change
LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is
High).
register [1251] DFF or LATCH Select
IN1
register [1250] Output Select (Q or nQ)
S0
From Connection Matrix Output [28]
register [1249] DFF Initial Polarity Select
OUT
2-bit LUT0
0: 2-bit LUT0 IN1
1: DFF0 Data
S1
IN0
LUT Truth
Table
To Connection Matrix
Input [1]
S0
S1
4-bits NVM
registers [1251:1248]
0: 2-bit LUT0 OUT
1: DFF0 OUT
DFF/
LATCH
D
S0
S1
From Connection Matrix Output [27]
Q/nQ
DFF0
0: 2-bit LUT0 IN0
1: DFF0 CLK
CLK
1-bit NVM
register [1260]
Figure 48: 2-bit LUT0 or DFF0
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GreenPAK Programmable Mixed-Signal Matrix with High
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register [1255] DFF or LATCH Select
register [1254] Output Select (Q or nQ)
register [1253] DFF Initial Polarity Select
IN1
S0
From Connection Matrix Output [32]
OUT
2-bit LUT1
0: 2-bit LUT1 IN1
1: DFF1 Data
S1
IN0
LUT Truth
Table
To Connection Matrix
S0
Input [2]
4-bits NVM
registers [1255:1252]
S1
0: 2-bit LUT1 OUT
1: DFF1 OUT
DFF/
LATCH
D
S0
S1
From Connection Matrix Output [31]
Q/nQ
DFF1
0: 2-bit LUT1 IN0
1: DFF1 CLK
CLK
1-bit NVM
register [1261]
Figure 49: 2-bit LUT1 or DFF1
register [1259] DFF or LATCH Select
register [1258] Output Select (Q or nQ)
register [1257] DFF Initial Polarity Select
IN1
S0
S1
From Connection Matrix Output [34]
OUT
2-bit LUT2
0: 2-bit LUT2 IN1
1: DFF2 Data
IN0
LUT Truth
Table
To Connection Matrix
S0
Input [3]
4-bits NVM
registers [1259:1256]
S1
0: 2-bit LUT2 OUT
1: DFF2 OUT
DFF/
LATCH
D
S0
S1
From Connection Matrix Output [33]
Q/nQ
DFF2
0: 2-bit LUT2 IN0
1: DFF2 CLK
CLK
1-bit NVM
register [1262]
Figure 50: 2-bit LUT2 or DFF2
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
11.1.1 2-bit LUT or D Flip-Flop Macrocell Used as 2-bit LUT
Table 46: 2-bit LUT0 Truth Table
IN1
0
IN0
0
OUT
register [1248]
register [1249]
register [1250]
register [1251]
LSB
0
1
1
0
1
1
MSB
Table 47: 2-bit LUT1 Truth Table
IN1
0
IN0
0
OUT
register [1252]
register [1253]
register [1254]
register [1255]
LSB
0
1
1
0
1
1
MSB
Table 48: 2-bit LUT2 Truth Table
IN1
0
IN0
0
OUT
register [1256]
register [1257]
register [1258]
register [1259]
LSB
0
1
1
0
1
1
MSB
This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-bit LUT0 is defined by registers [1251:1248]
2-bit LUT1 is defined by registers [1255:1252]
2-bit LUT2 is defined by registers [1259:1256]
Table 49 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the 2-bit LUT logic cells.
Table 49: 2-bit LUT Standard Digital Functions
Function
AND-2
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-2
OR-2
NOR-2
XOR-2
XNOR-2
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GreenPAK Programmable Mixed-Signal Matrix with High
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11.1.2 Initial Polarity Operations
VDD
Data
Clock
POR
Initial Polarity: High
Q with nReset (Case 1)
Initial Polarity: Low
Q with nReset (Case 1)
Figure 51: DFF Polarity Operations
11.2 2-BIT LUT OR PROGRAMMABLE PATTERN GENERATOR
The SLG47105 has one combination function macrocell that can serve as a logic or timing function. This macrocell can serve as
a Look Up Table (LUT), or a Programmable Pattern Generator (PGen).
When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection matrix and produces a single
output, which goes back into the connection matrix. When used as a LUT to implement combinatorial logic functions, the outputs
of the LUT can be configured to any user-defined function, including the following standard digital logic devices (AND, NAND,
OR, NOR, XOR, XNOR). The user can also define the combinatorial relationship between inputs and outputs to be any selectable
function.
It is possible to define the RST level for the PGen macrocell. There are both high-level reset (RST) and a low-level reset (nRST)
options available, which are selected by register [1193]. When operating as a Programmable Pattern Generator, the output of the
macrocell will clock out a sequence of two to sixteen bits that are user selectable in their bit values, and user selectable in the
number of bits (up to sixteen) that are output before the pattern repeats.
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GreenPAK Programmable Mixed-Signal Matrix with High
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From Connection Matrix Output [29]
From Connection Matrix Output [30]
IN0
IN1
OUT
2-bit LUT3
LUT Truth
Table
To Connection Matrix Input [4]
S0
S1
0: 2-bit LUT3 OUT
1: PGen OUT
registers [1171:1168]
Pattern
size
nRST/RST
CLK
PGen
OUT
PGen
Data
register [1192]
registers [1191:1176]
Figure 52: 2-bit LUT3 or PGen
VDD
t
t
nRST
CLK
OUT
1
2
6
8
16 17
3
5
7
0
4
9
10 11
14 15
12 13
t
D7
D6
D5
D10
D8
D4
D3
D2
D1
D15
D0
D9
D0
D15
D14
D13
D12
D11
D0
t
Figure 53: PGen Timing Diagram
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GreenPAK Programmable Mixed-Signal Matrix with High
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11.2.1 2-bit LUT or PGen Macrocell Used as 2-bit LUT
Table 50: 2-bit LUT1 Truth Table
IN1
0
IN0
0
OUT
register [1168]
register [1169]
register [1170]
register [1171]
LSB
0
1
1
0
1
1
MSB
This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-bit LUT3 is defined by registers [1171:1168]
Table 51 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the 2-bit LUT logic cells.
Table 51: 2-bit LUT Standard Digital Functions
Function
AND-2
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-2
OR-2
NOR-2
XOR-2
XNOR-2
11.3 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELLS
There are four macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset inputs. When used to implement
LUT functions, the 3-bit LUTs each takes in three input signals from the connection matrix and produces a single output, which
goes back into the connection matrix. When used to implement D Flip-Flop function, the three input signals from the connection
matrix go to the data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output going back to the
connection matrix. It is possible to define the active level for the reset/set input of DFF/LATCH macrocell. There are both active
high level reset/set (RST/SET) and active low level reset/set (nRST/nSET) options available, which are selected by register
[1226].
DFF3 functionality is different from the other DFFs. DFF3 operation will flow the functional description below:
If register [1228] = 0, and the CLK is rising edge triggered, then Q = D, otherwise Q will not change.
If register [1228] = 1, then data from D is written into the DFF by the rising edge on CLK and output to Q by the falling edge on
CLK.
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GreenPAK Programmable Mixed-Signal Matrix with High
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register [1231] DFF or LATCH Select
register [1230] Output Select (Q or nQ)
register [1229] DFF Initial Polarity Select
register [1228] Q1 or Q2 Select
register [1227] DFF nRST or nSET Select
register [1226] Active level selection for RST/
SET
IN2
IN1
From Connection
Matrix Output [37]
S0
S1
OUT
3-bit LUT0
IN0
LUT Truth
Table
From Connection
Matrix Output [36]
To Connection Matrix
S0
S1
Input [5]
S0
S1
8-bits NVM
registers [1231:1224]
From Connection
Matrix Output [35]
S0
S1
DFF/Latch
Registers
0
1
Q/nQ
DFF
DFF
D
D
Q
D
Q
nRST/
nRST/
nSET
CLK
CLK
nSET
nRST/nSET
CLK
register [1228]
1-bit NVM
register [1199]
Figure 54: 3-bit LUT0 or DFF3
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GreenPAK Programmable Mixed-Signal Matrix with High
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register [1159] DFF or LATCH Select
register [1158] Output Select (Q or nQ)
register [1157] DFF Initial Polarity Select
register [1156] DFF nRST or nSET Select
register [1155] Active level selection RST/
SET
IN2
IN1
From Connection
Matrix Output [46]
S0
S1
OUT
3-bit LUT3
IN0
LUT Truth
Table
From Connection
Matrix Output [45]
To Connection Matrix
S0
S1
Input [8]
S0
8-bits NVM
registers [1159:1152]
S1
DFF/
LATCH
D
From Connection
Matrix Output [44]
S0
S1
nRST/nSET
CLK
DFF6
Q/nQ
1-bit NVM
register [1174]
Figure 55: 3-bit LUT3 or DFF6
register [1167] DFF or LATCH Select
register [1166] Output Select (Q or nQ)
register [1165] DFF Initial Polarity Select
register [1164] DFF nRST or nSET Select
register [1163] Active level selection for RST/
SET
IN2
From Connection
Matrix Output [49]
S0
S1
IN1
IN0
OUT
3-bit LUT4
LUT Truth
Table
From Connection
Matrix Output [48]
To Connection Matrix
S0
S1
Input [9]
S0
8-bits NVM
registers [1167:1160]
S1
DFF/
LATCH
D
From Connection
Matrix Output [47]
S0
S1
nRST/nSET DFF7
Q/nQ
RST/SET
CLK
1-bit NVM
register [1175]
Figure 56: 3-bit LUT4 or DFF7
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GreenPAK Programmable Mixed-Signal Matrix with High
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register [1247] DFF or LATCH Select
register [1246] Output Select (Q or nQ)
register [1245] DFF Initial Polarity Select
register [1244] DFF nRST or nSET Select
register [1243] Active level selection for RST/
SET
IN2
From Connection
S0
Matrix Output [52]
IN1
IN0
OUT
3-bit LUT5
S1
LUT Truth
Table
From Connection
Matrix Output [51]
To Connection Matrix
S0
S1
S0
S1
Input [10]
8-bits NVM
registers [1247:1240]
DFF/
LATCH
D
From Connection
Matrix Output [50]
S0
S1
nRST/nSET DFF8
RST/SET
Q/nQ
CLK
1-bit NVM
register [1263]
Figure 57: 3-bit LUT5 or DFF8
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GreenPAK Programmable Mixed-Signal Matrix with High
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11.3.1 3-bit LUT or D Flip-Flop Macrocells Used as 3-bit LUTs
Table 52: 3-bit LUT0 Truth Table
Table 54: 3-bit LUT3 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1224]
register [1225]
register [1226]
register [1227]
register [1228]
register [1229]
register [1230]
register [1231]
LSB
register [1152]
register [1153]
register [1154]
register [1155]
register [1156]
register [1157]
register [1158]
register [1159]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 53: 3-bit LUT4 Truth Table
Table 55: 3-bit LUT5 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1160]
register [1161]
register [1162]
register [1163]
register [1164]
register [1165]
register [1166]
register [1167]
register [1240]
register [1241]
register [1242]
register [1243]
register [1244]
register [1245]
register [1246]
register [1247]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
1
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-bit LUT0 is defined by registers [1231:1224]
3-bit LUT3 is defined by registers [1159:1152]
3-bit LUT4 is defined by registers [1167:1160]
3-bit LUT5 is defined by registers [1247:1240]
Table 56 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the four 3-bit LUT logic cells.
Table 56: 3-bit LUT Standard Digital Functions
Function
AND-3
MSB
LSB
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-3
OR-3
NOR-3
XOR-3
XNOR-3
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11.3.2 Initial Polarity Operations
VDD
Data
Clock
POR
Initial Polarity: High
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Initial Polarity: Low
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Figure 58: DFF Polarity Operations with nReset
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VDD
Data
Clock
POR
Initial Polarity: High
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Initial Polarity: Low
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Figure 59: DFF Polarity Operations with nSet
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11.4 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELL OR PWM CHOPPER
There are two macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset inputs, or as PWM Chopper.
When used to implement LUT functions, the 3-bit LUTs each takes in three input signals from the connection matrix and
produces a single output, which goes back into the connection matrix. When used to implement D Flip-Flop function, the three
input signals from the connection matrix go to the data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop,
with the output going back to the connection matrix. It is possible to define the active level for the reset/set input of DFF/LATCH
macrocell. There are both active high-level reset/set (RST/SET) and active low-level reset/set (nRST/nSET) options available,
which are selected by register [1139] and register [1147]. When used to implement PWM Chopper function, the three input
signals from the connection matrix go to the PWM input (PWM) and Blanking Time input (Blanking Time), and Chopper input
(Chop) for the PWM Chopper, with the output (OUT) going back to the connection matrix.
register [1143] DFF or Latch Select
register [1142] Output Select (Q or nQ)
register [1141] DFF Initial Polarity Select
register [1140] DFF nRST or nSET Select
register [1139] Active level selection for RST/SET
S0
IN2
from Connection
Matrix Output [40]
S0
S1
IN1
IN0
OUT
3-bit LUT1
LUT Truth
Table
S1
S0
S1
from Connection
Matrix Output [39]
S0
S1
registers [1143:1136 ]
DFF/Latch
Register
S0
D
to Connection Matrix
Input [6]
S0
S0
S1
nRST/nSET
RST/SET
S1
Q/nQ
from Connection
Matrix Output [38]
DFF4
S0
S1
S1
CLK
1-bit NVM
register [1172]
PWM
Chop
Q/nQ
PWM Chopper0
Blanking time
LUT3_1/DFF4 or
Chopper0 select
register [1264]
Figure 60: 3-bit LUT1 or DFF4
register [1151] DFF or Latch Select
S0
IN2
register [1150] Output Select (Q or nQ)
register [1149] DFF Initial Polarity Select
register [1148] DFF nRST or nSET Select
register [1147] Active level selection for RST/SET
from Connection
Matrix Output [43]
S0
S1
IN1
OUT
3-bit LUT2
LUT Truth
Table
S1
IN0
S0
from Connection
Matrix Output [42]
S0
S1
registers [1151:1144]
DFF/Latch
Register
S0
S1
D
to Connection Matrix
Input [7]
S0
S0
S1
nRST/nSET
RST/SET
S1
Q/nQ
from Connection
Matrix Output [41]
DFF5
S0
S1
S1
CLK
1-bit NVM
register [1173]
PWM
Chop
Q/nQ
PWM Chopper1
Blanking time
LUT3_2/DFF5 or
Chopper1 select
register [1266]
Figure 61: 3-bit LUT2 or DFF5
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GreenPAK Programmable Mixed-Signal Matrix with High
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11.4.1 3-bit LUT or D Flip-Flop or PWM Chopper Macrocells Used as 3-bit LUTs
Table 57: 3-bit LUT1 Truth Table
Table 58: 3-bit LUT2 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1136]
register [1137]
register [1138]
register [1139]
register [1140]
register [1141]
register [1142]
register [1143]
LSB
register [1144]
register [1145]
register [1146]
register [1147]
register [1148]
register [1149]
register [1150]
register [1151]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
1
1
1
MSB
This macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-bit LUT1 is defined by registers [1143:1136]
3-bit LUT2 is defined by registers [1151:1144]
Table 59 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the four 3-bit LUT logic cells.
Table 59: 3-bit LUT Standard Digital Functions
Function
AND-3
MSB
LSB
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-3
OR-3
NOR-3
XOR-3
XNOR-3
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11.4.2 PWM chopper
PWM Chopper function can be used to chop PWM Duty Cycle by Current Comparator signal.
PWM
OUT+
Blanking
Time
PWM
OUT HV OUT
PWM Chopper
OUT
Delay
(falling)
PWM
Period
IN
OUT
Chop
OUT
Current CMP
Figure 62: PWM Chopper Circuit Example
In PWM Chopper mode all internal components of 3-bit LUT or D Flip-Flop, or PWM Chopper Macrocell are connected as
shown in Figure 63.
Mimic
Delay
POR
D
Q
DFF
Output
CLK
Delay
nRST
Mimic
Delay
Invert OUT
Register [1265] for Chopper0
Register [1267] for Chopper1
from PWM OUT+
from Current CMP
from Blanking Time
Combination
Logic
PWM chopper
Figure 63: PWM Chopper Interconnection
This configuration allows ignoring Current Comparator signal during Blanking time during the motor start period. Any active
signal from Current CMP after Blanking time causes PWM Duty Cycle chopping to currently Period end. The following figures
demonstrate PWM Chopper operation.
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PWM
OUT+
PWM
Period
Blanking
time
3us
Curr. CMP
out
OUT
Figure 64: PWM Chopper. Overcurrent Timing Diagram
PWM
OUT+
Blanking
time
3us
Curr. CMP
out
go low after
OUT
blanking time
Figure 65: PWM Chopper. Overcurrent Start During Blanking Time
PWM
OUT+
Blanking
time
Curr. CMP
out
OUT
Don’t go LOW if
blanking is HIGH
Figure 66: PWM Chopper. PWM Duty Cycle is Less than Blanking Time
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PWM
OUT+
PWM
PERIOD
Blanking
time
3us
Curr. CMP
out
OUT
Figure 67: PWM Chopper. 0% Duty Cycle
PWM
OUT+
Blanking
time
3us
Curr. CMP
out
OUT
Figure 68: PWM Chopper. Overcurrent when 100 % Duty Cycle
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11.4.3 Initial Polarity Operations
VDD
Data
Clock
POR
Initial Polarity: High
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Initial Polarity: Low
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Figure 69: DFF Polarity Operations with nReset
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GreenPAK Programmable Mixed-Signal Matrix with High
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VDD
Data
Clock
POR
Initial Polarity: High
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Initial Polarity: Low
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Figure 70: DFF Polarity Operations with nSet
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11.5 3-BIT LUT OR PIPE DELAY/RIPPLE COUNTER MACROCELL
There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay/Ripple Counter.
When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a
single output, which goes back into the connection matrix.
When used as a Pipe Delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK), and Reset (nRST). The Pipe
Delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF
cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell input (IN). Both of the two outputs (OUT0
and OUT1) provide user selectable options for 1 - 16 stages of delay. There are delay output points for each set of the OUT0 and
OUT1 outputs to a 4-input mux that is controlled by registers [1203:1200] for OUT0 and registers [1207:1204] for OUT1. The 4-
input mux is used to control the selection of the amount of delay.
The overall time of the delay is based on the clock used in the SLG47105 design. Each DFF cell has a time delay of the inverse
of the clock time (either external clock or the internal Oscillator within the SLG47105). The sum of the number of DFF cells used
will be the total time delay of the Pipe Delay logic cell. OUT1 Output can be inverted (as selected by register [1197]).
In the Ripple Counter mode, there are 3 options for setting which use 7 bits. There are 3 bits to set nSET value (SV) in the range
from 0 to 7. This value will be set into the Ripple Counter outputs when nSET input goes LOW. End value (EV) will use 3 bits for
setting output code, which will be last code in the cycle. After reaching the EV, the Ripple Counter goes to the first code by the
rising edge on CLK input. The Functionality mode option uses 1 bit. This setting defines how exactly Ripple Counter will operate.
The user can select one of the functionality modes by the register: RANGE or FULL. If the RANGE option is selected, the count
starts from SV. If UP input is LOW the count goes down: SV→EV→EV-1 to SV+1→SV, and others (if SV is smaller than EV), or
SV→SV-1 to EV+1→EV→SV (if SV is bigger than EV). If UP input is HIGH, the count starts from SV up to EV, and others.
In the FULL range configuration, the Ripple Counter functions as follows. If UP input is LOW, the count starts from SV and goes
down to 0. The current counter value jumps to EV and goes down to 0, and others.
If UP input is HIGH, the count goes up starting from SV. The current counter value jumps to 0 and counts up to EV, and others.
See Ripple Counter functionality example in Figure 72.
Every step is executed by the rising edge on CLK input.
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registers [1207:1200]
From Connection
Matrix Output [53]
IN0
From Connection
Matrix Output [54]
IN1
IN2
OUT
3-bit LUT6
From Connection
Matrix Output [55]
Pipe Delay registers [1207:1204]
register [1197]
0
1
0
1
OUT2
OUT1
To Connection
Matrix Input [14]
register [1196]
From Connection
Matrix Output [53]
IN
From Connection
Matrix Output [54]
nRST
16 Flip-Flops
0
OUT1
From Connection
Matrix Output [55]
CLK
To Connection
Matrix Input [13]
1
register [1196]
OUT0
0
OUT0
To Connection
Matrix Input [12]
0
1
1
registers [1203:1200]
1 Pipe OUT
register [1195]
Ripple Counter
3 Flip-Flops
UP
From Connection
Matrix Output [53]
UP/DOWN
Control
OUT0
D
Q
DFF1
CLK
From Connection
Matrix Output [55]
CLK
nQ
nSET
From Connection
Matrix Output [54]
SET
OUT1
OUT2
Control
D
Q
DFF2
CLK
nQ
Mode & SET/END
Value Control
D
Q
DFF3
CLK
nQ
registers [1206:1200]
Figure 71: 3-bit LUT6/Pipe Delay/Ripple Counter
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Figure 72: Example of Ripple Counter Functionality
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11.5.1 3-bit LUT or Pipe Delay Macrocells Used as 3-bit LUT
Table 60: 3-bit LUT6 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [1200]
register [1201]
register [1202]
register [1203]
register [1204]
register [1205]
register [1206]
register [1207]
LSB
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MSB
Macrocell, when programmed for a LUT function, uses an 8-bit register to define their output function:
3-bit LUT6 is defined by registers [1207:1200]
11.6 4-BIT LUT OR D FLIP-FLOP MACROCELL
There is one macrocell that can serve as either 4-bit LUT or as D Flip-Flop. When used to implement LUT functions, the 4-bit
LUT takes in two input signals from the connection matrix and produces a single output, which goes back into the connection
matrix. When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and
clock (CLK) inputs for the Flip-Flop, with the output going back to the connection matrix.
The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:
DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change.
LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output when CLK is
High).
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GreenPAK Programmable Mixed-Signal Matrix with High
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From Connection
register [1223] DFF or LATCH Select
register [1222] Output Select (Q or nQ)
register [1221] DFF Initial Polarity Select
register [1220] Q1 or Q2 Select
register [1219] DFF nRST or nSET Select
register [1218] Active level selection for RST/SET
S0
S1
Matrix Output [59]
IN3
IN2
From Connection
Matrix Output [58]
S0
S1
IN1
IN0
OUT
4-bit LUT0
LUT Truth
Table
From Connection
Matrix Output [57]
To Connection Matrix
S0
S1
Input [11]
S0
S1
16-bits NVM
registers [1223:1208]
From Connection
Matrix Output [56]
S0
S1
DFF/Latch
Registers
0
Q/nQ
DFF
DFF
D
D
Q
1
D
Q
nRST/
nSET
CL
nRST/
nSET
CL
nRST/nSET
CLK
register [1220]
1-bit NVM
register [1198]
Figure 73: 4-bit LUT0 or DFF9
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11.6.1 4-bit LUT Macrocell Used as 4-bit LUT
Table 61: 4-bit LUT0 Truth Table
IN3
0
IN2
0
IN1
0
IN0
0
OUT
register [1208]
register [1209]
register [1210]
register [1211]
register [1212]
register [1213]
register [1214]
register [1215]
register [1216]
register [1217]
register [1218]
register [1219]
register [1220]
register [1221]
register [1222]
register [1223]
LSB
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
MSB
This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:
4-bit LUT1 is defined by registers [1223:1208]
Table 62: 4-bit LUT Standard Digital Functions
Function
AND-4
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-4
OR-4
NOR-4
XOR-4
XNOR-4
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12 Multi-Function Macrocells
The SLG47105 has 5 Multi-Function macrocells that can serve as more than one logic or timing function. In each case, they can
serve as a LUT, DFF with flexible settings, or as CNT/DLY with multiple modes such as One Shot, Frequency Detect, Edge Detect,
and others. Also, the macrocell is capable to combine those functions: LUT/DFF connected to CNT/DLY or CNT/DLY connected
to LUT/DFF, see Figure 74.
See the list below for the functions that can be implemented in these macrocells:
Four macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-bit Counter/Delays
One macrocell that can serve as a 4-bit LUT/D Flip-Flop and as 16-bit Counter/Delay/FSM
To Connection Matrix
To Connection Matrix
From Connection
Matrix
To Connection
Matrix
From Connection
Matrix
To Connection
Matrix
LUT
or
DFF
LUT
or
DFF
CNT/DLY
CNT/DLY
Figure 74: Possible Connections Inside Multi-Function Macrocell
Inputs/Outputs for the 5 Multi-Function macrocells are configured from the connection matrix with specific logic functions being
defined by the state of NVM bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined
function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
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12.1 3-BIT LUT OR DFF/LATCH WITH 8-BIT COUNTER/DELAY MACROCELLS
There are four macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-bit Counter/Delays.
When used to implement LUT functions, the 3-bit LUTs each takes in three input signals from the connection matrix and produces
a single output, which goes back into the connection matrix or can be connected to CNT/DLY's input.
When used to implement D Flip-Flop function, the three input signals from the connection matrix go to the data (D), clock (CLK),
and Reset/Set (nRST/nSET) inputs of the Flip-Flop, with the output going back to the connection matrix or to the CNT/DLY's input.
When used to implement Counter/Delays, each macrocell has a dedicated matrix input connection. For flexibility, each of these
macrocells has a large selection of internal and external clock sources, as well as the option to chain from the output of the
previous (N-1) CNT/DLY macrocell, to implement longer count/delay circuits. These macrocells can also operate in a One-Shot
mode, which will generate an output pulse of user-defined width. They can also operate in a Frequency Detection or Edge
Detection mode.
Counter/Delay macrocell has an initial value, which defines its initial value after GPAK is powered up. It is possible to select initial
Low or initial High, as well as the initial value defined by a Delay In signal.
For example, in case the initial LOW option is used, the rising edge delay will start operation.
For timing diagrams refer to Section 12.3.
Only CNT0 and CNT4 current count value can be read via I2C. However, it is possible to change the counter data (value counter
starts operating from) for any macrocell using I2C write commands. In this mode, it is possible to load count data immediately
(after two DFF) or after counter ends counting. See Section 21.5.4 for further details.
Note: After two DFF – counters initialize with counter data = 0 after POR.
Initial state = 1 – counters initialize with counter data = 0 after POR.
Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.
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GreenPAK Programmable Mixed-Signal Matrix with High
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12.1.1 3-bit LUT or 8-bit CNT/DLY Block Diagrams
register [1039] DFF or LATCH Se-
lect
From Connection
register [1038] Output Select (Q or
nQ)
Matrix Output [62]
IN2
register [1037] (nRST or nSET)
from matrix Output
register [1036] DFF Initial Polarity
S0
3-bit LUT7
S0
S1
OUT
IN1
IN0
S1
LUT Truth
Table
From Connection
Matrix Output [61]
To Connection
S0
S0
S1
S0
S1
Matrix Input [20]
8-bits NVM
registers [1039:1032]
S1
DFF
Registers
D
From Connection
Matrix Output [60]
S0
S1
S0
S1
nRST/nSET
DFF/
Q/nQ
LATCH10
CLK
register [925]
LUT/DFF Sel
registers [1047:1040]
registers [924:921]
Mode Sel
CNT
Data
ext_CLK
To Connection
Matrix Input [16]
0
S0
OUT
CNT/DLY1
DLY_IN/CNT Reset
S0
S1
S2
S1
S2
S3
Config
Data
0
S3
registers [938:926]
Figure 75: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT7/DFF10, CNT/DLY1)
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register [1055] DFF or LATCH Select
register [1054] Output Select (Q or
nQ)
register [1053] (nRST or nSET) from
matrix Output
register [1052] DFF Initial Polarity Se-
lect
From Connection
Matrix Output [65]
IN2
S0
3-bit LUT8
S0
S1
OUT
IN1
IN0
S1
LUT Truth
Table
From Connection
Matrix Output [64]
To Connection
S0
S0
S1
S0
S1
Matrix Input [21]
8-bits NVM
registers [1055:1048]
S1
DFF
Registers
D
From Connection
Matrix Output [63]
S0
S1
S0
S1
DFF/
LATCH11
nRST/nSET
Q/nQ
CLK
register [943]
LUT/DFF Sel
registers [1063:1056]
registers [942:939]
Mode Sel
CNT
Data
ext_CLK
To Connection
Matrix Input [17]
0
S0
OUT
CNT/DLY2
DLY_IN/CNT Reset
S0
S1
S2
S1
S2
S3
Config
Data
0
S3
registers [956:944]
Figure 76: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF11, CNT/DLY2)
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GreenPAK Programmable Mixed-Signal Matrix with High
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register [1071] DFF or LATCH Select
register [1070] Output Select (Q or nQ)
register [1069] (nRST or nSET) from
matrix Output
register [1068] DFF Initial Polarity Se-
lect
From Connection
Matrix Output [68]
IN2
S0
3-bit LUT9
S0
S1
OUT
IN1
IN0
S1
LUT Truth
Table
From Connection
Matrix Output [67]
To Connection
S0
S0
S1
S0
S1
Matrix Input [22]
8-bits NVM
registers [1071:1064]
S1
DFF
Registers
D
From Connection
Matrix Output [66]
S0
S1
S0
S1
DFF/
LATCH12
nRST/nSET
Q/nQ
CLK
register [959]
LUT/DFF Sel
registers [1079:1072]
registers [967:964]
Mode Sel
CNT
Data
ext_CLK
To Connection
Matrix Input [18]
0
S0
OUT
CNT/DLY3
DLY_IN/CNT Reset
S0
S1
S2
S1
S2
S3
Config
Data
0
S3
registers [958:957], [963:960], [974:968]
Figure 77: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF12, CNT/DLY3)
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register [1087] DFF or LATCH Se-
lect
From Connection
register [1086] Output Select (Q or
nQ)
Matrix Output [71]
IN2
register [1085] (nRST or nSET)
from matrix Output
register [1084] DFF Initial Polarity
S0
3-bit LUT10
S0
S1
OUT
IN1
IN0
S1
LUT Truth
Table
From Connection
Matrix Output [70]
To Connection
S0
S0
S1
S0
S1
Matrix Input [23]
8-bits NVM
registers [1087:1080]
S1
DFF
Registers
D
From Connection
Matrix Output [69]
S0
S1
S0
S1
nRST/nSET DFF/
Q/nQ
LATCH13
CLK
register [979]
LUT/DFF Sel
registers [1095:1088]
registers [983:980]
Mode Sel
CNT
Data
ext_CLK
To Connection
Matrix Input [19]
0
S0
OUT
CNT/DLY4
DLY_IN/CNT Reset
S0
S1
S2
S1
S2
S3
Config
Data
0
S3
registers [978:975], [992:984]
Figure 78: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF13, CNT/DLY4)
There is a possibility to use LUT/DFF and CNT/DLY simultaneously.
Note: It is not possible to use LUT and DFF at once, one of these macrocells must be selected.
Case 1. LUT/DFF in front of CNT/DLY. Three input signals from the connection matrix go to previously selected LUT or DFF's
inputs and produce a single output which goes to a CND/DLY input. In its turn Counter/Delay's output goes back to the matrix.
Case 2. CNT/DLY in front of LUT/DFF. Two input signals from the connection matrix go to CND/DLY's inputs (IN and CLK). Its
output signal can be connected to any input of previously selected LUT or DFF, after which the signal goes back to the matrix.
Case 3. Single LUT/DFF or CNT/DLY. Also, it is possible to use a standalone LUT/DFF or CNT/DLY. In this case, all inputs
and output of the macrocell are connected to the matrix.
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12.1.2 3-bit LUT or CNT/DLYs Used as 3-bit LUTs
Table 63: 3-bit LUT7 Truth Table
Table 65: 3-bit LUT8 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1032]
register [1033]
register [1034]
register [1035]
register [1036]
register [1037]
register [1038]
register [1039]
LSB
register [1048]
register [1049]
register [1050]
register [1051]
register [1052]
register [1053]
register [1054]
register [1055]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 64: 3-bit LUT9 Truth Table
Table 66: 3-bit LUT10 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1064]
register [1065]
register [1066]
register [1067]
register [1068]
register [1069]
register [1070]
register [1071]
register [1080]
register [1081]
register [1082]
register [1083]
register [1084]
register [1085]
register [1086]
register [1087]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
1
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-bit LUT7 is defined by registers [1039:1032]
3-bit LUT8 is defined by registers [1055:1048]
3-bit LUT9 is defined by registers [1071:1064]
3-bit LUT10 is defined by registers [1087:1080]
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12.2 4-BIT LUT OR DFF/LATCH WITH 16-BIT COUNTER/DELAY MACROCELL
There is one macrocell that can serve as either 4-bit LUT or as 16-bit Counter/Delay. When used to implement LUT function, the
4-bit LUT takes in four input signals from the Connection Matrix and produces a single output, which goes back into the
Connection Matrix. When used to implement 16-bit Counter/Delay function, two of four input signals from the connection matrix
go to the external clock (EXT_CLK) and reset (DLY_IN/CNT Reset) for the Counter/Delay, with the output going back to the
connection matrix.
This macrocell has an optional Finite State Machine (FSM) function. There are two additional matrix inputs for Up and Keep to
support FSM functionality.
This macrocell can also operate in a one-shot mode, which will generate an output pulse of user-defined width.
This macrocell can also operate in a frequency detection or edge detection mode.
This macrocell can have its active count value read via I2C. See Section 21.5.4 for further details.
Note: After two DFF – counters initialize with counter data = 0 after POR.
Initial state = 1 – counters initialize with counter data = 0 after POR.
Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.
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GreenPAK Programmable Mixed-Signal Matrix with High
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12.2.1 4-bit LUT or DFF/LATCH with 16-bit CNT/DLY Block Diagram
From Connection
Matrix Output [75]
IN3
register [1015] DFF or Latch Select
register [1014] DFF Output Select
(Q or nQ)
register [1013] DFF Initial Polarity
Select
S0
S1
S1
S0
S1
S0
IN2
IN1
From Connection
Matrix Output [74]
0
4-bit LUT1
S1
S0
S0
S1
S1
S0
0
OUT
IN0
LUT Truth
Table
From Connection
Matrix Output [73]
S1
S0
To Connection
S0
S0
S1
S1
S0
Matrix Input [25]
registers
[897:896] ≠ 01
16-bits NVM
registers [1015:1000]
1
S1
From Connection
Matrix Output [72]
DFF
D
S1
S0
Registers
S0
S1
S1
S0
nSET
Q/nQ
DFF14
1
nRST
CLK
LUT/DFF Sel
register [900]
registers [902:901]
registers [1031:1016]
CNT
registers [899:896]
0
S0
S1
S2
S3
Data
ext_CLK
CMO* [74]
CMO* [73]
S0
S1
To Connection
Matrix Input [24]
S0
0
0
S0
S1
S2
S3
CMO* [75]
CMO* [74]
CMO* [73]
CMO* [72]
S1
S2
S3
OUT
CNT/DLY0
DLY_IN/CNT Reset
CMO* [73]
S1
S0
From Connection
Matrix Output [74]
0
KEEP
UP
From Connection
Matrix Output [75]
FSM
S1
S0
Config
Data
registers [902:901]
0
Note: CMO - Connection Matrix Output
register [897:896] = 01
Figure 79: 16-bit Multi-Function Macrocell Block Diagram (4-bit LUT1/DFF14, CNT/DLY/FSM0)
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12.2.2 4-bit LUT or 16-bit Counter/Delay Macrocells Used as 4-bit LUTs
Table 67: 4-bit LUT1 Truth Table
IN3
0
IN2
0
IN1
0
IN0
0
OUT
register [1000]
register [1001]
register [1002]
register [1003]
register [1004]
register [1005]
register [1006]
register [1007]
register [1008]
register [1009]
register [1010]
register [1011]
register [1012]
register [1013]
register [1014]
register [1015]
LSB
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
MSB
This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:
4-bit LUT1 is defined by registers [1015:1000]
Table 68: 4-bit LUT Standard Digital Functions
Function
AND-4
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-4
OR-4
NOR-4
XOR-4
XNOR-4
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12.3 CNT/DLY/FSM TIMING DIAGRAMS
12.3.1 Delay Mode CNT/DLY0 to CNT/DLY4
Delay In
Asynchronous delay variable
Asynchronous delay variable
OSC: force Power-On
(always running)
Delay Output
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
Delay In
offset
offset
OSC: auto Power-On
(powers up from delay in)
Delay Output
delay = offset + period x (counter data + 1)
See offset in Table 24
delay = offset + period x (counter data + 1)
See offset in Table 24
Figure 80: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3
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The macrocell shifts the respective edge to a set time and restarts by appropriate edge. It works as a filter if the input signal is
shorter than the delay time.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
Delay time
Delay Function
Rising Edge Detection
t
Delay Function
Falling Edge Detection
t
Delay Function
Both Edge Detection
t
Figure 81: Delay Mode Timing Diagram for Different Edge Select Modes
12.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY4
RESET_IN
CLK
Counter OUT
4 CLK period pulse
Count start in first rising edge CLK
Figure 82: Counter Mode Timing Diagram without Two DFFs Synced Up
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Note 1 This mode may cause counter data to be loaded wrong, if reset releases at the same time when the clock appears. As a
solution please use the mode with two DFFs synced up.
RESET_IN
CLK
Counter OUT
4 CLK period pulse
Count start in 0 CLK after reset
Figure 83: Counter Mode Timing Diagram with Two DFFs Synced Up
12.3.3 One-shot Mode CNT/DLY0 to CNT/DLY4
This macrocell will generate a pulse whenever a selected edge is detected on its input. Register bits set the edge selection. The
pulse width is determined by counter data and clock selection properties.
The output pulse polarity (non-inverted or inverted) is selected by register bit. Any incoming edges will be ignored during the pulse
width generation. The following diagram shows one-shot function for non-inverted output.
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.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Delay time
One-Shot Function
Rising Edge Detection
One-Shot Function
Falling Edge Detection
t
t
One-Shot Function
Both Edge Detection
Figure 84: One-Shot Function Timing Diagram
This macrocell generates a high level pulse with a set width (defined by counter data) when detecting the respective edge. It does
not restart while pulse is high.
12.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY4
Rising Edge: The output goes high if the time between two successive edges is less than the delay. The output goes low if the
second rising edge has not come after the last rising edge in specified time.
Falling Edge: The output goes high if the time between two falling edges is less than the set time. The output goes low if the
second falling edge has not come after the last falling edge in specified time.
Both Edge: The output goes high if the time between the rising and falling edges is less than the set time, which is equivalent to
the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not come.
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Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Delay time
Frequency Detector Function
Rising Edge Detection
Frequency Detector Function
Falling Edge Detection
t
t
Frequency Detector Function
Both Edge Detection
Figure 85: Frequency Detection Mode Timing Diagram
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12.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY4
The macrocell generates high level short pulse when detecting the respective edge.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Edge Detector Function
Rising Edge Detection
Edge Detector Function
Falling Edge Detection
t
t
Edge Detector Function
Both Edge Detection
Figure 86: Edge Detection Mode Timing Diagram
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12.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY4
In Delayed Edge Detection Mode, High level short pulses are generated on the macrocell output after the configured delay time,
if the corresponding edge was detected on the input.
If the input signal is changed during the set delay time, the pulse will not be generated. See Figure 87.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Delay time
Delayed Edge Detector Function
Rising Edge Detection
Delayed Edge Detector Function
Falling Edge Detection
t
t
Delayed Edge Detector Function
Both Edge Detection
Figure 87: Delayed Edge Detection Mode Timing Diagram
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12.3.7 CNT/FSM Mode CNT/DLY0
RESET IN
KEEP
COUNT END
CLK
3
2
1
0
3
2
1
0
3
2
1
3
2
1
0
0
Q
Note: Q = current counter value
Figure 88: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3
SET IN
KEEP
COUNT END
CLK
2
1
0
3
2
1
0
3
3
2
1
2
1
0
3
3
Q
Note: Q = current counter value
Figure 89: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3
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RESETI N
KEEP
COUNT END
CLK
65535
65533 65534
5
6
7
8
9
3
4
5
3
4
5
1
2
3
4
0
Q
Note: Q = current counter value
Figure 90: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3
SET IN
KEEP
COUNT END
CLK
65533 65534 65535
8
9
10 11 12
3
4
5
3
4
5
4
5
6
7
3
Q
Note: Q = current counter value
Figure 91: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator Is Forced On, UP = 1) for Counter Data = 3
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12.3.8 The Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes
There is a difference in counter value for Counter and Delay/One-Shot/Frequency Detect modes. Compared to Counter mode,
in Delay/One-Shot/Frequency Detect modes the counter value is shifted for two rising edges of the clock signal.
One-Shot/Freq. SET/Delay IN
CLK
CNT OUT
3
2
1
0
0
3
CNT Data
2
DLY OUT
3
3
2
Delay Data
1
3
3
3
One-Shot OUT
One-Shot Data
3
3
2
3
1
3
3
Figure 92: Counter Value, Counter Data = 3
12.4 WAKE AND SLEEP CONTROLLER
SLG47105 has a Wake and Sleep function for two General Purpose ACMPs. The macrocell CNT/DLY0 can be reconfigured for
this purpose by setting register [918] = 1 and registers [904:903] = 11. The WS serves for power saving, it allows to switch on and
off selected General Purpose ACMPs on a selected bit of 16-bit counter.
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Note 1 BG/Analog_Good time is long and should be considered in the wake and sleep timing in case it dynamically powers on/off.
Note 2 Wake time should be long enough to make sure ACMP and Vref have enough time to get a sample before going to sleep.
Power Control
from Connection Matrix Output[90] for 2.048 kHz OSC0
OSC0
WS Controller
CNT0_OUT
to Connection Matrix Input[24]
cnt_end
ck CNT0
Analog Control Block
Divider
CLK_OSC
WS_PD
ACMPxH WS EN[1:0]
register [672] / [673]
2
bg/regulator
pd
WS_out
form Connection Matrix
Output [87:86]
WS_PD
(from OSC PD)
ACMPxH_PD
2
WS_PD to WS OUT
state selection register [917]
WS_out
WS clock freq. selection
registers [910:907]
WS ratio control data
registers [1031:1016]
ACMPxH
WS mode: normal or short wake
register [674]
0
1
ACMPxH OUT
2
to Connection Matrix
Input [46:47]
Note: WS_PD is High at OSC0 power down
ACMPxH_PD
2
WS_out
BG/Analog_Good
Figure 93: Wake/Sleep Controller
time between Reset goes low
and 1st WS clock rsing edge
Force Wake
CNT_RST
(From Connection Matrix)
ACMP_PD is High
(From Connection Matrix)
CNT0_out
(To Connection Matrix)
WS_out
(internal signal)
Data is
BG/Analog_Good
(internal signal)
Sleep Mode
ACMP LATCHes Last Data
Normal ACMP
Operation
ACMP follows input
Sleep Mode
ACMP LATCHes New Data
Normal ACMP
Sleep Mode
ACMP LATCHes
New Data
Operation
ACMP follows input
BG/Analog
Startup time*
BG/Analog
Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.
Figure 94: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used
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time between Reset goes low
and 1st WS clock rsing edge
Force Wake
CNT_RST
(From Connection Matrix)
ACMP_PD is High
(From Connection Matrix)
CNT0_out
(To Connection Matrix)
WS_out
(internal signal)
Data is LATCHed
Data is LATCHed
BG/Analog_Good
(internal signal)
Sleep Mode
Sleep Mode
Normal ACMP
Operation for short time
ACMP follows input
Sleep Mode
ACMP LATCHes
New Data
ACMP LATCHes Last Data
ACMP LATCHes New Data
Normal ACMP
Operation for short time
ACMP follows input
BG/Analog
Startup time*
BG/Analog
Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.
Figure 95: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used
time between Reset goes low
and 1st WS clock rsing edge
Force Sleep
CNT_SET
(From Connection Matrix)
ACMP_PD is High
(From Connection Matrix)
CNT0_out
(To Connection Matrix)
WS_out
(internal signal)
Data is
BG/Analog_Good
(internal signal)
Sleep Mode
ACMP LATCHes Last Data
Normal ACMP
Operation
ACMP follows input
Sleep Mode
ACMP LATCHes New Data
BG/Analog
Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.
Figure 96: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used
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time between Reset goes low
and 1st WS clock rsing edge
Force Sleep
CNT_RST
(From Connection Matrix)
ACMP_PD is High
(From Connection Matrix)
CNT0_out
(To Connection Matrix)
WS_out
(internal signal)
Data is LATCHed
BG/Analog_Good
(internal signal)
Sleep Mode
Sleep Mode
ACMP LATCHes New Data
ACMP LATCHes Last Data
Normal ACMP
Operation for short time
ACMP follows input
BG/Analog
Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.
Figure 97: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Set is Used
Note: If low power BG is powered on/off by WS, the wake time should be longer than 2.1 ms. The BG/analog startup time will
take maximal 2 ms. Therefore, 8 periods of the Oscillator0 is recommended for the wake time, when BG is configured to Auto
Power mode. If low power BG is always on, Oscillator0 period is longer than required wake time. The short wake mode can be
used to reduce the current consumption. The short wake mode is edge triggered when the wake signal is latched by a rising edge
and released the Power-On signal after the ACMP output data is latched. This allows to have a valid ACMP data for any type of
wake signal and have the optimized current consumption.
To use any ACMP under WS controller, the following settings must be done:
ACMP Power-Up Input from matrix = 1 (for each ACMP separately);
CNT/DLY0 must be set to Wake and Sleep Controller function (for all ACMP);
Register WS → enable (for each ACMP separately);
CNT/DLY0 set/reset input = 0 (for all ACMP).
As the OSC, any oscillator with any pre-divider can be used. The user can select a period of time while the ACMP is sleeping in
a range of 1 - 65535 clock cycles. Before they are sent to sleep their outputs are latched, so the ACMPs remain their state (High
or Low) while sleeping.
WS controller has the following settings:
Wake and Sleep Output State (High/Low)
If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = High, the
ACMP is continuously on.
If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = Low, the
ACMP is continuously off.
Both cases WS function is turned off.
Counter Data (Range: 1 - 65535)
The User can select wake and sleep ratio of the ACMP; counter data = sleep time, one clock = wake time.
Q mode - defines the state of WS counter data when Set/Reset signal appears Reset - when active signal appears, the WS
counter will reset to zero and High level signal on its output will turn on the ACMPs. When Reset signal goes out, the WS
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counter will go Low and turn off the ACMP until the counter counts up to the end. Set - when active signal appears, the WS
counter will stop and Low level signal on its output will turn off the ACMP. When Set signal goes out, the WS counter will go on
counting and High level signal will turn on the ACMP while counter is counting up to the end.
Note: The OSC0 matrix power down to control ACMP WS is not supported for short wait time option.
Edge Select defines the edge for Q mode
High level Set/Reset - switches mode Set/Reset when level is High
Note: Q mode operates only in case of "High Level Set/Reset”.
Wake time selection - time required for wake signal to turn the ACMPxH on
Normal Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on until
WS signal is Low again. Wake time is one clock period. It should be longer than BG turn on time and minimal required com-
paring time of the ACMP.
Short Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on for 1 µs
and turn off regardless of WS signal. The WS signal width does not matter.
Keep - pauses counting while Keep = 1
Up - reverses counting
If Up = 1, CNT is counting up from user selected value to 65535.
If Up = 0, CNT is counting down from user selected value to 1.
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13 Pulse Width Modulator Macrocell (PWM)
The SLG47105 has two PWM blocks. Inputs/Outputs for the macrocells are configured from the connection matrix with specific
logic functions being defined by the state of NVM bits.
PWM macrocell features:
8-bit (7-bit) PWM Resolution
I2C/Matrix/Auto dynamically changeable Duty Cycle
Changeable Period by changing PWM clock source
Flexible OSC-integrated divider for PWM period selection
I2C Duty cycle read/write
Synchronous change of all PWM blocks by sequential I2C write command
Configurable dead band option for OUT+ and OUT-
16 Preset Duty Cycle Registers Switching Mode (for PWM sine or other waveforms)
Autostop at 0 % and 100 % of PWM duty cycle value
Synchro OFF Mode (wait for PWM period end before stop block)
Inv/non-Inv macrocell Output options
From 0 %, 0.4 % to 99.6 %,100 % Duty cycle for 8-bit resolution.
13.1 8-BIT/7-BIT PWM CONFIGURATIONS
When configured as PWM, this macrocell has an 8-bit resolution. It is also possible to select 7-bit PWM resolution if the higher
PWM frequency is needed.
The PWM block consists of two 8-bit counters. First one, named PWM Period CNT, is used to create PWM period and the
second one, named PWM Duty Cycle CNT, is used to set PWM Duty Cycle and to make dynamic changes in PWM functionality.
There is an ability to change the Duty Cycle from 0 % to 100 %. The PWM duty cycle step is 0.4 % for 8-bit resolution and 0.8 %
for 7-bit resolution mode. This step is constant in the whole range. Both 0 % and 100 % are included.
13.2 PWM INPUTS
Duty Cycle CNT Up/Down is the signal for defining the direction of duty cycle change.
If Duty Cycle CNT Up/Down = 1, the duty cycle increases from current value up to 255.
If Duty Cycle CNT Up/Down = 0, the duty cycle decreases from current value down to 0.
Duty Cycle CNT Keep/Stop.
When Keep function is selected (register [1461] = 0 for PWM0 and register [1479] = 0 for PWM1) HIGH logic level on this
input disables the change of Duty Cycle CNT (clock for Duty Cycle CNT is blocked). However, PWM block still generates
PWM output with a constant duty cycle.
When Stop function is selected (register [1461] = 1 for PWM0 and register [1479] = 1 for PWM1) HIGH logic level on this
input disables the change of both Duty Cycle CNT and PWM Period CNT. Consequently, if Stop signal is active (logic
HIGH) the output of PWM block remains constant.
Note that if no other macrocells except PWM block use the internal OSC, the logic HIGH on Stop input disables the work of
internal OSC that is used as a clock source for PWM Period CNT. For this case, logic LOW on this input enables OSC
again.
Duty Cycle CNT CLK is the clock signal for incrementing/decrementing duty cycle value. Keep in mind that the actual duty
cycle value will be updated during the next PWM period.
Power-down (PD) is an active high-level signal for updating Duty Cycle to default user-defined value. Keep in mind, that user
can change the default Duty Cycle value via I2C. The PD signal will apply right away when Sync Off (register [1301] = 1 for
PWM0 and register [1475] = 1 for PWM1) and after PWM period is completed when Sync On (register [1301] = 0 for PWM0
and register [1475] = 0 for PWM1, (Note )). HIGH logic level on PD input disables the change of all PWM internal counters
and stops the internal oscillator (if internal OSC isn't used by other macrocells) (see Section 13.10 Sync On/Off setting for
Power-down signal). This function is individual for each PWM block.
Note that for async mode a minimal time duration for HIGH level at PD input is 100 ns, which guarantee PWM response. A
pulse shorter than 100 ns might be ignored. An input pulse will be extended internally to this minimal required time to power
down the PWM block.
Ext PWM Period CNT CLK is clock input for PWM Period CNT. The clock at this input defines PWM signal frequency. PWM
Period CNT CLK comes from the internal predefined clock or from the matrix for the high flexibility of PWM frequency.
Note: First PWM period will be 2-3 clocks longer after PD signal is released.
13.3 PWM OUTPUTS
OUT+: PWM positive output
OUT-: PWM negative output
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PWM_PERIOD: PWM start period pulse (the duration of the high level is equal to one period of the PERIOD CNT CLK)
13.4 I2C/MATRIX/AUTO DYNAMICALLY CHANGEABLE DUTY CYCLE AND PERIOD
Duty Cycle in PWM macrocell can be changed in two ways:
1. PWM Duty Cycle CNT block has two parameters: Counter Data and Current Counter Value. The Current Counter Value
defines PWM Duty Cycle. Counter Data of PWM Duty Cycle CNT can be changed by I2C commands with a reload into Current
Counter Value. In this case, I2C Master can change PWM Duty Cycle by I2C. Therefore, Counter Data of PWM Duty Cycle CNT
must support change via I2C.
2. Matrix changeable Duty Cycle. In this case "Duty Cycle CNT CLK" and "Duty Cycle CNT Up/Down" inputs are used. Rising
edge at "Duty Cycle CNT CLK" changes Current Counter Value corresponding to "Duty Cycle CNT Up/Down" input state: if
"Duty Cycle CNT Up/Down" is LOW then Current Counter Value decreases and vice versa.
PWM period (frequency) can be changed only by changing PWM Period CNT Clock source. There are several different clock
options available for user selection. Therefore, for PWM frequency flexibility an OSC-integrated CNT divider can be used.
13.5 I2C PWM DUTY CYCLE READ/WRITE
The master I2C should be able to reliably read and write duty cycle value into PWM block. Synchro Buffer is used for correct I2C
reading of actual PWM duty cycle. The I2C command has some time duration. Synchro Buffer captures actual PWM duty cycle
for read command and I2C Master can read this data without errors.
The I2C Master can change PWM duty cycle via I2C write command. The newly written PWM duty cycle value will be loaded (but
not applied) to the PWM block as the default value. The load will happen when I2C "stop" command is issued. To apply a default
value to PWM block user must set the "I2C Trigger" bit to 1 via I2C interface. Note, that this value will be applied after the current
PWM period.
If the user wants to change both PWM blocks simultaneously, I2C sequential write command must be used.
Note: Avoid the change of PD signal during I2C read, since it causes the buffer value to update.
13.6 FLEXIBLE OSC-INTEGRATED DIVIDER
The OSC-integrated divider is built into 25 MHz OSC to configure the PWM period. This divider can be used for other chip
resources. There is 8-bit Counter with the source from OSC pre-divider and output to the matrix or directly to CNT/DLY block as
one possible selection. In many cases, for all PWM macrocells, the same clock frequency is used. It is possible to use this
Flexible OSC divider for fine frequency tuning of PWM cells.
The counter in flexible divider can be enabled/disabled by the register bit [741] only. When the counter in flexible divider is
enabled it will start to count down from the counter data till 0. That is why the frequency division is counter data + 1. Minimum
frequency after Flexible OSC-integrated Divider is at least twice smaller than input Flexible OSC-integrated Divider frequency.
Counter won‘t count with 0b00000000 counter data. There is a separate register bit selection to enable the flexible divider output
to the connection matrix.
Counter flexible divider resets with POR or RESET signal.
13.7 INVERTED OUTPUT OPTION
By default, PWM output begins from HIGH logic level and after reaching duty cycle value, output changes to LOW logic level.
Optionally the user can invert outputs of PWM block.
Each PWM macrocell Outputs has an inverter option enabled by registers. It is necessary for simple driving of different LED
types (common Anode/common Cathode), and others. Each OUT+ and OUT- outputs has one separate register to select its
inverted/non-inverted output option.
13.8 CHANGEABLE DEAD BAND OPTION FOR OUT+ AND OUT-
Dead band parameter is needed to drive external power FETs. The dead band helps to avoid short through for high power FETs.
Dead band parameter is configurable for driving different external transistor. It is possible to select no dead band time or dead
band equal to one, two or three PWM Period clock cycles.
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GreenPAK Programmable Mixed-Signal Matrix with High
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HVDD
HV_GPOx
DeadBand
PWR-GND
PWM OUT +
Output Polarity selection
register = 0
NMOS_H
V1
HV_GPO
R_pdown3
t
PWM OUT -
(Inverted)
Rload
Output Polarity selection
PWM
register = 1
Out +
Out -
t
DeadBand
NMOS_L
V2
HV_GPO
R_pdown4
PWM period
Figure 98: PWM Output Waveforms and Test Circuit Example for Driving NMOS FETs
DeadBand
R_pup
PWM OUT +
V
1
HV_GP
O
PMOS
(Inverted)
Output Polarity selection
register = 1
t
t
Rload
PWM
Out+
Out-
PWM OUT -
(Inverted)
Output Polarity selection
register = 1
NMO
S
V
2
HV_GP
O
DeadBand
PWM period
R_pdow
n
Figure 99: PWM Output Waveforms and Test Circuit Example for Driving NMOS and PMOS FETs
Note that external FETs must have Pull-up/Pull-down resistors between Gate and Source terminals to avoid unpredictable
behavior of FETs when output pins of SLG47105 are in Hi-Z state (Sleep Mode).
The waveforms for Phase Correct PWM Mode are shown in Figure 100. Note that in Phase Correct PWM mode dead band
delay is applied after phase correction, Figure 106.
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GreenPAK Programmable Mixed-Signal Matrix with High
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DeadBand
PWM OUT +
t
t
PWM OUT -
(Inverted)
DeadBand
PWM period
PWM period
PWM period
PWM period
Figure 100: PWM Output Waveforms for Phase Correct PWM Mode
13.9 INITIAL PWM VALUE
Initial PWM duty cycle value is selected by Counter Data of PWM Duty Cycle CNT for regular mode. If Preset Registers Mode is
selected, the initial value of PWM Duty Cycle CNT (Counter Data) is the preset registers address. Please refer to Section 13.11.
13.10 SYNC ON/OFF SETTING FOR POWER-DOWN SIGNAL
"SYNC On/Off" registers define the behavior of Power-down signal. This is the individual setting for each PWM macrocell. If this
option is disabled (register [1301] for PWM0 = 1 and register [1475] = 1 for PWM0), the PWM output goes low right away by
active Power-down, Figure 101. If this option is enabled (register [1301] for PWM0 = 0 and register [1475] = 0 for PWM0), the
PWM block will finish the current PWM period and then will go low, Figure 104.
SYNC On/Off has no effect on duty cycle change via I2C. In the case of duty cycle change via I2C interface, new duty cycle
value will be applied to PWM macrocell only after finishing the current PWM period.
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Dead Band = 0 clk
Sync On/Off = 1
(Asynchronous Power-Down)
200
default value
200
default value
Counter Data of
Duty Cycle CNT
t
200
201
202
200
200
201
200
200
201
202
200
default value
Duty Cycle CNT
Duty Cycle
t
t
t
t
t
t
t
200
default value
200
201
201
200
201
DUTY_CYCLE_CLK
(PWM block input)
T
T*
T
T + dT
T*
T + dT
T*
PERIOD_CNT_CLK
(From internal OSC)
dT
dT
OUT+
(PWM block output)
78.4%
78.4%
X%
78.4%
X%
78.4%
X%
OUT-
(PWM block output)
UP/DOWN
(PWM block input)
POWER_DOWN
(PWM block input)
t
t
OSC enable
(Internal signal)
Figure 101: Power-Down with SYNC On/Off = 1 and Dead Band = 0 CLK
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Dead Band = 1...3 clk (Rising edges of OUT+ and OUT- are delayed on DB time)
Sync On/Off = 1 (Asynchronous Power-Down)
200
default value
200
default value
Counter Data of
Duty Cycle CNT
t
t
t
t
t
t
t
t
200
201
202
200
201
202
201
200
200
201
200
default value
Duty Cycle CNT
Duty Cycle
200
default value
201
200
200
201
200
DUTY_CYCLE_CLK
(PWM block input)
T*
T
T
T + dT
78.4%
T*
T + dT
T*
PERIOD_CNT_CLK
(From internal OSC)
dT
dT
OUT+
(PWM block output)
78.4%
X%
78.4%
X%
78.4%
X%
OUT-
(PWM block output)
DB
DB
DB
UP/DOWN
(PWM block input)
POWER_DOWN
(PWM block input)
t
t
OSC enable
(Internal signal)
DB
DB
DB
Figure 102: Power-Down with SYNC On/Off = 1 and Dead Band = 1 to 3 CLK
In Figure 101 to Figure 104:
dT = 2-3 CLK and it is the additional number of clock pulses, that make first PWM period longer, after releasing PD signal;
DB - user selected Dead Band time between OUT+ and OUT-;
T* means the short period of x % duty cycle (T* < 255 PERIOD_CNT_CLK), that is finished at the moment of PD signal com-
ing.
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GreenPAK Programmable Mixed-Signal Matrix with High
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Dead Band = 0 clk
Sync On/Off = 0
(Synchronous Power-Down)
200 def. value
200 def. value
Counter Data of
Duty Cycle CNT
t
t
t
t
t
t
t
t
t
t
200
202
201
202
201
200
201
202 200
201
200
default value
Duty Cycle CNT
Duty Cycle
200
default value
200
200
200
201
200
201
DUTY_CYCLE_CLK
(PWM block input)
T
T
T
T + dT
78.4%
T
T
T
PERIOD_CNT_CLK
(From internal OSC)
dT
OUT+
(PWM block output)
78.4%
78.4%
78.8%
78.8%
78.4%
78.8%
OUT-
(PWM block output)
UP/DOWN
(PWM block input)
POWER_DOWN
(PWM block input)
OSC enable
(Internal signal)
Figure 103: Power-Down with SYNC On/Off = 0 and Dead Band = 0 CLK
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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Dead Band = 1...3 clk (Rising edges of OUT+ and OUT- are delayed on DB time)
Sync On/Off = 0 (Synchronous Power-Down)
200
default value
200
default value
Counter Data of
Duty Cycle CNT
t
t
t
t
t
t
t
t
t
t
200
202
201
202
200
201
202
200
201
200
default value
Duty Cycle CNT
Duty Cycle
200
default value
200
201
200
201
200
201
200
DUTY_CYCLE_CLK
(PWM block input)
T
T
T
T + dT
T
T
T
PERIOD_CNT_CLK
(From internal OSC)
dT
OUT+
(PWM block output)
78.4%
78.4%
78.8%
78.4%
78.8%
78.4%
78.8%
OUT-
(PWM block output)
DB
DB
DB
UP/DOWN
(PWM block input)
POWER_DOWN
(PWM block input)
OSC enable
(Internal signal)
Figure 104: Power-Down with SYNC On/Off = 0 and Dead Band = 1 to 3 CLK
13.11 REGULAR/PRESET REGISTERS MODE
In Regular Mode the value of duty cycle is changed every rising edge on Duty Cycle CNT CLK input. In Preset Registers Mode
the duty cycle is changed according to 16 predefined values, named Reg File, every rising edge on Duty Cycle CNT CLK input.
Selectable Preset registers are reserved to determine 16 different PWM Duty Cycle values. In Preset Registers mode the "Up/
Down" input and "Duty Cycle CNT CLK input" change the address of Preset Register, that will be applied to PWM block at the
rising edge on "Duty Cycle CNT CLK input".
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GreenPAK Programmable Mixed-Signal Matrix with High
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One 16-byte Preset Register is shared between two PWM macrocells.
Each PWM block can select Reg File as Duty Cycle source. When the Reg File is selected as a source, there are three options:
use all 16 bytes, use less significant 8 bytes, or use most significant 8 bytes. In this case, 4-bits (when using 16-Bytes Reg File)
or 3-bits (when using any of 8 bytes Reg File) LSB Current Value of PWM Duty Cycle CNT is used to select data address inside
the Reg File. The counter data of the Duty Cycle CNT will define the initial starting point in the Reg file. So, each PWM block has
its own initial position in the Reg File.
Table 69: Regular/Preset Mode Registers
Register Name
Mode of Operation
Register Definition
Regular Mode
00: from PWM Duty Cycle CNT
01: 8-byte MSB of RegFile
10: 8-byte LSB of RegFile
11: 16-byte RegFile
PWMx: Duty Cycle source
Preset Registers Mode
For more detailed description see Table 71 and Table 72.
13.12 PWM CONTINUOUS/AUTOSTOP MODE
“Continuous/Autostop mode” register enables Autostop mode. This mode can be used with both Preset Registers or Regular
Mode.
If PWM block works in Continuous Mode (register [1302] = 0 for PWM0 or register [1476] = 0 for PWM1), PWM Duty Cycle CNT
will overflow when it reaches boundaries. For example, for PWM Duty Cycle Counter counts up: 254th → 255th → 0th → 1st, and
for PWM Duty Cycle Counter counts down: 1st → 0th → 255th → 254th
…
Or in Preset Registers Mode, when Continuous Mode is selected (register [1302] = 0 for PWM0 or register [1476] = 0 for PWM1):
counting up 14th → 15th → 0th → 1st, and counting down 1st → 0th → 15th → 14th
…
If Autostop mode is active (register [1302] = 1 for PWM0 or register [1476] = 1 for PWM1), PWM duty cycle counter will stop when
it reaches boundaries. The conditions of Autostop are the next:
PWM Duty Cycle reaches the value 0 in Regular Mode or Least Significant Byte of Preset registers in Preset Registers Mode,
and Up/Down is LOW logic level (counting Down).
PWM Duty Cycle reaches the value 255 (127 in 7-bit submode) in Regular Mode or Most Significant Byte of Preset registers
in Preset Registers Mode and Up/Down is HIGH logic level (counting Up).
13.13 INTERNAL OSCILLATOR AUTO DISABLE MODE
There is an OSC Auto Disable/Enable control, in which internal OSC is enabled only when it is required for PWM block. This
Auto Disable Mode will operate only if user selects internal oscillator as a clock source for PWM Period Clock Counter ("PWM0
Period Clock Source selection" registers have a value from b0000 to b1001).
If the user selected PWM Period CNT overflow event as a clock source for Duty Cycle Counter (registers [1469:1468] = 01, or
registers [1469:1468] = 10, or registers [1469:1468] = 11 for PWM0 and registers [1485:1484] = 01, or registers [1485:1484] =
10, or registers [1485:1484] = 11 for PWM1), then no clocks will be on Duty Cycle Counter Clock input when PWM enters to
Autostop State (see Table 70).
The conditions, in which internal OSC will be automatically disabled, are shown in Table 70.
Table 70: Conditions for Disabling/Enabling an Internal Oscillator
N0
Disable Condition
Delay before OSC in disabled
Enable Condition
Disable OSC immediately if SYNC
On/Off register [1301] = 1 for PWM0
and register [1475] = 1 for PWM1
1
PD signal goes HIGH
PD signal goes LOW
Disable OSC after current duty cycle
period if SYNC On/Off register [1301]
= 0 for PWM0 and register [1475] = 0
for PWM1
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GreenPAK Programmable Mixed-Signal Matrix with High
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Table 70: Conditions for Disabling/Enabling an Internal Oscillator (Continued)
N0
Disable Condition
Delay before OSC in disabled
Enable Condition
2
Stop signal goes HIGH
Disable OSC immediately
Stop signal goes LOW
Up/Down is logic HIGH (counting up)
and actual PWM value is 255 (127 for
7-bit submode), "PWM boundary
OSC automatically disable" (register
[1303]=1forPWM0orregister[1477]
= 1 for PWM1)
"Continuous/Autostopmode"(register
[1302]=1forPWM0orregister[1476]
= 1 for PWM1) Figure 105
Disable OSC after one full PWM peri- Up/Down signal changes its level to
od. logic LOW (count down) Figure 105
3
4
Up/Down is logic LOW (counting
down) and actual PWM value is 0,
"PWM boundary OSC automatically
disable"(register [1303] = 1 for PWM0 Disable OSC after one full PWM peri- Up/Down signal changes its level to
or register [1477] = 1 for PWM1) and od.
"Continuous/Autostopmode"(register
[1302]=1forPWM0orregister[1476]
= 1 for PWM1)
logic HIGH (count up)
Note 1 If PWM boundary OSC automatically disable register [1303] = 1 for PWM0 or register [1477] = 1 for PWM1 and PWM
works with Preset Registers (registers [1467:1466] = 01 or registers [1467:1466] = 10, or registers [1467:1466] = 11 for PWM0
and registers [1483:1482] = 01 or registers [1483:1482] = 10, or registers [1483:1482] = 11 for PWM1), internal OSC will stop if
Preset Registers Index = 15 (7 when LSByte mode of Preset Registers is used) the Preset Register Index remains unchanged
until Up/Down signal changes. The same behavior has zero Preset Register Index (8 when MSByte mode of Preset Registers is
used). When this index will be reached and OSC Auto Disable Mode is active the Preset Register Index remains unchanged until
Up/Down signal changes.
Note 2 Other macrocells that use OSC, can start it or keep it enabled even if OSC Auto Disable Mode is active and condition for
disabling OSC occurs.
Note 3 If dead band is different from 0, then OSC will be disabled for Dead Band Time later.
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SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
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VDD
t
t
t
POR
default value
254
255
254
254
254
255
254
253
253
Duty Cycle CNT
default value
253
254
254
253
254
255
255
Duty Cycle
(actual PWM output)
t
Duty Cycle Clk
t
(External signal)
T
T
T
T
T
T
T
T
T
Period CNT Clk
(Internal OSC)
T = 256 Period CNT Clk
t
UP/DOWN
(PWM block input)
t
OSC enable
(Internal signal)
t
6)
4)
5)
1)
2)
3)
Figure 105: Example of PWM Auto Oscillator Control
In the example in Figure 105, Duty Cycle CLK is external to PWM block signal, Period CNT CLK is a signal from internal OSC.
"PWM boundary OSC automatically disable" register [1303] = 1 for PWM0 or register [1477] = 1 for PWM1. Autostop Mode is
active too ("Continuous/Autostop mode" register [1302] = 1 for PWM0 or register [1476] = 1 for PWM1). The key events of
Autostop are the next:
Event 1) after chip start-up, OSC is enabled. The clock from internal OSC is used to generate PWM period. Duty Cycle CNT
counts up since Up/Down input of PWM macrocell is logic HIGH. Note that first OSC pulse is delayed when OSC becomes
enabled (see Table 24).
Event 2) the value of Duty Cycle CNT is updated every rising edge at Duty Cycle CLK input. This value becomes valid at the
beginning of every PWM period.
When the Duty Cycle value of 100 % is reached and Up/Down input is logic HIGH, PWM macrocell disables internal OSC
after one full PWM period.
Event 3) internal OSC starts working because Up/Down signal becomes LOW and Duty Cycle = 100 %. This is the scenario
for starting OSC after it was automatically disabled.
Event 4) the Up/Down signal changes the direction of Duty Cycle counting because at the moment of signals rising edge on
Duty Cycle CLK input, the level of Up/Down input is logic HIGH.
Event 5) OSC is disabled because the value of Duty Cycle is 100 % and at the beginning of the next PWM period the Up/
Down input is logic HIGH.
Event 6) Since Up/Down goes low and Duty Cycle is equal to 100 %, this is the scenario for starting up the OSC.
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13.14 PHASE CORRECT PWM MODE
In normal mode, PWM output is HIGH, then LOW for each PWM period. When Phase correct PWM (also called Center Align)
register is active (register [1460] = 1 for PWM0 or register [1478] = 1 for PWM1), the PWM output is HIGH, then LOW for the first
period, then LOW again and HIGH for the second period. So, there are less edges (or less output switches) for the Phase
correct PWM mode.
PWM OUT+
Phase Correct Mode register = 0
PWM OUT+
Phase Correct Mode register = 1
PWM Period
PWM Period
PWM Period
PWM Period
Figure 106: Phase Correct PWM Mode
13.15 PWM PERIOD OUTPUT
PWM_PERIOD output indicates the start of the new PWM period at PWM_OUT+. This output doesn't depend on the PWM duty
cycle. The duration of the high level is equal to one period of the PERIOD_CNT_CLK.
PWM Period
PWM OUT+
PWM PERIOD
Figure 107: PWM Period Waveform
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13.16 PWM BLOCK DIAGRAMS
8-bit, 7-bit resolution: register [1298]
OUT+ Output Polarity selection: register [1299]
OUT- Output Polarity selection: register [1300]
Sync Off/On: register [1301]
Continuous/Autostop mode: register [1302]
Boundary OSC disable:register [1303]
Phase Correct mode: register [1460]
I2C initial value: registers [1295:1288]
Deadband selection: registers [1465:1464]
Duty Cycle Source selection: registers [1467:1466]
Keep/Stop: register [1461]
I2C trigger: register [1296]
from Connection Matrix Output [76]
from Connection Matrix Output [77]
from Connection Matrix Output [80]
CNT Data
UP/DOWN
Duty
Cycle
KEEP/STOP
Reg. File
Power-Down
DUTY_CYCLE_CLK
Coutner
(16 bytes)
Reg. File
to PWM1
from Connection Matrix Output [78]
PWM Period CNT
overflow
0
1
I2C current duty cycle value
registers [1319:1312]
/2
/8
Synchro
Buffer
Duty Cycle CNT
CLK source
registers [1469:1468]
Digital
CMP
CNT_OVF
CLK_OSC0
Period
Counter
CLK_OSC0/4
to Connection Matrix Input [40]
to Connection Matrix Input [41]
OUT+
OUT-
CLK_OSC1
. . .
. . .
PERIOD_
CNT_CLK
CLK_OSC1/262144
from Flexible Divider
PWM_PERIOD
to Connection Matrix Input [58]
from Connection Matrix Output [79]
external_CLK
PWM Period CNT
CLK source
registers [1459:1456]
PWM0
Figure 108: PWM0 Functional Diagram
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8-bit, 7-bit resolution: register [1472]
OUT+ Output Polarity selection: register [1473]
OUT- Output Polarity selection: register [1474]
Sync Off/On: register [1475]
Continuous/Autostop mode: register [1476]
Boundary OSC disable: register [1477]
Phase Correct mode: register [1478]
Deadband selection: registers [1481:1480]
I2C initial value: registers [1311:1304]
Duty Cycle Source selection: registers [1483:1482]
Keep/Stop: register [1479]
I2C trigger: register [1297]
CNT Data
Duty
Cycle
Coutner
from Connection Matrix Output [81]
from Connection Matrix Output [82]
UP/DOWN
KEEP/STOP
from Connection Matrix Output [85]
Power-Down
DUTY_CYCLE_CLK
from Connection Matrix Output [83]
from Reg. File
PWM Period CNT
overflow
I2C current duty cycle value
registers [1327:1320]
0
1
/2
/8
Synchro
Buffer
Duty Cycle CNT
CLK source
registers [1485:1484 ]
Digital
CMP
CNT_OVF
CLK_OSC0
Period
Counter
CLK_OSC0/4
to Connection Matrix Input [42]
to Connection Matrix Input [43]
OUT+
OUT-
CLK_OSC1
. . .
. . .
PERIOD_
CNT_CLK
CLK_OSC1/262144
from Flexible Divider
PWM_PERIOD
to Connection Matrix Input [59]
from Connection Matrix Output [84]
external_CLK
PWM Period CNT CLK source
Registers [1491:1488]
PWM1
Figure 109: PWM1 Functional Diagram
13.17 PWM REGISTER SETTINGS
Table 71: PWM0 Register Settings
Signal Function
Register Bit Address Register Definition
0: 8-bit PWM0
1 bit [1298] register
PWM0: 8-bit or 7-bit resolution
PWM0: OUT+ polarity selection
PWM0: OUT- polarity selection
PWM0: SYNC On/Off
1: 7-bit PWM0
0: Non-Inverted Output
1 bit [1299] register
1: Inverted Output
0: Non-Inverted Output
1 bit [1300] register
1: Inverted Output
0: Synchronous Power-Down
1 bit [1301] register
1: Asynchronous Power-Down
0: Continuous mode
1 bit [1302] register
PWM0: Continuous/Autostop mode
PWM0: Boundary OSC disable
PWM0: Phase Correct mode
1: PWM Duty Cycle Counter Autostop at 0 % or 100 %
0: OSC is always enabled at boundaries
1: Automatically Disable OSC
1 bit [1303] register
1 bit [1460] register
0: Disable
1: Enable
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Table 71: PWM0 Register Settings (Continued)
Signal Function
Register Bit Address Register Definition
00: No Deadband
2 bits
[1465:1464] registers
01: 1 PWM0 clock cycles
10: 2 PWM0 clock cycles
11: 3 PWM0 clock cycles
PWM0: Deadband selection
0: Keep
1: Stop
PWM0: Keep/Stop selection
PWM0: I2C trigger
1 bit [1461] register
1 bit [1296] register
0: Don't update duty cycle value
1: Update duty cycle value
00: from PWM Duty Cycle CNT (Regular Mode)
01: 8-byte MSB of RegFile (Preset Registers Mode)
10: 8-byte LSB of RegFile (Preset Registers Mode)
11: 16-byte RegFile (Preset Registers Mode)
2 bits
[1467:1466] registers
PWM0: Duty Cycle source
0000: CLK_OSC0
0001: CLK_OSC0/4
0010: CLK_OSC1
0011: CLK_OSC1/8
0100: CLK_OSC1/64
0101: CLK_OSC1/512
0110: CLK_OSC1/4096
0111: CLK_OSC1/32768
1000: CLK_OSC1/262144
1001: From Flexible Divider
1010: Reserved
PWM0 Period Counter Clock Source
selection
4 bits
[1459:1456] registers
1011: Matrix OUT [79] (external clock)
00: Matrix output
PWM0: Duty Cycle Counter Clock
Source selection
2 bits
[1469:1468] registers
01: PWM Period CNT overflow
10: every 2nd pulse of PWM Period CNT overflow
11: every 8th pulse of PWM Period CNT overflow
PWM0: Preset 16-byte Registers
byte [0...15]
16 bytes
[1455:1328] registers
Preset 16 bytes Duty Cycle values
Initial PWM0 Duty Cycle value
8 bits
[1295:1288] registers
PWM0: Initial value
8 bits
[1319:1312] registers
PWM0: Current duty cycle value
Current PWM0 duty cycle value for I2C read
Table 72: PWM1 Register Settings
Signal Function
Register Bit Address Register Definition
8 bits
[1311:1304] registers
PWM1: Initial value
Initial PWM1 Duty Cycle value
8 bits
[1327:1320] registers
PWM1: Current duty cycle value
PWM1: 8-bit or 7-bit resolution
PWM1: OUT+ output polarity selection
PWM1: OUT- polarity selection
PWM1: SYNC On/Off
Current PWM1 duty cycle value for I2C read
0: 8-bit PWM1
1: 7-bit PWM1
1 bit [1472] register
1 bit [1473] register
1 bit [1474] register
1 bit [1475] register
1 bit [1476] register
0: Non-Inverted Output
1: Inverted Output
0: Non-Inverted Output
1: Inverted Output
0: Synchronous Power-Down
1: Asynchronous Power-Down
0: Continuous mode
1: PWM Duty Cycle Counter Autostop at 0 % or 100 %
PWM1: Continuous/Autostop mode
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Table 72: PWM1 Register Settings (Continued)
Signal Function
Register Bit Address Register Definition
0: OSC is always enabled at boundaries
1: Automatically Disable OSC
PWM1: Boundary OSC disable
1 bit [1477] register
1 bit [1478] register
0: Disable
1: Enable
PWM1: Phase Correct mode
PWM1: Deadband selection
00: No Deadband
2 bits
[1481:1480] registers
01: 1 PWM1 clock cycles
10: 2 PWM1 clock cycles
11: 3 PWM1 clock cycles
0: Keep
1: Stop
PWM1: Keep/Stop Selection
PWM1: I2C trigger
1 bit [1479] register
1 bit [1297] register
0: Don't update duty cycle value
1: Update duty cycle value
00: from PWM Duty Cycle CNT (Regular Mode)
01: 8-byte MSB of RegFile (Preset Registers Mode)
10: 8-byte LSB of RegFile (Preset Registers Mode)
11: 16-byte RegFile (Preset Registers Mode)
2 bits
[1483:1482] registers
PWM1: Duty Cycle source
0000: CLK_OSC0
0001: CLK_OSC0/4
0010: CLK_OSC1
0011: CLK_OSC1/8
0100: CLK_OSC1/64
0101: CLK_OSC1/512
0110: CLK_OSC1/4096
0111: CLK_OSC1/32768
1000: CLK_OSC1/262144
1001: From Flexible Divider
1010: Reserved
PWM1 Period Counter Clock Source
selection
4 bits
[1491:1488] registers
1011: Matrix OUT [84] (external clock)
00: Matrix output
PWM1: Duty Cycle Counter Clock Source 2 bits
selection [1485:1484] registers
01: PWM Period CNT overflow
10: every 2nd pulse of PWM Period CNT overflow
11: every 8th pulse of PWM Period CNT overflow
"Keep/Stop" register defines which function will be performed by "Duty Cycle CNT Keep/Stop" input. Keep/Stop signal is active
HIGH level.
"PWM Period Clock Source selection" registers define clock source for "PWM Period CNT CLK" input: from the matrix, from
OSCx and OSCx dividers, from the flexible OSC-integrated divider. Also, there is an option to select counter overflow condition
as a source for PWM Period Clock.
"PWM: Duty Cycle Source selection" defines the clock source for changing the duty cycle. It can be:
clock source from the connection matrix;
clock pulse that is generated after the end of PWM cycle period (PWM Period Counter overflow). This pulse is generated
every 255 (for 8-bit option) or 127 (for 7-bit option) PWM Period Clocks;
clock pulse that is generated once per 2 PWM period, or every 510 (for 8-bit option) or 254 (for 7-bit option) PWM Period
Clocks;
clock pulse that is generated once per 8 PWM period, or every 2040 (for 8-bit option) or 1016 (for 7-bit option) PWM Period
Clocks.
"I2C Trigger" register allows to update duty cycle value via I2C command:
When I2C_Trigger = 0, PWM duty cycle isn't updated;
When I2C_Trigger = 1, PWM duty cycle is updated from register at I2C stop pulse after the current PWM period is completed.
The I2C_Trigger bit will be automatically cleared after the I2C stop pulse.
"SYNC On/Off" registers define the Power-down signal behavior on PWM block. This is the individual setting for each PWM
macrocell. If this option is disabled (register [1301] = 1 for PWM0 or register [1475] = 1 for PWM1), then PWM output is changed
right away by active Power-down. If this option is enabled (register [1301] = 0 for PWM0 or register [1475] = 0 for PWM1), the
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PWM block will finish the current PWM period and then will react to Power-down signal.
"Continuous/Autostop mode" register enables Autostop mode. This mode can be used with both Preset Registers or Regular
Mode. If PWM block works in Continuous Mode (register [1302] = 0 for PWM0 or register [1476] = 0 for PWM1), PWM Duty
Cycle CNT will overflow when it reaches boundaries. For example, for PWM Duty Cycle Counter counts up: 254th → 255th →
0th → 1st, and for PWM Duty Cycle Counter counts down: 1st → 0th → 255th → 254th … If Autostop mode is active (register
[1302] = 1 for PWM0 or register [1476] = 1 for PWM1), PWM duty cycle counter will stop when it reaches boundaries. Please
refer to Section 13.12.
"PWMx boundary OSC disable" is the function, that allows disabling internal oscillator when there is no need for PWM to be
clocked (boundary is reached in Autostop Mode only). This feature is useful for energy saving, but the user can optionally
disable it and keeps the oscillator always enabled.
"Phase Correct mode". In normal mode, PWM output is HIGH, then LOW for each PWM period. When Phase correct PWM (also
called Center Align) register is active (register [1460] = 1 for PWM0 or register [1478] = 1 for PWM1), then PWM output is HIGH,
then LOW for the first period, then LOW again, and HIGH for the second period. So, there are less edges (or less output
switches) for the Phase correct PWM mode.
"Duty Cycle source" (registers [1467:1466] for PWM0 or registers [1483:1482] for PWM1) defines the Regular Mode of
operation (registers [1467:1466] = 00 for PWM0 or registers [1483:1482] = 00 for PWM1) or Preset Registers Mode (registers
[1467:1466] = 01, registers [1467:1466] = 10, registers [1467:1466] = 11 for PWM0 or registers [1483:1482] = 01, registers
[1483:1482] = 10, registers [1483:1482] = 11 for PWM1). In Regular Mode, the value of duty cycle is changed every rising edge
on Duty Cycle CNT CLK input. In Preset Registers Mode the duty cycle is changed according to values, saved in 8-byte MSB of
RegFile (registers [1467:1466] = 01 for PWM0 or registers [1483:1482] = 01 for PWM1), 8-byte LSB of RegFile (registers
[1467:1466] = 10 for PWM0 or registers [1483:1482] = 10 for PWM1) or 16-byte of RegFile (registers [1467:1466] = 11 for
PWM0 or registers [1483:1482] = 11 for PWM1). The address of RegFile value, that is applied to PWM block, is changed every
rising edge on Duty Cycle CNT CLK input.
"OUT+ polarity selection" registers enable/disable inverted option for Output+ of PWM macrocell.
"OUT- polarity selection" registers enable/disable inverted option for Output- of PWM macrocell.
"Deadband selection" registers [1465:1464] for PWM0 and registers [1481:1480] for PWM1 chose dead band time between
OUT+ and OUT- signals. It is 0, 1, 2, or 3 clock period of PWM Period CNT CLK signal.
"8-bit/7-bit PWM resolution". It is possible to select 7-bit instead of default 8-bit resolution for the PWM to increase the PWM
speed. If the 7-bit resolution is selected, the maximum value of the duty cycle counter is 127.
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14
Analog Comparators
There are two Rail-to-Rail General Purpose Analog Comparators (ACMP) macrocells in the SLG47105. In order for the ACMP
cells to be used in a GreenPAK design, the power-up signals (ACMP0H_nPD, ACMP1H_nPD) need to be active. By connecting
to signals coming from the Connection Matrix, it is possible to have each ACMP be on continuously, off continuously, or switched
on periodically, based on a digital signal coming from the Connection Matrix. When ACMP is powered down, the output is low
(the output remains its state while sleeping).
The General-Purpose Rail-to-Rail Analog Comparators are optimized for high-speed operation (ACMP0H and ACMP1H).
Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources and can also have a
selectable gain stage before connection to the analog comparator. Each of the ACMP cells has a negative input signal that is
either created from an internal Vref or provided by a way of the external sources.
Power-Up = 1 => ACMP is powered up.
Power-Up = 0 => ACMP is powered down.
During power-up, the ACMP output will remain LOW, and then becomes valid after power up signal goes high for ACMP0H and
ACMP1H (see parameter tstart in Table 27). Input bias current < 1 nA (typ). The Gain divider is unbuffered and consists of 2 MΩ
resistors. IN- voltage range: 0 - 2.016 V.
Each cell also has a hysteresis selection, to offer hysteresis of (0, 32, 64, 192) mV. The hysteresis option is available when using
an internal Vref only.
The ESD resistors should be taken into consideration when using pull-up/pull-down resistors. It may affect VIH and VIL. See
sections 6.6 to 6.9.
ACMP0H IN+ options are GPIO5, VDD
ACMP1H IN+ options are GPIO6, ACMP0H IN+ MUX output, Temp Sensor OUT
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14.1 ACMP0H BLOCK DIAGRAM
to ACMP1H, MUX input
registers [652:651]
Hysteresis
Selection
registers [681:680]
GPIO5: ACMP0H(+)
ACMP
Ready
0
1
Selectable
Gain
+
-
To Connection
Matrix Input [46]
0
1
Internal VDD 2.3V - 5.5 V
Vref
Power-Up
LATCH
HighSpeed
ACMP
ACMP0_H IN+ Selection: register [655]
register [672]
W/S Control
Off after
1us
Internal
Vref
000000-
111110
From Connection
Matrix Output [86]
Ext. Vref0 (GPI)
111111
registers [687:682]
Figure 110: ACMP0H Block Diagram
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14.2 ACMP1H BLOCK DIAGRAM
registers [661:660]
Hysteresis
Selection
registers [689:688]
GPIO6: ACMP1H(+)
ACMP
Ready
00
01
10
ACMP0H IN+ MUX Output
Temp sensor
Selectable
Gain
+
-
To Connection
Matrix Input [47]
0
1
Vref
Power-Up
LATCH
HighSpeed
ACMP
ACMP1_H IN+ Selection: registers [656:657]
register [673]
W/S Control
Off after
1us
Internal
Vref
000000-
111110
From Connection
Matrix Output [87]
Ext. Vref1 (GPIO4)
111111
registers [695:690]
Figure 111: ACMP1H Block Diagram
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14.3 ACMP TYPICAL PERFORMANCE
10
8
6
Upper Limit
4
Lower Limit
2
0
0
512
1024
1536
-2
-4
-6
-8
-10
Vref (mV)
Figure 112: ACMPxH Input Offset Voltage vs. Vref at VDD = 2.3 V to 5.5 V, T = -40 °C to 85 °C
3
2.5
2
1.5
1
High To Low, Overdrive = 10 mV
Low to High, Overdrive = 10 mV
High to Low, Overdrive = 100 mV
Low to High, Overdrive = 100 mV
0.5
0
0
512
1024
1536
Vref (mV)
Figure 113: Propagation Delay vs. Vref for ACMPxH at T = 25 °C, at VDD = 2.3 V to 5.5 V, Gain = 1, Hysteresis = 0
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24
22
20
18
16
14
12
T = -40 °C
T = 25 °C
T = 85 °C
2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VDD (V)
Figure 114: ACMPxH Power-On Delay vs. VDD
39
37
35
33
31
29
27
25
Tj = 150 °C
Tj = 85 °C
Tj = 25 °C
Tj = -40 °C
2.4
2.9
3.4
3.9
4.4
4.9
5.4
VDD (V)
Figure 115: ACMPxH Current Consumption vs. VDD at Vref = 32 mV
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50
48
46
44
42
40
38
36
34
32
30
Tj = 150 °C
Tj = 85 °C
Tj = 25 °C
Tj = -40 °C
2.4
2.9
3.4
3.9
4.4
4.9
5.4
VDD (V)
Figure 116: ACMPxH Current Consumption vs. VDD at Vref = 1024 mV
49
47
45
43
41
39
37
35
Tj = 150 °C
Tj = 85 °C
Tj = 25 °C
Tj = -40 °C
2.4
2.9
3.4
3.9
4.4
4.9
5.4
VDD (V)
Figure 117: ACMPxH Current Consumption vs. VDD at Vref = 2016 mV
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15 Programmable Delay/Edge Detector
The SLG47105 has a programmable time delay logic cell that can generate a delay that is selectable from one of four timings
(time2) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay patterns,
rising edge detection, falling edge detection, both edge detection, and both edge delay. These four patterns can be further
modified with the addition of delayed edge detection, which adds an extra unit of delay, as well as glitch rejection during the delay
period. See Figure 118 for further information.
Note The input signal must be longer than the delay, otherwise it will be filtered out.
registers [1237:1236]
Delay Value Selection
registers [1239:1238]
Edge Mode Selection
To Connection
Matrix Input [15]
Programmable
From Connection Matrix Output [89]
IN
OUT
Delay
Figure 118: Programmable Delay
15.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT
width
width
IN
time1
Rising Edge Detector
time1
Falling Edge Detector
Edge Detector
Output
Both Edge Detector
Both Edge Delay
time2
time2
time1 is a fixed value
time2 delay value is selected via register
Figure 119: Edge Detector Output
Please refer to Table 16.
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16 Additional Logic Function. Deglitch Filter
The SLG47105 has one Deglitch Filter macrocell with inverter function that is connected directly to the Connection Matrix inputs
and outputs. In addition, this macrocell can be configured as an Edge Detector, with the following settings:
Rising Edge Detector
Falling Edge Detector
Both Edge Detector
Both Edge Delay
Filter
R
From Connection Matrix
Output [88]
0
1
C
0
1
To Connection Matrix
Input [52]
Edge
Detector
Logic
register [1232]
registers [1235:1234]
register [1233]
Figure 120: Deglitch Filter/Edge Detector
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17 Voltage Reference
17.1 VOLTAGE REFERENCE OVERVIEW
The SLG47105 has a Voltage Reference (Vref) macrocell to provide references to the four analog comparators. This macrocell
can supply a user selection of fixed voltage references, or temperature sensor output. The macrocell also has the option to output
reference voltages on GPIO0. See Table 73 for the available selections for each analog comparator.
Also, see Figure 73, which shows the reference output structure.
17.2 VREF SELECTION TABLE
Table 73: Vref Selection Table
SEL
0
SEL[5:0]
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Vref
0.032
0.064
0.096
0.128
0.16
SEL
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
SEL[5:0]
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Vref
1.056
1.088
1.12
1
2
3
1.152
1.184
1.216
1.248
1.28
4
5
0.192
0.224
0.256
0.288
0.32
6
7
8
1.312
1.344
1.376
1.408
1.44
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0.352
0.384
0.416
0.448
0.48
1.472
1.504
1.536
1.568
1.6
0.512
0.544
0.576
0.608
0.64
1.632
1.664
1.696
1.728
1.76
0.672
0.704
0.736
0.768
0.8
1.792
1.824
1.856
1.888
1.92
0.832
0.864
0.896
0.928
0.96
1.952
1.984
2.016
External
0.992
1.024
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17.3 MODE SELECTION
Table 74: Mode Selection Table
Conditions
M[2]
0
M[1]
0
M[0]
0
Mode
Analog Power-down
0
0
1
Analog Power-down
0
1
0
Vref_OUT to ACMP only
Vref_OUT to ACMP only
Analog Power-down
GPIO0 isn't config-
ured as Analog IO
(registers[756:755]
≠ 11) OR GPIO0
OE is HIGH
0
1
1
1
0
0
1
0
1
Vts_OUT to ACMP only
Vts_OUT to ACMP only
Analog Power-down
1
1
0
1
1
1
0
0
0
Analog Power-down
0
0
1
Vref_OUT to GPIO0 only
Vref_OUT to ACMP only
Vref_OUT to GPIO0 and ACMP
Vts_OUT to GPIO0 only
Vts_OUT to ACMP only
Vts_OUT to GPIO0 and ACMP
Vref_OUT to GPIO0 bypass analog buffer
0
1
0
GPIO0 is config-
ured as Analog IO
(registers[756:755]
= 11) AND GPIO0
OE is LOW
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Note:VoltageReference canbeoutputtedto GPIO0according toM[2:0] statewhenthis GPIO is configured asAnalogIO (registers
[756:755] = 11) AND GPIO0 OE is LOW.
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17.4 VREF BLOCK DIAGRAM
2.016
PwrUp
1.984
Bandgap
Vref
0.064
ACMP0_H ref
selection
0.032
to ACMP0_H
inverting input
Ext Vref0 input
reg_vref_sel[647:646]
reg_ts_range_sel[650]
Vref0
111111
2.016
111110
111101
1.984
Vref1
Vts
GPIO0
0.064
0.032
000001
000000
Vref OUT
To ACMP
GPIO0_OE
Vref Logic and
Buffer
M[2]
M[1]
M[0]
registers [687:682]
reg_pdb[643]
0
1
PDb
ACMP1_H ref
selection
Ext Vref1 input
matrix_pdb[92]
resetb
111111
reg_load_range_sel
[645]
2.016
1.984
111110
111101
reg_pd_sel[644]
to ACMP1_H
inverting input
0.064
0.032
000001
000000
registers [695:690]
Temp
Sensor
Figure 121: Voltage Reference Block Diagram
Note 1: reg_ts_range_sel register, that defines voltage range of Vref Block Output, is valid for Temp Sensor source only.
Note 2: reg_load_range_sel register should be set to 1 for better stability when the load resistance at GPIO0 is more than
100 kΩ. This option affects consumption current.
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17.5 VREF LOAD REGULATION
Note It is not recommended to use Vref connected to external pin without buffer.
350
300
250
VDD = 5 V
200
150
100
50
VDD = 3.3 V
VDD = 2.5 V
0
0
5
10
15
20
25
30
I, mA
Figure 122: Typical Load Regulation, Vref = 320 mV, T = -40 °C to +85 °C, Buffer - Enabled
.
700
600
500
400
300
200
100
0
VDD = 5 V
VDD = 3.3 V
VDD = 2.5 V
0
5
10
15
20
25
30
I, mA
Figure 123: Typical Load Regulation, Vref = 640 mV, T = -40 °C to +85 °C, Buffer - Enabled
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.
1400
1200
1000
VDD = 5 V
800
600
400
200
0
VDD = 3.3 V
VDD = 2.5 V
0
5
10
15
20
25
30
I, mA
Figure 124: Typical Load Regulation, Vref = 1280 mV, T = -40 °C to +85 °C, Buffer - Enabled
.
2100
1800
1500
1200
900
600
300
0
VDD = 5 V
VDD = 3.3 V
VDD = 2.5 V
0
5
10
15
20
25
30
I, mA
Figure 125: Typical Load Regulation, Vref = 2016 mV, T = -40 °C to +85 °C, Buffer - Enabled
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18 Clocking
18.1 OSC GENERAL DESCRIPTION
The SLG47105 has two internal oscillators to support a variety of applications:
Oscillator0 (2.048 kHz)
Oscillator1 (25 MHz).
There are two divider stages for each oscillator that gives the user flexibility for introducing clock signals to the connection matrix,
as well as various other macrocells. The Pre-divider (first stage) for Oscillator allows the selection of /1, /2, /4 or /8, and /12 in
Oscillator1(25 MHz) to divide down frequency from the fundamental. The second stage divider has an input of frequency from
the Pre-divider, and outputs one of eight different frequencies divided by /1, /2, /3, /4, /8, /12, /24, or /64 on Connection Matrix
Input lines [53], [54], [55], and [56]. Please see Figure 126 for more details on the SLG47105 clock scheme.
Oscillator1 (25 MHz) has an additional function of 100 ns delayed startup, which can be enabled/disabled by register [722]. This
function is recommended to use when analog blocks are used along with the Oscillator.
The Matrix Power-down/Force On function allows switching off or force on the oscillator using an external pin. The Matrix Power-
down/Force-On (Connection Matrix Output [90], [91]) signal has the highest priority. The OSC operates according to the following
table:
Table 75: Oscillator Operation Mode Configuration Settings
OSC Enable
Signal from
CNT/DLY
Register:
Power-Down
or Force On by
Matrix Input
OSC
Operation
Mode
Signal From
Connection
Matrix
Register: Auto
Power-On or
Force On
External Clock
Selection
POR
Macrocells
0
1
X
1
X
X
X
X
X
X
X
X
OFF
Internal OSC is
OFF, logic is ON
1
1
1
0
0
0
1
1
0
0
1
X
X
1
X
X
X
OFF
ON
ON
ON
X
CNT/DLY re-
quires OSC
1
1
0
0
0
0
X
X
0
0
CNT/DLY does
not require OSC
OFF
Note The OSC will run only when any macrocell that uses OSC is powered on.
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18.2 OSCILLATOR0 (2.048 KHZ)
from Connection Matrix
Output [90]
Power-Down/Force On
Matrix Output control register [724]
2.048 kHz Pre-divider Clock
OSC Power Mode
register [723]
Power-Down/
Force On
to PWMs and CNT/DLYs Clock Scheme
registers [729:728 ]
OSC0
(2.048 kHz)
Auto Power-On
Force Power-On
OUT
0
1
0
1
0
DIV/1 /2 /4/8
Ext. Clock
/2
/4
1
2
Predivider
OSC0 matrix OUT0 Enable
register [726]
Ext. CLK Sel
register [725]
to Connection Matrix
Input [55]
/3
3
4
5
6
7
OUT0
OUT1
/8
to Connection Matrix
Input [56]
/12
/24
/64
OSC0 matrix OUT1 Enable
register [739]
registers
[732:730]
registers
[738:736]
Second Stage Divider
Figure 126: Oscillator0 Block Diagram
18.3 OSCILLATOR1 (25 MHZ)
from Connection Matrix
Output [91]
Power-Down/Force On
Matrix Output control register [713]
to HV GPO Charge Pumps
OSC Power Mode
register [712]
Power-Down/
Force On
25 MHz Pre-divider Clock
registers [716:714]
OSC1
(25 MHz)
to PWMs and CNT/DLYs Clock Scheme
Auto Power-On
Force Power-On
OUT
0
1
0
1
Startup delay
0
DIV /1 /2 /4 /8 /12
register [722]
/2
/4
1
2
3
4
5
6
Predivider
Ext. Clock
OSC1 Matrix OUT Enable register [721]
Ext. CLK Sel
register [720]
/3
to Connection Matrix
Input [53]
/8
/12
/24
/64
7
OSC1 Matrix OUT Enable for
flexible divider register [740]
registers
[719:717]
Flexible Divider
OUT
CLK
OSC1 CLK Enable for
Flexible Divider reg [741]
to Flex-Divider out Connection
Matrix Input [54]
CNT
Data
Second Stage
Divider
To PWMx Period
Counter Clock
registers [751:744]
Figure 127: Oscillator1 Block Diagram
The OSC-integrated divider is built into 25 MHz OSC for saving chip resources. Actually, this divider is created especially for
PWM, but it can be used for other chip resources thanks to its output to the matrix. There is 8-bit Counter with the source from
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OSC pre-divider and output to the matrix. In many cases for all PWM macrocells, the same frequency is a need. In these cases,
it is possible to use this PWM divider for fine frequency tuning of PWM cells by I2C or from NVM.
18.4 CNT/DLY CLOCK SCHEME
Each CNT/DLY within Multi-Function macrocell has its own additional clock divider connected to oscillators pre-divider. Available
dividers are:
OSC0/1, OSC0/8, OSC0/64, OSC0/512, OSC0/4096, OSC0/32768, OSC0/262144
OSC1/1, OSC1/4
It is possible also to connect input from CNT(x-1) overflow or from Connection Matrix OUT.
Clock source sel [3:0]
0
1
25 MHz Pre-divided clock
Div4
2
3
Div8
CNT/DLY/
ONESHOT/
FREQ_DET/
2.048 kHz Pre-divided clock
Div64
Div512
4
5
6
7
8
9
DLY_EDGE_DET
Div4096
Div32768
Div262144
CNT (x) overflow
CNT (x-1) overflow
10
From Connection Matrix Out
(separate for each CNT/DLY macrocell)
CNT0/CNT1/CNT2/CNT3/CNT4
Figure 128: Clock Scheme
18.5 PWM CLOCK SCHEME
Each PWM macrocell has its own additional clock divider connected to oscillators pre-divider. Available dividers are:
OSC1/1, OSC1/8, OSC1/64, OSC1/512, OSC1/4096, OSC1/32768, OSC1/262144
OSC0/1, OSC0/4
It is possible also to connect input from Flexible Divider (OSC1 clock divider) or from Connection Matrix OUT.
Clock source sel[3:0]
0
1
2.048 kHz Pre-divided clock
Div4
2
3
Div8
25 MHz Pre-divided clock
Div64
Div512
4
5
PWM
Div4096
Div32768
Div262144
6
7
8
9
from Flexible Divider
10
From Connection Matrix OUT (separate
for each PWM macrocell)
PWM0/PWM1
Figure 129: PWM Clock Scheme
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18.6 EXTERNAL CLOCKING
The SLG47105 supports several ways to use an external, higher accuracy clock as a reference source for internal operations.
Note that the Low Voltage Digital Input pin type can only support up to 1 MHz.
18.6.1 GPIO1 Source for Oscillator0 (2.048 kHz)
When register [725] is set to 1, an external clocking signal on GPIO1 will be routed in place of the internal oscillator derived 2.048
kHz clock source. See Figure 126. The low and high limits for external frequency that can be selected are 0 MHz and 10 MHz.
18.6.2 GPIO4 Source for Oscillator 1 (25 MHz)
When register [720] is set to 1, an external clocking signal on GPIO4 will be routed in place of the internal oscillator derived 25
MHz clock source. See Figure 127. The external frequency range is 0 MHz to 20 MHz at VDD = 2.3 V, 30 MHz at VDD = 3.3 V, 50
MHz at VDD = 5.0 V. When an external clock is selected for OSC1, the oscillator's output signal will be inverted with respect to
the GPIO4 input signal.
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18.7 OSCILLATORS POWER-ON DELAY
OSC enable
Power-On
Delay
CLK
Figure 130: Oscillator Startup Diagram
Note 1 OSC power mode: “Auto Power-On”.
Note 2 “OSC enable” signal appears when any macrocell that uses OSC is powered on.
750
700
650
600
550
500
450
400
VDD (V)
Figure 131: Oscillator0 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 2.048 kHz
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160
140
120
100
80
Start with Delay
Normal Start
60
40
20
0
VDD (V)
Figure 132: Oscillator1 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC1 = 25 MHz
18.8 OSCILLATORS ACCURACY
Note: OSC power setting: Force Power-On; Clock to matrix input - enable; Bandgap: turn on by register - enable..
2.2
Fmax @ VDD = 2.5 V to 5 V
2.15
Ftyp @ VDD = 3.3 V
Fmin @ VDD = 2.5 V to 5 V
2.1
2.05
2
1.95
1.9
T (°C)
Figure 133: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz
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26.2
25.8
25.4
25
Fmax @ VDD = 2.5 V to 5 V
Ftyp @ VDD = 3.3 V
Fmin @ VDD = 2.5 V to 5 V
24.6
24.2
23.8
T (°C)
Figure 134: Oscillator1 Frequency vs. Temperature, OSC1 = 25 MHz
7
6
5
4
3
2
1
2.048 kHz Total Error @ VDD = 2.3 V to 5.5 V
25 MHz Total Error @ VDD = 2.3 V to 5.5 V
T (°C)
Figure 135: Oscillators Total Error vs. Temperature
Note For more information see section 3.12.
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18.9 OSCILLATORS SETTLING TIME
490
485
480
475
470
465
460
455
450
445
440
0
1
2
3
4
Period
Figure 136: Oscillator0 Settling Time, VDD = 3.3 V, T = 25 °C, OSC0 = 2 kHz
90
80
70
60
50
40
30
20
10
0
2
4
6
8
10
12
Period
Figure 137: Oscillator1 Settling Time, VDD = 3.3 V, T = 25 °C, OSC1 = 25 MHz (Normal Start)
14
16
18
20
22
24
26
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130
110
90
70
50
30
10
0
2
4
6
8
10
12
14
16
18
20
Period
Figure 138: Oscillator1 Settling Time, VDD = 3.3 V, T = 25 °C, OSC1 = 25 MHz (Start with Delay)
18.10 OSCILLATORS CURRENT CONSUMPTION
3.2
2.7
2.2
1.7
1.2
0.7
0.2
Tj = 150 °C
Tj = 85 °C
Tj = 25 °C
Tj = -40 °C
2.4
2.9
3.4
3.9
4.4
4.9
5.4
VDD (V)
Figure 139: OSC0 Current Consumption vs. VDD (All Pre-Dividers)
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150
140
130
120
110
100
90
Tj = 150 °C
Tj = 85 °C
Tj = 25 °C
Tj = -40 °C
80
70
60
50
2.4
2.9
3.4
3.9
4.4
4.9
5.4
VDD (V)
Figure 140: OSC1 Current Consumption vs. VDD (Pre-Divider = 1)
120
110
100
90
80
70
Tj = 150 °C
Tj = 85 °C
Tj = 25 °C
Tj = -40 °C
60
50
40
2.4
2.9
3.4
3.9
4.4
4.9
5.4
VDD (V)
Figure 141: OSC1 Current Consumption vs. VDD (Pre-Divider = 2)
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100
90
80
70
60
50
40
30
Tj = 150 °C
Tj = 85 °C
Tj = 25 °C
Tj = -40 °C
2.4
2.9
3.4
3.9
4.4
4.9
5.4
VDD (V)
Figure 142: OSC1 Current Consumption vs. VDD (Pre-Divider = 4)
90
80
70
60
50
40
30
Tj = 150 °C
Tj = 85 °C
Tj = 25 °C
Tj = -40 °C
2.4
2.9
3.4
3.9
4.4
4.9
5.4
VDD (V)
Figure 143: OSC1 Current Consumption vs. VDD (Pre-Divider = 8)
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90
80
70
60
50
40
30
Tj = 150 °C
Tj = 85 °C
Tj = 25 °C
Tj = -40 °C
2.4
2.9
3.4
3.9
4.4
4.9
5.4
VDD (V)
Figure 144: OSC1 Current Consumption vs. VDD (Pre-Divider = 12)
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19 Low Power Bandgap (LP_BG)
Low Power Bandgap is the analog part, that is used by analog macrocells in HV PAK, such as 25 MHz OSC1, ACMPs, HV
GPOs, UVLO, and others. The high efficiency low power Bangap consumes just 510 nA. However, it requires about 2 ms Start
Up Time for stable functionality. For these reasons, it is recommended to keep LP_BG always on.
It is still possible to turn off the LP_BG through the connection matrix when no analog blocks are used.
Please note that OSC0 (2.048 kHz) does not use LP_BG.
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20 Power-On Reset
The SLG47105 has a Power-On Reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in
the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first
ramping to the device, and also while the VDD is falling during Power-down. To accomplish this goal, the POR drives a defined
sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of
the IOs.
20.1 GENERAL OPERATION
The SLG47105 is guaranteed to be powered down and non-operational when the VDD voltage (voltage on Pin 1) is less than
Power-Off Threshold (see in Table 7), but not less than -0.6 V. Another essential condition for the chip to be powered down is that
no voltage higher (Note ) than the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3 V, applying a voltage
higher than 0.3 V to any other pin is incorrect, and can lead to incorrect or unexpected device behavior.
Note There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes.
To start the POR sequence in the SLG47105, the voltage applied on the VDD should be higher than the Power-On Threshold
(Note ). The full operational VDD range for the SLG47105 is 2.3 V to 5.5 V. This means that the VDD voltage must ramp up to the
operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power-On threshold.
After the POR sequence is started, the SLG47105 will have a typical period of time to go through all the steps in the sequence
(noted in the datasheet for that device) and will be ready and completely operational after the POR sequence is complete.
Note The Power-On Threshold is defined in Table 7.
To power-down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down it
should be less than Power-Off Threshold.
All Pins are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step
in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin
configuration at this point in time is defined by the design programmed into the chip. Also, as it was mentioned before the voltage
on Pins can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.
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20.2 POR SEQUENCE
The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 145.
VDD
t
POR_NVM
(reset for NVM)
t
t
t
t
t
t
t
NVM_ready_out
POR_GPI
(reset for input enable)
POR_LUT
(reset for LUT/FILTER)
POR_CORE
(reset for DLY/RCO/DFF/LATCH/
Pipe DLY/ACMP/
Edge Detector in Filter)
POR_OUT
(generate low to high to matrix)
POR_GPO
(reset for output enable)
Figure 145: POR Sequence
As can be seen from Figure 145 after the VDD has started ramping up and crosses the Power-On threshold, first, the on-chip NVM
memory is reset. Next, the chip reads the data from NVM and transfers this information to a CMOS LATCH, that serves to configure
each macrocell, and the Connection Matrix, which routes signals between macrocells. The third stage causes the reset of the
input pins, and then enables them. After that, the LUTs are reset and become active. After LUTs, the Delay cells, OSCs, DFFs,
LATCHES, and Pipe Delay are initialized. Only after all macrocells are initialized internal POR signal (POR macrocell output) goes
from LOW to HIGH. The last portion of the device to be initialized are the output pins, which transition from high impedance to
active at this point.
The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many
environmental factors, such as: slew rate, VDD value, temperature, and even will vary from chip to chip (process influence).
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20.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE
To have a full picture of SLG47105 operation during powering and POR sequence, review the overview the macrocell output
states during the POR sequence (Figure 146 describes the output signals states).
First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output pins which are in high
impedance state). On the next step, some of the macrocells start initialization: input pins output state becomes LOW; LUTs also
output LOW. Only P_DLY macrocell configured as edge detector becomes active at this time. After that input pins are enabled.
Next, only LUTs are configured. Next, all other macrocells are initialized. After macrocells are initialized, internal POR matrix signal
switches from LOW to HIGH. The last are output pins that become active and determined by the input signals.
VDD
Guaranteed HIGH before POR_GPI
t
VDD _out
to matrix
Unpredictable
t
Input Pin_out
Unpredictable
Unpredictable
Unpredictable
Determined by External Signal
Determined by Input signals
to matrix
t
LUT/FILTER_out
to matrix
Determined by input signals
OUT = IN without Delay
t
t
t
t
t
t
Programmable Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
Determined by initial state
DFF/LATCH/ACMP/
Edge Detector in
Filter_out to matrix
Unpredictable
Unpredictable
Unpredictable
Determined by Input signals
Determined by input signals
OUT = IN without Delay
Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
POR_out
to matrix
Ext. GPO
Tri-state
Determined by input signals
Output State Unpredictable
Figure 146: Internal Macrocell States During POR Sequence
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20.3.1 Initialization
All internal macrocells by default have initial low level. Starting from indicated power-up time of 1.80 V to 2.16 V, macrocells in
SLG47105 are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then
the reset signal is released for internal macrocells and they start to initialize according to the following sequence:
Input pins, ACMP, Pull-up/down.
LUTs.
DFFs, Delays/Counters, Pipe Delay.
POR output to matrix.
Output pin corresponds to the internal logic.
The Vref output pin driving signal can precede POR output signal going high by 3 µs to 5 µs. The POR signal going high indicates
the mentioned power-up sequence is complete.
Note: The maximum voltage applied to any pin should not be higher than the VDD level. There are ESD Diodes between pin →
VDD and pin → GND on each pin. So, if the input signal applied to pin is higher than VDD, then current will sink through the diode
to VDD. Exceeding VDD results in leakage current on the input pin, and VDD will be pulled up, following the voltage on the input
pin.There is no effect from input pin when input voltage is applied at the same time as VDD
.
20.3.2 Power-Down
VDD (V)
2 V
1.83 V
1.33 V
1 V Vref Out Signal
1 V
Time
Not guaranteed output state
Figure 147: Power-Down
During Power-down, macrocells in SLG47105 are powered off after VDD falling down below Power-Off Threshold. Please note
that during a slow rampdown, outputs can possibly switch state during this time.
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21 I2C Serial Communications Macrocell
21.1 I2C SERIAL COMMUNICATIONS MACROCELL OVERVIEW
In the standard use case for the GreenPAK devices, the configuration choices made by the user are stored as bit settings in the
Non-Volatile Memory (NVM), and this information is transferred at startup time to volatile RAM registers that enable the
configuration of the macrocells. Other RAM registers in the device are responsible for setting the connections in the Connection
Matrix to route signals in the manner most appropriate for the user’s application.
The I2C Serial Communications Macrocell in this device allows an I2C bus Master to read and write this information via a serial
channel directly to the RAM registers, allowing the remote re-configuration of macrocells and remote changes to signal chains
within the device.
The I2C bus Master is also able to read and write other register bits that are not associated with NVM memory. As an example,
the input lines to the Connection Matrix can be read as digital register bits. These are the signal outputs of each of the
macrocells in the device, giving the I2C bus Master the capability to remotely read the current value of any macrocell.
The user has the flexibility to control read access and write access via registers bits registers [1967:1965]. See Section 21.5.1
for more details on I2C read/write memory protection.
Normally, when VDD is not applied, the external I2C Pull-up resistors can be connected to the I2C pins of the SLG47105. It does
not affect the chip functionality and doesn't increase its current consumption.
21.2 I2C SERIAL COMMUNICATIONS DEVICE ADDRESSING
Each command to the I2C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are
shown in Figure 148. After the Start bit, the first four bits are a control code. Each bit in a control code can be sourced
independently from the register or by value defined externally by GPI, GPIO6, GPIO4, and GPIO1. The LSB of the control code
is defined by the value of GPI, while the MSB is defined by the value of GPIO1. The address source (either register bit or Pin for
each bit in the control code is defined by registers [2027:2024]. This gives the user flexibility on the chip level addressing of this
device and other devices on the same I2C bus. The Block Address is the next three bits (A10, A9, A8), which will define the most
significant bits in the addressing of the data to be read or written by the command. The last bit in the Control Byte is the R/W bit,
which selects whether a read command or write command is requested, with a “1” selecting for a Read command, and a “0”
selecting for a Write command. This Control Byte will be followed by an Acknowledge bit (ACK), which is sent by this device to
indicate successful communication of the Control Byte data.
In the I2C-bus specification and user manual, there are two groups of eight addresses (0000 xxx and 1111 xxx) that are
reserved for the special functions, such as a system General Call address. If the user of this device choses to set the Control
Code to either “1111” or “0000” in a system with other slave device, please consult the I2C-bus specification and user manual to
understand the addressing and implementation of these special functions, to ensure reliable operation.
In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of
information, resulting in a total address space of 2K bytes. Of this 2K byte address space, the valid addresses accessible to the
I2C Macrocell on the SLG47105 are in the range from 0 (0x00) to 255 (0xFF). The MSB address bits (A10, A9, and A8) will be
“0” for all commands to the SLG47105.
With the exception of the Current Address Read command, all commands will have the Control Byte followed by the Word
Address. Figure 148 shows this basic command structure.
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Start
bit
Acknowledge
bit
Control Byte
Word Address
A
10
A
9
A
8
A
7
A
0
S
X
X
X
X
R/W ACK
Control
Code
Block
Address
Not used, set to
0
Read/Write bit
(1 = Read, 0 = Write)
Figure 148: Basic Command Structure
21.3 I2C SERIAL GENERAL TIMING
General timing characteristics for the I2C Serial Communications macrocell are shown in Figure 149. Timing specifications can
be found in the AC Characteristics section.
tHIGH
tF
tR
tLOW
SCL
tSU STA
tHD DAT
tHD STA
tSU DAT
tSU STO
SDA IN
tBUF
tAA
tDH
SDA OUT
Figure 149: I2C General Timing Characteristics
21.4 I2C SERIAL COMMUNICATIONS COMMANDS
21.4.1 Byte Write Command
Following the Start condition from the Master, the Control Code [4 bits], the Block Address [3 bits], and the R/W bit (set to “0”)
are placed onto the I2C bus by the Master. After the SLG47105 sends an Acknowledge bit (ACK), the next byte transmitted by
the Master is the Word Address. The Block Address (A10, A9, A8), combined with the Word Address (A7 through A0), together
set the internal address pointer in the SLG47105, where the data byte is to be written. After the SLG47105 sends another
Acknowledge bit, the Master will transmit the data byte to be written into the addressed memory location. The SLG47105 again
provides an Acknowledge bit and then the Master generates a Stop condition. The internal write cycle for the data will take place
at the time that the SLG47105 generates the Acknowledge bit.
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It is possible to LATCH all IOs during I2C write command, register [1961] = 1 - Enable. It means that IOs will remain their state
until the write command is done.
Acknowledge
bit
Acknowledge
bit
Start
bit
Acknowledge
bit
Bus Activity
Control Byte
Word Address
Data
A
10
A
9
A
8
A
7
A
0
D
7
D
0
S
X
X
X
X
W
ACK
ACK
ACK
SDA LINE
P
Control
Code
Block
Address
Stop
bit
Not used,
set to 0
R/W bit = 0
Figure 150: Byte Write Command, R/W = 0
21.4.2 Sequential Write Command
The write Control Byte, Word Address, and the first data byte are transmitted to the SLG47105 in the same way as in a Byte Write
command. However, instead of generating a Stop condition, the Bus Master continues to transmit data bytes to the SLG47105.
Each subsequent data byte will increment the internal address counter, and will be written into the next higher byte in the command
addressing. As in the case of the Byte Write command, the internal write cycle will take place at the time that the SLG47105
generates the Acknowledge bit.
Acknowledge
Acknowledge
bit
Start
bit
bit
Bus Activity
Data (n + 1)
Data (n + x)
Control Byte
Word Address (n)
Data (n)
A
10
A
8
A
9
ACK
ACK
P
SDA LINE
S
X
X
X
X
W
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
Not used, set to 0
Write bit
Figure 151: Sequential Write Command
21.4.3 Current Address Read Command
The Current Address Read Command reads from the current pointer address location. The address pointer is incremented at the
first STOP bit following any write control byte. For example, if a Sequential Read command (which contains a write control byte)
reads data up to address n, the address pointer would get incremented to n + 1 upon the STOP of that command. Subsequently,
a Current Address Read that follows would start reading data at n + 1. The Current Address Read Command contains the Control
Byte sent by the Master, with the R/W bit = “1”. The SLG47105 will issue an Acknowledge bit, and then transmit eight data bits
for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition.
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Start
bit
Acknowledge
bit
Stop
bit
Bus Activity
Control Byte
Data (n)
A
10
A
9
A
8
S
X
X
X
X
R
ACK
SDA LINE
P
Control
Code
Block
Address
No Ack
bit
Not used, set to 0
R/W bit = 1
Figure 152: Current Address Read Command, R/W = 1
21.4.4 Random Read Command
The Random Read command starts with a Control Byte (with R/W bit set to “0”, indicating a write command) and Word Address
to set the internal byte address, followed by a Start bit, and then the Control Byte for the read (exactly the same as the Byte Write
command). The Start bit in the middle of the command will halt the decoding of a Write command, but will set the internal address
counter in preparation for the second half of the command. After the Start bit, the Bus Master issues a second control byte with
the R/W bit set to “1”, after which the SLG47105 issues an Acknowledge bit, followed by the requested eight data bits.
Acknowledge
Stop
bit
Start
bit
bit
Bus Activity
SDA LINE
Not used, s
Data (n)
Control Byte
Word Address (n)
Control Byte
A
A
9
A
8
A
A
9
A
8
R
ACK
P
S
ACK
X
X
X
X
W
ACK
S
X
X
X
X
10
10
Control
Code
Block
Address
Control
Code
Block
Address
No Ack
bit
et to 0
Write bit
Read bit
Figure 153: Random Read Command
21.4.5 Sequential Read Command
The Sequential Read command is initiated in the same way as a Random Read command, except that, once the SLG47105
transmits the first data byte, the Bus Master issues an Acknowledge bit as opposed to a Stop condition in a random read. The
Bus Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition.
Acknowledge
Start
bit
bit
Bus Activity
Data (n + 2)
Data (n + x)
Control Byte
Data (n)
Data (n + 1)
A
10
A
9
A
8
ACK
P
SDA LINE
S
X
X
X
X
R
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
No Ack
bit
Read bit
Figure 154: Sequential Read Command
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21.5 I2C SERIAL COMMAND REGISTER MAP
21.5.1 Register Read/Write Protection
There are seven read/write protect modes for the design sequence from being corrupted or copied. See Table 76 for details.
Table 76: Read/Write Protection Options
Protection Modes Configuration
Partly
Partly
Lock
Partly
Lock
Lock
Read/
Write
Data
Output
From
Lock
Read2/
Write
Lock
Read
Lock
Write
Register
Address
Configurations
Unlocked
Read1
Read2
(Mode 0) (Mode1) (Mode2) (Mode3) (Mode4) (Mode5) (Mode 6)
I2C Byte Write Bit
Masking
R/W
R/W
R/W
R/W
W
R
-
Memory
F6
(section 21.5.5)
I2C Serial Reset
Command
(section 21.5.2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
R
R
R
-
-
-
Memory
Memory
Macrocell
F5,b'0
F5,b'1
4C
Outputs LATCHing
During I2C Write
Connection Matrix
Virtual Inputs
(section 10.3)
ConfigurationBits for
All Macrocells
(IO Pins, ACMPs,
Combination
FunctionMacrocells,
and others)
R/W
R/W
R/W
W
W
W
-
-
W
W
R
R
-
-
Memory
Memory
Macrocells Inputs
Configuration
(Connection Matrix
Outputs, section
10.2)
0~47
Protection Mode
Enable
R
R
R
R
R
R
R
R
R
R
R
R
R
Memory
Memory
F5,b'4
Protection Mode
Selection
R/W
F5,b'7~5
Macrocells Output
Values (Connection
MatrixInputs,section
10.1)
48~4B;
4D~4F
R
R
R
R
-
R
-
Macrocell
Macrocell
Counter Current
Value
(for 16-bit CNT)
R
R
R
R
R
R
R
R
-
-
R
R
-
-
89, 8A
Counter Current
Value
Macrocell 8B, A4, A5
(for 8-bit CNT)
I2C Control Code
(section 21.2)
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Memory
Memory
FD,b'3~0
FD,b'7~4
Pin Slave Address
Select
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Table 76: Read/Write Protection Options(Continued)
Protection Modes Configuration
Partly
Partly
Lock
Partly
Lock
Lock
Read/
Write
Data
Output
From
Lock
Read2/
Write
Lock
Read
Lock
Write
Register
Address
Configurations
Unlocked
Read1
Read2
(Mode 0) (Mode1) (Mode2) (Mode3) (Mode4) (Mode5) (Mode 6)
I2C Disable/Enable
R
R
R
R
R
R
R
Memory
FE,b'0
R/W
W
R
Allow Read and Write Data
Allow Write Data Only
Allow Read Data Only
-
The Data is protected for Read and Write
It is possible to read some data from macrocells, such as counter current value, connection matrix, and connection matrix virtual
inputs. The I2C write will not have any impact on data in case data comes from macrocell output, except Connection Matrix Virtual
Inputs. The silicon identification service bits allows identifying silicon family, its revision, and others.
See Section 23 for detailed information on all registers.
21.5.2 I2C Serial Reset Command
If I2C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including
configuration of all macrocells, and all connections provided by the Connection Matrix. This is implemented by setting register
[1960] I2C reset bit to “1”, which causes the device to re-enable the Power-On Reset (POR) sequence, including the reload of all
register data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has taken place,
the contents of register [1960] will be set to “0” automatically. Figure 155 illustrates the sequence of events for this reset function
.
Acknowledge
bit
Acknowledge
bit
Start
bit
Acknowledge
bit
Bus Activity
Control Byte
Word Address
Data
A
10
A
9
A
8
A
7
A
0
D
7
D
0
S
X
X
X
X
W
ACK
ACK
ACK
SDA LINE
P
Internal Reset bit
Control
Code
Block
Address
Stop
bit
Not used, set to
0
Write bit
by I2C Stop Signal
Reset-bit register output
DFF output gated by stop signal
Internal POR for core only
Figure 155: Reset Command Timing
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21.5.3 I2C Additional Options
When Output latching during I2C write, register [1961] = 1 allows all Pins output value to be latched until I2C write is done. It will
protect the output change due to configuration process during I2C write in case multiple register bytes are changed. Inputs and
internal macrocells retain their status during I2C write.
If the user sets GPIO3 and GPIO2 function to a selection other than SDA and SCL, all access via I2C will be disabled.
Note: Any write commands that come to the device via I2C that are not blocked, based on the protection bits, will change the
contents of the RAM register bits that mirror the NVM bits. These write commands will not change the NVM bits themselves, and
a POR event will restore the register bits to original programmed contents of the NVM.
See Section 23 for detailed information on all registers.
21.5.4 Reading Current Counter Data via I2C
The current counter value in two counters in the device can be read via I2C. The counters that have this additional functionality
are 16-bit CNT0 and 8-bit CNT4.
21.5.5 I2C Byte Write Bit Masking
The I2C macrocell inside SLG47105 supports masking of individual bits within a byte that is written to the RAM memory space.
This function is supported across the entire RAM memory space. To implement this function, the user performs a Byte Write
Command (see Section 21.4.1 for details) on the I2C Byte Write Mask Register (address 0xF6) with the desired bit mask pattern.
This sets a bit mask pattern for the target memory location that will take effect on the next Byte Write Command to this register
byte. Any bit in the mask that is set to “1” in the I2C Byte Write Mask Register will mask the effect of changing that particular bit
in the target register, during the next Byte Write Command. The contents of the I2C Byte Write Mask Register are reset (set to
00h) after valid Byte Write Command. If the next command received by the device is not a Byte Write Command, the effect of the
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bit masking function will be aborted, and the I2C Byte Write Mask Register will be reset with no effect. Figure 156 shows an
example of this function.
User Actions
Byte Write Command, Address = F6h, Data = 11110000b [sets mask bits]
Byte Write Command, Address = 74h, Data = 10101010b [writes data with mask]
Memory Address 74h (original contents)
Mask to choose bit from new
write command
1
1
1
1
0
0
1
1
0
0
0
0
Mask to choose bit from
original register contents
Memory Address 74h (new data in write command)
0 1
1
0
1
0
Bit from new write command
Memory Address F6h (mask register)
1
1
1
0
0
0
Bit from original register
contents
Memory Address 74h (new contents after write command)
1
1
0
0
1
0
1
0
Figure 156: Example of I2C Byte Write Bit Masking
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22 Analog Temperature Sensor
The SLG47105 has an Analog Temperature sensor (TS) with an output voltage linearly-proportional to the Centigrade tempera-
ture. The TS cell shares buffer with Vref0, so it is impossible to use both cells simultaneously, its output can be connected directly
to the ACMP1_H positive input. The TS is rated to operate over a -40 °C to 150 °C junction temperature range. The error in the
whole temperature range does not exceed ±2 %. For more details refer to Section 3.16.
The equation below calculates the typical analog voltage passed from the TS to the ACMPs' IN+ source input. It is important to
note that there will be a chip to chip variation of about ±2 °C.
VTS1 = -2.4 x T + 912.3
VTS2 = -2.9 x T + 1101.3
where:
VTS1 (mV) - TS Output Voltage, range 1
VTS2 (mV) - TS Output Voltage, range 2
T (°C) - Temperature
Temperature hysteresis can be setup by enabling the GreenPAK's internal ACMP hysteresis.
TS
Power-Down Source
register [649]
VDD
register[648]
0
1
Power-
Down
from Connection
Matrix Output [92]
reg_vref_sel[646:647]
reg_ts_range_sel[650]
Vref0
Vref1
Vts
ACMP0H Vref
ACMP1H Vref
GPIO0
Vref Out
To ACMP
GPIO0_OE
Vref Logic and
Buffer
M[2]
M[1]
M[0]
reg_pdb[643]
0
1
PDb
nRESET
matrix_pdb[92]
reg_pd_sel[644]
reg_load_range_sel
[645]
Figure 157: Analog Temperature Sensor Structure Diagram
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1.22
1.17
1.12
1.07
1.02
0.97
0.92
0.87
0.82
0.77
0.72
0.67
0.62
0.57
0.52
Range 2
Range 1
T (°C)
Figure 158: TS Output vs. Temperature, VDD = 2.3 V to 5.5 V
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23 Register Definitions
23.1 REGISTER MAP
Table 77: Register Map
Address
Signal Function
Register Bit Definition
Byte Register Bit
Matrix Output
0
0
5:0
Matrix OUT0
Matrix OUT1
GPIO0 Digital Output
11:6
GPIO0 Digital Output OE
1
1
17:12
Matrix OUT2
GPIO1 Digital Output
2
2
23:18
29:24
Matrix OUT3
Matrix OUT4
GPIO1 Digital Output OE
GPIO2 Digital Output
3
3
35:30
41:36
Matrix OUT5
Matrix OUT6
GPIO3 Digital Output
GPIO4 Digital Output
4
4
5
5
47:42
53:48
Matrix OUT7
Matrix OUT8
GPIO4 Digital Output OE
GPIO5 Digital Output
6
6
59:54
65:60
Matrix OUT9
Matrix OUT10
GPIO5 Digital Output OE
GPIO6 Digital Output
7
7
8
8
71:66
77:72
Matrix OUT11
Matrix OUT12
GPIO6 Digital Output OE
HV GPO0 Digital Output
9
9
83:78
89:84
Matrix OUT13
Matrix OUT14
HV GPO0 Digital Output OE
HV GPO1 Digital Output
A
A
B
B
C
C
D
D
E
E
F
F
10
10
11
95:90
Matrix OUT15
Matrix OUT16
HV GPO1 Digital Output OE
HV GPO2 Digital Output
101:96
107:102
113:108
Matrix OUT17
Matrix OUT18
HV GPO2 Digital Output OE
HV GPO3 Digital Output
119:114
125:120
Matrix OUT19
Matrix OUT20
HV GPO3 Digital Output OE
Reserved
131:126
137:132
Matrix OUT21
Matrix OUT22
Reserved
Reserved
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Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
HV GPO0 SLEEP or Power-up Current Sense
Comparator A
11
12
143:138
149:144
Matrix OUT23
Matrix OUT24
HV GPO1 SLEEP or Power-up Current Sense
Comparator A
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
1A
1A
1B
1B
1C
1C
1D
HV GPO2 SLEEP or Power-up Current Sense
Comparator B
155:150
161:156
Matrix OUT25
Matrix OUT26
HV GPO3 SLEEP or Power-up Current Sense
Comparator B
167:162
173:168
Matrix OUT27
Matrix OUT28
IN0 of LUT2_0 or Clock Input of DFF0
IN1 of LUT2_0 or Data Input of DFF0
179:174
185:180
Matrix OUT29
Matrix OUT30
IN0 of LUT2_3 or Clock Input of PGen
IN1 of LUT2_3 or nRST of PGen
191:186
197:192
Matrix OUT31
Matrix OUT32
IN0 of LUT2_1 or Clock Input of DFF1
IN1 of LUT2_1 or Data Input of DFF1
203:198
209:204
Matrix OUT33
Matrix OUT34
IN0 of LUT2_2 or Clock Input of DFF2
IN1 of LUT2_2 or Data Input of DFF2
215:210
221:216
Matrix OUT35
Matrix OUT36
IN0 of LUT3_0 or Clock Input of DFF3
IN1 of LUT3_0 or Data Input of DFF3
227:222
233:228
Matrix OUT37
Matrix OUT38
IN2 of LUT3_0 or nRST(nSET) of DFF3
IN0 of LUT3_1 or Clock Input of DFF4
or Blanking of Chopper0
IN1 of LUT3_1 or Data Input of DFF4
or Chop of Chopper0
1D
1E
239:234
245:240
Matrix OUT39
Matrix OUT40
IN2 of LUT3_1 or nRST(nSET) of DFF4 of PWM of
Chopper0
1E
1F
1F
20
IN0 of LUT3_2 or Clock Input of DFF5
or Blanking of Chopper1
251:246
257:252
Matrix OUT41
Matrix OUT42
IN1 of LUT3_2 or Data Input of DFF5
or Chop of Chopper1
IN2 of LUT3_2 or nRST(nSET) of DFF5 of PWM of
Chopper1
20
263:258
269:264
Matrix OUT43
Matrix OUT44
21
21
22
IN0 of LUT3_3 or Clock Input of DFF6
275:270
Matrix OUT45
IN1 of LUT3_3 or Data Input of DFF6
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Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
22
281:276
23
Matrix OUT46
IN2 of LUT3_3 or nRST(nSET) of DFF6
23
24
24
25
25
26
26
27
27
28
28
29
29
2A
2A
2B
2B
2C
2C
287:282
293:288
Matrix OUT47
Matrix OUT48
IN0 of LUT3_4 or Clock Input of DFF7
IN1 of LUT3_4 or Data Input of DFF7
299:294
305:300
Matrix OUT49
Matrix OUT50
IN2 of LUT3_4 or nRST(nSET) of DFF7
IN0 of LUT3_5 or Clock Input of DFF8
311:306
317:312
Matrix OUT51
Matrix OUT52
IN1 of LUT3_5 or Data Input of DFF8
IN2 of LUT3_5 or nRST(nSET) of DFF8
IN0 of LUT3_6 or Input of Pipe Delay or UP Signal of
RIPP CNT
323:318
329:324
Matrix OUT53
Matrix OUT54
IN1 of LUT3_6 or nRST of Pipe Delay or nSET of RIPP
CNT
335:330
341:336
Matrix OUT55
Matrix OUT56
IN2 of LUT3_6 or Clock of Pipe Delay/RIPP_CNT
IN0 of LUT4_0 or Clock Input of DFF9
347:342
Matrix OUT57
IN1 of LUT4_0 or Data Input of DFF9
353:348
359:354
Matrix OUT58
Matrix OUT59
IN2 of LUT4_0 or nRST(nSET) of DFF9
IN3 of LUT4_0
MULTFUNC_8BIT_1: IN0 of LUT3_7 or Clock Input of
DFF10;
Delay1 Input (or Counter1 nRST input)
2D
2D
2E
365:360
Matrix OUT60
MULTFUNC_8BIT_1: IN1 of LUT3_7 or nRST (nSET) of
DFF10;
Delay1 Input (or Counter1 nRST Input) or Delay/
Counter1 External Clock Source
371:366
Matrix OUT61
2E
2F
MULTFUNC_8BIT_1: IN2 of LUT3_7 or Data Input of
DFF10;
Delay1 Input (or Counter1 nRST Input)
377:372
383:378
Matrix OUT62
Matrix OUT63
MULTFUNC_8BIT_2: IN0 of LUT3_8 or Clock Input of
DFF11;
Delay2 Input (or Counter2 nRST Input)
2F
30
MULTFUNC_8BIT_2: IN1 of LUT3_8 or nRST (nSET) of
DFF11;
Delay2 Input (or Counter2 nRST Input) or Delay/
Counter2 External Clock Source
389:384
Matrix OUT64
MULTFUNC_8BIT_2: IN2 of LUT3_8 or Data Input of
DFF11;
Delay2 Input (or Counter2 nRST Input)
30
31
Matrix OUT65
Matrix OUT66
395:390
401:396
MULTFUNC_8BIT_3: IN0 of LUT3_9 or Clock Input of
DFF12;
Delay3 Input (or Counter3 nRST Input)
31
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Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
MULTFUNC_8BIT_3: IN1 of LUT3_9 or nRST (nSET) of
DFF12;
Delay3 Input (or Counter3 nRST Input) or Delay/
Matrix OUT67
32
33
407:402
Counter3 External Clock Source
MULTFUNC_8BIT_3: IN2 of LUT3_9 or Data Input of
DFF12;
Delay3 Input (or Counter3 nRST Input)
Matrix OUT68
Matrix OUT69
413:408
419:414
MULTFUNC_8BIT_4: IN0 of LUT3_10 or Clock Input of
DFF13;
Delay4 Input (or Counter4 nRST Input)
33
34
34
MULTFUNC_8BIT_4: IN1 of LUT3_10 or nRST (nSET)
of DFF13;
Delay4 Input (or Counter4 nRST Input) or Delay/
Counter4 External Clock Source
Matrix OUT70
425:420
35
35
MULTFUNC_8BIT_4: IN2 of LUT3_10 or Data Input of
DFF13;
Delay4 Input (or Counter4 nRST Input)
Matrix OUT71
Matrix OUT72
431:426
437:432
MULTFUNC_16BIT_0: IN0 of LUT4_1 or Clock Input of
DFF14;
Delay0 Input (or Counter0 RST/SET Input)
36
MULTFUNC_16BIT_0: IN1 of LUT4_1 or nRST of
DFF14;
Delay0 Input (or Counter0 nRST Input) or Delay/
Counter0 External Clock Source
36
37
Matrix OUT73
Matrix OUT74
Matrix OUT75
443:438
449:444
455:450
MULTFUNC_16BIT_0: IN2 of LUT4_1 or nSET of
DFF14 or KEEP Input of FSM0 or External Clock Input
of Delay0 (or Counter0)
37
38
MULTFUNC_16BIT_0: IN3 of LUT4_1 or Data Input of
DFF14;
Delay0 Input (or Counter0 nRST Input) or UP Input of
FSM0
38
Matrix OUT76
Matrix OUT77
PWM0_UP/DOWN
39
39
3A
3A
3B
3B
3C
3C
3D
3D
3E
3E
3F
3F
40
461:456
467:462
PWM0_KEEP/STOP
Matrix OUT78
PWM0_DUTY_CYCLE_CNT
473:468
Matrix OUT79
Matrix OUT80
PWM0_EXT_CLK
479:474
485:480
PWM0_Power-down
Matrix OUT81
Matrix OUT82
PWM1_UP/DOWN
PWM1_KEEP/STOP
491:486
497:492
Matrix OUT83
Matrix OUT84
PWM1_ DUTY_CYCLE_CNT
PWM1_EXT_CLK
503:498
509:504
Matrix OUT85
PWM1_Power-down
515:510
Datasheet
31-Aug-2021
Revision 3.4
193 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
40
Matrix OUT86
nPD of ACMP0H from the matrix
521:516
41
Matrix OUT87
Matrix OUT88
nPD of ACMP1H from the matrix
Filter/Edge detect input
41
42
42
43
43
44
44
45
45
46
46
47
47
527:522
533:528
Matrix OUT89
Matrix OUT90
Programmable delay/edge detect input
OSC0 Enable from matrix
539:534
545:540
Matrix OUT91
Matrix OUT92
OSC1 Enable from matrix
551:546
557:552
Vref Output and Temp sensor nPD from matrix
Matrix OUT93
BG Power-down from the matrix
563:558
Matrix OUT94
Matrix OUT95
Diff_Amp_Integrator_En
Reserved
569:564
575:570
Matrix Input
Matrix Input 0
Matrix Input 1
Matrix Input 2
Matrix Input 3
Matrix Input 4
Matrix Input 5
Matrix Input 6
Matrix Input 7
Matrix Input 8
Matrix Input 9
Matrix Input 10
Matrix Input 11
Matrix Input 12
Matrix Input 13
Matrix Input 14
Matrix Input 15
GND
576
LUT2_0/DFF0 output
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
LUT2_1/DFF1 output
LUT2_2/DFF2 output
48
LUT2_3/PGen output
LUT3_0/DFF3 output
LUT3_1/DFF4/Chopper0 output
LUT3_2/DFF5/Chopper1 output
LUT3_3/DFF6 output
LUT3_4/DFF7 output
LUT3_5/DFF8 output
LUT4_0/DFF9 output
49
LUT3_6/PD/RIPP CNT output0
LUT3_6/PD/RIPP CNT output1
LUT3_6/PD/RIPP CNT output2
PROG_DLY_EDET_OUT
Datasheet
31-Aug-2021
Revision 3.4
194 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
Matrix Input 16
Matrix Input 17
Matrix Input 18
Matrix Input 19
Matrix Input 20
Matrix Input 21
Matrix Input 22
Matrix Input 23
Matrix Input 24
Matrix Input 25
Matrix Input 26
Matrix Input 27
Matrix Input 28
Matrix Input 29
Matrix Input 30
Matrix Input 31
Matrix Input 32
MULTFUNC_8BIT_1: DLY_CNT_OUT
MULTFUNC_8BIT_2: DLY_CNT_OUT
MULTFUNC_8BIT_3: DLY_CNT_OUT
MULTFUNC_8BIT_4: DLY_CNT_OUT
MULTFUNC_8BIT_1: LUT3_DFF_OUT
MULTFUNC_8BIT_2: LUT3_DFF_OUT
MULTFUNC_8BIT_3: LUT3_DFF_OUT
MULTFUNC_8BIT_4: LUT3_DFF_OUT
MULTFUNC_16BIT_0: DLY_CNT_OUT
MULTFUNC_16BIT_0: LUT4_DFF_OUT
GPIO0 Digital Input
592
593
594
595
4A
596
597
598
599
600
601
602
GPI Digital Input
603
4B
GPIO1 Digital Input
604
GPIO4 Digital Input
605
606
607
608
609
GPIO5 Digital Input
GPIO6 Digital Input
GPIO2 digital input or I2C_virtual_0 Input
GPIO3 digital input or I2C_virtual_1 Input
I2C_virtual_2 Input
Matrix Input 33
Matrix Input 34
Matrix Input 35
Matrix Input 36
Matrix Input 37
Matrix Input 38
610
I2C_virtual_3 Input
611
4C
I2C_virtual_4 Input
612
I2C_virtual_5 Input
613
I2C_virtual_6 Input
614
615
616
617
618
I2C_virtual_7 Input
PWM0_OUT+
Matrix Input 39
Matrix Input 40
Matrix Input 41
Matrix Input 42
Matrix Input 43
Matrix Input 44
Matrix Input 45
Matrix Input 46
Matrix Input 47
PWM0_OUT-
PWM1_OUT+
PWM1_OUT-
619
4D
Diff. Amp +Integrator UPWARD
Diff. Amp +Integrator EQUAL
ACMP0H_OUT
620
621
622
623
ACMP1H_OUT
Datasheet
31-Aug-2021
Revision 3.4
195 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
Matrix Input 48
Matrix Input 49
Matrix Input 50
Matrix Input 51
Matrix Input 52
Matrix Input 53
Matrix Input 54
Matrix Input 55
Matrix Input 56
Matrix Input 57
Matrix Input 58
Matrix Input 59
Matrix Input 60
Matrix Input 61
Matrix Input 62
Matrix Input 63
CurrentSenseComp0_OUT
CurrentSenseComp1_OUT
Fault_A
624
625
626
Fault_B
627
4E
EDET_FILTER_OUT
Oscillator1(Ring_osc) output
Flex-Divider output
Oscillator0(LF_OSC) output 0
Oscillator0(LF_OSC) output 1
POR OUT
628
629
630
631
632
633
634
PWM0_PERIOD
PWM1_PERIOD
OCP_FAULT_A
635
4F
636
OCP_FAULT_B
637
638
639
TSD_FAULT
VDD
Datasheet
31-Aug-2021
Revision 3.4
196 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
ACMP Vref
1. With registers [756:755] ≠ 11 or GPIO0 OE = 1:
000: Analog Power-down
001: Analog Power-down
010: Vref_OUT to ACMP only by analog buffer
011: Vref_OUT to ACMP only by analog buffer
100: Analog Power-down
101: Vts_OUT to ACMP only by analog buffer
110: Vts_OUT to ACMP only by analog buffer
111: Analog Power-down.
642:640
Vref OUT (to GPIO0) Mode Selection
2. With registers [756:755] = 11 and GPIO0 OE = 0:
000: Analog Power-down;
001: Vref_OUT to GPIO0 only by analog buffer
010: Vref_OUT to ACMP only by analog buffer
011: Vref_OUT to GPIO0 and ACMP by analog buffer
100: Vts_OUT to GPIO0 only by analog buffer
101: Vts_OUT to ACMP only by analog buffer
110: Vts_OUT to GPIO0 and ACMP by analog buffer
111: Vref_OUT to GPIO0 bypass analog buffer
50
1: On
0: Off
643
644
645
Vref OUT (to GPIO0) register Power-On/Off
Vref OUT (to GPIO0) Power-down selection
Vref OUT Buffer sink current selection
0: Come from register [643]
1: Come from Matrix OUT 92
0: 2 uA
1: 12 uA
00: None;
01: ACMP0_H Vref,
10: ACMP1_H Vref;
11: Temp sensor
646:647
Vref OUT (to GPIO0) input selection
0: Power-down
1: Power-On
648
649
650
Temp sensor register Power-down control
Temp sensor register Power-down select
Temp sensor range select
0: Come from register [648]
1: Come Matrix OUT 92
0: 0.62V ~ 0.99V (TYP),
1: 0.75V ~ 1.2V (TYP)
00: 0 mV
51
01: 32 mV
10: 64 mV
11: 192 mV
652:651
ACMP0_H hysteresis
653
654
Reserved
Reserved
0: Disable
1: Enable
ACMP0_H input tie to VDD enable
655
Datasheet
31-Aug-2021
Revision 3.4
197 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
ACMP1_H input come from Temp sensor
output enable
0: Disable
1: Enable
656
ACMP1_H positive input come from
ACMP0_H's input mux output enable
0: Disable
1: Enable
657
658
Reserved
Reserved
52
659
00: 0 mV
01: 32 mV
10: 64 mV
11: 192 mV
661:660
663:662
ACMP1_H hysteresis
Reserved
Integrator Vref select:
000000: 32 mV ~ 111110: 2.016 V
step = 32 mV
669:664
Integrator Vref select
53
54
111111: External Vref
671:670
672
Reserved
0: Disable
1: Enable
ACMP0_H Wake/sleep enable
0: Disable
1: Enable
673
674
ACMP1_H Wake/sleep enable
ACMP wake/sleep time selection
0: Short time
1: Normal WS
675
676
Reserved
Reserved
Reserved
679:677
00: 1x
01: 0.5x
10: 0.33x
11: 0.25x
681:680
687:682
689:688
695:690
ACMP0_H Gain divider select
ACMP0_H Vref select
55
000000: 32 mV ~ 111110: 2.016 V/
step = 32 mV;
111111: External Vref
00: 1x
01: 0.5x
10: 0.33x
11: 0.25x
ACMP1_H Gain divider select
ACMP1_H Vref select
56
000000: 32 mV ~ 111110: 2.016 V/
step = 32 mV;
111111: External Vref
Datasheet
31-Aug-2021
Revision 3.4
198 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
000000: 32 mV ~ 111110: 2.016 V/
step = 32 mV;
701:696
Current Sense A Vref select
111111: External Vref
57
0: Select static from current sense A Vref registers
[701:696]
Current Sense A Vref registers [5:0] source
selection
702
1: Select dynamic from PWM0
703
Reserved
000000: 32 mV ~ 111110: 2.016 V/ step = 32 mV;
111111: External Vref
709:704
Current Sense B Vref select
0: Select static from Current Sense A Vref registers
[709:704]
58
Current Sense B Vref registers [5:0] source
selection
710
1: Select dynamic from PWM1
711
Reserved
OSC1 (25 MHz)
When matrix output enable/PD control signal = 0:
0: Auto on by delay cells
712
Turn on by register
1: Always on
0: Matrix down
1: Matrix on
713
59
Matrix Power-down/on select
000: div 1
001: div 2
010: div 4
011: div 8
100: div 12
716:714
Pre-divider ratio control
000: /1
001: /2
010: /4
011: /3
100: /8
101: /12
110: /24
111: /64
719:717
720
Second stage divider ratio control
0: Internal OSC1
1: External clock from GPIO4
External clock source enable
Matrix OUT enable
0: Disable
1: Enable
5A
721
722
0: Enable
1: Disable
Startup delay with 100ns
OSC0 (2.048 kHz)
Datasheet
31-Aug-2021
Revision 3.4
199 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
When matrix output enable/pd control signal = 0:
0: Auto on by delay cells
723
Turn on by register
1: Always on
0: Matrix down
1: Matrix on
724
Matrix Power-down/on select
External clock source enable
5A
0: Internal OSC0
1: External clock from GPIO1
725
0: Disable
1: Enable
726
727
Matrix OUT enable
Reserved
00: div 1
01: div 2
10: div 4
11: div 8
729:728
Pre-divider ratio control
000: /1
001: /2
010: /4
011: /3
100: /8
101: /12
110: /24
111: /64
5B
732:730
Second stage divider ratio control
735:733
Reserved
OSC0 second Output control
000: /1
001: /2
010: /4
011: /3
100: /8
101: /12
110: /24
111: /64
738:736
Matrix divider ratio control
5C
0: Disable
1: Enable
739
Second output to matrix enable
OSC1 matrix OUT enable for flexible divider
0: Disable
1: Enable
740
OSC1 Matrix OUT enable for flexible divider
5C
0: Disable
1: Enable
741
OSC1 Enable for flexible divider
Reserved
743:742
Flexible divider for OSC1
Data[7:0]
5D
751:744
Flexible divider for OSC1 (8-b counter)
Equation: divider number = Data[7:0] + 1 (exclude
Data[7:0] = 0000 0000)
HV_GPO_HD Common
Datasheet
31-Aug-2021
Revision 3.4
200 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
752
Reserved
Differential amplifier with integrator output
duty cycle vs input duty cycle of Full Bridge
drivers: invert_UPWARD
5E
0: IN → OUT
1: IN → nOUT
753
IO Common
0: Disable
1: Enable
IO fast Pull-up/down enable at VDD start
5E
754
GPIO0
00: Digital without Schmitt trigger
01: Digital with Schmitt trigger
10: Low voltage digital in
11: Analog IO
756:755
758:757
760:759
Input mode configuration
5E
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain 1x
11: Open-Drain 2x
Output mode configuration
Pull-up/down resistance selection
5E
5F
00: Floating
01: 10 k
10: 100 k
11: 1 M
0: Pull-down
1: Pull-up
761
762
Pull-up/down selection
Reserved
5F
GPI
00: Digital without Schmitt trigger
01: Digital with Schmitt trigger
10: Low voltage digital in
11: Analog IO
764:763
Input mode configuration
00: Floating
01: 10 k
10: 100 k
11: 1 M.
5F
766:765
767
Pull-up/down resistance selection
0: Pull-down
1: Pull-up
Pull-up/down selection
Reserved
Reserved
60
775:768
HV_GPO0_HD
Datasheet
31-Aug-2021
Revision 3.4
201 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
00: Hi-Z
01: NMOS Open-Drain LOW side on
10: NMOS HIGH side on
777:776
Output mode configuration
11: NMOS HIGH side and LOW side on
000: Delay 492 us
001: Delay 656 us
010: Delay 824 us
011: Delay 988 us
100: Delay 1152 us
101: Delay 1316 us
110: Delay 1480 us
111: Delay 1640 us
780:778
61
Control delay of OCP0 retry
0: Slow slew rate for motor driver
1: Fast slew rate for pre-driver mode
781
782
HV_GPO0/HV_GPO1 Slew rate control
HV_GPO0/HV_GPO1 Full Bridge/Half Bridge 0: Half Bridge mode
mode select
1: Full Bridge.
783
Reserved
HV_GPO1_HD
00: Hi-Z
01: NMOS Open-Drain LOW side on
10: NMOS HIGH side on
11: NMOS HIGH side and LOW side on
785:784
Output mode configuration
Control delay of OCP1 retry
000: Delay 492 us
001: Delay 656 us
010: Delay 824 us
011: Delay 988 us
100: Delay 1152 us
101: Delay 1316 us
110: Delay 1480 us
111: Delay 1640 us
62
788:786
789
Reserved
Reserved
Reserved
62
790
791
HV_GPO2_HD
Datasheet
31-Aug-2021
Revision 3.4
202 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
00: Hi-Z
01: NMOS Open-Drain LOW side on
10: NMOS HIGH side on
793:792
Output mode configuration
11: NMOS HIGH side and LOW side on
000: Delay 492 us
001: Delay 656 us
010: Delay 824 us
011: Delay 988 us
100: Delay 1152 us
101: Delay 1316 us
110: Delay 1480 us
111: Delay 1640 us
796:794
63
Control delay of OCP2 retry
0: Slow slew rate for motor driver
1: Fast slew rate for pre-driver mode.
797
798
HV_GPO2/HV_GPO3 slew rate control
HV_GPO2/HV_GPO3 Full Bridge/Half Bridge 0: Half Bridge mode
mode select
1: Full Bridge mode
799
Reserved
HV_GPO3_HD
00: Hi-Z
01: NMOS Open-Drain LOW side on
10: NMOS HIGH side on
11: NMOS HIGH side and LOW side on
801:800
Output mode configuration
Control delay of OCP3 retry
000: Delay 492 us
001: Delay 656 us
010: Delay 824 us
011: Delay 988 us
100: Delay 1152 us
101: Delay 1316 us
110: Delay 1480 us
111: Delay 1640 us
64
804:802
807:805
Reserved
Reserved
Reserved
65
815:808
Datasheet
31-Aug-2021
Revision 3.4
203 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
GPIO1 (LED)
00: Digital without Schmitt trigger
01: Digital with Schmitt trigger
10: Low voltage digital in
11: Analog IO
817:816
Input mode configuration
Output mode configuration
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain 1x
11: Open-Drain 2x
819:818
66
00: Floating
01: 10 k
10: 100 k
11: 1 M
821:820
Pull-up/down resistance selection
Pull-up/down selection
0: Pull-down
1: Pull-up
822
823
Reserved
Reserved
67
824
GPIO2/SCL
00: Digital without Schmitt trigger
01: Digital with Schmitt trigger
10: Low voltage digital in
11: Reserved
826:825
Input mode configuration
00: Floating
01: 10 k
10: 100 k
11: 1 M
828:827
Pull-up/down resistance selection
Pull-up/down selection
67
0: Pull-down
1: Pull-up
829
830
831
0: I2C Fast Mode +
1: I2C Standard/Fast Mode.
I2C mode selection (only GPIO3 SDA)
0: Disable
1: Enable (3.2x)
Open-Drain output enable (3.2x drivability)
GPIO3/SDA
00: Digital without Schmitt trigger
01: Digital with Schmitt trigger
10: Low voltage digital in
11: Reserved
833:832
Input mode configuration
00: Floating
01: 10 k
10: 100 k
11: 1 M
835:834
836
Pull-up/down resistance selection
Pull-up/down selection
68
0: Pull-down
1: Pull-up
0: Disable
1: Enable (3.2x)
837
838
Open-Drain output enable (3.2x drivability)
Reserved
Datasheet
31-Aug-2021
Revision 3.4
204 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
68
839
Reserved
GPIO4
00: Digital without Schmitt trigger
01: Digital with Schmitt trigger
10: Low voltage digital in
11: Analog IO
841:840
Input mode configuration
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain 1x
11: Open-Drain 2x
843:842
845:844
Output mode configuration
Pull-up/down resistance selection
69
00: Floating
01: 10 k
10: 100 k
11: 1 M
0: Pull-down
1: Pull-up
846
847
Pull-up/down selection
Reserved
GPIO5 (LED)
00: Digital without Schmitt trigger
01: Digital with Schmitt trigger
10: Low voltage digital in
11: Analog IO
849:848
Input mode configuration
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain 1x
11: Open-Drain 2x
851:850
853:852
Output mode configuration
Pull-up/down resistance selection
6A
00: Floating
01: 10 k
10: 100 k
11: 1 M
0: Pull-down
1: Pull-up
854
855
Pull-up/down selection
Reserved
GPIO6
00: Digital without Schmitt trigger
01: Digital with Schmitt trigger
10: Low voltage digital in
11: Analog IO
857:856
859:858
861:860
Input mode configuration
Output mode configuration
Pull-up/down selection
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain 1x
11: Open-Drain 2x
6B
00: Floating
01: 10 k
10: 100 k
11: 1 M
Datasheet
31-Aug-2021
Revision 3.4
205 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
0: Pull-down
1: Pull-up
862
6B
Pull-up/down selection
Reserved
863
0: Disable
1: Enable
V
V
DD2_A UVLO0 register enable/disable
DD2_B UVLO1 register enable/disable
864
0: Disable
1: Enable
865
866
0: x8
1: x4
Current sense A amplifier gain selection
Current sense comparator A output polarity
Current sense B amplifier gain selection
Current sense comparator B output polarity
Current sense A register enable/disable
0: OUT
867
1: Inverted OUT
6C
0: x8
1: x4
868
0: OUT
869
870
871
1: Inverted OUT
0: Disable
1: Enable
0: Disable
1: Enable
Current sense B register enable/disable
Reserved
6D
872
Mode control for HV GPO0/1
0: Without deglitch time
1: With deglitch time
873
874
OCP deglitch time enable for HV GPO0/1
Control selection for HV_GPO0/1
6D
0: IN-IN mode
1: PH-EN mode
Mode control for HV GPO2/3
0: Without deglitch time
1: With deglitch time
875
OCP deglitch time enable for HV GPO2/3
6D
0: IN-IN mode
876
877
Control selection for HV_GPO2/3
Reserved
1: PH-EN mode
Reserved
6D
6E
6F
879:878
887:880
895:888
Reserved
Reserved
Reserved
Datasheet
31-Aug-2021
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
Multifunction0 (LUT4_DFF)
0000000:
Matrix A - In3
Matrix B - In2
Matrix C - In1
Matrix D - In0
DLY_IN - LOW
Single 4-bit LUT
0010000:
Matrix A - D
Matrix B - nSET
Matrix C - nRST
Matrix D - CLK
DLY_IN - LOW
Single DFF nRST and SET
0000001:
Matrix A - UP (CNT)
Matrix B - KEEP (CNT)
Matrix C - EXT_CLK (CNT)
Matrix D - DLY_IN (CNT)
DLY_OUT connected to LUT/DFF
Single CNT/DLY
70
902:896
0000010:
Matrix A - DLY_IN
Matrix B - In2
CNT/DLY → LUT
Matrix C - In1
Matrix D - In0
DLY_OUT connected to In3
0010010:
Matrix A - DLY_IN
Matrix B - nSET
Matrix C - nRST
Matrix D - CLK
CNT/DLY → DFF
DLY_OUT connected to D
Datasheet
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Revision 3.4
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
0100010:
Matrix A - DLY_IN
Matrix B - EXT_CLK (CNT)
Matrix C - In1
CNT/DLY → LUT
Matrix D - In0
DLY_OUT connected to In3,
In2 tied LOW
0110010:
Matrix A - DLY_IN
Matrix B - EXT_CLK (CNT)
Matrix C - nRST
Matrix D - CLK
DLY_OUT connected to D,
nSET tied HIGH
CNT/DLY → DFF
CNT/DLY → LUT
1000010:
Matrix A - DLY_IN
Matrix B - In2
Matrix C - EXT_CLK (CNT)
Matrix D - In0
70
902:896
DLY_OUT connected to In3,
In1 tied LOW
1010010:
Matrix A - DLY_IN
Matrix B - nSET
CNT/DLY → DFF
CNT/DLY → LUT
Matrix C - EXT_CLK (CNT)
Matrix D - CLK
DLY_OUT connected to D,
nRST tied HIGH
0000110:
Matrix A - In3
Matrix B - DLY_IN
Matrix C - In1
Matrix D - In0
DLY_OUT connected to In2
Datasheet
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Revision 3.4
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
0010110:
Matrix A - D
Matrix B - DLY_IN
Matrix C - nRST
Matrix D - CLK
CNT/DLY → DFF
DLY_OUT connected to nSET
1000110:
Matrix A - In3
Matrix B - DLY_IN
Matrix C - EXT_CLK (CNT)
Matrix D - In0
DLY_OUT connected to In2,
In1 tied LOW
CNT/DLY → LUT
CNT/DLY → DFF
1010110:
Matrix A - D
Matrix B - DLY_IN
Matrix C - EXT_CLK (CNT)
Matrix D - CLK
DLY_OUT connected to nSET,
nRST tied HIGH
0001010:
Matrix A - In3
Matrix B - In2
Matrix C - DLY_IN
Matrix D - In0
70
902:896
CNT/DLY → LUT
CNT/DLY → DFF
DLY_OUT connected to In1
0011010:
Matrix A - D
Matrix B - nSET
Matrix C - DLY_IN
Matrix D - CLK
DLY_OUT connected to nRST
0101010:
Matrix A - In3
Matrix B - EXT_CLK (CNT)
Matrix C - DLY_IN
Matrix D - In0
DLY_OUT connected to In1,
In2 tied LOW
CNT/DLY → LUT
CNT/DLY → DFF
0111010:
Matrix A - D
Matrix B - EXT_CLK (CNT)
Matrix C - DLY_IN
Matrix D - CLK
DLY_OUT connected to nRST,
nSET tied HIGH
Datasheet
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Revision 3.4
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
0001110:
Matrix A - In3
Matrix B - In2
Matrix C - In1
CNT/DLY → LUT
Matrix D - DLY_IN
DLY_OUT connected to In0
0011110:
Matrix A - D
Matrix B - nSET
Matrix C - nRST
Matrix D - DLY_IN
DLY_OUT connected to CLK
CNT/DLY → DFF
CNT/DLY → LUT
0101110:
Matrix A - In3
Matrix B - EXT_CLK (CNT)
Matrix C - In1
Matrix D - DLY_IN
DLY_OUT connected to In0,
In2 tied LOW
0111110:
Matrix A - D
Matrix B - EXT_CLK (CNT)
Matrix C - nRST
Matrix D - DLY_IN
DLY_OUT connected to CLK,
nSET tied HIGH
CNT/DLY → DFF
CNT/DLY → LUT
70
902:896
1001110:
Matrix A - In3
Matrix B - In2
Matrix C - EXT_CLK (CNT)
Matrix D - DLY_IN
DLY_OUT connected to In0,
In1 tied LOW
1011110:
Matrix A - D
Matrix B - nSET
CNT/DLY → DFF
LUT → CNT/DLY
Matrix C - EXT_CLK (CNT)
Matrix D - DLY_IN
DLY_OUT connected to CLK,
nRST tied HIGH
0000011:
Matrix A - In3
Matrix B - In2
Matrix C - In1
Matrix D - In0
LUT_OUT connected to DLY_IN
Datasheet
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Revision 3.4
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
0010011:
Matrix A - D
Matrix B - nSET
Matrix C - nRST
Matrix D - CLK
DFF → CNT/DLY
DFF_OUT connected to DLY_IN
0100011:
Matrix A - In3
Matrix B - EXT_CLK (CNT)
Matrix C - In1
LUT → CNT/DLY
DFF → CNT/DLY
LUT → CNT/DLY
Matrix D - In0
LUT_OUT connected to DLY_IN,
In2 tied LOW
0110011:
Matrix A - D
Matrix B - EXT_CLK (CNT)
Matrix C - nRST
70
902:896
Matrix D - CLK
DFF_OUT connected to DLY_IN,
nSET tied LOW
1000011:
Matrix A - In3
Matrix B - In2
Matrix C - EXT_CLK (CNT)
Matrix D - In0
LUT_OUT connected to DLY_IN,
In1 tied LOW
1010011:
Matrix A - D
Matrix B - nSET
DFF → CNT/DLY
Matrix C - EXT_CLK (CNT)
Matrix D - CLK
DFF_OUT connected to DLY_IN,
nRST tied HIGH
70
71
00: DLY
01: One Shoot
904:903
DLY/CNT0 Mode Selection
10: Frequency Detection
11: CNT register [912] = 0
Datasheet
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Revision 3.4
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
00: Both edge
01: Falling edge
10: Rising edge;
906:905
DLY/CNT0 Edge Mode Selection
11: HIGH Level Reset (only in CNT mode)
Clock source sel[3:0]
0000: 25 MHz(OSC1)
0001: 25 MHz/4
0010: Not used
0011: Not used
0100: Not used
0101: Not used
0110: 2.048 kHz(OSC0)
0111: 2.048 kHz/8
1000: 2.048 kHz/64
1001: 2.048 kHz/512
1010: 2.048 kHz/4096
1011: 2.048 kHz/32768
1100: 2.048 kHz/262144
1101: CNT4_END
1110: External
71
910:907
DLY/CNT0 Clock Source Select
1111: Not used
0: Reset to 0
1: Set to data
911
912
FSM0 SET/RST Selection
0: Normal
CNT0 DLY EDET FUNCTION Selection
1: DLY function edge detection (registers [904:903] =
00)
0: Bypass
913
914
UP signal SYNC selection
Keep signal SYNC selection
1: After two DFF
0: Bypass
1: After two DFF
00: Bypass the initial
01: Initial 0
72
916:915
CNT0 initial value selection
10: Initial 1
11: Initial 1
0: LOW
1: HIGH
917
918
Wake/sleep Power-down state selection
Wake/sleep mode selection
0: Default Mode
1: Wake/Sleep Mode
(registers [904:903] = 11)
0: Default Output
1: Inverted Output
919
920
CNT0 output polarity selection
0: Bypass
73
CNT0 CNT mode SYNC selection
1: After two DFF
Multifunction1
Datasheet
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Revision 3.4
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
00000:
Matrix A - In2
Matrix B - In1
Matrix C - In0
DLY_IN - LOW
Single 3-bit LUT
10000:
Matrix A - D
Single DFF with nRST/nSET
Single CNT/DLY
Matrix B - nSET/nRST
Matrix C - CLK
DLY_IN - LOW
00001:
Matrix A - DLY_IN (CNT)
Matrix B - EXT_CLK (CNT)
Matrix C - NC
DLY_OUT connected to LUT/DFF
00010:
Matrix A - DLY_IN
Matrix B - In1
CNT/DLY → LUT
CNT/DLY → DFF
CNT/DLY → LUT
CNT/DLY → DFF
CNT/DLY → LUT
Matrix C - In0
DLY_OUT connected to In2
73
925:921
10010:
Matrix A - DLY_IN
Matrix B - nSET/nRST
Matrix C - CLK
DLY_OUT connected to D
00110:
Matrix A - In2
Matrix B - DLY_IN
Matrix C - In0
DLY_OUT connected to In1
10110:
Matrix A - D
Matrix B - DLY_IN
Matrix C - CLK
DLY_OUT connected to nSET/nRST
01010:
Matrix A - In2
Matrix B - In1
Matrix C - DLY_IN
DLY_OUT connected to In0
Datasheet
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Revision 3.4
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
11010:
Matrix A - D
CNT/DLY → DFF
Matrix B - nSET/nRST
Matrix C - DLY_IN
DLY_OUT connected to CLK
00011:
Matrix A - In2
73
925:921
LUT → CNT/DLY
DFF → CNT/DLY
Matrix B - In1
Matrix C - In0
LUT_OUT connected to DLY_IN
10011:
Matrix A - D
Matrix B - nSET/nRST
Matrix C - CLK
DLY_OUT connected to DLY_IN
0000: Both edge Delay
0001: Falling edge delay
0010: Rising edge delay
0011: Both edge One Shot
0100: Falling edge One Shot
0101: Rising edge One Shot
0110: Both edge freq detect
0111: Falling edge freq. detect
1000: Rising edge freq. detect
1001: Both edge detect
73
74
929:926
CNT1 function and edge mode selection
1010: Falling edge detect
1011: Rising edge detect
1100: Both edge reset CNT
1101: Falling edge reset CNT
1110: Rising edge reset CNT
1111: HIGH level reset CNT
00: Bypass the initial
01: Initial 0
74
931:930
CNT1 initial value selection
10: Initial 1
11: Initial 1
Datasheet
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Revision 3.4
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
Clock source sel[3:0]
0000: 25 MHz(OSC1)
0001: 25 MHz/4
0010: Not used
0011: Not used
0100: Not used
0101: Not used
0110: 2.048 kHz(OSC0)
0111: 2.048 kHz/8
1000: 2.048 kHz/64
1001: 2.048 kHz/512
1010: 2.048 kHz/4096
1011: 2.048 kHz/32768
1100: 2.048 kHz/262144
1101: CNT0_END
1110: External
74
935:932
DLY/CNT1 Clock Source Select
1111: Not used
0: Default Output
1: Inverted Output
936
937
CNT1 output polarity selection
0: Bypass
CNT1 CNT mode SYNC selection
75
1: After two DFF
0: Normal
938
CNT1 DLY EDET FUNCTION Selection
1: DLY function edge detection
(registers [929:926] = 0000/0001/0010)
Multifunction2
00000:
Matrix A - In2
Matrix B - In1
Matrix C - In0
DLY_IN - LOW
Single 3-bit LUT
10000:
Matrix A - D
Single DFF w RST and SET
Single CNT/DLY
Matrix B - nSET/nRST
Matrix C - CLK
DLY_IN - LOW
75
943:939
00001:
Matrix A - DLY_IN (CNT)
Matrix B - EXT_CLK (CNT)
Matrix C - NC
DLY_OUT connected to LUT/DFF
00010:
Matrix A - DLY_IN
Matrix B - In1
CNT/DLY → LUT
Matrix C - In0
DLY_OUT connected to In2
Datasheet
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Revision 3.4
215 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
10010:
Matrix A - DLY_IN
Matrix B - nSET/nRST
Matrix C - CLK
CNT/DLY → DFF
DLY_OUT connected to D
00110:
Matrix A - In2
CNT/DLY → LUT
CNT/DLY → DFF
CNT/DLY → LUT
CNT/DLY → DFF
LUT → CNT/DLY
Matrix B - DLY_IN
Matrix C - In0
DLY_OUT connected to In1
10110:
Matrix A - D
Matrix B - DLY_IN
Matrix C - CLK
DLY_OUT connected to nSET/nRST
01010:
Matrix A - In2
Matrix B - In1
75
943:939
Matrix C - DLY_IN
DLY_OUT connected to In0
11010:
Matrix A - D
Matrix B - nSET/nRST
Matrix C - DLY_IN
DLY_OUT connected to CLK
00011:
Matrix A - In2
Matrix B - In1
Matrix C - In0
LUT_OUT connected to DLY_IN
10011:
Matrix A - D
DFF → CNT/DLY
Matrix B - nSET/nRST
Matrix C - CLK
DFF_OUT connected to DLY_IN
00: Bypass the initial
01: Initial 0
CNT2 initial value selection
76
945:944
10: Initial 1
11: Initial 1
0000: Both edge Delay
0001: Falling edge delay
0010: Rising edge delay
0011: Both edge One Shot
0100: Falling edge One Shot
0101: Rising edge One Shot
0110: Both edge freq detect
0111: Falling edge freq detect
1000: Rising edge freq detect
1001: Both edge detect
CNT2 function and edge mode selection
76
949:946
1010: Falling edge detect
1011: Rising edge detect
1100: Both edge reset CNT
1101: Falling edge reset CNT
1110: Rising edge reset CNT
1111: HIGH level reset CNT
Datasheet
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Revision 3.4
216 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
Clock source sel[3:0]
0000: 25 MHz(OSC1)
0001: 25 MHz/4
76
0010: Not used
0011: Not used
0100: Not used
0101: Not used
0110: 2.048 kHz(OSC0)
0111: 2.048 kHz/8
1000: 2.048 kHz/64
1001: 2.048 kHz/512
1010: 2.048 kHz/4096
1011: 2.048 kHz/32768
1100: 2.048 kHz/262144
1101: CNT1_END
1110: External
DLY/CNT2 Clock Source Select
953:950
77
1111: Not used
0: Default Output
1: Inverted Output
CNT2 output polarity selection
954
955
0: Bypass
1: After two DFF
CNT2 CNT mode SYNC selection
0: Normal
1: DLY function edge detection
(registers [949:946] = 0000/0001/0010)
CNT2 DLY EDET Function Selection
956
Multifunction3
00: Bypass the initial
01: Initial 0
10: Initial 1
CNT3 initial value selection
Multi3 register configuration
958:957
77
11: Initial 1
Refer table in register [967:964]
959
0000: Both edge Delay
0001: Falling edge delay
0010: Rising edge delay
0011: Both edge One Shot
0100: Falling edge One Shot
0101: Rising edge One Shot
0110: Both edge freq detect
0111: Falling edge freq detect
1000: Rising edge freq detect
1001: Both edge detect
CNT3 function and edge mode selection
78
963:960
1010: Falling edge detect
1011: Rising edge detect
1100: Both edge reset CNT
1101: Falling edge reset CNT
1110: Rising edge reset CNT
1111: HIGH level reset CNT
Datasheet
31-Aug-2021
Revision 3.4
217 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
00000:
Matrix A - In2
Matrix B - In1
Matrix C - In0
DLY_IN - LOW
Single 3-bit LUT
10000:
Matrix A - D
Single DFF w RST and SET
Single CNT/DLY
Matrix B - nSET/nRST
Matrix C - CLK
DLY_IN - LOW
00100:
Matrix A - DLY_IN (CNT)
Matrix B - EXT_CLK (CNT)
Matrix C - NC
DLY_OUT connected to LUT/DFF
01000:
Matrix A - DLY_IN
CNT/DLY → LUT
CNT/DLY → DFF
CNT/DLY → LUT
CNT/DLY → DFF
CNT/DLY → LUT
CNT/DLY → DFF
LUT → CNT/DLY
DFF → CNT/DLY
Matrix B - In1
Matrix C - In0
DLY_OUT connected to In2
11000:
Matrix A - DLY_IN
Matrix B - nSET/nRST
Matrix C - CLK
DLY_OUT connected to D
01001:
Matrix A - In2
959
78
Matrix B - DLY_IN
Matrix C - In0
967:964
DLY_OUT connected to In1
11001:
Matrix A - D
Matrix B - DLY_IN
Matrix C - CLK
DLY_OUT connected to nSET/nRST
01010:
Matrix A - In2
Matrix B - In1
Matrix C - DLY_IN
DLY_OUT connected to In0
11010:
Matrix A - D
Matrix B - nSET/nRST
Matrix C - DLY_IN
DLY_OUT connected to CLK
01100:
Matrix A - In2
Matrix B - In1
Matrix C - In0
LUT_OUT connected to DLY_IN
11100:
Matrix A - D
Matrix B - nSET/nRST
Matrix C - CLK
(DFF_OUT connected to DLY_IN)
Datasheet
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Revision 3.4
218 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
Clock source sel[3:0]
0000: 25 MHz(OSC1)
0001: 25 MHz/4
0010: Not used
0011: Not used
0100: Not used
0101: Not used
0110: 2.048 kHz(OSC0)
0111: 2.048 kHz/8
1000: 2.048 kHz/64
1001: 2.048 kHz/512
1010: 2.048 kHz/4096
1011: 2.048 kHz/32768
1100: 2.048 kHz/262144
1101: CNT2_END
1110: External
DLY/CNT3 Clock Source Select
971:968
79
1111: Not used
0: Default Output
1: Inverted Output
CNT3 output polarity selection
972
973
0: Bypass
1: After two DFF
CNT3 CNT mode SYNC selection
0: normal
CNT3 DLY EDET FUNCTION Selection
1: DLY function edge detection
(registers [963:960] = 0000/0001/0010)
974
Multifunction4
0: Bypass
1: After two DFF
CNT4 CNT mode SYNC selection
CNT4 initial value selection
79
975
00: bypass the initial
01: Initial 0
10: Initial 1
977:976
11: Initial 1
0: Normal
1: DLY function edge detection
(registers [991:988] = 0000/0001/0010)
CNT4 DLY EDET FUNCTION Selection
Single 3-bit LUT
978
00000:
7A
Matrix A - In2
Matrix B - In1
Matrix C - In0
DLY_IN - LOW
979
10000:
983:980
Matrix A - D
Single DFF with RST and SET
Matrix B - nSET/nRST
Matrix C - CLK
DLY_IN - LOW
Datasheet
31-Aug-2021
Revision 3.4
219 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
00001:
Matrix A - DLY_IN (CNT)
Matrix B - EXT_CLK (CNT)
Matrix C - NC
Single CNT/DLY
DLY_OUT connected to LUT/DFF
00010:
Matrix A - DLY_IN
Matrix B - In1
CNT/DLY → LUT
CNT/DLY → DFF
CNT/DLY → LUT
CNT/DLY → DFF
CNT/DLY → LUT
CNT/DLY → DFF
LUT → CNT/DLY
DFF → CNT/DLY
Matrix C - In0
DLY_OUT connected to In2
10010:
Matrix A - DLY_IN
Matrix B - nSET/nRST
Matrix C - CLK
DLY_OUT connected to D
00110:
Matrix A - In2
Matrix B - DLY_IN
Matrix C - In0
DLY_OUT connected to In1
10110:
Matrix A - D
979
7A
Matrix B - DLY_IN
Matrix C - CLK
983:980
DLY_OUT connected to nSET/nRST
01010:
Matrix A - In2
Matrix B - In1
Matrix C - DLY_IN
DLY_OUT connected to In0
11010:
Matrix A - D
Matrix B - nSET/nRST
Matrix C - DLY_IN
DLY_OUT connected to CLK
00011:
Matrix A - In2
Matrix B - In1
Matrix C - In0
LUT_OUT connected to DLY_IN
10011:
Matrix A - D
Matrix B - nSET/nRST
Matrix C - CLK
DFF_OUT connected to DLY_IN
Datasheet
31-Aug-2021
Revision 3.4
220 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
Clock source sel[3:0]
0000: 25 MHz(OSC1)
0001: 25 MHz/4
0010: Not used
0011: Not used
0100: Not used
0101: Not used
0110: 2.048 kHz(OSC0)
0111: 2.048 kHz/8
1000: 2.048 kHz/64
1001: 2.048 kHz/512
1010: 2.048 kHz/4096
1011: 2.048 kHz/32768
1100: 2.048 kHz/262144
1101: CNT3_END
1110: External
DLY/CNT4 Clock Source Select
987:984
1111: Not used
7B
0000: Both edge Delay
0001: Falling edge delay
0010: Rising edge delay:
0011: Both edge One Shot
0100: Falling edge One Shot
0101: Rising edge One Shot
0110: Both edge freq detect
0111: Falling edge freq detect
1000: Rising edge freq detect
1001: Both edge detect
CNT4 function and edge mode selection
991:988
1010: Falling edge detect
1011: Rising edge detect
1100: Both edge Reset CNT
1101: Falling edge Reset CNT
1110: Rising edge Reset CNT
1111: HIGH level Reset CNT
0: Default Output
1: Inverted Output
CNT4 output polarity selection
Reserved
992
7C
999:993
[15]:LUT4_1 [15]/DFF14 or LATCH Select
0: DFF function
7D
1: LATCH function
[14]:LUT4_1 [14]/DFF14 Output Select
0: Q output
1: nQ output
[13]:LUT4_1 [13] /DFF14 Initial Polarity Select
0: LOW
1: HIGH
[12:0]:LUT4_1 [12:0]
Multi0_LUT4_DFF setting
REG_CNT0_D [15:0]
1015:1000
7E
7F
Data[15:0]
1031:1016
80
Datasheet
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221 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
[7]:LUT3_7 [7]/DFF10 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_7 [6]/DFF10 Output Select
0: Q output
1: nQ output
Multi1_LUT3_DFF setting
REG_CNT1_D[7:0]
[5]:LUT3_7 [5]/DFF10
0: nRST from Matrix Output
1: nSET from Matrix Output
[4]:LUT3_7 [4]/DFF10 Initial Polarity Select
0: LOW
1: HIGH
[3:0]:LUT3_7 [3:0]
81
82
1039:1032
1047:1040
Data[7:0]
[7]:LUT3_8 [7]/DFF11 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_8 [6]/DFF11 Output Select
0: Q output
1: nQ output
[5]:LUT3_8 [5]/DFF11
0: nRST from Matrix Output
1: nSET from Matrix Output
[4]:LUT3_8 [4]/DFF11 Initial Polarity Select
0: LOW
83
84
1055:1048 Multi2_LUT3_DFF setting
1: HIGH
[3:0]:LUT3_8 [3:0]
1063:1056 REG_CNT2_D [7:0]
Data [7:0]
[7]:LUT3_9 [7]/DFF12 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_9[6]/DFF12 Output Select
0: Q output
1: nQ output
85
86
1071:1064 Multi3_LUT3_DFF setting
[5]:LUT3_9 [5]/DFF12
0: nRST from Matrix Output
1: nSET from Matrix Output
[4]:LUT3_9 [4]/DFF12 Initial Polarity Select
0: LOW
1: HIGH
[3:0]:LUT3_9 [3:0]
1079:1072 REG_CNT3_D [7:0]
Data[7:0]
Datasheet
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Revision 3.4
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
[7]: LUT3_10 [7]/DFF13 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_10[6]/DFF13 Output Select
0: Q output
1: nQ output
87
1087:1080 Multi4_LUT3_DFF setting
[5]:LUT3_10 [5]/DFF13
0: nRST from Matrix Output
1: nSET from Matrix Output
[4]:LUT3_10 [4]/DFF13 Initial Polarity Select
0: LOW
1: HIGH
[3:0]:LUT3_10 [3:0]
88
89
8A
8B
8C
8D
1095:1088 REG_CNT4_D [7:0]
Data[7:0]
1111:1096 CNT0 (16bits) Counted Value
Virtual Input
Virtual Input
1119:1112 CNT4 (8bits) Counted Value
1127:1120 Reserved
1135:1128 Reserved
Combinational Logic
[7]:LUT3_1 [7]/DFF4 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_1 [6]/DFF4 Output Select
0: Q output
1: nQ output
[5]:LUT3_1 [5]/DFF4 Initial Polarity Select
0: LOW
1: HIGH
8E
1143:1136 LUT3_1_DFF4 or Chopper0 setting
[4]:LUT3_1 [4]/DFF4
0: nRST from Matrix Output
1: nSET from Matrix Output
[3]:LUT3_1 [3]/DFF4 Active level selection for RST/SET
0: Active LOW-level reset/set
1: Active HIGH-level reset/set
[2:0]: LUT3_1 [2:0]
Datasheet
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Revision 3.4
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
[7]:LUT3_2 [7]/DFF5 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_2 [6]/DFF5 Output Select
0: Q output
1: nQ output
[5]:LUT3_2 [5]/DFF5 Initial Polarity Select
0: LOW
1: HIGH
8F
1151:1144 LUT3_2_DFF5 or Chopper1 setting
[4]:LUT3_2 [4]/DFF5
0: nRST from Matrix Output
1: nSET from Matrix Output
[3]:LUT3_2 [3]/DFF5 Active level selection for RST/SET
0: Active LOW-level reset/set
1: Active HIGH level reset/set
[2:0]: LUT3_2 [2:0]
[7]:LUT3_3 [7]/DFF6 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_3 [6]/DFF6 Output Select
0: Q output
1: nQ output
[5]:LUT3_3 [5]/DFF6 Initial Polarity Select
0: LOW
1: HIGH
90 1159:1152
LUT3_3_DFF6 setting
[4]:LUT3_3 [4]/DFF6
0: nRST from Matrix Output
1: nSET from Matrix Output
[3]:LUT3_3 [3]/DFF6 Active level selection for RST/SET
0: Active LOW-level reset/set
1: Active HIGH level reset/set
[2:0]: LUT3_3 [2:0]
[7]:LUT3_4 [7]/DFF7 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_4 [6]/DFF7 Output Select
0: Q output
1: nQ output
[5]:LUT3_4 [5]/DFF7 Initial Polarity Select
0: LOW
1: HIGH
91 1167:1160
LUT3_4_DFF7 setting
[4]:LUT3_4 [4]/DFF7
0: nRST from Matrix Output
1: nSET from Matrix Output
[3]:LUT3_4 [3]/DFF7 Active level selection for RST/SET
0: Active LOW-Level reset/set
1: Active HIGH-Level reset/set
[2:0]: LUT3_4 [2:0]
Datasheet
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Revision 3.4
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
1171:1168 LUT2_3 value or PGen Size
LUT2_3[3:0] or PGen pattern size[3:0]
LUT3_1 or DFF4 Select
1172
0: LUT3_1
1: DFF4
or Chopper 0 registers [1265:1264]
LUT3_2 or DFF5 Select
1173
0: LUT3_2
1: DFF5
92
or Chopper 1 registers [1267:1266]
0: LUT3_3
1: DFF6
1174
1175
LUT3_3 or DFF6 Select
LUT3_4 or DFF7 Select
0: LUT3_4
1: DFF7
93
94
1191:1176
PGen data
PGen Data[15:0]
0: LUT2_3
1: PGen
1192
1193
1194
1195
1196
1197
1198
1199
LUT2_3 or PGen Select
LUT2_3 or PGen Active level selection for
RST/SET
0: Active LOW-Level reset/set
1: Active HIGH-Level reset/set
LUT3_6 or Pipe Delay/RIPP CNT Active level 0: Active LOW-Level reset/set
selection for RST/SET
1: Active HIGH-Level reset/set
OUT of LUT3_6 or Out0 of Pipe Delay/RIPP
CNT Select
0: LUT3_6
1: OUT0 of Pipe Delay or RIPP CNT
95
0: Pipe delay mode selection
1: Ripple Counter mode selection
Pipe Delay or RIPP CNT Selection
Pipe Delay OUT1 Polarity Select
LUT4_0 or DFF9 Select
0: Non-inverted
1: Inverted
0: LUT4_0
1: DFF9
0: LUT3_0
1: DFF3
LUT3_0 or DFF3 Select
[7:4]: LUT3_6 [7:4]/REG_S1[3:0] Pipe Delay OUT1 sel
[3:0]: LUT3_6 [3:0]/REG_S0[3:0] Pipe Delay OUT0 sel
at RIPP CNT mode:
bits[1202:1200] is the nSET value.
bits[1205:1203] is the END value.
bit[1206] is the range control:
LUT value or Pipe Delay OUT sel or nSET/
END value
96
1207:1200
0: Full cycle
1: Range cycle
bit[1207]: Not used
Datasheet
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
97
[15]:LUT4_0 [15]/DFF9 or LATCH Select
0: DFF function
1: LATCH function
[14]:LUT4_0 [14]/DFF9 Output Select
0: Q output
1: nQ output
[13]:LUT4_0 [13]/DFF9 Initial Polarity Select
0: LOW
1: HIGH
[12]:LUT4_0 [12]/DFF9 stage selection
0: Q of first DFF
1223:1208
98
LUT4_0_DFF9 setting
1: Q of second DFF
[11]:LUT4_0 [11]/DFF9
0: nRST from Matrix Output
1: nSET from Matrix Output
[10]:LUT4_0 [10]/DFF9 Active level selection for RST/
SET
0: Active LOW-Level reset/set
1: Active HIGH-Level reset/set
[9:0]: LUT4_0 [9:0]
[7]:LUT3_0 [7]/DFF3 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_0 [6]/DFF3 Output Select
0: Q output
1: nQ output
[5]:LUT3_0 [5]/DFF3 Initial Polarity Select
0: LOW
1: HIGH
[4]:LUT3_0 [4]/DFF3stage selection
0: Q of first DFF
99 1231:1224
LUT3_0_DFF3 setting
1: Q of second DFF
[3]:LUT3_0 [3]/DFF3
0: nRST from Matrix Output
1: nSET from Matrix Output
[2]:LUT3_0 [2]/DFF3 Active level selection for RST/SET
0: Active LOW-Level reset/set
1: Active HIGH-Level reset/set
[1:0]: LUT3_0 [1:0]
Datasheet
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Revision 3.4
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
0: Filter
1: Edge Det.
1232
Filter or Edge Detector selection
0: Non-inverted output
1: Inverted output
1233
Filter or Edge Detector Output Polarity Select
00: Rising Edges Det.
01: Falling Edge Det.
10: Both Edge Det.
11: Both Edge Delay
1235:1234 Filter or Edge Detector Select the edge mode
9A
00: 125 ns
01: 250 ns
10: 375 ns
11: 500 ns
Delay Value Select for Programmable Delay
or Edge Detector
1237:1236
00: Rising Edge Detector
01: Falling Edge Detector
10: Both Edge Detector
11: Both Edge Delay
Select the Edge Mode of Programmable
1239:1238
Delay or Edge Detector
[7]:LUT3_5 [7]/DFF8 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_5 [6]/DFF8 Output Select
0: Q output
1: nQ output
[5]:LUT3_5 [5]/DFF8 Initial Polarity Select
0: LOW
9B
1247:1240 LUT3_5_DFF8 setting
1: HIGH
[4]:LUT3_5 [4]/DFF8
0: nRST from Matrix Output
1: nSET from Matrix Output
[3]:LUT3_5 [3]/DFF8 Active level selection for RST/SET
0: Active LOW level reset/set
1: Active HIGH level reset/set
[2:0]: LUT3_5 [2:0]
Datasheet
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Revision 3.4
227 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
[3]:LUT2_0 [3]/DFF0 or LATCH Select
0: DFF function
1: LATCH function
[2]:LUT2_0 [2]/DFF0 Output Select
0: Q output
1: nQ output
[1]:LUT2_0 [1]/DFF0 Initial Polarity Select
0: LOW
1: HIGH
1251:1248 LUT2_0/DFF0 setting
1255:1252 LUT2_1/DFF1 setting
1259:1256 LUT2_2/DFF2 setting
[0]:LUT2_0 [0]
9C
[3]:LUT2_1 [3]/DFF1 or LATCH Select
0: DFF function
1: LATCH function
[2]:LUT2_1 [2]/DFF1 Output Select
0: Q output
1: nQ output
[1]:LUT2_1 [1]/DFF1 Initial Polarity Select
0: LOW
1: HIGH
[0]:LUT2_1 [0]
[3]:LUT2_2 [3]/DFF2 or LATCH Select
0: DFF function
1: LATCH function
[2]:LUT2_2 [2]/DFF2 Output Select
0: Q output
1: nQ output
[1]:LUT2_2 [1]/DFF2 Initial Polarity Select
0: LOW
1: HIGH
[0]:LUT2_2 [0]
9D
0: LUT2_0
1: DFF0
1260
1261
1262
1263
1264
1265
1266
1267
LUT2_0 or DFF0 Select
0: LUT2_1
1: DFF1
LUT2_1 or DFF1 Select
0: LUT2_2
1: DFF2
LUT2_2 or DFF2 Select
0: LUT3_5
1: DFF8
LUT3_5 or DFF8 Select
0: LUT3_1/DFF_4
1: Chopper 0
LUT3_1/DFF4 or Chopper0 Select
Chopper0 polarity Select
LUT3_2/DFF5 or Chopper1 Select
Chopper1 polarity Select
0: Q
1: nQ
9E
0: LUT3_2/DFF_5
1: Chopper 1
0: Q
1: nQ
1271:1268 Reserved
1272 Reserved
1279:1273 Reserved
9F
9F
Datasheet
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228 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
PWM Macrocell
A0
A1
1287:1280 Reserved
1295:1288 Initial PWM0 Duty Cycle value
PWM0 Initial Duty Cycle value [7:0]
0: Don't update duty cycle value
1: Update duty cycle value
I2C trigger for PWM0
1296
0: Don't update duty cycle value
1: Update duty cycle value
I2C trigger for PWM1
1297
0: 8-bit PWM0
1: 7-bit PWM0
PWM0 8-bit or 7-bit resolution
1298
A2
0: Non-Inverted Output
1: Inverted Output
PWM0 OUT+ output polarity selection
1299
0: Non-Inverted Output
1: Inverted Output
PWM0 OUT- output polarity selection
1300
0: Synchronous Power-Down
1: Asynchronous Power-Down
PWM0 SYNC On/Off for PWM0
1301
0: Continuous mode
1: PWM Duty Cycle Counter Autostop at 0 % or 100 %
PWM0 Continuous/Autostop mode
1302
A2
0: OSC is always enabled at boundaries
1: Automatically Disable OSC
1303
PWM0 Boundary OSC disable
A3
A4
1311:1304 Initial PWM1 Duty Cycle value
1319:1312
PWM1 Initial Duty Cycle value [7:0]
Current PWM0 Duty Cycle value for I2C read PWM0 Current Duty Cycle value for I2C read [7:0]
A5
A6
1327:1320 Current PWM1 Duty Cycle value for I2C read PWM1 Current Duty Cycle value for I2C read [7:0]
PWM0 Preset 16 bytes Duty Cycle/CCMP
1335:1328
1343:1336
1351:1344
1359:1352
1367:1360
1375:1368
1383:1376
1391:1384
1399:1392
1407:1400
1415:1408
Byte0 [7:0]
Vref values → byte0
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte1
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
Byte1 [15:8]
Byte2 [23:16]
Byte3 [31:24]
Byte4 [39:32]
Byte5 [47:40]
Byte6 [55:48]
Byte7 [63:56]
Byte8 [71:64]
Byte9 [79:72]
Byte10 [87:80]
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte2
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte3
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte4
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte5
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte6
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte7
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte8
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte9
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte10
Datasheet
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Revision 3.4
229 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte11
B1
B2
B3
B4
B5
1423:1416
1431:1424
1439:1432
1447:1440
1455:1448
Byte11 [95:88]
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values→ byte12
Byte12 [103:96]
Byte13 [111:104]
Byte14 [119:112]
Byte15 [127:120]
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte13
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte14
PWM0 Preset 16 bytes Duty Cycle/CCMP
Vref values → byte15
0000: CLK_OSC0
0001: CLK_OSC0/4
0010: CLK_OSC1
0011: CLK_OSC1/8
0100: CLK_OSC1/64
0101: CLK_OSC1/512
0110: CLK_OSC1/4096
0111: CLK_OSC1/32768
1000: CLK_OSC1/262144
1001: From Flexible Divider
1010: Reserved
1459:1456 PWM0 Period Counter Clock Source selection
B6
1011: External clock through matrix (Matrix OUT [79])
0: Disable
1: Enable
PWM0 Phase Correct mode
1460
0: Keep
1: Stop
PWM0 Keep/Stop selection
1461
1463:1462 Reserved
Datasheet
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
00: No Deadband
01: 1PWM0 clock cycles
10: 2PWM0 clock cycles
11: 3PWM0 clock cycles
1465:1464 PWM0 Deadband selection
1467:1466 PWM0 Duty Cycle source
Regular Mode:
00: from PWM Duty Cycle CNT
Preset Registers Modes:
01: 8-byte MSB of RegFile
10: 8-byte LSB of RegFile
11: 16-byte RegFile
B7
00: Matrix output
01: PWM Period CNT overflow
PWM0 Duty Cycle Counter Clock Source
selection
1469:1468
10: Every 2nd pulse of PWM Period CNT overflow
11: Every 8th pulse of PWM Period CNT overflow
1471:1470 Reserved
0: 8-bit PWM1
1: 7-bit PWM1
1472
1473
1474
1475
1476
1477
1478
1479
PWM1 8-bit or 7-bit resolution
0: Non-Inverted Output
1: Inverted Output
PWM1 OUT+ output polarity selection
PWM1 OUT- output polarity selection
PWM1 SYNC On/Off
0: Non-Inverted Output
1: Inverted Output
B8
0: Synchronous Power-Down
1: Asynchronous Power-Down
0: Continuous mode
1: PWM Duty Cycle Counter Autostop at 0 % or 100 %
PWM1 Continuous/Autostop mode
PWM1 Boundary OSC disable
PWM1 Phase Correct mode
0: OSC is always enabled at boundaries
1: Automatically Disable OSC
0: Disable
1: Enable
B8
0: Keep
1: Stop
PWM1 Keep/Stop selection
Datasheet
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231 of 253
© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
00: No Deadband
01: 1PWM1 clock cycles
10: 2PWM1 clock cycles
11: 3PWM1 clock cycles
1481:1480 PWM1 Deadband selection
1483:1482 PWM1 Duty Cycle source
Regular Mode:
00: from PWM Duty Cycle CNT
Preset Registers Modes:
01: 8-byte MSB of RegFile
10: 8-byte LSB of RegFile
11: 16-byte RegFile
B9
00: Matrix output
01: PWM Period CNT overflow
PWM1 Duty Cycle Counter Clock Source
selection
1485:1484
10: Every 2nd pulse of PWM Period CNT overflow
11: Every 8th pulse of PWM Period CNT overflow
1487:1486 Reserved
0000: CLK_OSC0
0001: CLK_OSC0/4
0010: CLK_OSC1
0011: CLK_OSC1/8
0100: CLK_OSC1/64
0101: CLK_OSC1/512
0110: CLK_OSC1/4096
0111: CLK_OSC1/32768
1000: CLK_OSC1/262144
1001: From Flexible Divider
1010: Reserved
1491:1488 PWM1 Period Counter Clock Source selection
BA
1011: External clock through matrix (Matrix OUT [84])
1495:1492 Reserved
1503:1496 Reserved
1511:1504 Reserved
1519:1512 Reserved
BB
BC
BD
Reserved
1520
1521
1522
1523
Reserved
Reserved
Reserved
Reserved
BE
BE
BF
1527:1524 Reserved
1531:1528 Reserved
1532
1533
Reserved
Reserved
1535:1534 Reserved
Datasheet
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
1539:1536 Reserved
1540
Reserved
Reserved
С0
1541
1543:1542 Reserved
1551:1544 Reserved
1559:1552 Reserved
1567:1560 Reserved
1575:1568 Reserved
1583:1576 Reserved
1591:1584 Reserved
1599:1592 Reserved
1607:1600 Reserved
1615:1608 Reserved
1623:1616 Reserved
1631:1624 Reserved
1639:1632 Reserved
1647:1640 Reserved
1655:1648 Reserved
1663:1656 Reserved
1671:1664 Reserved
1679:1672 Reserved
1687:1680 Reserved
1695:1688 Reserved
1703:1696 Reserved
1711:1704 Reserved
1719:1712 Reserved
1727:1720 Reserved
1735:1728 Reserved
1743:1736 Reserved
1751:1744 Reserved
1759:1752 Reserved
1767:1760 Reserved
1775:1768 Reserved
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
Reserved
1776
1777
1778
1779
1780
Reserved
Reserved
Reserved
Reserved
Reserved
DE
Datasheet
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© 2021 Dialog Semiconductor
CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
1781
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DE
DF
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
E0
E1
E2
Datasheet
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CFR0011-120-00
SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features
Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
1816
1817
1818
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1819
E3
1820
1821
1822
1823
1824
1825
1826
1827
E4
1828
1829
1830
1831
1832
1833
1834
1835
E5
1836
1837
1838
1839
1840
1841
1842
E6
E6
1843
1844
1845
1846
1847
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Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
1848
1849
1850
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1851
E7
1852
1853
1854
1855
1856
1857
1858
1859
E8
1860
1861
1862
1863
1864
1865
1866
1867
E9
1868
1869
1870
1871
1872
1873
1874
1875
EA
1876
1877
1878
1879
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Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
1880
1881
1882
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1883
EB
1884
1885
1886
1887
1888
1889
1890
1891
EC
1892
1893
1894
1895
1896
1897
1898
ED
1899
1900
1902:1901 Reserved
1903
1904
1905
1906
1907
Reserved
Reserved
Reserved
Reserved
Reserved
EE
1910:1908 Reserved
1911
1912
1913
1914
1915
Reserved
Reserved
Reserved
Reserved
Reserved
EF
1918:1916 Reserved
1919 Reserved
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Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
1920
1921
Reserved
Reserved
Reserved
Reserved
1922
F0
1923
1926:1924 Reserved
1927
1928
1929
Reserved
Reserved
Reserved
Reserved
Reserved
1930
F1
1931
1934:1932 Reserved
1935
1936
1937
1938
1939
1940
1941
1942
1943
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
F2
1947:1944 Reserved
F3
F4
1948
Reserved
1951:1949 Reserved
1952
1953
1954
1955
Reserved
Reserved
Reserved
Reserved
1958:1956 Reserved
1959 Reserved
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Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
I2C reset bit with reloading NVM into Data
register (soft reset)
0: Keep existing condition
1: Reset execution
1960
0: Disable
1: Enable
IO Latching Enable During I2C Write Interface
1961
1963:1962 Reserved
0: Disable
1: Enable
1964
Protect mode enable
F5
000: All open read/write (mode 0)
001: Partly lock read (mode 1)
010: Partly lock read2 (mode 2)
011: Partly lock read2/write (mode 3)
100: All lock read (mode 4)
1965
Register protection mode bit 0
101: All lock write (mode 5)
1966
1967
Register protection mode bit 1
Register protection mode bit 2
110: All lock read/write (mode 6)
1: Mask
0: Overwrite
I2C write mask bits
F6
1975:1968
F7
F8
F9
1983:1976 Reserved
1991:1984 Reserved
1992
1993
Reserved
Reserved
F9
1995:1994 Reserved
1999:1996 Reserved
2007:2000 Reserved
FA
FB
FC
2015:2008 Reserved
2023:2016 Reserved
2027:2024
I2C slave address
0: From register [2024]
1: From GPI
2028
2029
2030
2031
Slave address selection bit0
Slave address selection bit1
Slave address selection bit2
Slave address selection bit3
0: From register [2025]
1: From GPIO1
FD
0: From register [2026]
1: From GPIO4
0: From register [2027]
1: From GPIO6
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Table 77: Register Map (Continued)
Address
Signal Function
Register Bit Definition
Byte Register Bit
0: I2C operation enable; matrix in 32/33 select
I2C_virtual_0/1 Input
1: I2C operation disable; matrix in 32/33 select GPIO2/3
digital input
I2C operation disable bit
2032
FE
2033
Reserved
Reserved
2034
2039:2035 Reserved
2047:2040 Reserved
FF
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24 Package Top Marking Definitions
24.1 STQFN 20L 2 MM X 3 MM 0.4P FCD GREEN
PPPPP Part Code
WWNNN
ARR
Date Code + S/N Code
Pin 1 Identifier
Assembly House Code +
Revision Code
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25 Package Information
25.1 PACKAGE OUTLINES FOR STQFN 20L 2 MM X 3 MM 0.4P FCD GREEN PACKAGE
Side View
Top View
Notes:
1. All dimensions are in millimeters.
2. Dimension “b” applies to metalized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on the
other end of the terminal, the dimension “b” should not
be measured in that radius area.
3. Bilateral co-planarity zone applies to the exposed
heat sink slug as well as the terminal.
Controlling dimension: mm
Bottom View
“A1” max lead co-planarity 0.05 mm
Standard tolerance: ±0.05
Figure 159: STQFN 20L 2x3mm 0.4P FCD Package
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25.2 MOISTURE SENSITIVITY LEVEL
The Moisture Sensitivity Level (MSL) is an indicator for the maximum allowable time period (floor lifetime) in which a moisture
sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a specified maximum
temperature and a maximum relative humidity before the solder reflow process. The MSL classification is defined in Table 78.
For detailed information on MSL levels refer to the IPC/JEDEC standard J-STD-020, which can be downloaded from
http://www.jedec.org.
The [PACKAGE_NAME] package is qualified for MSL [n].
Table 78: MSL Classification
MSL Level
MSL 4
Floor Lifetime
72 hours
168 hours
4 weeks
Conditions
30 °C / 60 % RH
30 °C / 60 % RH
30 °C / 60 % RH
30 °C / 60 % RH
30 °C / 60 % RH
MSL 3
MSL 2A
MSL 2
1 year
MSL 1
Unlimited
25.3 SOLDERING INFORMATION
Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can be downloaded from
www.jedec.org.
26 Ordering Information
Table 79: Ordering Information
Part Number
SLG47105V
Type
20-pin STQFN
SLG47105VTR
20-pin STQFN - Tape and Reel (3k units)
26.1 TAPE AND REEL SPECIFICATIONS
Max Units
Leader (min)
Length
Trailer (min)
Nominal
# of
Pins
Reel &
Hub Size
(mm)
Tape Part
Width Pitch
(mm) (mm)
Package Type
Package Size
(mm)
Length
(mm)
per Reel per Box
Pockets
Pockets
(mm)
STQFN 20L
2 mm x 3 mm
0.4P FCD Green
20
2.0x3.0x0.55
3000
3000
178/60
100
400
100
400
8
4
26.2 CARRIER TAPE DRAWING AND DIMENSIONS
Index Hole Index Hole
PocketBTMPocketBTM Pocket Index Hole Pocket Index Hole
to Tape
Edge
(mm)
to Pocket Tape Width
Center
(mm)
Length
(mm)
Width
(mm)
Depth
(mm)
Pitch
(mm)
Pitch Diameter
(mm)
Package Type
(mm)
P1
(mm)
D0
A0
B0
K0
P0
E
F
W
STQFN 20L
2 mm x 3 mm
0.4P FCD Green
2.2
3.15
0.76
4
4
1.5
1.75
3.5
8
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27 Thermal Guidelines
Actual thermal characteristics will depend on number and position of vias, PCB type, copper layers, and other factors. Operating
temperature range is from -40 °C to 85 °C. To guarantee reliable operation, the junction temperature of the SLG47105 must not
exceed 150 °C.
To avoid overheating of the power MOSFETs (as shown in Figure 109), a good thermal design of the PCB layout must be
implemented, especially when device operates near its maximum thermal limits. Refer to Section 3.4 to find max value of
Thermal Resistance.
Figure 160: Die Temperature when HV OUTs are Active
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28 Layout consideration
PCB should have enough ground plane to dissipate heat. SLG47105 has two additional pads which provide enhanced thermal
dissipation. Thermal vias are used to transfer heat from chip to other layers of the PCB.
The sense resistors and power capacitors should be placed as close as possible to the chip for reducing parasitic parameters.
Typical Application Circuit is shown in Figure 161.
Figure 161: Typical Application Circuit
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Figure 162: PCB Layout Example
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29 Layout Guidelines
29.1 STQFN 20L 2 MM X 3.0 MM X 0.55 MM 0.4P FCD PACKAGE
It’s highly recommended to place low-ESR capacitor between VDD2_A, VDD2_B, and GND pin to keep input voltage stable and
reduce ripple. This capacitor should be placed as close to the pins as possible. Also, the capacitor must have the low input
impedance at the switching frequency. The recommended value of this capacitor is 1-10 µF for most applications. Motors with
larger armature inductors require larger input capacitors.
Also, it's highly recommended to place 0.1 µF ceramic capacitor between VDD and GND.
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Glossary
A
ACK
Acknowledge bit
ACMP
ACMPH
Analog Comparator
Analog Comparator High Speed
B
BG
Bandgap
C
CCMP
CLK
CMO
CNT
Current Sense Comparator
Clock
Connection matrix output
Counter
D
DFF
DLY
D Flip-Flop
Delay
E
ESD
EV
Electrostatic discharge
End Value
F
FSM
Finite State Machine
G
GPI
GPIO
GPO
General Purpose Input
General Purpose Input/Output
General Purpose Output
H
HV
High Voltage
I
IN
IO
Input
Input/Output
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L
LP_BG
LPF
LS
Low Power Bandgap
Low Pass Filter
Level Shifter
LSB
LUT
LV
Least Significant Bit
Look Up Table
Low Voltage
M
MSB
MUX
Most Significant Bit
Multiplexer
N
NPR
nRST
NVM
Non-Volatile Memory Read/Write/Erase Protection
Reset
Non-Volatile Memory
O
OCP
OD
Overcurrent Protection
Open-Drain
OE
Output Enable
Oscillator
OSC
OTP
OUT
One Time Programmable
Output
P
PD
Power-Down
PGen
POR
PP
Pattern Generator
Power-On Reset
Push-Pull
PWM
PWR
P DLY
Pulse Width Modulator
Power
Programmable Delay
R
R/W
Read/Write
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S
SCL
SDA
SLA
SMT
SV
I2C Clock Input
I2C Data Input/Output
Slave Address
With Schmitt Trigger
nSET Value
T
TSD
TS
Thermal Shutdown
Temperature Sensor
U
UVLO
Under-Voltage-Lockout
Voltage Reference
V
Vref
W
WOSMT
WS
Without Schmitt Trigger
Wake and Sleep Controller
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Revision History
Revision
Date
Description
Updated section Analog Comparators
Updated table ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless
Otherwise Noted
Updated table EC at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Updated figure GPIO Matrix OE IO Structure Diagram
Updated figure GPIO with I2C Mode Structure Diagram
Updated figure GPI Structure Diagram
3.4
31-Aug-2021
Added subsection ESD Protection
Updated section GPIO4 Source for Oscillator 1 (25 MHz)
Updated table Typical Current Estimated for Each Macrocell
Fixed typos
3.3
3.2
18-Jun-2021
11-Jun-2021
Updated section Package Information
Corrected Wake and Sleep Controller Block Diagram
Updated table Absolute Maximum Ratings
Fixed typos
3.1
3.0
12-Apr-2021
15-Feb-2021
Updated parameter VOL in EC table
Final version
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Status Definitions
Revision Datasheet Status
Product Status
Definition
1.<n>
Target
Development
This datasheet contains the design specifications for product development. Specifications may
change in any manner without notice.
2.<n>
Preliminary
Qualification
Production
This datasheet contains the specifications and preliminary characterization data for products in
pre-production. Specifications may be changed at any time without notice in order to improve the
design.
3.<n>
4.<n>
Final
This datasheet contains the final specifications for products in volume production. The
specifications may be changed at any time in order to improve the design, manufacturing and
supply. Major specification changes are communicated via Customer Product Notifications.
Datasheet changes are communicated via www.dialog-semiconductor.com.
Obsolete
Archived
This datasheet contains the specifications for discontinued products. The information is provided
for reference only.
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