SLG4X42522-AGTR [DIALOG]
GreenPAK ⢠Voltage Monitor;
| 型号： | SLG4X42522-AGTR |
| 厂家： | 
Dialog Semiconductor |
| 描述： | GreenPAK ⢠Voltage Monitor |
| 文件： | 总17页 (文件大小：840K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLG4X42522-A
GreenPAK ™
Voltage Monitor
General Description
Pin Configuration
Dialog SLG4X42522-A is a low power and small
form device. The SoC is housed in a 6.5mm x
6.4mm TSSOP package which is optimal for using
with small devices.
Features
• Low Power Consumption
• Pb - Free / RoHS Compliant
• Halogen - Free
• TSSOP - 20 Package
Output Summary
5 Outputs - Open Drain NMOS 1X
2 Outputs - Push Pull 1X
Pin name
Pin # Pin name
Pin # Pin name
1
2
3
4
5
6
7
8
9
10
VDD
NC
11
12
13
14
15
16
17
18
19
20
GND
SENSE4L
SENSE2
Data
RESET1
SENSE4H
MR
SENSE1
WDI
SENSE3
WDO
RESET4
Clock
FAULT
FAULT_IND
RESET2
NC
RESET3
Dialog Semiconductor ©
SLG4X42522-A_DS_r010
SLG4X42522-A_GP_r001
Preliminary
Rev 0.10
Revised August 15th, 2019
SLG4X42522-A
Voltage Monitor
Block Diagram
Matrix0
Preliminary
Page 2
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Matrix1
Preliminary
Page 3
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Pin Configuration
Internal
Resistor
Pin #
Pin Name
Type
Pin Description
1
2
VDD
NC
PWR
--
Supply Voltage
Keep Floating or Connect to GND
Open Drain NMOS 1X
Analog Input/Output
--
--
3
RESET1
SENSE4H
MR
Digital Output
Analog Input/Output
Digital Input
floating
floating
floating
floating
floating
floating
floating
floating
--
4
5
Digital Input without Schmitt trigger
Analog Input/Output
6
SENSE1
WDI
Analog Input/Output
Digital Input
7
Digital Input without Schmitt trigger
Analog Input/Output
8
SENSE3
WDO
Analog Input/Output
Digital Output
Digital Output
GND
9
Open Drain NMOS 1X
Open Drain NMOS 1X
Ground
10
11
12
13
14
15
16
17
18
19
20
RESET4
GND
SENSE4L
SENSE2
Data
Analog Input/Output
Analog Input/Output
Digital Input
Analog Input/Output
floating
floating
floating
floating
floating
floating
floating
--
Analog Input/Output
Digital Input without Schmitt trigger
Digital Input without Schmitt trigger
Push Pull 1X
Clock
Digital Input
FAULT
FAULT_IND
RESET2
NC
Digital Output
Digital Output
Digital Output
--
Push Pull 1X
Open Drain NMOS 1X
Keep Floating or Connect to GND
Open Drain NMOS 1X
RESET3
Digital Output
floating
Ordering Information
Part Number
Package Type
20-pin TSSOP
SLG4X42522-AG
SLG4X42522-AGTR
20-pin TSSOP - Tape and Reel (4k units)
Preliminary
Page 4
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Absolute Maximum Conditions
Parameter
Min.
-0.5
GND -
0.5V
--
--
--
-1.0
--
--
--
--
--
--
-65
--
2000
500
Max.
7
VDD +
0.5V
1.98/G
10
Unit
V
Supply Voltage on VDD relative to GND
DC Input Voltage
V
PGA Input voltage
Maximum Average or DC Current
(Through pin)
Single-ended
Push-Pull 1x
OD 1x
V
mA
mA
nA
14
1.0
Current at Input Pin
Vin = 0 V
Vin = VDD
Vin = 0 V
Vin = VDD
Vin = 0 V
Vin = VDD
0.29
0.92
0.13
0.49
0.39
142.92
150
150
--
ACMP Input Leakage
PGA Input Leakage
nA
nA
Logic Input without Schmitt
Trigger(Floating) Leakage
Storage Temperature Range
Junction Temperature
°C
°C
V
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
Moisture Sensitivity Level
--
V
1
Electrical Characteristics
Symbol
VDD
TA
Parameter
Condition/Note
Min.
1.71
-40
--
--
--
Typ.
3.3
25
200
0.1
4
Max.
3.6
105
--
--
--
Unit
V
°C
µA
µF
pF
Supply Voltage
Operating Temperature
Quiescent Current
Capacitor Value at VDD
Input Capacitance
Maximal Voltage Applied
to any PIN in High-
Impedance State
IQ
CVDD
CIN
Static inputs and floating outputs
VO
--
--
--
--
--
--
--
--
--
--
VDD
45
V
Maximum Average or DC
Current Through VDD Pin
(Per chip side, see Note
2)
TJ = 85°C
TJ = 110°C
TJ = 85°C
TJ = 110°C
mA
mA
mA
mA
IVDD
21
Maximum Average or DC
Current Through GND Pin
(Per chip side, see Note
2)
69
IGND
33
Logic Input at VDD=1.8V
Logic Input at VDD=3.3V
Logic Input at VDD=1.8V
Logic Input at VDD=3.3V
Push-Pull 1X, IOH=100µA at
VDD=1.8V
Push-Pull 1X, IOH=3mA at
VDD=3.3V
Push-Pull 1X, IOL=100µA, at
VDD=1.8V
1.087
1.949
0
--
--
--
--
VDD
VDD
0.759
1.286
V
V
V
V
VIH
VIL
HIGH-Level Input Voltage
LOW-Level Input Voltage
0
1.680
2.713
--
1.788
3.095
0.010
--
--
V
V
V
HIGH-Level Output
Voltage
VOH
LOW-Level Output
Voltage
VOL
0.015
Preliminary
Page 5
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Push-Pull 1X, IOL=3mA, at
VDD=3.3V
--
0.148
0.007
0.080
1.703
10.774
1.660
7.795
2.534
12.370
0.228
V
Open Drain NMOS 1X,
IOL=100µA, at VDD=1.8V
Open Drain NMOS 1X,
IOL=3mA, at VDD=3.3V
Push-Pull 1X, VOH=VDD-0.2V
at VDD=1.8V
Push-Pull 1X, VOH=2.4V at
VDD=3.3V
Push-Pull 1X, VOL=0.15V, at
VDD=1.8V
--
0.010
V
--
0.147
V
1.027
5.608
0.917
4.875
1.375
7.313
--
--
--
--
--
--
mA
mA
mA
mA
mA
mA
ms
µs
HIGH-Level Output
Current (see Note 1)
IOH
Push-Pull 1X, VOL=0.4V, at
VDD=3.3V
LOW-Level Output
Current (see Note 1)
IOL
Open Drain NMOS 1X,
VOL=0.15V, at VDD=1.8V
Open Drain NMOS 1X,
VOL=0.4V, at VDD=3.3V
At temperature 25°C
At temperature -40 +105°C
At temperature 25°C
At temperature -40 +105°C
At temperature 25°C
At temperature -40 +105°C
At temperature 25°C
At temperature -40 +105°C
At temperature 25°C
At temperature -40 +105°C
Low to High transition, at
temperature 25°C
Low to High transition, at
temperature -40 +105°C
High to Low transition, at
temperature 25°C
High to Low transition, at
temperature -40 +105°C
Low to High transition, at
temperature 25°C
Low to High transition, at
temperature-40 +105°C
High to Low transition, at
temperature 25°C
High to Low transition, at
temperature-40 +105°C
Low to High transition, at
temperature 25°C
Low to High transition, at
temperature-40 +105°C
High to Low transition, at
temperature 25°C
High to Low transition, at
temperature-40 +105°C
518
381
816
600
816
600
816
600
816
600
621
670
725
960
TDLY2
TDLY5
TDLY6
TDLY7
TDLY8
Delay2 Time
Delay5 Time
Delay6 Time
Delay7 Time
Delay8 Time
1002
1087
1002
1087
1002
1087
1002
1087
1188
1574
1188
1574
1188
1574
1188
1574
µs
µs
µs
891
888
890
887
791
789
790
788
791
789
790
788
900
900
900
900
800
800
800
800
800
800
800
800
914
917
914
915
813
816
813
814
813
816
813
814
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
Analog Comparator0
Threshold Voltage
VACMP0
VACMP1
VACMP2
Analog Comparator1
Threshold Voltage
Analog Comparator2
Threshold Voltage
Preliminary
Page 6
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Low to High transition, at
temperature 25°C
Low to High transition, at
temperature-40 +105°C
High to Low transition, at
temperature 25°C
High to Low transition, at
temperature -40 +105°C
Low to High transition, at
temperature 25°C
Low to High transition, at
temperature-40 +105°C
High to Low transition, at
temperature 25°C
High to Low transition, at
temperature-40 +105°C
Low to High transition, at
temperature 25°C
Low to High transition, at
temperature-40 +105°C
High to Low transition, at
temperature 25°C
High to Low transition, at
temperature-40 +105°C
Low to High transition
High to Low transition
Low to High transition
High to Low transition
891
888
890
887
791
789
790
788
891
888
890
887
900
900
900
900
800
800
800
800
900
900
900
900
914
917
914
915
813
816
813
814
914
917
914
915
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
Analog Comparator3
Threshold Voltage
VACMP3
Analog Comparator4
Threshold Voltage
VACMP4
Analog Comparator5
Threshold Voltage
VACMP5
--
782
--
884
0.660
--
--
--
--
1.4
819
--
917
--
DCMP0 Threshold
Voltage
DCMP2 Threshold
Voltage
VDCMP0
VDCMP2
TSU
mV
ms
V
Startup Time (see Note 3) From VDD rising past PONTHR
DD Level Required to Start Up
3.740
V
PONTHR
Power On Threshold
0.953
0.935
1.462
1.103
1.707
1.281
the Chip
VDD Level Required to Switch
Off the Chip
POFFTHR Power Off Threshold
Note:
V
1. DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
2. The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7, 8, 9 and 10 are connected to one side,
pins 12, 13, 14, 15, 16, 17, 18, 19 and 20 to another.
3. VDD ramp rising speed must be less than 0.6 V/μs after power on. Violating this specification may cause chip to
restart.
Preliminary
Page 7
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Typical Application Circuit
Preliminary
Page 8
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Functionality Waveforms
Channel 1 (yellow/top line) – PIN#6 (SENSE1)
D0 – PIN#5 (MR)
D1 – PIN#7 (WDI)
D2 – PIN#3 (RESET1) with external 5kΩ pull up resistor
D3 – PIN#9 (WDO) with external 5kΩ pull up resistor
1. RESET1 functionality
2. WDO functionality
Channel 1 (yellow/top line) – PIN#4 (SENSE4H)
Channel 2 (light blue/2nd line) – PIN#12 (SENSE4L)
D0 – PIN#10 (RESET4) with external 5kΩ pull up resistor
3. RESET4 functionality
Preliminary
Page 9
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Channel 1 (yellow/top line) – PIN#13 (SENSE2)
D0 – PIN#18 (RESET2) with external 5kΩ pull up resistor
4. RESET2 functionality
Channel 1 (yellow/top line) – PIN#8 (SENSE3)
D0 – PIN#20 (RESET3) with external 5kΩ pull up resistor
5. RESET3 functionality
Preliminary
Page 10
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
D0 – PIN#15 (Clock)
D1 – PIN#14 (Data)
D2 – PIN#17 (FAULT_IND)
D3 – PIN#16 (FAULT)
6. FAULT_IND and FAULT functionality
Preliminary
Page 11
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Package Top Marking
Datasheet Programming
Lock
Status
U
Checksum Part Code
Revision
Date
Revision
Code Number
0.10
001
0x2FB67D3E
08/15/2019
The IC security bit is locked/set for code security for production unless otherwise specified. Revision
number is not changed for bit locking.
Preliminary
Page 12
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Package Drawing and Dimensions
Preliminary
Page 13
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Tape and Reel Specification
Max Units
Leader (min)
Length
Trailer (min)
Part
Pitch
[mm]
Tape
Width
[mm]
Nominal
Package Size
[mm]
Package # of
Reel & Hub
Size [mm]
Type
Pins
Length
per Reel per Box
Pockets
Pockets
[mm]
[mm]
TSSOP
20L 173
MIL
TSSOP
20L 173
MIL
20
6.5 x 6.4
4000
4000
330 / 100
42
336
42
20
6.5 x 6.4
Green
Green
Package
Package
Carrier Tape Drawing and Dimensions
Index
Index
Hole
Pitch
Index
Hole
Index
Hole to
Pocket
BTM
Length
Pocket
BTM
Width
Hole to
Pocket
Center
Tape
Width
Pocket
Depth
Pocket
Pitch
Diameter Tape Edge
Package
Type
A0
B0
K0
P0
P1
D0
E
F
W
TSSOP
20L 173
MIL Green
Package
6.8
6.9
1.6
4
8
1.5
1.75
7.5
16
Recommended Reflow Soldering Profile
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 25.74 mm3 (nominal).
More information can be found at www.jedec.org.
Preliminary
Page 14
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Recommended Land Pattern
Preliminary
Page 15
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
Datasheet Revision History
Date
Version
Change
08/15/2019
0.10
New design for SLG46620-AG chip
Preliminary
Page 16
SLG4X42522-A_DS_r010
SLG4X42522-A
Voltage Monitor
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Dialog Semiconductor's suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU
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Preliminary
Page 17
SLG4X42522-A_DS_r010
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