EDJ5308AASE-AG-E [ELPIDA]
DDR DRAM, 64MX8, CMOS, PBGA78, ROHS COMPLIANT, MICRO, BGA-78;
| 型号： | EDJ5308AASE-AG-E |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | DDR DRAM, 64MX8, CMOS, PBGA78, ROHS COMPLIANT, MICRO, BGA-78 存储 内存集成电路 动态存储器 双倍数据速率 时钟 |
| 文件： | 总130页 (文件大小：1562K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
512M bits DDR3 SDRAM
EDJ5304BASE (128M words × 4 bits)
EDJ5308BASE (64M words × 8 bits)
EDJ5316BASE (32M words × 16 bits)
Features
pecifications
• Dsity: 5
• Organiza
⎯ 16M wonks (EDJ5304BASE)
⎯ 8M words anks (5308BASE)
⎯ 4M words × 16 ts × 8 ba(EDJ5316BASE)
• Package
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
⎯ 78-ball FBGA (EDJ5/5308BASE)
⎯ 96-ball FBGA (EDJ531ASE)
⎯ Lead-free (RoHS complia
• Power supply: VDD, VDDQ = 1.5V 0.075V
• Data rate
⎯ 1333Mbps/1066Mbps/800Mbps (max
• 1KB page size (EDJ5304/5308BASE)
⎯ Row address: A0 to A12
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
ted /CAS by programmable additive latency for
better command and data bus efficiency
⎯ Column address: A0 to A9, A11 (EDJ5304BASE)
A0 to A9 (EDJ5308BASE)
• On-Termination (ODT) for better signal quality
⎯ us ODT
DT
⎯ nous ODT
• Multi Purpose r (MP) for temperature read
out
• 2KB page size (EDJ5316BASE)
⎯ Row address: A0 to A11
⎯ Column address: A0 to A9
• Eight internal banks for concurrent operation
• Interface: SSTL_15
• Burst lengths (BL): 8 and 4 with Burst Chop (BC)
• Burst type (BT):
⎯ Sequential (8, 4 with BC)
• ZQ calibrae and ODT
• ProgrammaArray lf-Refresh (PASR)
• /RESET pin for wer-up uence and reset
function
⎯ Interleave (8, 4 with BC)
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10
• /CAS Write Latency (CWL): 5, 6, 7, 8
• Precharge: auto precharge option for each burst
access
• SRT range:
⎯ Normal/extended
⎯ Auto/manual self-refresh
• Programmable Output driver impence cont
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
• Refresh: auto-refresh, self-refresh
• Refresh cycles
⎯ Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
• Operating case temperature range
⎯ TC = 0°C to +95°C
Document No. E0966E60 (Ver. 6.0) This product became EOL in September, 2010.
Date Published July 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2006-2007
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Ordering Information
Mask
version
Organization
(words × bits)
Internal
banks
JEDEC speed bin
(CL-tRCD-tRP)
Part number
Package
EDJ5304BASE-DG-E
EDJ5304BASE-DJ-E
EDJ5304BASE-AC-E
EDJ53ASE-AE-E
EDJBE-AG-E
E04BASA-E
J4BASE-E
DDR3-1333G (8-8-8)
DDR3-1333H (9-9-9)
DDR3-1066E (6-6-6)
DDR3-1066F (7-7-7)
DDR3-1066G (8-8-8)
DDR3-800D (5-5-5)
DDR3-800E (6-6-6)
A
128M × 4
8
78-ball FBGA
EDJ53ASE-DG-E
EDJ5308BSE-DJ-E
J5308BASE-A
E308BAS
EDJ508BA
EDJ5308BA
EDJ5308BA
DDR3-1333G (8-8-8)
DDR3-1333H (9-9-9)
DDR3-1066E (6-6-6)
DDR3-1066F (7-7-7)
DDR3-1066G (8-8-8)
DDR3-800D (5-5-5)
DDR3-800E (6-6-6)
64M × 8
EDJ5316BAS
EDJ5316BASE-
EDJ5316BASE-AC-E
EDJ5316BASE-AE-E
EDJ5316BASE-AG-E
EDJ5316BASE-8A-E
EDJ5316BASE-8C-E
DDR3-1333G (8-8-8)
DDR3-1333H (9-9-9)
DDR3-1066E (6-6-6)
DDR3-1066F (7-7-7)
DDR3-1066G (8-8-8)
DDR3-800D (5-5-5)
DDR3-800E (6-6-6)
32M × 16
96-ball FBGA
Part Number
E D J 53 04 B A SE - DG - E
Elpida Memory
Type
D: Monolithic Device
Environment code
E: Lead Free
Product Family
J: DDR3
(RoHS compliant)
peed
Density / Bank
53: 512M / 8-bank
G: R3-1333G (8-8-8)
DR3-1333H (9-9-9)
DDR3-1066E (6-6-6)
E: DD-1066F (7-7-7)
AG: D1066G (8-8-8)
8A: R3-800D (5-5-5)
8DR3-800E 6-6-6)
Organization
04: x4
08: x8
16: x16
Pac
SE: GA
Power Supply, Interface
B: 1.5V, SSTL_15
Die Rev
Preliminary Data Sheet E0966E60 (Ver. 6.0)
2
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Pin Configurations (×4, ×8 configuration)
/xxx indicates active low signal.
78-ball FBGA (×4 configuration)
78-ball FBGA (×8 configuration)
1
2
3
7
8
9
1
2
3
7
8
9
A
A
B
V
VDD
NC
NC
VSS
VDD
VSS
VDD
NC
NU/(/TDQS) VSS
VDD
VSS VQ DQ0
DM VSSQ VDDQ
VSS VSSQ DQ0
VDDQ
DM/TDQS VSSQ VDDQ
C
D
C
D
VQ
VSSQ
DQ2 DQS
DQ1
VDD
NC
DQ3 VSSQ
VSSQ
NC VDDQ
NC
VDD CKE
DQ2 DQS
DQ1
VDD
DQ7
DQ3 VSSQ
VSSQ
VSS
VSSQ DQ6 /DQS
VSS
DQ5
E
F
G
H
J
E
F
G
H
J
DQ4
VREF
NC
ODT VDD /CAS
VREFDQ VDDQ
VDDQ
NC
/CK
VSS
NC
VSS /RAS
CK
/CK
VSS
ODT VDD /CAS
VDD CKE
A10(AP)
A10(AP)
NC
/CS
/WE
ZQ
NC
NC
/CS
/WE
ZQ
NC
VSS
VDD
VSS
VDD
VSS
BA0
A3
BA2
A0
NC VREFCA VSS
VSS
VDD
VSS
VDD
VSS
BA0
A3
BA2
A0
NC VREFCA VSS
K
L
K
L
12(/BC) BA1
V
VDD
VSS
A12(/BC) BA1
VDD
VSS
VDD
VSS
A5
A2
A1
A11
NC
A4
6
A8
A5
A2
A1
A11
NC
A4
A6
A8
M
N
M
N
A7
A9
A7
A9
/RESET NC
/RESET NC
(Top view)
(Top view)
Pin name
Function
Address inputs
A10 (AP): Auto precharge
A12(/BC): Burst chop
P
/RES
Function
A0 to A12*3
Active low asynchronous reset
BA0 to BA2*3
DQ0 to DQ7
DQS, /DQS
TDQS, /TDQS
/CS*3
Bank select
VDD
ly voltage for internal circuit
Ground or internal circuit
Supoltage for DQ circuit
und for DQ cuit
erence age for DQ
Referevoltag
Data input/output
Differential data strobe
Termination data strobe
Chip select
VSS
VDDQ
VSSQ
VREFDQ
VREFCA
ZQ
NC*1
NU*2
/RAS, /CAS, /WE*3
CKE*3
Command input
Clock enable
Reference pin ZQ caliion
No connectio
CK, /CK
Differential clock input
Write data mask
ODT control
DM
ODT*3
Not usable
Notes: 1. Not internally connected with die.
2. Don’t connect. Internally connected.
3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
3
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Pin Configurations (×16 configuration)
/xxx indicates active low signal.
96-ball FBGA
3
1
2
7
8
9
A
B
C
D
E
VDDQ DQU5 DQU7
VSSQ VDD VSS
DQU4 VDDQ VSS
/DQSU DQU6 VSSQ
DQSU DQU2 VDDQ
DQU0 VSSQ VDD
VDDQ
DQU3 DQU1
VSSQ VDDQ DMU
VSS VSSQ DQL0
DML VSSQ VDDQ
DQL1 DQL3 VSSQ
F
G
H
J
VDDQ DQL2 DQSL
VSSQ DQL6 /DQSL
VREFDQ VDDQ DQL4
VDD
VSS VSSQ
DQL7 DQL5 VDDQ
NC
VSS S
CK
VSS
VDD
NC
CKE
NC
K
L
/CK
ODT
N
/CS
BA2
A10(AP) ZQ
M
N
P
R
T
VSS
BA0
NC VREFCA VSS
VDD
VSS
VDD
A3
A5
A7
A
A2
A9
A12(/BC) BA1
VDD
VSS
VDD
NC
A8
VSS /RESET NC
(Top view)
Pin name
A0 to A11*2
Function
Address inputs
Pin name
ODT*2
Functio
Ocontrol
A10(AP): Auto precharge
A12(/BC) *2
BA0 to BA2
Burst chop
/RESET*2
VDD
ive low chronous reset
Supplage for l circuit
Bank select
DQU0 to DQU7
DQL0 to DQL7
Data input/output
VSS
Ground for inal circuit
DQSU, /DQSU
DQSL, /DQSL
Differential data strobe
VDDQ
Supply voltage DQ circuit
/CS*2
/RAS, /CAS, /WE*2
CKE*2
Chip select
VSSQ
VREFDQ
VREFCA
ZQ
Ground for DQ circuit
Reference voltage for DQ
Reference voltage
Command input
Clock enable
CK, /CK
Differential clock input
Write data mask
Reference pin for ZQ calibration
No connection
DMU, DML
NC*
Note: 1. Not internally connected with die.
2. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
4
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin nfrations (×4, ×8 configuration)......................................................................................................3
onfiguions (×16 configuration)..........................................................................................................4
Electrl Conditions......................................................................................................................................7
Absolute ximum Ratings .......................................................................................................................... 7
Orature Condition ................................................................................................................ 7
Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V 0.075V)................... 8
Measument Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V 0.075V)....................... 8
Diffeput Loevels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V 0.075V)..................................... 8
AC and DC OutMeasurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V 0.075V).................. 11
AC Overshoondershoot Specification..................................................................................................... 13
Output Driver Impance......................................................................................................................... 14
On-Die Termination (ODT) Levels anacteristics ......................................................................... 16
ODT Timing Definitions.................................................................................................... 18
IDD Measurement Conditions C = 0°C °C, VDD, VDDQ = 1.5V 0.075V)................................... 22
Electrical Specifications...........................................................................................................................33
DC Characteristics 1 (TC = 0°C to +85°C, VDDD1.5V 0.075V) ................................................. 33
DC Characteristics 2 (TC = 0°C to +85°C, D, VDDQ = 5V 0.075V) ................................................. 34
Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.5V ............................................................. 34
Standard Speed Bins............................................................................................................ 35
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 10.0S, VSQ = 0V)....................... 38
Block Diagram ......................................................................................................................50
Pin Function..............................................................................................................................51
Command Operation ........................................................................................................................53
Command Truth Table....................................................................................................................... 53
CKE Truth Table............................................................................................................................... 57
Simplified State Diagram............................................................................................................58
RESET and Initialization Procedure...................................................................................................59
Power-Up and Initialization Sequence..................................................................................................
Reset and Initialization with Stable Power ............................................................................................ 60
Programming the Mode Register............................................................................................................61
Mode Register Set Command Cycle Time (tMRD) ..................................................................................... 61
MRS Command to Non-MRS Command Delay (tMOD) ............................................................................. 61
DDR3 SDRAM Mode Register 0 [MR0] ...................................................................................................... 62
DDR3 SDRAM Mode Register 1 [MR1] ...................................................................................................... 63
DDR3 SDRAM Mode Register 2 [MR2] ...................................................................................................... 64
Preliminary Data Sheet E0966E60 (Ver. 6.0)
5
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
DDR3 SDRAM Mode Register 3 [MR3] ...................................................................................................... 65
Burst Length (MR0) .................................................................................................................................... 66
Burst Type (MR0) ....................................................................................................................................... 66
DLL Enable (MR1)...................................................................................................................................... 67
DLL Disable (MR1) ..................................................................................................................................... 67
dditive Latency (MR1)............................................................................................................................... 70
WriLeveling (MR1) .................................................................................................................................. 71
TDQS, /TDQS function (MR1) .................................................................................................................... 74
Extenperature Usage (MR2)......................................................................................................... 75
Mister (MR3)..................................................................................................................... 76
Operation RAM..................................................................................................................84
Rnition........................................................................................................................... 84
Read tion .................................................................................................................................... 86
Write Timing Dtion................................................................................................................................ 92
Write Operatio......................................................................................................................................... 93
Write Timing Violans .......................................................................................................................... 99
Write Data Mask .................................................................................................................... 100
Precharge ..................................................................................................................... 101
Auto Precharge Operation ............................................................................................................... 102
Auto-Refresh....................................................................................................................................... 103
Self-Refresh........................................................................................................................................ 104
Power-Down Mode ....................................................................................................................... 105
Input Clock Frequency Change during Precharge P........................................................... 112
On-Die Termination (ODT).................................................................................................... 113
ZQ Calibration..................................................................................................................... 125
Package Drawing ..............................................................................................................126
Recommended Soldering Conditions.......................................................................................128
Preliminary Data Sheet E0966E60 (Ver. 6.0)
6
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Electrical Conditions
• All voltages are referenced to VSS (GND)
• Execute power-up and Initialization sequence before proper device operation is achieved.
Absolute Maximum Ratings
Parame
Symbol
VDD
Rating
Unit
V
Notes
1, 3
1, 3
1
Poupvoltage
supply vge for output
Input vge
−0.4 to +1.975
−0.4 to +1.975
−0.4 to +1.975
−0.4 to +1.975
−0.4 to 0.6 × VDD
−0.4 to 0.6 × VDDQ
−55 to +100
1.0
VDDQ
VIN
V
V
utput voltage
VOUT
VREFCA
VREFDQ
Tstg
V
1
Rence volt
Reference v
Storage tem
Power dissipa
V
3
V
3
°C
W
mA
1, 2
1
PD
Short circuit output t
IOUT
50
1
Notes: 1. Stresses greatean those listed under Absolute Maximum Ratings may cause permanent damage to
the device. s is a stress rating only and functional operation of the device at these or any other
conditions abothose indicated in the operational sections of this specification is not implied. Exposure
to absolute maximm rating conditions foxtended periods may affect reliability.
2. Storage temperature s the case surfarature on the center/top side of the DRAM.
3. VDD and VDDQ must be within 3other at all times; and VREF must be no greater than
0.6 × VDDQ, When VDD and V500mV; VREF may be equal to or less than 300mV.
Caution
Exposing the device to stress above those listed n Absolute Maximum Ratings could cause
permanent damage. The device is not meant to rated under conditions outside the limits
described in the operational section of this spcation. Exposure to Absolute Maximum Rating
conditions for extended periods may affect devireliability.
Operating Temperature Condition
Parameter
Symbol
TC
Rating
Unit
Notes
1, 2, 3
Operating case temperature
0 to +95
°C
Notes: 1. Operating temperature is the case surface temperature on the e of the DRAM.
2. The Normal Temperature Range specifies the temperatures whll DRspecifications will be
supported. During operation, the DRAM case temperature must bmaintabetween 0°C to +85°C
under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Tempature Re between +85°C
and +95°C case temperature. Full specifications are guaranteed in this range, e following additional
conditions apply:
a)
Refresh commands must be doubled in frequency, therefore reducing the refreinterval EFI to
3.9μs. (This double refresh requirement may not apply for some devices.)
b)
If Self-refresh operation is required in the Extended Temperature Range, then it andato
either use the Manual Self-Refresh mode with Extended Temperature Range capability (bit
[A6, A7] = [0, 1]) or enable the optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]
Preliminary Data Sheet E0966E60 (Ver. 6.0)
7
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Recommended DC Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V 0.075V)
Parameter
Symbol
VDD
min.
typ.
1.5
1.5
max.
Unit
V
Notes
1, 2
Supply voltage
1.425
1.425
1.575
1.575
Supply voltage for DQ
Input reference voltage
VDDQ
V
1, 2
VREFCA (DC) 0.49 × VDDQ
0.50 × VDDQ 0.51 × VDDQ
0.50 × VDDQ 0.51 × VDDQ
V
3, 4
Input e voltage for DQ VREFDQ (DC) 0.49 × VDDQ
Tation vge VTT VDDQ/2 – TBD
V
3, 4
TBD
VDDQ/2 + TBD
V
otes. Under all conditions VDDQ must be less than or equal to VDD.
2VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. The oise on VREF may not allow VREF to deviate from VREF(DC) by more than 1% VDD (for
re15 mV).
4. ox. VDD/2 15 mV.
AC and DC ment Lvels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V 0.075V)
Parameter
Sol
H (DC)
VIL (DC)
VIH (AC)
(AC)
VIHdiff
min.
typ.
⎯
max.
Unit
V
Notes
DC input logic high
DC input logic low
AC input logic high
AC input logic low
Differential input logic high
Differential input logic low
VREF + 0.1
TBD
1
1
TBD
⎯
VREF – 0.1
⎯
V
1, 2
1, 2
VREF + 0.175
⎯
V
⎯
⎯
⎯
VREF – 0.175
⎯
V
+
V
⎯
VILdiff
–0.200
V
Notes: 1 For DQ and DM: VREF = VRDQ. Fonly pins except /RESET; VREF = VREFCA
2. See Overshoot and Undershoot Specifications secon.
Differential Input Logic Levels (TC = 0°C to +85°C, VDVDD= 1.5V 0.075V)
Parameter
Symbol
min.
TBD
max.
Unit
V
Note
1
AC differential input voltage
VID (AC)
VDDQ + 0.6
Differential input cross point voltage
relative to VDD/2
VIX
− 150
150
mV
V
AC differential cross point voltage
VOX (AC)
TBD
Note: 1. To guarantee tight setup and hold times as well as output swith respect to clock and
strobe, each cross point voltage of differential input signals DQS, /DQS) must meet the
requirements in table above.
The differential input cross point voltage VIX is measured from e actucross point of true and
complement signal to the midlevel between of VDD and VSS.
VDD
CK, DQS
VIX
VDD/2
VIX
VIX
/CK, /DQS
VSS
VIX Definition
Preliminary Data Sheet E0966E60 (Ver. 6.0)
8
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Input Slew Rate Definitions
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF and the first crossing of VIH (AC) min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of VREF and the first crossing of VIL (AC) max.
Hold (tIH, tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC)
max ahe first crossing of VREF. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew
rattwethe last crossing of VIH (DC) min and the first crossing of VREF.
e-ended put Slew Rate Definition]
Measured
scription
From
To
Defined by
VIH (AC) (min.) – VREF
Applicable for
Inpuew rat
VREF
VIH (AC) (min.)
Setup (tIS, tDS)
ΔTRS
VREF – VIL (AC) (max.)
ΔTFS
VREF – VIL (DC) (max.)
ΔTRH
Input slew raVREF
Input slew rate foe
VIL (AC) (max.)
VC) (max.) VREF
Hold (tIH, tDH)
VIH (DC) (min.) – VREF
ΔTFH
Input slew rate for falling edgVIH (DC) (min.) VREF
Note: This nominal slew e applies for linear signal waveforms.
Setup
VDDQ
VIH (AC) min.
VIH (DC) min.
VREF
VIL (DC) max.
max.
VREF
−
VIL (AC) max.
Falling slew =
ing sle=
ΔTFS
ΔTFS
ΔTRS
VIH (AC) min.
−
VREF
Hold
ΔTRS
VDDQ
VIH (AC) m
VIH (DC) min.
VREF
VIL (DC) max.
VIL (AC) max.
VC) max.
REF
VSSQ
Falling slew =
Rising slew =
ΔTFH
ΔTFH
ΔTRH
VREF
DC) m
ΔTRH
Input Nominal Slew Rate Definition for Single-Ended Signals
Preliminary Data Sheet E0966E60 (Ver. 6.0)
9
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
[Differential Input Slew Rate Definition]
Measured
From
Description
To
Defined by
Applicable for
Note
Differential input slew rate for
rising edge
(CK - /CK and DQS - /DQS)
VIHdiff (min.) – VILdiff (max.)
VILdiff (max.)
VIHdiff (min.)
VIHdiff (min.)
ΔTRdiff
Differenput slew rate for
fallige
(CK and S - /DQS)
VIHdiff (min.). – VILdiff max.
VILdiff (max.)
ΔTFdiff
ote: he differential signal (i.e. CK, /CK and DQS, /DQS) must be linear between these thresholds.
VIHdiff(min.)
0
VILdiff (max.)
ΔTRdiff
ΔTFdiff
VIHdiff (min.)
−
VILd
VIHdiff (min.)
−
VILdiff (max.)
Falling slew =
Rising slew =
ΔTFdiff
ΔTRdiff
Differential Inpuew Ration for DQS, /DQS and CK, /CK
Preliminary Data Sheet E0966E60 (Ver. 6.0)
10
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
AC and DC Output Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V 0.075V)
Parameter
Symbol
Specification
Unit
V
Notes
DC output high measurement level
(for IV curve linearity)
VOH (DC)
0.8 × VDDQ
DC output middle measurement level
(for IV cve linearity)
V
V
VOM (DC)
VOL (DC)
VOH (AC)
VOL (AC)
VOHdiff
0.5 × VDDQ
DC ow measurement level
(focurve earity)
0.2 × VDDQ
put high asurement level
for out slew rate)
VTT + 0.1 × VDDQ
VTT − 0.1 × VDDQ
0.2 × VDDQ
V
V
V
V
1
1
2
2
AC outpuw measurement level
r output slew rat
Afferential surement
level for out
AC differentement
level (for ou
VOLdiff
−0.2 × VDDQ
Notes: 1. T.1 × VQ is based on approximately 50% of the static single-ended output high or low
swing driver edance of 34Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the
differential outpu
2. The swing of 2 × VDDQ is based on approximately 50% of the static single-ended output high or low
swing with a der impedance of 34Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the
differential outpu
Output Slew Rate Definitions
[Single-Ended Output Slew Rate Definn]
Measured
Description
From
To
Defined by
VOH (AC) – VOL (AC)
ΔTRse
VOH (AC) – VOL (AC)
ΔTFse
Output slew rate for rising edge VOL (AC)
Output slew rate for falling edge VOH (AC)
VOH (A
VOL (AC)
C)
TT
VO)
ΔTRse
ΔTFse
VOH (AC)
−
VOL (AC)
VOH (AC)
−
VOL (AC)
Falling slew =
Rising slew =
ΔTFse
ΔTRse
Input Slew Rate Definition for Single-Ended Signals
Preliminary Data Sheet E0966E60 (Ver. 6.0)
11
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
[Differential Output Slew Rate Definition]
Measured
From
Description
To
Defined by
VOHdiff(AC) – VOLdiff (AC)
ΔTRdiff
VOHdiff (AC) – VOLdiff (AC)
ΔTFdiff
Differential output slew rate for
rising edge
VOLdiff (AC)
VOHdiff (AC)
VOHdiff (AC)
Differentl output slew rate for
falling
VOLdiff (AC)
VOHdiff (AC)
0
VOLdiff (AC)
ΔTRdiff
Fdiff
VOHdiff (AC)
−
VOLdiff (AC)
VOHdiff (AC)
−
VOLdiff (AC)
Falling =
Rising slew =
ΔTFdiff
ΔTRdiff
Diffntial Input Slew Rate Definition for DQS, /DQS and CK, /CK
Output Slew Rate (RON = RZQ/7 setting)
Parameter
Symbol
SRQse
Spe
n.
2.5
max.
5
Unit
Notes
D3-800
DDR3-1066
DDR3-1333
Output slew rate
(Single-ended)
V/ns
DDR3-800
DDR3-1066
DDR3-1333
Output slew rate
(Differential)
SRQdiff
5
10
V/ns
Remark: SR = slew rate. se = single-ended signals. diff = diffels. Q = Query output
Reference Load for AC Timing and Output Slew Rate
Measurement point
DQ
VTT = 0.5 ×
RT =25Ω
Reference Output Load
Preliminary Data Sheet E0966E60 (Ver. 6.0)
12
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
AC Overshoot/Undershoot Specification
Parameter
Pins
Specification
0.4V
Command, Address,
CKE, ODT
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
0.4V
Maximvershoot area above VDD
D1
0.4V-ns
R3-1066
DD800
0.5V-ns
0.67V-ns
Maximum dershoot area below VSS
DDR3-1333
0.4V-ns
R3-1066
0.5V-ns
0.67V-ns
0.4V
DDR3-80
Maximum pd for overshoot
Maximum peawed foershoot
CK, /CK
0.4V
Maximum overshoot area above
DDR3-1333
0.15V-ns
DDR3-1066
DDR3-800
0.19 V-ns
0.25V-ns
Maximum undershoot area below S
DDR3-1333
0.15V-ns
DDR3-1066
0.19 V-ns
0.25V-ns
0.4V
DDR3-800
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
DQ, DQS, /DQS, DM
0.4V
Maximum overshoot area above VDDQ
DDR3-1333
0.15V-ns
DDR3-1066
DDR3-800
0.19 V-ns
0.25V-ns
Maximum undershoot area below VSSQ
DDR3-1333
0.15V-ns
DDR3-1066
DDR3-800
-ns
Maximum ame
Ovoot area
VDD, VDDQ
Volts (V)
VSS, VSSQ
Undershoot are
Time (ns)
Overshoot/Undershoot Definition
Preliminary Data Sheet E0966E60 (Ver. 6.0)
13
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Output Driver Impedance
Assuming RZQ will be 240Ω (nom), DDR3 SDRAM data output driver impedance will be RON = RZQ/7 (nom.)
RON will be achieved by the DDR3 SDRAM after proper I/O calibration. Tolerance and linearity requirements are
referred to the Output Driver DC Electrical Characteristics table.
A funcnal representation of the output buffer is shown in the figure Output Driver: Definition of Voltages and
Cur.
is definby the value of the external reference resistor RZQ as follows:
RO0 = RZQ / 6
• RON3RZQ / 7
e individual ppull-down resistors (RONPu and RONPd) are defined as follows:
Parameter
Symbol
RONPu
Definition
VDDQ − VOUT
Conditions
Output drive
RONPd is turned off
⏐IOUT⏐
VOUT
⏐IOUT⏐
Output driver pull-dmpedanc
RONPd
RONPu is turned off
Chip in Drive Mode
Output Driver
VDDQ
To
other
circu
lik
RCV,
...
DQ
IOut
RONPd
IPd
VOut
VSSQ
Output Driver: Definition of VCurrents
Preliminary Data Sheet E0966E60 (Ver. 6.0)
14
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Output Driver DC Electrical Characteristics
(RZQ = 240Ω, entire operating temperature range; after proper ZQ calibration)
RONnom Resistor
VOUT
min.
nom.
max.
Unit
Notes
1, 2, 3
VOL (DC)
VOM (DC)
VOH (DC)
VOL (DC)
VOM (DC)
VOH (DC)
VOL (DC)
VOM (DC)
VOH (DC)
VOL (DC)
VOM (DC)
VOH (DC)
0.6
0.9
0.9
0.9
0.9
0.6
0.6
0.9
0.9
0.9
0.9
0.6
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.4
1.4
1.1
1.1
1.1
1.1
1.4
1.4
1.1
1.1
40Ω
RON40Pd
R40Pu
RON34Pd
RZQ/6
RZQ/6
RZQ/7
1, 2, 3
1, 2, 3
34Ω
RZQ/7
%
1, 2, 3
1, 2, 4
Mismatch bpull do, MMPuPd
VOM (DC)
−10
10
Notes: 1. The limits specified after calibration with stable voltage and temperature.
For the behavior he tolerance limits if temperature or voltage changes after calibration, see following
section on voland temperature sensitivity.
2. The tolerance its are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
3. Pull-down and pup output driver impences are recommended to be calibrated at 0.5 × VDDQ. Other
calibration schemes ay be used to e the linearity spec shown above, e.g. calibration at 0.2 ×
VDDQ and 0.8 × VDDQ.
4. Measurement definition for mism-up and pull-down, MMPuPd:
Measure RONPu and RONPdth at 0Q:
RONPu -RONPd
MMPuPd =
× 100
RONnom
Output Driver Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, he tolerans widen according to the table Output Driver
Sensitivity Definition and Output Driver Voltage and Temperatu.
ΔT = T − T (@calibration); ΔV= VDDQ − VDDQ (@calibration)Q
Note: dRONdT and dRONdV are not subject to production test but are verifieign acharacterization.
[Output Driver Sensitivity Definition]
min
max
unit
RONPu@VOH (DC) 0.6 − dRONdTH × |ΔT| − dRONdVH × |ΔV|
1.1 + dRONdTΔT| + ddVH × |ΔV|
1.1 + dRONdTM × |ΔTRONdVM |ΔV|
1.1 + dRONdTL × |ΔTdRONd|ΔV|
RZQ/7
RZQ/7
RZQ/7
RON@ VOM (DC)
RONPd@VOL (DC)
0.9 − dRONdTM × |ΔT| − dRONdVM × |ΔV|
0.6 − dRONdTL × |ΔT| − dRONdVL × |ΔV|
[Output Driver Voltage and Temperature Sensitivity]
min.
0
max.
Unit
dRONdTM
dRONdVM
dRONdTL
dRONdVL
dRONdTH
dRONdVH
1.5
%/°C
%/mV
%/°C
%/mV
%/°C
%/mV
0
0.15
1.5
0
0
TBD
1.5
0
0
TBD
Preliminary Data Sheet E0966E60 (Ver. 6.0)
15
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
On-Die Termination (ODT) Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of the MR1 Register.
ODT is applied to the DQ, DM, DQS, /DQS and TDQS, /TDQS (×8 devices only) pins.
A functional representation of the on-die termination is shown in the figure On-Die Termination: Definition of Voltages
and Currents.
The indual pull-up and pull-down resistors (RTTPu and RTTPd) are defined as follows:
eter
Symbol
RTTPu
Definition
Conditions
VDDQ − VOUT
⏐IOUT⏐
ODT puresistance
RTTPd is turned off
VOUT
⏐IOUT⏐
pull-down rTTPd
RTTPu is turned off
Chip in Termination Mode
ODT
VDDQ
IPu
I
Out = IPd - IPu
To
RTTPu
other
circuitry
like
RCV,
...
DQ
IOut
VOut
VSSQ
On-Die Termination: Definitif Voltages and Currents
Assuming RZQ will be 240Ω (nom), the value of the tination resistor can be set via MRS command to RTT60 =
RZQ/4 (nom) or RTT120 = RZQ/2 (nom).
RTT60 or RTT120 will be achieved by the DDR3 SDRAer IO calibration has been performed.
Tolerances requirements are referred to the ODT DC Electricacs table.
Measurement Definition for RTT
Apply VIH (AC) to pin under test and measure current I(VIH(AC)), then aptn under test and measure
current I(VIL(AC)) respectively.
VIH(AC) − VIL(AC)
RTT =
I(VIH(AC)) − I(VIL(AC))
Measurement Definition for ΔVM
Measure voltage (VM) at test pin (midpoint) with no load.
⎛ 2× VM
ΔVM = ⎜
⎞
-1⎟ ×100
⎜
⎟
VDDQ
⎝
⎠
Preliminary Data Sheet E0966E60 (Ver. 6.0)
16
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
ODT DC Electrical Characteristics
(RZQ = 240Ω, entire operating temperature range; after proper ZQ calibration)
MR1
[A9, A6, A2] RTT
Resistor
VOUT
min.
nom.
max.
Unit
Notes
VOL (DC)
VOM (DC)
VOH (DC)
0.6
0.9
0.9
1.0
1.0
1.0
1.1
1.1
1.4
[0, 1, 0]
120Ω RTT120Pd240
RZQ
1, 2, 3, 4
VOL (DC)
VOM (DC)
VOH (DC)
0.9
0.9
0.6
1.0
1.0
1.0
1.4
1.1
1.1
RTT120Pu240
0
RZQ
1, 2, 3, 4
VIL (AC) to VIH (AC)
0.9
1.0
1.6
RZQ/2 1, 2, 5
VOL (DC)
VOM (DC)
VOH (DC)
VOL (DC)
VOM (DC)
VOH (DC)
0.6
0.9
0.9
0.9
0.9
0.6
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.4
1.4
1.1
1.1
[0, 0, 1]
[0, 1.1]
[1, 0, 1]
[1, 0, 0]
40Ω
30Ω
20Ω
0
RZQ/2 1, 2, 3, 4
Pu120
RTT60
RZQ/2 1, 2, 3, 4
RZQ/4 1, 2, 5
VIL (AC) to VIH (AC)
0.9
1.0
1.6
VOL (DC)
VOM (DC)
VOH (DC)
VOL (DC)
VOM (D
VOH )
0.6
0.9
0.9
0.9
0.9
0.6
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.4
1.4
1.1
1.1
RTT40P0
RZQ/3 1, 2, 3, 4
RTT40Pu80
RTT40
RZQ/3 1, 2, 3, 4
RZQ/6 1, 2, 5
VIL C) to VI
0.9
1.0
1.6
VOL (DC)
VOM (DC)
VOH (DC)
VOL (DC)
VOM (DC)
VOH (DC)
6
0.9
0.9
0.9
0
1.0
1.0
1.0
1.0
.0
1.1
1.1
1.4
1.4
1.1
1.1
RTT30Pd60
RZQ/4 1, 2, 3, 4
RTT30Pu60
RTT30
RZQ/4 1, 2, 3, 4
RZQ/8 1, 2, 5
VIL (AC) to VIH (AC)
0
1.6
VOL (DC)
VOM (DC)
VOH (DC)
VOL (DC)
VOM (DC)
VOH (DC)
0.6
0.9
0.9
0.9
0.9
0.6
1.0
1.
1.
1.0
1.1
1
4
1.4
1.1
RTT20Pd40
RZQ/6 1, 2, 3, 4
RTT20Pu40
RTT20
RZQ/6 1, 2, 3, 4
RZQ/12 1, 2, 5
VIL (AC) to VIH (AC)
0.9
1.0
.6
5
Deviation of VM w.r.t. VDDQ/2, ΔVM
−5
%
1, 2, 5, 6
Notes: 1. The tolerance limits are specified after calibration with stable voltage and tempee.
For the behavior of the tolerance limits if temperature or voltage changes after calibrn, see owing
section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ VSS.
3. Pull-down and pull-up output resistors are recommended to be calibrated at 0.5 × VDDQ. Other calibon
schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 × VDDQ d 0.8
× VDDQ.
4. Not a specification requirement, but a design guide line.
5. Measurement Definition for RTT:
Apply VIH (AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test
and measure current I(VIL(AC)) respectively.
VIH(AC) − VIL(AC)
RTT =
I(VIH(AC)) − I(VIL(AC))
Preliminary Data Sheet E0966E60 (Ver. 6.0)
17
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
6. Measurement Definition for VM and ΔVM:
Measure voltage (VM) at test pin (midpoint) with no load:
⎛ 2× VM
ΔVM = ⎜
⎞
-1⎟ ×100
⎜
⎟
VDDQ
⎝
⎠
ODT Temperature and Voltage Sensitivity
If temature and/or voltage change after calibration, the tolerance limits widen according to the table ODT
Sentefinition and ODT Voltage and Temperature Sensitivity.
ΔT − T (alibration); ΔV= VDDQ − VDDQ (@calibration); VDD = VDDQ
Note: dRdT and dRTTdV are not subject to production test but are verified by design and characterization.
[ODSensi
max.
Unit
RTT
|ΔT| - RTTdV × |ΔV|
1.6 + dRTTdT×|ΔT| + dRTTdV × |ΔV|
RZQ/2, 4, 6, 8, 12
[ODT Voltage and Tempere Sensitivity]
min.
max.
1.5
Unit
dRTTdT
dRTTdV
0
%/°C
%/mV
.15
ODT Timing Definitions
Test Load for ODT Timings
Different than for timing measurements, the reference loDT timings are defined in ODT Timing Reference
Load.
VDDQ
DUT
DQ, DM
CK, /CK
DQS, /DQS
TDQS, /TDQS
RT
= 25
VSSQ
Timing Reference Points
ODT Timing Reference Load
Preliminary Data Sheet E0966E60 (Ver. 6.0)
18
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
ODT Measurement Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in the following table and subsequent figures.
Symbol
Begin Point Definition
End Point Definition
Figure
Rising edge of CK - /CK defined by the end
point of ODTLon
tAON
Extrapolated point at VSSQ
Figure a)
Rising edge of CK - /CK with ODT being first
registered high
tAON
Extrapolated point at VSSQ
Figure b)
Rising edge of CK - /CK defined by the end
point of ODTLoff
End point: Extrapolated point at VRTT_Nom Figure c)
End point: Extrapolated point at VRTT_Nom Figure d)
Rising edge of CK - /CK with ODT being first
regered low
tAOFPD
tA
of CK - /CK defined by the end
cnw, ODTLcwn4 or ODTLcwn8
End point: Extrapolated point at VRTT_WR
Figure e)
and VRTT_Nom respectively
Reference T TimiMeasurements
Measurement reference settare provided in the following Table.
Measured Parameter RTTm Setting
RTT_WR Setting
VSW1 [V]
VSW2 [V]
0.10
Note
tAON
RZQ
N/A
N/A
N/A
N
/A
N/A
N/A
N/A
RZQ/2
0.05
RZQ/12
RZQ/4
0.10
0.20
tAONPD
tAOF
0.05
0.10
RZQ/12
RZQ/4
0.10
0.20
0.05
0.10
RZQ/12
RZQ/4
0.10
0.20
tAOFPD
tADC
5
0.10
RZQ/12
RZQ/12
0.10
0.20
0.
0.30
Begin point: Rising edge of CK - /CK
defined by the end point of ODTLon
CK
VTT
/CK
tAON
tSW2
tSW1
DQ, DM
DQS, /DQS
TDQS, /TDQS
VSW2
VSW1
VSSQ
VSSQ
End point: Extrapolated point at VSSQ
a) Definition of tAON
Preliminary Data Sheet E0966E60 (Ver. 6.0)
19
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Begin point: Rising edge of CK - /CK with
ODT being first registered high
CK
VTT
/CK
tAONPD
tSW2
tSW1
DQ, DM
DQS
DQS
VSW2
VSW1
VSSQ
VSSQ
End point: Extrapolated point at VSSQ
b) Definition of tAONPD
Begin point: Rising edge of CK - /CK
defined by the end point of ODTLoff
CK
VTT
/CK
tAOF
End poitrapolated point at VRTT_Nom
VRTT_Nom
VSW2
t
tSW1
DQ, DM
DQS, /DQS
TDQS, /TDQS
VSW1
VSSQ
c) Definition of tAO
Begin point: Rising edge of CK - /CK with
ODT being first registered low
CK
T
/CK
tAOFPD
End point: Extrapolated point at VRTT_Nom
VRTT_Nom
VSW2
tSW2
tSW1
DQ, DM
DQS, /DQS
TDQS, /TDQS
VSW1
VSSQ
d) Definition of tAOFPD
Preliminary Data Sheet E0966E60 (Ver. 6.0)
20
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Begin point: Rising edge of CK - /CK
defined by the end point of ODTLcnw
Begin point: Rising edge of CK - /CK defined by
the end point of ODTLcwn4 or ODTLcwn8
CK
VTT
K
tADC
tADC
VRTT_Nom
TSW21
VRTT_Nom
point:
lated
RTT_Nom
DQ, DM
DQS, /
TDQ
TSW22
TSW12
TSW11
VSW1
VSW2
VRTT_Wr
End point: Extrapolated point at VRTT_Wr
VSSQ
e) Definition of tADC
Preliminary Data Sheet E0966E60 (Ver. 6.0)
21
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
IDD Measurement Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V 0.075V)
Within the tables about IDD measurement conditions, the following definitions are used:
• L: VIN ≤ VIL (AC)(max.)
• H: VIN ≥ VIH (AC)(min.);
• STA: inputs are stable at H or L level
• FTI: inputs are VREF = VDDQ / 2
TCHINDescribed in the following Definition of SWITCHING table.
• N/A: ot available
Definition of SWITCHING]
Sals
Definitions
ot otherwise mentioned the inputs are stable at H or L during 4 clocks and change then to the
osite value
Address (ro
g. Ax Ax Ax Ax /Ax /Ax /Ax /Ax Ax Ax Ax Ax .....
Please each IDDx definition for details
If nerwise mentioned the bank addresses should be switched like the row/column
esses - please see each IDDx definition for details
Bank address
efine D = {/CS, /RAS, /CAS, /WE } := {H, L, L, L}
Define /D = {/CS, /RAS, /CAS, /WE } := {H, H, H, H}
Command
DeCommand Backgroattern = D D /D /D D D /D /D D D /D /D ...
(/CS, /RAS, /CAS, /WE)
If other commands . ACT for IDD0 or Read for IDD4R) the Background Pattern
Command is subed tive /CS, /RAS, /CAS, /WE levels of the necessary command.
See each IDDx finition foand figures of Example of IDD1, IDD2N/IDD3N, IDD4R.
Data DQ is changing between H and L every other data transfer (once per clock) for DQ signals,
which means that data DQ is stable g one clock;
Data (DQ)
see each IDDx definition for exces frhis rule and for further details.
See figures of Example of IDDD2N/IDD3N, IDD4R.
Data Masking (DM)
NO Switching; DM must be driven L all the
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR3-1333
DDR3-1066
6-6-6
6
DR3-80
5-5-5
5
Parameter
8-8-8
8
9-9-9
9
7-7-7
7
8-8-8
8
6-6-6
6
Unit
tCK
ns
CL (IDD)
tCK min.(IDD)
tRCD min. (IDD)
tRC min. (IDD)
tRAS min.(IDD)
tRP min. (IDD)
tFAW (IDD)-×4/×8
tFAW (IDD)-×16
tRRD (IDD)-×4/×8
tRRD (IDD)-×16
tRFC (IDD)
1.5
12
1.5
13.5
49.5
36
1.875
11.25
48.75
37.5
11.25
37.5
50
1.875
13.13
50.63
37.5
13.13
37.5
50
1.875
15
2.5
.5
15
12.5
50
n
48
52.50
37.5
15
52
37.5
15
ns
36
37.5
12.5
40
ns
12
13.5
30
ns
30
37.5
50
40
45
45
50
50
ns
6.0
7.5
90
6.0
7.5
90
7.5
7.5
7.5
10
10
ns
10
10
10
10
10
ns
90
90
90
90
90
ns
Preliminary Data Sheet E0966E60 (Ver. 6.0)
22
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
The following conditions apply:
• IDD specifications are tested after the device is properly initialized.
• Input slew rate is specified by AC Parametric test conditions.
• IDD parameters are specified with ODT and output buffer disabled (MR1 bit A12 = 1).
IDD Measurement Conditions for IDD0 and IDD1
Symbol
IDD0
IDD1
Operating Current 1
-> One Bank Activate
-> Read
Operating Current 0
-> One Bank Activate
-> Precharge
-> Precharge
easurement Condi
TiDiagra
Figure IDD1 Example
CKE
H
External Clo
tCK
on
tCK mD)
tRn (IDD)
AS min (IDD)
N/A
tCK min (IDD)
tRC min (IDD)
tRAS min (IDD)
tRCD min (IDD)
N/A
tRC
tRAS
tRCD
tRRD
CL
N
N/A
CL(IDD)
AL
N/A
0
/CS
H between. Actand ommands H between Activate, Read and Precharge
SWITCHING (see Definition of SWITCHING
table); only exceptions are Activate a
SWITCHING (see Definition of SWITCHING
table); only exceptions are Activate, Read and
Precharge commands; example of tern: Precharge commands; example of IDD1 pattern:
A0 D /D /D D D /D /D D D /D/D /D P0 A0 D /D /D D R0 /D /D D D /D/D D D /D P0
(DDR3-800: tRAS = 37.5ns been (A)ctivate (DDR3-800 -555: tRCD = 12.5ns between
Command inputs
(/CS, /RAS, /CAS, /WE)
and (P)recharge to bank 0;
tivate and (R)ead to bank 0;
Definition of D and /D: see Definition of
SWITCHING table
tion of D and /D: see Definition of
TCHING table
Row addresses SWITCHING (see Definition oRow aSWITHING (see Definition of
SWITCHING table); A10 must be L all the time! SWe)must be L all the time!
Row, column addresses
Bank addresses
Bank address is fixed (bank 0)
Bad (bank 0)
Reaut data witches every clock,
which methat Rdata is stable during one
clock cycle.
SWITCHING (see Definition of SWITCHING
table)
Data I/O
To achieve IOU0mA the ut buffer should
be switched off MR1 bi2 set to “1”.
When there is no read burst frRAM the
DQ I/O should be FLOTING.
Output Buffer DQ, DQS
/ MR1 bit A12
off / 1
off / 1
disabled
/ [0,0]
disabled
/ [0,0]
ODT
/ MR1 bits [A6, A2]
Burst length
Active banks
Idle banks
N/A
8 fixed / MR0 bits [A1, A0] = {0,0}
one
one
ACT-PRE loop
ACT-READ-PRE loop
all other
all other
Precharge Power-down
Mode / MR0 bit A12
N/A
N/A
Preliminary Data Sheet E0966E60 (Ver. 6.0)
23
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12
T13
T14 T15 T16
T17
T18
CK
/CK
BA 0 to 2
0
Address
3FF
000
000
3FF
0 0 0
3FF
11
(A0 to
ess
A10)
Add
(A11 to A
11
00
00
00
0 0
/CS
/RAS
/CAS
/WE
Command
DQ
ACT
D
/D
D
READ
/D
D
D
/D
0
/D
1
D
0
D
/D
PRE
D
D
/D
/D
0
1
0
1
1
asurement loop
DM
IDD1 Example* (DDR3-0-555, 512Mb ×8)
Note: Data DQ is shown but the output buffer should bitcheoff (per MR1 bit A12 = 1) to achieve IOUT = 0mA.
Address inputs are split into 3 parts.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
24
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
IDD Measurement Conditions for IDD2N, IDD2P (1), IDD2P (0) and IDD2Q
Symbol
IDD2N
IDD2P (1)*1
IDD2P (0)*1
IDD2Q
Precharge power-down Precharge power-down
current
current
Precharge standby
current
Precharge quiet
standby current
Name
(fast exit
(slow exit
MR0 bit A12= 1)
MR0 bit A12= 0)
Meaent Condition
g DiagrExample
Figure IDD2N/IDD3N
Example
⎯
⎯
⎯
CKE
H
L
L
H
External Clock
t
on
on
on
on
tCK min (IDD)
tCK min (IDD)
N/A
tCK min (IDD)
N/A
tCK min (IDD)
tRC
/A
N/A
N/A
N
/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
H
tRAS
tRCD
tRRD
CL
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
AL
N/A
N/A
/CS
SABLE
STABLE
Bank address,
STCHING (see
row address and command
inputs
Definition of SWITCH
table)
STABLE
STABLE
Data inputs
SWITCHING
G
FLOATING
off / 1
FLOATING
off / 1
Output buffer DQ, DQS
/ MR1 bit A12
off / 1
off / 1
disabled
/ [0,0]
disable
/ [0,
disabled
/ [0,0]
disabled
/ [0,0]
ODT
/ MR1 bits [A6, A2]
Burst length
Active banks
Idle banks
N/A
none
all
N/A
none
all
N/A
ne
N/A
none
all
Slow e0
Fast exit / 1
Sl
Precharge Power-down
Mode / MR0 bit A12
N/A
N/A
(any valid command
after tXP*2)
(
satisfy
t
Notes: 1. In DDR3 the MR0 bit A12 defines DLL-on/off behaviors only for prarge pr-down. There are two
different precharge power-down states possible: one with DLL-on (fast ebit A12 = 1) and one with
DLL-off (slow exit, bit A12 = 0).
2. Because it is an exit after precharge power-down the valid commands arbanctivate (ACT), auto-
refresh (REF), mode register set (MRS), self-refresh (SELF).
Preliminary Data Sheet E0966E60 (Ver. 6.0)
25
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK
/CK
BA
0 to 2
7
0
0
Address
(A0 to A12)
1FFF
0 0 0 0
0000
H
/CS
/RAS
Comm
/D
/D
D
D
/D
/D
D
D
/D
/D
D
DQ
FF 00 00 FF FF 000 00 FF FF 00 00 FF FF 00 00 FF FF 00 00
0 to 7
2N/ IDD3N measurement loop
DM
IDD2N/IDD3N Example (D-800-555, 512Mb ×8)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
26
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
IDD Measurement Conditions for IDD3N, IDD3P (fast exit)
Symbol
IDD3N
IDD3P (1)
Active power-down current*
(always fast exit)
Name
Active standby current
Measurement Condition
Timinagram Example
Figure IDD2N/IDD3N Example
⎯
C
H
L
al Clock
tCK
on
on
tCK min (IDD)
tCK min (IDD)
N/A
RC
N/A
N/A
N/A
N/A
N/A
N/A
H
t
tRCD
tRRD
CL
N/A
N/A
N/A
N/A
AL
N/A
/CS
STABLE
SWITCHIN
(see Definition of SWITCHING table)
Address and command inp
Data inputs
STABLE
FLOATING
off / 1
SWITCHIN
(see DeWITCHING table)
Output buffer DQ, DQS
/ MR1 bit A12
off
abled
/ [0,0]
disabled
/ [0,0]
ODT
/ MR1 bits [A6, A2]
Burst length
Active banks
Idle banks
N/A
none
all
N/A
none
all
Precharge Power-down
Mode / MR0 bit A12
N/A (Active Power-down
N/A
Mode is always “Fast Exit” with DLL-on)
Note: DDR3 will offer only one active power-down mode with ast exit). MR0 bit A12 will not be used for
active power-down. Instead bit A12 will be used to swittweeifferenprecharge power-down
modes.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
27
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
IDD Measurement Conditions for IDD4R, IDD4W and IDD7
Symbol
IDD4R
IDD4W
IDD7
Operating current
(Burst read operating)
Operating current
(Burst write operating)
Name
All bank interleave read current
Measurement Condition
Timing gram Example
IDD4R Example
⎯
⎯
CK
H
H
H
al Clock
tCK
on
on
on
tCK min (IDD)
tCK min (IDD)
tCK min (IDD)
tRC min. (IDD)
tRAS min. (IDD)
tRCD min. (IDD)
tRRD min. (IDD)
CL (IDD)
C
N/A
N/A
tR
tRCD
tRRD
CL
/A
N/A
N/A
A
N/A
CL (ID
CL (IDD)
AL
0
0
tRCD min. − 1tCK
H between valid commands
/CS
etween valid commands
H between valid commands
SWITCHING (see Definition of
WITCHING table);
SWITCHING (see Definition of
SWITCHING table);
onxceptions are read
comands -> IDD4R pa
only exceptions are write
commands -> IDD4W pattern:
Command inputs
For patterns see pattern in IDD7
Timing Patterns section
R0 D /D /D R1 D /D /D /D /D W1 D /D /D W2 D /D
/D R3 D /D /D R4
(/CS, /RAS, /CAS, /WE)
W3 D /D /D W4...
Rx = Read from k x;
Definition of D and /D: see
= Write to bank x;
Definition of D and /D: see
Definition of SWITCHING table Defion of SWITCHING table
Column addresses SWITCHING dresses SWITCHING
(see Definition of SWITCHING
table);
ee Defnition of SWITCHING
table);
Row, column addresses
Bank addresses
STABLE during DESELECTs
A10 must be L all the time!
A10 muhe time!
bank address cycling
(0 -> 1 -> 2 -> 3 ...), see pattern
in IDD7 Timing Patterns section
bank address cycling
(0 -> 1 -> 2 -> 3 ...)
bank
(0 ->
Seamless read data burst (BL8):
output data switches every
clock, which means that Read
data is stable during one clock
cycle.
Rdata (BL8): output data
Seamless write daches every clock, which
input data switcheeans that Read data is stable
which means that w
stable during one clock c
durinone clock cycle.
Data I/O
achieve IOUT = 0mA the
utput buffould be switched
ff by Mit A12 set to “1”.
To achieve IOUT = 0mA the
output buffer should be switched
off by MR1 bit A12 set to “1”.
DM is low all the time
Output Buffer DQ, DQS
/ MR1 bit A12
off / 1
off / 1
off /
disabled
/ [0,0]
disabled
/ [0,0]
disabled
/ [0,0]
ODT
/ MR1 bits [A6, A2]
8 fixed / MR0 bits [A1, A0] =
{0,0}
8 fixed / MR0 bi1, A0]
{0,0}
Burst length
8 fixed / MR0 [A1, A0] = {0,0}
Active banks
Idle banks
all
all
all, rotational
none
none
none
Precharge Power-down
Mode / MR0 bit A12
N/A
N/A
N/A
Preliminary Data Sheet E0966E60 (Ver. 6.0)
28
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12
CK
/CK
BA
1
2
3
0
0 to 2
ddress
(AA9)
3FF
000
3FF
0 0 0
Address
(A10)
L
Addr
(A11 t
11
00
11
0 0
/RAS
/CAS
/WE
Command
0 to 2
READ
D
/D
/D
READ
D
/D
/D
READ
D
/D
/D
READ
D
DQ
00 00 FF F 00 00 FF FF 00 00 FF FF 00 00 FF FF
0 to 7
Start of measurement loop
DM
IDD4R Example* (DDR3-800-5512M
Note: Data DQ is shown but the output buffer should be switched off (pe1) to achieve IOUT = 0mA.
Address inputs are split into 3 parts.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
29
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
IDD7 Timing Patterns
The detailed timings are shown in the IDD7 Timing Patterns for 8 Banks tables.
tFAW tFAW tRRD tRRD
Speed bins
Bin
Organization (ns)
(tCK) (ns)
(tCK) Timing Patterns
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4
RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D
DDR3-800
all
×4/×8
×16
40
16
10
4
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
D A4 RA4 D D A5 RA5 D D A6 RA6 DD A7 RA7 D D D D
D D
all
all
all
50
20
10
4
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD D D D
D A4 RA4 D D A5 RA5 D D A6 RA6 DD A7 RA7 D D D D
D D
DDR3-6
DDR3-1333
×4/×8
37.5
50
20
27
20
30
7.5
10
6
4
6
4
5
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D DD D A3
RA3 D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6
RA6 D D D D A7 RA7 D D D DD D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
D A4 RA4 D D A5 RA5 D D A6 RA6 DD A7 RA7 D D D D
D D
×16
30
A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D
D D D D D D D D D D D A4 RA4 D D DA5 RA5 D D D A6
RA6 D D D A7 RA7 D D D DD D D D D D D D D
45
7.5
Remark: Ax = Active cmand for bank x.
RAx = Read with to precharge command from bank x.
ex. RA0 = READA mmand from ban
Notes: 1. All banks are being interleaved at m(IDD) without violating tRRD (IDD) and tFAW (IDD) using
a burst length = 8.
2. Control and address bus inpue STng DESELECTs.
3. IOUT = 0mA.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
30
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
IDD Measurement Conditions for IDD5B
Symbol
IDD5B
Name
Burst refresh current
Measurement Condition
Timing Diagram Example
CKE
H
nal Clo
on
CK
tCK min. (IDD)
tRC
N/A
AS
N/A
tRC
N/A
tRRD
N/A
tRFC
tRFC min. (IDD)
N/A
CL
AL
N/A
/CS
H between valid commands
SWITCHING
SING
Address and command inpu
Data inputs
Output buffer DQ, DQS
/ MR1 bit A12
d
/ [0,0
ODT
/ MR1 bits [A6, A2]
Burst length
Active banks
Idle banks
N/A
Refresh cand ery tRFC = tRFC (min.)
none
Precharge Power-down
Mode / MR0 bit A12
N/A
Preliminary Data Sheet E0966E60 (Ver. 6.0)
31
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
IDD Measurement Conditions for IDD6 and IDD6ET
Symbol
IDD6
IDD6ET
Self-refresh current extended temperature
range
Self-refresh current normal temperature range
Name
TC = 0 to +85°C
TC = 0 to +95°C
Measurement Condition
Tem
TC = +85°C
TC = +95°C
Aelf-refre(ASR) /
R2 A6
Disabled / 0
Disabled / 0
Self-Refh Temperature Range
SRT) / MR2 bit A7
Disabled / 0
Enabled / 1
C
L
L
External Clo
tCK
OFF; CK and /CK at L
OFF; CK and /CK at L
N/A
N/A
tRC
N
N/A
tRAS
tRCD
tRRD
CL
A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
AL
/A
N/A
/CS
FLOATING
FLOATING
Command inputs
/RAS, /CAS, /WE)
FLOATIN
FLOATING
Row, column addresses
Bank addresses
Data I/O
FLOATING
FLOATING
FLOATING
FLOATING
FLOATING
FLOATING
Output Buffer DQ, DQS
/ MR1 bit A12
off / 1
off / 1
disabled
/ [0,0]
sabled
[0,0]
ODT
/ MR1 bits [A6, A2]
Burst length
Active banks
Idle banks
8 fixed / MR0 bits [A1, A0] = {0,0}
all during self-refresh actions
all between self-refresh actions
8 fi0 bits A1, A0] = {0,0}
-sh actions
lf-refresh actions
Precharge Power-down
Mode / MR0 bit A12
N/A
N/A
IDD6 Current Definition
Parameter
Symbol
Parameter/Condition
CKE ≤ 0.2V; external clock off, CK and /CK at 0V; Other conand adds
inputs are FLOATING; Data Bus inputs are FLOATING, PASdisabled.
Applicable for MR2 settings A6 = 0 and A7 = 0.
Normal temperature range self-
refresh current
IDD6
CKE ≤ 0.2V; external clock off, CK and /CK at 0V; Other control and addre
inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled.
Applicable for MR2 settings A6 = 0 and A7 = 1
Extended temperature range
self-refresh current
IDD6ET
IDD6TC
CKE ≤ 0.2V; external clock off, CK and /CK at 0V; Other control and address
inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled.
Applicable when ASR is enabled by MR2 settings A6 = 1 and A7 = 0.
Auto self-refresh current
.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
32
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Electrical Specifications
DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V 0.075V)
× 4
× 8
× 16
Parameter
Symbol
IDD0
Data rate (Mbps) max.
max.
max.
Unit
mA
Notes
1333
1066
800
125
110
105
125
110
105
145
125
120
Operrrent
(ARE)
1333
1066
800
140
135
125
140
135
125
175
165
150
peracurrent
(ACT-REPRE)
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
m
mA
1333
1066
800
45
40
35
45
40
35
45
40
35
2PF
2PS
ID
Fast PD Exit
Slow PD Exit
Precharge p
standby cur
1333
1066
800
12
11
10
12
11
10
12
11
10
1333
1066
800
75
65
55
75
65
55
75
65
55
Precharge quiet standby
current
1333
1066
800
80
70
0
80
70
60
80
70
60
Precharge standby current IN
1333
1066
800
50
45
35
50
45
35
Active power-down current
IDD3P
(Always fast exit)
13
1066
800
85
70
100
85
70
110
95
80
Active standby current
IDD3N
IDD4R
IDD4W
IDD5B
IDD7R
1333
1066
800
190
1
5
10
175
140
325
270
220
Operating current
(Burst read operating)
1333
1066
800
205
170
135
315
260
205
Operating current
(Burst write operating)
1333
1066
800
305
295
280
2
280
305
Burst refresh current
1333
1066
800
350
290
265
365
300
270
3
All bank interleave read
current
Self-Refresh Current (TC = 0°C to +85°C, VDD, VDDQ = 1.5V 0.075V)
× 4
× 8
× 16
Parameter
Symbol
IDD6S
Grade max.
max.
max.
Unit
mA
Notes
Self-refresh current
normal temperature range
8
8
8
Self-refresh current
extended temperature
range
IDD6ET
IDD6TC
16
16
16
16
16
16
mA
mA
Auto self-refresh current
Preliminary Data Sheet E0966E60 (Ver. 6.0)
33
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V 0.075V)
Parameter
Symbol
⏐ILI⏐
Value
TBD
TBD
Unit
μA
Notes
Input leakage current
Output leakage current
VDD ≥ VIN ≥ VSS
VDDQ ≥ VOUT ≥ VSS
⏐ILO⏐
μA
Pin pacnce (TC = 25°C, VDD, VDDQ = 1.5V 0.075V)
raer
Symbol
CCK
Pins
min.
TBD
TBD
max.
Unit
pF
Notes
1, 2, 4
1, 2, 4
Input pin pacitance, CK and /CK
DDR3-1333
CK, /CK
TBD
1.6
R3-1066,
CCK
pF
Delta input pnd
/CK
CDCK
TBD
TBD
pF
1, 2, 3
DDR3-133
DDR3-1066
CK
0
0.15
TBD
1.5
pF
pF
pF
pF
1, 2, 3
Input pin capacitanntrol pin
DDR3-1333
CIN_CTRL
CIN_CTRL
CIN_ADD_CMD
/CS, CKE, ODT
TBD
TBD
TBD
1
1
1
DDR3-1066, 800
Input pin capacitance, addreand
command pins
/RAS, /CAS, /WE,
ddress
1.5
Delta input pin capacitance, contro
pins
CDIN_CTRL
CDIN_L
CDIN_ADD_CMD
CDIN_ADD_CMD
CIO
E, ODT
TBD
−0.5
TBD
−0.5
TBD
0.3
pF
pF
pF
pF
pF
1, 5
1, 5
1, 6
1, 6
1, 7
DDR3-1333
DDR3-1066, 800
Delta input pin capacitance, address
and command pins
DDR3-1333
/RAS, /CAS, /WE,
Addres
TBD
0.5
DDR3-1066, 800
D, DQS, /DQ
TDQS, /TD
DM
Input/output pin capacitance
DDR3-1333
2.5
DDR3-1066, 800
CIO
3.0
pF
pF
pF
1, 7
Delta input/output pin capacitance
DDR3-1333
CDIO
CDIO
TBD
TBD
1, 8, 9
1, 8, 9
DDR3-1066, 800
−
Notes: 1. VDD, VDDQ, VSS, VSSQ applied and all other pins (except the est) floting.
VDD = VDDQ =1.5V, VBIAS=VDD/2
2. This parameter is Non-stacked (monolith) DDR3 SDRAM spec. Stacked des pin parsitics are TBD.
3. Absolute value of CCK(CK-pin) − CCK(/CK-pin)
4. CCK (min.) will be equal to CIN (min.)
5. CDIN_CTRL = CIN_CTRL − 0.5 × (CCK(CK-pin) + CCK(/CK-pin))
6. CDIN_ADD_CMD = CIN_ADD_CMD − 0.5 × (CCK(CK-pin) + CCK(/CK-pin))
7. TDQS/TDQS are not necessarily input function, but since TDQS is sharing DM pin nd the para
characterization of TDQS/TDQS should be close as much as possible, CIO and CDIO uiremes
applied.
8. DQ should be in high impedance state.
9. CDIO = CIO (DQ) −0.5 × (CIO(DQS-pin) + CIO(/DQS-pin)).
Preliminary Data Sheet E0966E60 (Ver. 6.0)
34
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Standard Speed Bins
[DDR3-1333 Speed Bins]
Speed Bin
DDR3-1333G
DDR3-1333H
9-9-9
CL-tRCD-tRP
8-8-8
/CAS write
Symb
latency
min.
max.
min.
max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCK
Notes
tA
12
20
13.5
20
CD
12
⎯
13.5
⎯
tRP
12
⎯
13.5
⎯
48.0
⎯
49.5
⎯
tRA
36
9 × tREFI
3.3
36
9 × tREFI
Reserved
Reserved
3.3
8
tCK (avg)@
6, 7
L = 5
CWL =
CW7
CW5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5, 6
CWL= 7
2.5
Reserved
Reserved
2.5
1, 2, 3, 4, 7
eserved
2.5
Reserved
3.3
4
tCK (avg)@CL=
tCK (avg)@CL=7
tCK (avg)@CL=8
1, 2, 3, 7
Reserved
Reserved
Reserved
1.875
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.875
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
< 2.5
1, 2, 3, 4, 7
4
4
1, 2, 3, 4, 7
Reserved
Reserve
1.875
d
1, 2, 3, 4
4
1, 2, 3, 7
1.5
< 1.875
Reserv
< 1
Reserved
< 1.875
Optional
Reserved
Reserved
< 1.5
Reserved
Reserved
< 1.875
Reserved
< 1.875
Optional
1, 2, 3, 4
tCK (avg)@CL=9
tCK (avg)@CL=10
Reserved
1.5
4
1, 2, 3, 4
CWL = 5, 6
CWL= 7
Reserved
1.5
d
4
1, 2, 3
5
CWL= 7
Optional
5, 6, 7, 8, 9, 10
9, 10
Supported CL settings
Supported CWL
settings
5, 6, 7
5, 6, 7
nCK
Preliminary Data Sheet E0966E60 (Ver. 6.0)
35
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
[DDR3-1066 Speed Bins]
Speed Bin
DDR3-1066E
6-6-6
DDR3-1066F
7-7-7
DDR3-1066G
8-8-8
CL-tRCD-tRP
/CAS write
Symbol
latency
min.
max.
min.
max.
min.
15
max.
Unit
ns
Notes
tAA
11.25
11.25
11.25
48.75
37.5
20
13.125
13.125
13.125
50.625
37.5
20
20
tRC
⎯
⎯
15
⎯
ns
⎯
⎯
15
⎯
ns
tRC
⎯
⎯
52.50
37.5
⎯
ns
RAS
9 × tREFI
9 × tREFI
9 × tREFI
ns
8
1, 2, 3,
4, 6
tCvg)@CL
2.5
3.3
Reserved Reserved Reserved Reserved ns
tCK (avg)@
Reserved Reserved Reserved Reserved Reserved Reserved ns
4
2.5
3.3
2.5
3.3
2.5
3.3
ns
1, 2, 3, 6
1, 2, 3, 4
4
1
< 2.5
Reserved Reserved Reserved Reserved ns
tCK (avg)@CL=7 CWL = 5
CWL =
eserved Reserved Reserved Reserved Reserved Reserved ns
1.875 < 2.5 1.875 < 2.5 Reserved Reserved ns
Reserved Reserved Reserved Reserved Reserved Reserved ns
1, 2, 3, 4
4
tCK (avg)@CL=8 CWL =
CWL = 6
875
< 2.5
875
< 2.5
1.875
6, 8
< 2.5
ns
1, 2, 3
Supported CL
settings
5, 6, 7, 8
nCK
Supported CWL
settings
5, 6
5, 6
nCK
[DDR3-800 Speed Bins]
Speed Bin
DDR3-800F
5-5-5
DDR3-800E
CL-tRCD-tRP
/CAS write
Symbol
latency
min.
12.5
12.5
12.5
50
max.
max.
0
Unit
ns
ns
ns
ns
ns
s
Notes
tAA
20
tRCD
⎯
15
tRP
⎯
15
tRC
⎯
52.5
37.5
Reserved
2.5
tRAS
37.5
2.5
9 × tREFI
3.3
9 × tRE
Resed
3.3
8
tCK (avg)@CL=5
tCK (avg)@CL=6
Supported CL settings
Supported CWL settings
CWL = 5
CWL = 5
1, 2, 3, 4
1, 2, 3
2.5
3.3
5, 6
5
6
nC
n
5
Notes: 1 The CL setting and CWL setting result in tCK (avg) (min.) and tCK (avg) (max.) rerements. W
making a selection of tCK (avg), both need to be fulfilled: Requirements from CL seas we
requirements from CWL setting.
2. tCK (avg) (min.) limits: Since /CAS latency is not purely analog - data and strobe output are synonized
by the DLL - all possible intermediate frequencies may not be guaranteed. An application should se the
next smaller JEDEC standard tCK (avg) value (2.5, 1.875, 1.5, or 1.25ns) when calculating
CL (ntCK) = tAA(ns) / tCK(avg)(ns), rounding up to the next ‘Supported CL’.
3. tCK (avg) (max.) limits: Calculate tCK (avg) + tAA (max.)/CLselected and round the resulting tCK (avg)
down to the next valid speed bin limit (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). This result is tCK (avg)
(max.) corresponding to CLselected.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
36
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a
mandatory feature.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table
DDR3-1066 Speed Bins which are not subject to production tests but verified by design/characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table
DDR3-1333 Speed Bins which is not subject to production tests but verified by design/characterization.
. EFI depends on operating case temperature (TC).
Preliminary Data Sheet E0966E60 (Ver. 6.0)
37
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V 0.075V, VSS, VSSQ = 0V)
AC Characteristics [DDR3-1333]
-DG, -DJ
1333
Data rate (Mbps)
Parame
Symbol
min.
max.
3333
Unit
ps
Notes
6
Avclocycle time
tCK (avg)
1500
m clock le time
DLL-mode)
tCK (DLL-off)
8
⎯
ns
Average high-level width
rage CK low
tCH (avg)
tCL (avg)
0.47
0.47
0.53
0.53
tCK (avg)
tCK (avg)
12 (DG)
13.5 (DJ)
Active to readelay
Precharge c
tRCD
tRP
⎯
⎯
⎯
ns
ns
ns
26
26
26
12 (DG)
13.5 (DJ)
48 (DG)
49.5 (DJ)
Active to active/ah commtime
tRC
Active to precharge comman
tRAS
tRRD
tRRD
t
36
6
9 × tREFI
ns
26
Active bank A to active bancommand period
⎯
⎯
⎯
⎯
ns
26, 27
26, 27
26, 27
26, 27
(x4/x8)
4
nCK
ns
Active bank A to active bank B comand period
(x16)
7.5
4
nCK
Four active window
(x4/x8)
tF
30
⎯
⎯
⎯
ns
ns
ps
26
(x16)
tFAW
45
26
Address and control input hold time
(VIH/VIL (DC) levels)
tIH (base)
T
16, 23
Address and control input setup time
(VIH/VIL (AC) levels)
tIS (bae)
tDH (base)
tDS (base)
TB
T
⎯
⎯
ps
ps
ps
16, 23
17, 25
17, 25
DQ and DM input hold time
(VIH/VIL (DC) levels)
DQ and DM input setup time
(VIH/VIL (AC) levels)
Control and Address input pulse width for each input tIPW
0.6
tCK (avg)
tCK (avg)
ps
DQ and DM input pulse width for each input
DQ high-impedance time
tDIPW
0.35
⎯
tHZ (DQ)
tLZ (DQ)
250
12, 13, 14
12, 13, 14
DQ low-impedance time
−500
ps
DQS, /DQS high-impedance time
(RL + BL/2 reference)
tHZ (DQS)
tLZ (DQS)
⎯
250
250
ps
12, 13, 14
DQS, /DQS low-impedance time
(RL − 1 reference)
−500
113, 14
12,
DQS, /DQS to DQ skew, per group, per access
tDQSQ
tCCD
tQH
⎯
125
⎯
p
/CAS to /CAS command delay
4
nC
DQ output hold time from DQS, /DQS
0.36
⎯
tCK (avg) 12, 1
ps 13
DQS, /DQS rising edge output access time from
rising CK, /CK
tDQSCK
tDQSS
−225
225
DQS latching rising transitions to associated clock
edges
−0.25
0.25
tCK (avg) 24
DQS falling edge hold time from rising CK
DQS falling edge setup time to rising CK
DQS input high pulse width
tDSH
0.2
0.2
0.4
0.4
⎯
tCK (avg) 24
tCK (avg) 24
tCK (avg)
tDSS
⎯
tDQSH
tDQSL
0.6
0.6
DQS input low pulse width
tCK (avg)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
38
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
-DG, -DJ
1333
Data rate (Mbps)
Parameter
Symbol
tQSH
min.
0.38
0.38
4
max.
⎯
Unit
Notes
DQS output high time
tCK (avg) 12, 13
tCK (avg) 12, 13
nCK
DQS output low time
tQSL
⎯
Mode er set command cycle time
Megisteet command update delay
tMRD
tMOD
tMOD
tRPRE
tRPST
tWPRE
tWPST
tWR
⎯
15
⎯
ns
27
27
12
⎯
nCK
Read preble
ad postamble
Wrireamb
Write posta
Write recove
0.9
0.3
0.9
0.4
15
⎯
tCK (avg) 1, 19
⎯
tCK (avg) 11, 12, 13
⎯
tCK (avg)
tCK (avg)
ns
1
⎯
1
⎯
26
WR + RU
Auto precharge ry + prrge time
tDAL
tRTW
tRTW
⎯
⎯
⎯
nCK
(tRP/tCK (avg))
Read to write command delay
(BC4MRS, BC4OTF)
RL + tCCD/2 +
2nCK − WL
RL + tCCD + 2nCK
− WL
(BL8MRS, BL8OTF)
Internal write to read command de
tW
tRTP
7.5
⎯
⎯
⎯
⎯
ns
18, 26, 27
18, 26, 27
26, 27
4
nCK
ns
Internal read to precharge command delay
7.5
4
nCK
26, 27
Minimum CKE low width for self-refresh entry to exit
timing
tCKESR
CKE (min.)+1nCK ⎯
Valid clock requirement after self-refresh entry or
power-down entry
⎯
tCKSR
tCKSRE
tCKSRX
tCKSRX
tXS
10
ns
27
27
27
27
27
27
⎯
5
nCK
ns
Valid clock requirement before self-refresh exit or
power-down exit
⎯
⎯
7.8
3.9
⎯
5
nCK
ns
Exit self-refresh to commands not requiring
a locked DLL
tRFC (min.)
tXS
5
nCK
nCK
n
Exit self-refresh to commands requiring a locked
DLL
tXSDLL
tRFC
tDLLK (min.)
Auto-refresh to active/auto-refresh command time
90
Average periodic refresh interval
(0°C ≤ TC ≤ +85°C)
tREFI
⎯
s
(+85°C < TC ≤ +95°C)
tREFI
⎯
μs
CKE minimum pulse width
(high and low pulse width)
tCKE
5.625
ns
27
tCKE
tXPR
tXPR
tDLLK
tPD
3
⎯
nCK
ns
27
27
27
Exit reset from CKE high to a valid command
tRFC (min.)+10
⎯
5
⎯
nCK
nCK
DLL locking time
512
⎯
Power-down entry to exit time
tCKE (min.)
9 × tREFI
15
Preliminary Data Sheet E0966E60 (Ver. 6.0)
39
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
-DG, -DJ
1333
Data rate (Mbps)
Parameter
Symbol
tXPDLL
tXPDLL
min.
24
max.
⎯
Unit
ns
Notes
Exit precharge power-down with DLL frozen to
commans requiring a locked DLL
2
2
10
⎯
nCK
Ewer-dowith DLL on to any valid command;
t charge per- down with DLL frozen to
commanot requiring a locked DLL
tXP
6
⎯
ns
27
27
tXP
3
1
1
1
⎯
⎯
⎯
⎯
nCK
nCK
nCK
nCK
Cmand pass delay
tCPDED
tACTPDEN
tPRPDEN
Timing of lasower-down entry
Timing of laower-down entry
20
20
Timing of last mmanpower-
down entry
tRDPDEN
tWRPDEN
tWRPDEN
RL + 4 + 1
⎯
⎯
⎯
nCK
nCK
nCK
Timing of last WRIT command to er-down entry
(BL8MRS, BL8OTF, BC4OTF
WL + 4 +
tWR/tCK (avg)
9
9
WL + 2 +
tWR/tCK (avg)
(BC4MRS)
Timing of last WRITA command power-down
entry
(BL8MRS, BL8OTF, BC4OTF)
tWN
WL + 4 + WR + 1
⎯
nCK
10
(BC4MRS)
tR
WL + 2 + WR + 1
⎯
⎯
⎯
nCK
nCK
10
Timing of last REF command to power-down y
1
20, 21
Timing of last MRS command to power-down entry tMRSPDEN
tMOD (min.)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
40
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
ODT AC Electrical Characteristics [DDR3-1333]
-DG, -DJ
1333
Data rate (Mbps)
Parameter
Symbol
tAON
min.
max.
250
Unit
ps
Notes
7, 12
RTT turn-on
−250
Asyncus RTT turn-on delay
(podowith DLL frozen)
tAONPD
tAOF
1
9
ns
om and T_WR turn-off time
om TLoff reference
0.3
0.7
9
tCK (avg) 8, 12
Asynchrous RTT turn-off delay
ower-down with Den)
tAOFPD
tANPD
1
ns
Oto power-
laten
WL – 1.0
⎯
nCK
ODT turn-o
ODT turn-off
ODTLon
TLoff
WL – 2.0
WL – 2.0
WL – 2.0
WL – 2.0
nCK
nCK
ODT Latency for rom
RTT_Nom to RTT_WR
ODTLcnw
WL – 2.0
WL – 2.0
nCK
nCK
ODT Latency for change from
RTT_WR to RTT_Nom
(BC4)
ODTLcwn4
⎯
4 + ODTLoff
ODT Latency for change from
RTT_WR to RTT_Nom
(BL8)
ODTLcwn8
ODTH4
6 + ODTLoff
nCK
ODT high time without WRIT
command or with WRIT command
and BC4
6
⎯
⎯
nCK
nCK
ODT high time with WRIT command
and BL8
ODTH8
tADC
RTT dynamic change skew
0.
0.7
⎯
tCK (avg) 12
nCK
Power-up and reset calibration time tZQinit
Normal operation full calibration time tZQoper
2
256
⎯
nCK
Normal operation short calibration
time
tZQCS
TBD
⎯
nCK
Preliminary Data Sheet E0966E60 (Ver. 6.0)
41
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
AC Characteristics [DDR3-1066, 800]
-AC, -AE, -AG
1066
-8A, -8C
800
Data rate (Mbps)
Parameter
Symbol
min.
max.
3333
min.
max.
3333
Unit
ps
Notes
6
Clock cycle time Average CL = X
tCK(avg)
1875
2500
Minimck cycle time
(Dmo
tCK(DLL-off)
8
⎯
8
⎯
ns
e duty chigh-level
Averagty cycle low-level
tCH (avg)
tCL (avg)
0.47
0.47
0.53
0.53
0.47
0.47
0.53
0.53
tCK (avg)
tCK (avg)
11.25 (AC)
13.1 (AE)
15 (AG)
12.5 (8A)
15 (8C)
ve to read or nd delay tRCD
⎯
⎯
⎯
⎯
⎯
⎯
ns
ns
ns
26
26
26
11.25 (AC)
13.1 (AE)
15 (AG)
12.5 (8A)
15 (8C)
Precharge c
tRP
tRC
48.75 (AC)
50.6 (AE)
52.5 (AG)
Active to active/acomm
time
50 (8A)
52.5 (8C)
Active to precharge comma
tRAS
37.5
7.5
9 × tREFI 37.5
9 × tREFI ns
26
Active bank A to active bank
command period
tRRD
tRRD
⎯
⎯
⎯
⎯
⎯
⎯
⎯
10
4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ns
26, 27
26, 27
26, 27
26, 27
26
(x4/x8)
nCK
ns
Active bank A to active bank B
command period
tRRD
tRRD
10
4
(x16)
4
nCK
ns
Four active window
(x4/x8)
tFAW
tFAW
tIH (base)
37.5
50
40
50
275
(x16)
ns
26
Address and control input hold time
(VIH/VIL (DC) levels)
200
ps
16, 23
Address and control input setup time
(VIH/VIL (AC) levels)
tIS (base)
tDH (base)
tDS (base)
tIPW
125
100
25
00
150
⎯
ps
16, 23
17, 25
17, 25
DQ and DM input hold time
(VIH/VIL (DC) levels)
⎯
⎯
ps
DQ and DM input setup time
(VIH/VIL (AC) levels)
⎯
ps
Control and Address input pulse width
for each input
0.6
0.35
⎯
⎯
0.35
⎯
⎯
tCK (avg)
DQ and DM input pulse width for each
input
tDIPW
⎯
⎯
tCK (avg)
12, 13,
14
DQ high-impedance time
DQ low-impedance time
tHZ (DQ)
tLZ (DQ)
tHZ (DQS)
tLZ (DQS)
300
300
300
300
150
400
40
400
400
200
ps
s
ps
ps
12, 13,
14
−600
⎯
−800
⎯
DQS, /DQS high-impedance time
(RL + BL/2 reference)
12, 13,
14
DQS, /DQS low-impedance time
(RL − 1 reference)
DQS, /DQS -DQ skew, per group, per
access
3,
−600
⎯
−800
⎯
tDQSQ
tCCD
ps
12, 13
/CAS to /CAS command delay
4
⎯
⎯
4
⎯
⎯
nCK
DQ output hold time from DQS, /DQS tQH
DQS, /DQS rising edge output access
time from rising CK, /CK
0.36
0.36
tCK (avg) 12, 13
ps 12, 13
tCK (avg) 24
tDQSCK
−265
+265
−350
+350
DQS latching rising transitions to
associated clock edges
tDQSS
−0.25
0.25
−0.25
0.25
Preliminary Data Sheet E0966E60 (Ver. 6.0)
42
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
-AC, -AE, -AG
1066
-8A, -8C
800
Data rate (Mbps)
Parameter
Symbol
tDSH
min.
max.
min.
max.
Unit
Notes
DQS falling edge hold time from rising
CK
0.2
0.2
⎯
0.2
0.2
⎯
tCK (avg) 24
tCK (avg) 24
DQS falling edge setup time to rising
CK
tDSS
⎯
⎯
Dput hpulse width
S put low pe width
DQS outhigh time
tDQSH
tDQSL
tQSH
0.4
0.4
0.38
0.38
4
0.6
0.6
⎯
0.4
0.4
0.38
0.38
4
0.6
0.6
⎯
tCK (avg)
tCK (avg)
tCK (avg) 12, 13
tCK (avg) 12, 13
nCK
QS output low ti
tQSL
⎯
⎯
Moegister e time tMRD
⎯
⎯
Mode registte
delay
tMOD
15
⎯
15
⎯
ns
27
27
OD
12
⎯
⎯
12
⎯
⎯
nCK
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.9
tCK (avg) 1, 19
11, 12,
13
0.3
⎯
0.3
⎯
tCK (avg)
Write preamble
tWPRE
tWPST
tWR
0.9
0.4
⎯
⎯
⎯
0.9
0.4
15
⎯
⎯
⎯
tCK (avg)
tCK (avg)
ns
1
Write postamble
Write recovery time
1
26
Auto precharge write recovery +
precharge time
))
WR + RU
(tRP/tCK (avg))
tDAL
tRTW
tRTW
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
nCK
Read to write command delay
(BC4MRS, BC4OTF)
RL 2 +
2nCK − WL
RL + tCCD
2nCK − W
RL + tCCD/2 +
2nCK − WL
RL + tCCD +
2nCK − WL
(BL8MRS, BL8OTF)
18, 26,
27
Internal write to read command delay tWTR
tWTR
7.5
7.5
ns
18, 26,
27
4
nCK
Internal read to precharge command
delay
tRTP
7.5
4
⎯
⎯
7.5
⎯
⎯
ns
26, 27
26, 27
tRTP
nCK
Minimum CKE low width for self-
refresh entry to exit timing
tCKE (min.)
+1nCK
tCKESR
Valid clock requirement after self-
refresh entry or power-down entry
tCKSRE
tCKSRE
tCKSRX
tCKSRX
tXS
10
5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
10
5
⎯
⎯
⎯
⎯
⎯
⎯
ns
27
27
27
27
27
2
nCK
ns
Valid clock requirement before self-
refresh exit or power-down exit
10
10
5
5
CK
ns
Exit self-refresh to commands not
requiring a locked DLL
tRFC (min.) +
10
tRFC (min.) +
10
tXS
5
5
tCK
Exit self-refresh to commands
requiring a locked DLL
tXSDLL
tDLLK (min.)
tDLLK (min.)
Auto-refresh to active/auto-refresh
command time
tRFC
90
⎯
90
⎯
ns
Average periodic refresh interval
(0°C ≤ TC ≤ +85°C)
tREFI
tREFI
⎯
⎯
7.8
3.9
⎯
⎯
7.8
3.9
μs
μs
(+85°C < TC ≤ +95°C)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
43
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
-AC, -AE, -AG
1066
-8A, -8C
800
Data rate (Mbps)
Parameter
Symbol
tCKE
min.
max.
⎯
min.
max.
⎯
Unit
ns
Notes
27
CKE minimum pulse width
(high anlow pulse width)
5.625
3
7.5
3
tCKE
⎯
⎯
nCK
ns
27
Eset from KE high to a valid
mnd
tXPR
tRFC(min.)+10 ⎯
tRFC(min.)+10 ⎯
27
tXPR
tDLLK
tPD
5
⎯
⎯
5
⎯
nCK
nCK
27
LL locking time
512
512
⎯
Po-down e
tCKE (min.)
9 × tREFI tCKE (min.)
9 × tREFI
15
2
Exit precharDLL
frozen to coocked tXPDLL
DLL
24
⎯
24
⎯
ns
XPDLL
10
⎯
⎯
10
⎯
⎯
nCK
ns
2
Fast exit/active precharge powern
to any command
tXP
7.5
7.5
27
27
tXP
3
1
⎯
⎯
3
1
⎯
⎯
nCK
nCK
Command pass disable/enabllay tCPDED
Timing of last ACT command to
tACTPDEN
1
⎯
⎯
⎯
1
⎯
⎯
⎯
nCK
nCK
nCK
20
20
power-down entry
Timing of last PRE command to
power-down entry
tPRPDE
tRDPDEN
1
Timing of last READ/READA
command to power-down entry
RL + 4 1
RL + 4 + 1
Timing of last WRIT command to
power-down entry
(BL8MRS, BL8OTF, BC4OTF)
WL + 4 +
tWR/tCK g)
WL + 4 +
tWR/tCK (avg)
tWRPDEN
tWRPDEN
tWRAPDEN
⎯
⎯
⎯
⎯
⎯
nCK
nCK
nCK
9
WL + 2 +
tWR/tCK (avg)
WL + 2 +
WR/tCK (avg)
(BC4MRS)
9
Timing of last WRITA command to
power-down entry
(BL8MRS, BL8OTF, BC4OTF)
WL + 4 + WR +
1
L + 4 +
WR + 1
10
WL + 2 + WR +
1
W+
(BC4MRS)
tWRAPDEN
tREFPDEN
⎯
⎯
⎯
⎯
nCK
nCK
10
Timing of last REF command to
power-down entry
1
20, 21
Timing of last MRS command to
power-down entry
tMRSPDEN tMOD (min.)
tMOD in.)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
44
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
ODT AC Electrical Characteristics [DDR3-1066, 800]
-AC, -AE, -AG
-8A, -8C
800
Data rate (Mbps)
Parameter
1066
Symbol
tAON
min.
max.
300
min.
max.
400
Unit
ps
Notes
7, 12
RTT turn-on
–300
–400
Asyncus RTT turn-on delay
(podowith DLL frozen)
tAONPD
tAOF
1
9
1
9
ns
om and T_WR turn-off
me fODTLoff reference
0.3
0.7
9
0.3
0.7
9
tCK (avg) 8, 12
ODT turn(power-down mode) tAOFPD
1
1
ns
T to power-doit
tANPD
laty
WL – 1.0
⎯
WL – 1.0
⎯
nCK
ODT turn-on
ODT turn-of
ODTLon
ODTLoff
WL – 2.0
WL – 2.0
WL – 2.0
WL – 2.0
WL – 2.0
WL – 2.0
WL – 2.0
WL – 2.0
nCK
nCK
ODT Latency
RTT_Nom to RT
Lcnw
WL – 2.0
WL – 2.0
WL – 2.0
WL – 2.0
nCK
nCK
ODT Latency for change from
RTT_WR to RTT_Nom
(BC4)
ODTLcwn4
⎯
4 + ODTLoff
⎯
4 + ODTLoff
ODT Latency for change from
RTT_WR to RTT_Nom
(BL8)
ODTLcwn8
⎯
6 + ODTLoff
⎯
6 + ODTLoff
nCK
ODT high time without WRIT
command or with WRIT command ODTH4
and BC4
6
⎯
4
6
⎯
⎯
nCK
nCK
ODT high time with WRIT
ODTH8
command and BL8
RTT dynamic change skew
tADC
0.3
0.3
0.7
tCK (avg) 12
nCK
Power-up and reset calibration time tZQinit
512
⎯
512
⎯
Normal operation full calibration
time
tZQoper
tZQCS
256
⎯
⎯
6
⎯
⎯
nCK
nCK
Normal operation short calibration
time
TBD
Write Leveling Characteristics
Parameter
Symbol
tWLMRD
min.
Unit
CK
Notes
3
First DQS pulse rising edge after write
leveling mode is programmed
40
⎯
DQS, /DQS delay after write leveling
mode is programmed
tWLDQSEN
tWLS
25
⎯
⎯
⎯
nCK
3
Write leveling setup time from rising CK,
/CK crossing to rising DQS, /DQS crossing
0.15
0.15
(avg)
Write leveling hold time from rising DQS,
/DQS crossing to rising CK, /CK crossing
tWLH
tCK (a
Write leveling output delay
Write leveling output error
tWLO
0
0
9
2
ns
ns
tWLOE
Preliminary Data Sheet E0966E60 (Ver. 6.0)
45
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Notes for AC Electrical Characteristics
Notes: 1. Actual value dependent upon measurement level definitions that are TBD.
2. Commands requiring locked DLL are: READ (and READA) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register.
Value must be rounded-up to next integer value.
. here is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. Oturn on time (min.) is when the device leaves high impedance and ODT resistance begins to turn on.
ODT urn on time (max.) is when the ODT resistance is fully on. Both are measured from ODTLon.
ODT turn-off time (min.) is when the device starts to turn-off ODT resistance. ODT turn-off time (max.) is
when ths is in high impedance. Both are measured from ODTLoff.
9. tWns, for calculation of tWRPDEN it is necessary to round up tWR/tCK to the next integer.
10. as programmed in MR0.
11. amble is bound by tHZDQS(max.)
12. atings re relative to the SDRAM input clock. When the device is operated with input
cloparamneeds to be derated by TBD.
13. Value is only valid RON34.
14. Single ended sl parameter. Refer to the section of tLZ (DQS), tLZ (DQ), tHZ (DQS), tHZ (DQ) Notes
for definition measurement method.
15. tREFI depends operating case temperature (TC).
16. tIS(base) and tIH(be) values are for s command/address single-ended slew rate and 2V/ns CK,
/CK differential slew rate. Note for Dsignals, VREF(DC) = VREFDQ(DC). For input only pins
except /RESET, VREF(DC) = VRAddress / Command Setup, Hold and Derating section
17. tDS(base) and tDH(base) vaars DQ single-ended slew rate and 2V/ns DQS, /DQS
differential slew rate. Note for Q and DM als, VREF(DC) = VREFDQ(DC). For input only pins except
/RESET, VREF(DC) = VREFCA(DC). See Data Seup, Hold and Slew Rate Derating section.
18. Start of internal write transaction is definited as
For BL8 (fixed by MRS and on- the-flRising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly): Rising clock ede 4 clock cafter WL.
For BC4 (fixed by MRS): Rising clock edge 2 after WL.
19. The maximum preamble is bound by tLZDQS(max.
20. CKE is allowed to be registered low while operations w activation, precharge, auto precharge or
refresh are in progress, but power-down IDD spec will not be applinishithose operations.
21. Although CKE is allowed to be registered low after a refresh coFPDEN(min.) is satisfied,
there are cases where additional time such as tXPDLL(min.) ed. See Figure Power-Down
Entry/Exit Clarifications - Case 2.
22. tJIT(duty) = { 0.07 × tCK(avg) – [(0.5 - (min (tCH(avg), tCL(avg))) × K(avg
For example, if tCH/tCL was 0.48/0.52, tJIT(duty) would calculate out to 1s for DD-800.
The tCH(avg) and tCL(avg) values listed must not be exceeded.
23. These parameters are measured from a command/address signal (CKE, /CSS, /CAWE, ODT,
BA0, A0, A1, etc.) transition edge to its respective clock signal (CK, /CK) crossg. Thec ves are
not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the up and ld are
relative to the clock signal crossing that latches the command/address. That is, these arameters shol
be met whether clock jitter is present or not.
24 These parameters are measured from a data strobe signal ((L/U/T)DQS, /DQS) crossing to its restive
clock signal (CK, /CK) crossing. The spec values are not affected by the amount of clock jitter apd (i.e.
tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these pameters
should be met whether clock jitter is present or not.
25. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge
to its respective data strobe signal ((L/U/T)DQS/DQS) crossing.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
46
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
26. For these parameters, the DDR3 SDRAM device is characterized and verified to support
tnPARAM [nCK] = RU{tPARAM [ns] / tCK(avg)}, which is in clock cycles, assuming all input clock jitter
specifications are satisfied.
For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock
jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will
support tnRP =RU{tRP / tCK(avg)} = 6, i.e. as long as the input clock jitter specifications are met, prechar
ge command at Tm and active command at Tm+6 is valid even if (Tm+6 − Tm) is less than 15ns due to
nput clock jitter.
27. se parameters should be the larger of the two values, analog (ns) and number of clocks (nCK).
Preliminary Data Sheet E0966E60 (Ver. 6.0)
47
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Clock Jitter [DDR3-1333]
-DG, -DJ
1333
Data rate (Mbps)
Parameter
Symbol
min.
max.
3333
Unit
ps
Notes
Average clock period
tCK (avg)
1500
1
tCK(avg)min +
tJIT(per)min
tCK(avg)max+
tJIT(per)max
Absck period
tCK (abs)
tJIT (per)
ps
ps
ps
ps
ps
2
6
6
7
7
period jitt
−80
−70
⎯
80
Clock pod jitter during DLL locking
period
tJIT (per, lck)
tJIT (cc)
70
le to cycle pe
160
140
Cyco cycle
during DLL l
tJIT (cc, lck)
⎯
Cumulative
Cumulative eres
Cumulative error ac4 cycles
Cumulative error across 5 cy
tERR (2per)
tERR (3per)
tERR (4per)
tERR (5per)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
ps
ps
8
8
8
8
8
Cumulative error across
n = 6, 7, 8, 9, 10 cycles
tERR (6-10per)
TBD
TBD
TBD
ps
ps
Cumulative error across
n = 11, 12,…49, 50 cycles
8
tERR (11-50pBD
Average high pulse width
Average low pulse width
Duty cycle jitter
tCH (avg
tCL (
tJIT (duty)
0
0.53
0.53
60
tCK (avg)
tCK (avg)
ps
3
4
5
Clock Jitter [DDR3-1066, 800]
-AC, -AE, G
-8A, -8C
Data rate (Mbps)
Parameter
1066
min.
Symbol
max
3333
.
max.
3333
Unit
ps
Notes
1
Average clock period
tCK (avg)
1875
2500
tCK(avg)min + tCK(avg)max+ tCtCg)max+
tJIT(per)min tJIT(per)max t(per)max
Absolute clock period
tCK (abs)
ps
ps
ps
ps
ps
2
6
6
7
7
Clock period jitter
tJIT (per)
−90
−80
⎯
90
−
−90
⎯
100
Clock period jitter during
DLL locking period
tJIT
(per, lck)
80
90
Cycle to cycle period jitter
tJIT (cc)
180
160
0
180
Cycle to cycle clock period jitter
during DLL locking period
tJIT (cc, lck)
⎯
⎯
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
tERR (2per) TBD
tERR (3per) TBD
tERR (4per) TBD
tERR (5per) TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
s
ps
ps
8
8
8
8
Cumulative error across
n=6,7,8,9,10 cycles
tERR
(6-10per)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
Cumulative error across
n=11, 12,…49,50 cycles
tERR
(11-50per)
8
TBD
Average high pulse width
Average low pulse width
Duty cycle jitter
tCH (avg)
tCL (avg)
tJIT (duty)
0.47
0.47
−75
0.53
0.53
75
0.47
0.47
−100
0.53
0.53
100
tCK (avg)
tCK (avg)
ps
3
4
5
Preliminary Data Sheet E0966E60 (Ver. 6.0)
48
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Notes: 1. tCK (avg) is calculated as the average clock period across any consecutive 200cycle window, where each
clock period is calculated from rising edge to rising edge.
N
tCK
N
j
Σ
j = 1
N = 200
CK (abs) is the absolute clock period, as measured from one rising edge to the next consecutive rising
ee. tCK (abs) is not subject to production test.
3. tCH vg) is defined as the average high pulse width, as calculated across any consecutive 200 high
pulses.
N
(N × t
)
tCH
CK(avg)
j
Σ
j = 1
N = 200
4. tCed as average low pulse width, as calculated across any consecutive 200 low pulses.
N
tCL
(N × t
)
j
CK(avg)
Σ
j = 1
N = 200
5. tJIT (duty) is defines the cumulative tCH jitter and tCL jitter. tCH jitter is the largest deviation of
any single tCH from tCH (avg). tthe largest deviation of any single tCL from tCL (avg).
tJIT (duty) is not subject to produc
tJIT (duty) = Min./Max. of {tJIT ), tJhere:
tJIT (CH) = {tCHj- tCH (avg) where j = 1 to 200}
tJIT (CL) = {tCLj- tCL (avg) where j = 1 to 200}
6. tJIT (per) is defined as the largest deviation of sintCK from tCK (avg).
tJIT (per) = Min./Max. of { tCKj − tCK (avg) re j = 1 to 200}
tJIT (per) defines the single period jitter when the Dady locked. tJIT (per, lck) uses the same
definition for single period jitter, during the DLL locnly. tJIT (per) and tJIT (per, lck) are not
subject to production test.
7. tJIT (cc) is defined as the absolute difference in clock tween two consecutive clock cycles:
tJIT (cc) = Max. of {tCKj+1 - tCKj}
tJIT (cc) is defines the cycle when the DLL is already locked. ses the same definition for
cycle to cycle jitter, during the DLL locking period only. tJIT T (cc, lck) are not subject to
production test.
8. tERR (nper) is defined as the cumulative error across n multiple conscutive es from tCK (avg).
tERR (nper) is not subject to production test.
9. These parameters are specified per their average values, however it is nderstthat the following
relationship between the average timing and the absolute instantaneous timing at all ti
(minimum and maximum of spec values are to be used for calculations in the table belo
Parameter
Symbol
min.
max.
nit
Absolute clock period
tCK (abs) tCK (avg), min. + tJIT (per),min. tCK (avg), max. + tJIT (ax. ps
Absolute clock high pulse
width
tCH (avg), min. × tCK (avg),min. tCH (avg), max. × tCK (avg),max.
tCH (abs)
tCL (abs)
+ tJIT (duty),min.
tCL (avg), min. × tCK (avg),min. tCL (avg), max. × tCK (avg),max.
+ tJIT (duty),min. + tJIT (duty),max.
+ tJIT (duty),max.
Absolute clock low pulse
width
Preliminary Data Sheet E0966E60 (Ver. 6.0)
49
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Block Diagram
CK
/CK
CKE
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
A0 tA12,
BA0, BA1, B
Row
address
Memory cell array
Bank 0
buffer
and
refresh
counter
Mode
reg
Sense amp.
Column decoder
ddr
buffer
and
/CS
/RAS
/CAS
/WE
burst
counter
Data control circuit
h circuit
DQS, /DQS
TDQS, /TDQS
CK, /CK
DLL
Input &
ODT
DM
DQ
Preliminary Data Sheet E0966E60 (Ver. 6.0)
50
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Pin Function
CK, /CK (input pins)
CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK
(both directions of crossing).
/CS uin)
mmanare masked when /CS is registered high. /CS provides for external rank selection on systems with
ultiranks. CS is considered part of the command code.
AS, /CAS, /Wpins)
/R, /CAS with /CS) define the command being entered.
A0 to A12
Provided thfor actcommands and the column address for read/write commands to select one
location out of ory arin the respective bank. (A10(AP) and A12(/BC) have additional functions, see
below) The address inputs arovide the op-code during mode register set commands.
[Address Pins Table]
Address (A0 to A12)
Notes
Part number
age size
1KB
Raddress (RA)
12
Column address (CA)
AY0 to AY9, AY11
AY0 to AY9
EDJ5304BASE
EDJ5308BASE
EDJ5316BASE
2
2KB
11
AY0 to AY9
A10(AP) (input pin)
A10 is sampled during read/write commands to detene whether auto precharge should be performed to the
accessed bank after the read/write operation. (high: ao precharge; w: no auto precharge)
A10 is sampled during a precharge command to determine whecharge applies to one bank (A10 = low)
or all banks (A10 = high). If only one bank is to be prechargedelected by bank addresses (BA).
A12(/BC) (input pin)
A12 is sampled during read and write commands to determine if burst cho) be performed.
(A12 = high: no burst chop, A12 = low: burst chopped.) See command tetails.
BA0 to BA2 (input pins)
BA0, BA1 and BA2 define to which bank an active, read, write or precharge commis being plied. BA0 and
BA1 also determine which mode register (MR0 to MR3) is to be accessed during a Mcycle.
[Bank Select Signal Table]
BA0
L
BA1
L
BA2
L
Bank 0
Bank 1
H
L
L
L
Bank 2
H
H
L
L
Bank 3
H
L
L
Bank 4
H
H
H
H
Bank 5
H
L
L
Bank 6
H
H
Bank 7
H
Remark: H: VIH. L: VIL.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
51
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
CKE (input pin)
CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers.
Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down
(row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the
power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper
self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read
and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers,
excluKE, are disabled during self-refresh.
MU, DMinput pins)
DM is nput mask signal for write data. Input data is masked when DM is sampled high coincident with that input
ata during a write access. DM is sampled on both edges of DQS. For ×8 configuration, the function of DM or
QS, /TDQS y mode register A11 setting in MR1.
DQ, DQU, pins)
Bi-direction
DQS, /DQS, DQSU, /DQSU, SL, /DQSL (input/output pins)
Output with read data, inpith write data. Edge-aligned with read data, center-aligned with write data.
The data strobe DQS is red with differential signal /DQS to provide differential pair signaling to the system during
READs and WRITEs.
TDQS, /TDQS (output pins)
TDQS and /TDQS is applicable for ×8 confighen enabled via mode register A11 = 1 in MR1, DRAM
will enable the same termination resistancnS, /TDQS as is applied to DQS, /DQS. When disabled
via mode register A11 = 0 in MR1, DM/TS will pe data mask function and /TDQS is not used.
In ×4/×16 configuration, the TDQS function must be disabled via mode register A11 = 0 in MR1.
/RESET (input pin)
/RESET is a CMOS rail to rail signal with DC high aow at 80% and 20% of VDD (1.20V for DC high and 0.30V
for DC low).
It is negative active signal (active low) and is referred to GNDermination required on this signal. It will
be heavily loaded across multiple chips. /RESET is destructivents.
ODT (input pins)
ODT (registered high) enables termination resistance internal to the DDhen enabled, ODT is only
applied to each DQ, DQS, /DQS, DM/TDQS, NU(/TDQS) (when TDQS is mode register A11 = 1 in MR1)
signal for ×4/×8 configuration. For ×16 configuration ODT is applied to each DQSDQSU, DQSL, /DQSL,
DMU, and DML signal. The ODT pin will be ignored if the mode register (MR1) iprograed to disable ODT.
ZQ (supply)
Reference pin for ZQ calibration.
VDD, VSS, VDDQ, VSSQ (power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply s fr the ou
buffers.
VREFCA, VREFDQ (power supply)
Reference voltage
Preliminary Data Sheet E0966E60 (Ver. 6.0)
52
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Command Operation
Command Truth Table
The DDR3 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Previous Current
BA0 to A12
A10
(AP)
Address
Fun
Symbol cycle
cycle
/CS /RAS /CAS /WE BA2
(/BC)
Notes
register
uto-rsh
MRS
REF
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
BA
V
op-code
H
H
V
V
V
V
V
V
Self-refresentry
SELF
V
6, 8, 11
6, 7, 8,
11
Sefresh ex
SREX
L
H
H
V
V
V
V
V
V
V
L
H
H
H
H
H
H
H
L
L
L
L
L
L
H
L
H
H
H
H
L
H
L
L
H
L
L
L
V
V
V
L
V
V
V
Single bank
Precharge all b
Bank activate
RE
H
H
H
H
H
H
BA
V
V
PALL
A
L
V
H
L
BA
BA
BA
BA
RA
V
12
Write (Fixed BL)
RIT
WRS4
S8
H
H
H
L
L
L
CA
CA
CA
Write (BC4, on the fly)
Write (BL8, on the fly)
L
L
L
H
Write with auto precharge
(Fixed BL)
WRITA
WRAS4
WRAS8
H
H
H
H
H
H
L
H
H
H
L
L
L
L
L
L
BA
BA
BA
V
L
H
H
H
CA
CA
CA
Write with auto precharge
(BC4, on the fly)
Write with auto precharge
(BL8, on the fly)
H
Read (Fixed BL)
READ
RDS4
RDS8
H
H
H
H
H
H
L
L
H
H
L
H
H
BA
BA
BA
V
L
L
L
L
CA
CA
CA
Read (BC4, on the fly)
Read (BL8, on the fly)
H
Read with auto precharge
(Fixed BL)
READA
RDAS4
RDAS8
H
H
H
H
H
H
L
L
L
H
H
H
L
H
H
BA
V
L
H
H
H
CA
CA
CA
Read with auto precharge
(BC4, on the fly)
Read with auto precharge
(BL8, on the fly)
No operation
NOP
H
H
H
H
L
H
H
L
L
H
H
L
H
×
H
×
H
×
×
V
×
V
×
V
×
9
Device deselect
DESL
PDEN
10
Power-down mode entry
V
H
V
H
H
H
V
H
V
H
H
H
V
H
V
H
L
V
V
V
V
×
V
V
×
V
V
V
H
L
V
V
V
×
5, 11
L
Power-down mode exit
PDEX
H
H
H
H
H
L
5, 11
L
ZQ calibration long
ZQ calibration short
ZQCL
ZQCS
H
H
L
L
L
×
×
×
Remark: H = VIH. L = VIL. × = VIH or VIL. V = Valid
BA = Bank addresses. RA = Row Address. CA = Column Address.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
53
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Notes: 1. All DDR3 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the
clock. The most significant bit (MSB) of BA, RA, and CA are device density and configuration dependent.
2. /RESET is an active low asynchronous signal that must be driven high during normal operation
3. Bank Addresses (BA) determine which bank is to be operated upon. For MRS, BA selects an mode
register.
4. Burst READs or WRITEs cannot be terminated or interrupted and fixed/on the fly BL will be defined by
MRS.
. he power-down mode does not perform any refresh operations.
6. Tstate of ODT does not affect the states described in this table. The ODT function is not available
durinself-refresh.
7Self-refresh exit is asynchronous.
8. VREF REFDQ and VREFCA) must be maintained during self-refresh operation.
9. Tcommand (NOP) should be used in cases when the DDR3 SDRAM is in an idle or a
rpose of the NOP command is to prevent the DDR3 SDRAM from registering any
ds between operations. A NOP command will not terminate a previous operation that is
h as a burst read or write cycle.
10. Thmand orms the same function as a NOP command.
11. Refer to the CKE h Table for more detail with CKE transition.
12. No more than anks may be activated in a rolling tFAW window. Converting to clocks is done by
dividing tFAs) by tCK (ns) and rounding up to next integer value. As an example of the rolling
window, if (tFACK) rounds up to 10 clocks, and an activate command is issued in clock N, no more
than three further vate commands me issued in clock N+1 through N+9.
No Operation Command [NOP]
The No Operation command (NOP) should be used ases when the DDR3 SDRAM is in an idle or a wait state.
The purpose of the NOP command is to prevent the DDRSDRAM from registering any unwanted commands
between operations. A NOP command will not terminate us operation that is still executing, such as a burst
read or write cycle.
The no operation (NOP) command is used to instruct the selecDRAM to perform a NOP (/CS low, /RAS,
/CAS, /WE high). This prevents unwanted commands from bd during idle or wait states. Operations
already in progress are not affected.
Device Deselect Command [DESL]
The deselect function (/CS high) prevents new commands from being exDDR3 SDRAM. The DDR3
SDRAM is effectively deselected. Operations already in progress are not a
Mode Register Set Command [MR0 to MR3]
The mode registers are loaded via row address inputs. See mode register descrons in tProgramming the
Mode Register section. The mode register set command can only be issued wheall nks are idle, and a
subsequent executable command cannot be issued until tMRD is met.
Bank Activate Command [ACT]
This command is used to open (or activate) a row in a particular bank for a subsequent access. Tlues on
BA inputs select the bank, and the address provided on row address inputs selects the row. This row remains tive
(or open) for accesses until a precharge command is issued to that bank. A precharge command must ssued
before opening a different row in the same bank.
Note: No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing
tFAW (ns) by tCK (ns) and rounding up to next integer value. As an example of the rolling window, if
(tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further
activate commands may be issued in clock N+1 through N+9.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
54
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Read Command [READ, RDS4, RDS8, READA, RDAS4, RDAS8]
The read command is used to initiate a burst read access to an active row. The values on the BA inputs select the
bank, and the address provided on column address inputs selects the starting column location. The value on input
A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent
accesses.
Writmand [WRIT, WRS4, WRS8, WRITA, WRAS4, WRAS8]
Trite comand is used to initiate a burst write access to an active row. The values on the BA inputs select the
nnd the dress provided on column address inputs selects the starting column location. The value on input
A10 demines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be
recharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent
esses. Inpearing on the DQ is written to the memory array subject to the DM input logic level
appring ce data. If a given DM signal is registered low, the corresponding data will be written to
memory; if egistered high, the corresponding data inputs will be ignored, and a write will not be
executed tlocation.
Precharge CoPRE, PL]
The precharge command is ed to deactivate the open row in a particular bank or the open row in all banks. The
bank(s) will be available subsequent row access a specified time (tRP) after the precharge command is issued.
Input A10 determines wher one or all banks are to be precharged, and in the case where only one bank is to be
precharged, inputs BA set the bank. Otherwise BA are treated as "Don't Care." Once a bank has been
precharged, it is in the idle se and must be acd prior to any read or write commands being issued to that
bank. A precharge command will be treated if there is no open row in that bank (idle state), or if the
previously open row is already in the process
Auto precharge Command [READA, WRITA]
Before a new row in an active bank can be opened, the actibank must be precharged using either the precharge
command or the auto precharge function. When a read ocommand is given to the DDR3 SDRAM, the /CAS
timing accepts one extra address, column address A10allow the active bank to automatically begin precharge at
the earliest possible moment during the burst read orite cycle. I10 is low when the read or write command is
issued, then normal read or write burst operation is executed k remains active at the completion of the
burst sequence. If A10 is high when the read or write comed, then the auto precharge function is
engaged. During auto precharge, a read command will execl with the exception that the active bank
will begin to precharge on the rising edge which is /CAS latencck cycles before the end of the read burst.
(This timing is equal to the rising edge which is (AL* + BL/2) cycles lthe d with auto precharge
command.)
Auto precharge can also be implemented during write commands. The eration engaged by the Auto
precharge command will not begin until the last data of the burst write sepropestored in the memory
array.
This feature allows the precharge operation to be partially or completely hidden durinurst read cles (dependent
upon /CAS latency) thus improving system performance for random data access. ThRAS lout circuit internally
delays the Precharge operation until the array restore operation has been completeso the auto precharge
command may be issued with any read or write command.
Note: AL (Additive Latency), refer to Posted /CAS description in the Register Definition section.
Auto-Refresh Command [REF]
Auto-refresh is used during normal operation of the DDR3 SDRAM and is analogous to /CAS-before-/R(CBR)
refresh in FPM/EDO DRAM. This command is nonpersistent, so it must be issued each time a refresh is requed.
The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during an
auto-refresh command.
A maximum of eight auto-refresh commands can be posted to any given DDR3, meaning that the maximum absolute
interval between any auto-refresh command and the next auto-refresh command is 9 × tREFI. This maximum
absolute interval is to allow DDR3 output drivers and internal terminators to automatically recalibrate compensating
for voltage and temperature changes.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
55
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Self-Refresh Command [SELF]
The self-refresh command can be used to retain data in the DDR3, even if the rest of the system is powered down.
When in the self-refresh mode, the DDR3 retains data without external clocking. The self-refresh command is
initiated like an auto-refresh command except CKE is disabled (low). The DLL is automatically disabled upon
entering self-refresh and is automatically enabled and reset upon exiting self-refresh. The active termination is also
disabled upon entering self-refresh and enabled upon exiting self-refresh. (512 clock cycles must then occur before
a read command can be issued). Input signals except CKE are "Don't Care" during self-refresh. The procedure for
exitin-refresh requires a sequence of commands. First, CK and /CK must be stable prior to CKE going back
higOncKE is high, the DDR3 must have NOP commands issued for tXSDLL because time is required for the
etion of y internal refresh in progress. A simple algorithm for meeting both refresh, DLL requirements and
ut-palibration is to apply NOPs for 512 clock cycles before applying any other command to allow the DLL to lock
and the put drivers to recalibrate.
ZQ libratiZQCL, ZQCS]
ZQ calibrart or long) is used to calibrate DRAM RON and ODT values over PVT.
ZQ Calibr) command is used to perform the initial calibration during power-up initialization
sequence.
ZQ Calibration QCS) cmand is used to perform periodic calibrations to account for VT variations.
All banks must be prechargnd tRP met before ZQCL or ZQCS commands are issued by the controller.
ZQ calibration commandn also be issued in parallel to DLL lock time when coming out of self-refresh.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
56
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
CKE Truth Table
CKE
Previous
Current
Command (n)*3
Current state*2
Power-down
cycle (n-1)*1 cycle (n)*1
/CS, /RAS, /CAS, /WE Operation (n)*3
Notes
L
L
H
L
H
L
L
L
L
L
L
×
Maintain power-down
14, 15
L
DESL or NOP
×
Power-down exit
11, 14
Seresh
L
Maintain self-refresh
Self-refresh exit
15, 16
L
DESL or NOP
DESL or NOP
DESL or NOP
DESL or NOP
DESL or NOP
DESL or NOP
DESL or NOP
REFRESH
8, 12, 16
11, 13, 14
Bank Ac
ading
H
H
Active power-down entry
Power-down entry
11, 13, 14, 17
11, 13, 14, 17
Wri
Power-down entry
11, 13, 14, 17
Precharging
Refreshing
All banks idle
Power-down entry
Precharge power-down entry
Precharge power-down entry
Self-refresh entry
11
11, 13, 14, 18
9, 13, 18
Any state other than
listed above
H
H
Refer to the Command Truth Table
10
Remark: H = VIH. L = VIL. = Don’t care
Notes: 1. CKE (n) is the logitate of CKE at cdge n; CKE (n−1) is the state of CKE at the previous clock
edge.
2. Current state is the state of the Dmediately prior to clock edge n.
3. Command (n) is the commangisterk edge n, and operation (n) is a result of Command (n).
ODT is not included here.
4. All states and sequences not shown are illegal eserved unless explicitly described elsewhere in this
document.
5. The state of ODT does not affect the stateescribed in this table. The ODT function is not available
during self-refresh.
6. CKE must be registered with the same value on tCsecutive positive clock edges. CKE must
remain at the valid input level the entire time it tae the tCKE (min.) clocks of registration.
Thus, after any CKE transition, CKE may not transivalid level during the time period of tIS +
tCKE (min.) + tIH.
7. DESL and NOP are defined in the Command Truth Table.
8. On self-refresh exit, DESL or NOP commands must be issuek edge occurring during the
tXS period. Read or ODT command may be issued only after tXtisfied.
9. Self-refresh mode can only be entered from the all banks idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for power-down entry and exit are NOP and DESL only.
12. Valid commands for self-refresh exit are NOP and DESL only.
13. Self-refresh can not be entered while read or write operations, (extended) mode egistet opeions or
precharge operations are in progress. See section Power-Down and self-refresh Comnd for a tailed
list of restrictions.
14. The power-down does not perform any refresh operations.
15. “×” means “don’t care” (including floating around VREF) in self-refresh and power-down. It also aps to
address pins.
16. VREF (Both VREFDQ and VREFCA) must be maintained during self-refresh operation.
17. If all banks are closed at the conclusion of the read, write or precharge command, the precharge power-
down is entered, otherwise active power-down is entered.
18. Idle state means that all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress. CKE
is high and all timings from previous operation are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS,
etc.) as well as all self-refresh exit and power-down exit parameters are satisfied (tXS, tXP, tXPDLL, etc).
Preliminary Data Sheet E0966E60 (Ver. 6.0)
57
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Simplified State Diagram
CKE_L
MRS, MPR,
WRITE
LEVELING
POWER
SELF
REFRESH
APPLIED
POWER
ON
RESET
PROCEDURE
INITIALIZATION
SELF
MRS
SELFX
ZQCL
ZQCS
FM ANY
STA
RESET
REF
ZQ
REFRESHING
IDLE
CALIBRATION
PDEN
ACT
PDEX
ACTIVE
POWER
DOWN
ACTIVATING
PRECHARGE
POWER
DOWN
CKE_L
PDEX
CKE_L
PDEN
WR
BANK
ACTIVE
READ
WRIT
READ
READA
WRI
WRIT
READ
WRITING
READING
READA
WRITA
WRITA
A
PRE, PALL
WRITING
ING
PRE, PALL
PR
PRECHARGING
Autoic sequence
mand sequence
Preliminary Data Sheet E0966E60 (Ver. 6.0)
58
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
RESET and Initialization Procedure
Power-Up and Initialization Sequence
1. Apply power (/RESET is recommended to be maintained below 0.2 × VDD, (all other inputs may be undefined). )
/RESET needs to be maintained for minimum 200μs with stable power. CKE is pulled low anytime before
/RESET being de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDD (min.) must
breater than 200ms; and during the ramp, VDD > VDDQ and (VDD − VDDQ) < 0.3V.
• and DQ are driven from a single power converter output
AND
• The vage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one ide and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to
.95V max oamp is finished,
AN
• VREF tra
OR
• Apply VDD without any sreversal before or at the same time as VDDQ.
• Apply VDDQ without slope reversal before or at the same time as VTT and VREF.
• The voltage levels on all s other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be lar than or equal to VQ and VSS on the other side.
2. After /RESET is de-asserted, wait for anothuntil CKE become active. During this time, the DRAM will
start internal state initialization; this will be dently of external clocks.
3. Clocks (CK, /CK) need to be started astat least 10ns or 5tCK (which is larger) before CKE goes
active. Since CKE is a synchronous snal, the onding set up time to clock (tIS) must be met. Also a NOP
or DESL command must be registered (with tIS set up tme to clock) before CKE goes active. Once the CKE
registered “high” after Reset, CKE needs to be continly registered high until the initialization sequence is
finished, including expiration of tDLLK and tZQinit.
4. The DDR3 SDRAM will keep its on-die terminatin high-impedance state during /RESET being asserted at
least until CKE being registered high. Therefore, the ODT sibe in undefined state until tIS before CKE
being registered high. After that, the ODT signal must be (low) until the power-up and initialization
sequence is finished, including expiration of tDLLK and tZQ
5. After CKE being registered high, wait minimum of tXPR, bing the first MRS command to load mode
register. (tXPR = max. (tXS ; 5 × tCK)
6. Issue MRS command to load MR2 with all application settings. (To issnd for MR2, provide low to
BA0 and BA2, high to BA1.)
7. Issue MRS command to load MR3 with all application settings. (To issue mmanor MR3, provide low to
BA2, high to BA0 and BA1.)
8. Issue MRS command to load MR1 with all application settings and DLL ened. (To ue DLL Enable
command, provide low to A0, high to BA0 and low to BA1 and BA2).
9. Issue MRS command to load MR0 with all application settings and DLL reset. (To isDLL reset command,
provide high to A8 and low to BA0 to BA2).
10.Issue ZQCL command to start ZQ calibration.
11.Wait for both tDLLK and tZQinit completed.
12.The DDR3 SDRAM is now ready for normal operation.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
59
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK, /CK
VDD, VDDQ
ESET
max. (10 ns; 5tCK)
200μs
500μs
tIS
10ns
CK
2
*
tDLLK
ZQcal
tXPR
tIS
tMRD
tMRD
MRS
MR3
tMRD
tMOD
tZQinit
Comma
1
MRS
MR2
MRS
MR1
MRS
MR0
*
tIS
O
DRAM_RTT
Notes: 1. From time pod" until "Tk", NOP or DESL commands must be
applied betweMRS and ZQcal commands.
2. tXPR = max. (tXtCK)
: VIH or VIL
Ret and Initializatiequence at Power-On Ramping
Reset and Initialization with Stable Power
The following sequence is required for /RET at interruption initialization.
1. Assert /RESET below 0.2 × VDD anytime when reset is needed (all other inputs may be undefined). /RESET
needs to be maintained for minimum 100ns. CKE is pullow before /RESET being de-asserted (minimum time
10ns).
2. Follow Power-Up Initialization Sequence steps 2 t.
3. The reset sequence is now completed; DDR3 SDRAM is reamal operation.
Ta
Tb
Tc
Td
Te
Th
Ti
Tj
Tk
CK, /CK
VDD, VDDQ
/RESET
max. (10 ns; 5tCK)
100ns
500μs
tIS
10ns
CKE
2
*
tDLL
ZQCL
tXPR
tIS
tMRD
tMRD
MRS
MR3
tMRD
tMOD
tZt
Command
BA
1
MRS
MR2
MRS
MR1
MRS
MR0
*
tIS
ODT
DRAM_RTT
Notes: 1. From time point "Td" until"Tk", NOP or DESL commands must be
applied between MRS and ZQCL commands.
2. tXPR = max. (tXS; 5tCK)
: VIH or VIL
Reset Procedure at Power Stable Condition
Preliminary Data Sheet E0966E60 (Ver. 6.0)
60
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Programming the Mode Register
For application flexibility, various functions, features and modes are programmable in four mode registers, provided
by the DDR3 SDRAM, as user defined variables, and they must be programmed via a Mode Register Set (MRS)
command. As the default values of the Mode Registers (MR#) are not defined, content of mode registers must be
fully initialized and/or re-initialized, i.e. written, after Power-up and/or reset for proper operation. Also the contents of
the mode registers can be altered by re-executing the MRS command during normal operation. When programming
the megisters, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the
aced de register must be redefined when the MRS command is issued. MRS command and DLL Reset
not affearray contents, which means these commands can be executed any time after power-up without
ffectthe array contents.
The modregister set command cycle time, tMRD is required to complete the write operation to the mode register
d is the minimrequired between two MRS commands. The MRS command to non-MRS command delay,
tMD, is reqRAM to update the features except DLL reset and is the minimum time required from an
MRS commS command excluding NOP and DESL. The mode register contents can be changed
using the stiming requirements during normal operation as long as the DRAM is in idle state, i.e.
all banks aed state with tRP satisfied, all data bursts are completed and CKE is already high prior
to writing intgister. e mode registers are divided into various fields depending on the functionality
and/or modes.
Mode Register Set Comd Cycle Time (tMRD)
tMRD is the minimum tirequired from an MRS command to the next MRS command. As DLL enable and DLL
reset are both MRS commas, tMRD is applicable etween MRS to MR1 for DLL enable and MRS to MR0 for DLL
reset, and not tMOD.
/CK
CK
Command
MRS
NOP
MRS
NOP
tMRD
tMRD Timi
MRS Command to Non-MRS Command Delay (tMOD)
tMOD is the minimum time required from an MRS command to a non-MRnd luding NOP and DESL.
Note that additional restrictions may apply, for example, MRS to MR0 for d by read.
/CK
CK
Command
MRS
NOP
non-MRS
NOP
tMOD
Old
setting
Updating
New Settin
tMOD Timing
Preliminary Data Sheet E0966E60 (Ver. 6.0)
61
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
DDR3 SDRAM Mode Register 0 [MR0]
The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM.
It controls burst length, read burst type, /CAS latency, test mode, DLL reset, WR and DLL control for precharge
power-down, which include various vendor specific options to make DDR3 SDRAM useful for various applications.
The mode register is written by asserting low on /CS, /RAS, /CAS, /WE, BA0 and BA1, while controlling the states of
address pins according to the table below.
BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address field
0*1
0
0
PPD
WR
DLL TM /CAS latency RBT CL
BL
Mode register 0
Burst length
set
A7
0
Mode
Normal
Test
A3 Read burst type
A1
0
BL
8 (Fixed)
A0
0
0
1
Nibble sequential
Interleave
1
0
4 or 8 (on the fly)
4 (Fixed)
1
BA1 BA0
1
0
0
0
1
1
0
1
0
1
1
Reserved
1
Write recovery for autoprecharge
/CAS latency
MR
A11 A10 A9
WR
A6
0
A5
0
A4
0
A2
Latency
MR2
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Reserved
0
0
0
0
0
0
0
0
Reserved
MR3
2
5*
6*
7*
0
0
1
5
2
2
2
0
1
0
6
A12 DLL Control for Prece PD
0
1
1
7
0
1
Slow exit (DLL off)
Fast exit (DLL on)
1
0
0
8
1
0
1
9
10
1
1
0
rved
1
1
1
Reserved
Notes: 1. BA2 is reserved for future use and must be programmed tduring MRS.
2. WR (min.) (Write Recovery for autoprecharge) is deterK (max.) and WR (max.) is determined by tCK (min.).
WR in clock cycles is calculated by dividing tWR (in y tCK (in ns) and rounding up to the next integer
(WR (min.) [cycles] = roundup tWR (ns) / tCK (ns
(The WR value in the mode register must be programmed to be ger than WR (min.)
This is also used with tRP to determine tDAL.
MR0 Program
Preliminary Data Sheet E0966E60 (Ver. 6.0)
62
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
DDR3 SDRAM Mode Register 1 [MR1]
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom
impedance, additive latency, write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by
asserting low on /CS, /RAS, /CAS, /WE, high on BA0 and low on BA1, while controlling the states of address pins
according to the table below
A2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address field
0*1
1
0*1
0*1 Level Rtt_Nom D.I.C
AL
D.I.C DLL
Mode register 1
Rtt_Nom
Rtt_Nom
Qoff
TDQS
TDQS enable
RTT_Nom*5
ODT Disabled
RZQ/4
A9 A6 A2
Disabled
Enaled
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
A0
DLL enable
Enable
0
1
RZQ/2
Disable
RZQ/6
4
RZQ/12
*
Write eling enable
Diled
A7
4
RZQ/8
*
0
1
Reserved
Reserved
Enabled
Output driver
Qoff
Output buffers enabled
A12
0
A5
0
A1
0
impedance control
Reserved for RZQ/6
RZQ/7
A3
0
A4
0
Adve Latency
AL abled)
CL-1
2
Output buffers disabled
*
1
0
1
1
0
1
0
RZQ/TBD
0
1
1
1
RZQ/TBD
1
1
R
Notes: 1. BA2, A8 and A10 are reserved for future use (RFUd mugramed to 0 during MRS.
2. Outputs disabled - DQ, DQS, /DQS.
3. RZQ = 240Ω
4. If RTT_Nom is used during writes, only the values RZQ/2d RAQ/6 are allowed.
5. In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12]=1, all Nom sngs are allowed;
in Write Leveling Mode (MR1[bit7] =1) with MR1[bit12]=0, only RTT_Nsettings of RZQ/2,
RZQ/4 and RZQ/6 are allowed
MR1 Programming
Preliminary Data Sheet E0966E60 (Ver. 6.0)
63
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
DDR3 SDRAM Mode Register 2 [MR2]
The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and /CAS write
latency (CWL). The Mode Register 2 is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA1 and low on
BA0, while con-trolling the states of address pins according to the table below.
Address field
BA2 BA1 BA0 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0*1
1
0
Mode register 2
0*1
Rtt_WR
0*1 SRT ASR
CWL
PASR* 2
A7
Self-refresh range
Normal self-refresh
Partial array self-refresh
A2 A1 A0
Refresh array
xtend temperture
self-refresh
⎯
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full
(Optional)
(BA [2:0]
(BA [2:0]
(BA [2:0]
(BA [2:0]
(BA [2:0]
(BA [2:0]
(BA [2:0]
=
=
=
=
=
=
=
000, 001, 010, 011)
000, 001)
Half
: Bank 0 to Bank 3
Quarter: Bank 0 and Bank 1
000)
1/8
3/4
Half
: Bank 0
A6 Aelf-refresh method
010, 011, 100, 101,110 ,111)
100, 101, 110, 111)
110, 111)
: Bank 2 to Bank 7
: Bank 4 to Bank 7
anual SR reference
0
(SRT)
ASR enable
Quarter: Bank 6 and Bank 7
1/8 : Bank 7
(Optional)
111)
A5
0
A4
0
A3
CAS write Latency (CWL)
5 (tCK ≥ 2.5ns)
A10 A9
Rtt_WR
0
0
Dynamic ODT off (write dos not
affect Rtt value)
0
0
(2.5ns > tCK ≥ 1.875ns)
875ns > tCK ≥ 1.5ns)
5ns > tCK ≥ 1.25ns)
Reserved
0
0
1
1
1
0
1
RZQ/4
RZQ/2
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
rved
Notes: 1. BA2 is RFU and must be programmed to 0 during MRS.
2. Optiona in DDR3 SDRAM: If PASR (Partial Array Self-Refreshlocated in areas of the array beyond
the specified address range will be lost if self-refresh is enterell be maintained if tREF conditions are
met and no self-refresh command is issued.
MR2 Programm
Preliminary Data Sheet E0966E60 (Ver. 6.0)
64
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
DDR3 SDRAM Mode Register 3 [MR3]
The Mode Register MR3 controls Multi Purpose Registers (MPR). The Mode Register 3 is written by asserting low
on /CS, /RAS, /CAS, /WE, high on BA1 and BA0, while controlling the states of address pins according to the table
below.
Address field
BA2 BA1 BA0 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode register 3
0*1
0
1
MPR MPR Loc
MPR Address
A1 A0
MPR location
2
MPR Operation
A2
0
0
1
1
0
1
0
1
Predefined pattern*
MPR
RFU
RFU
RFU
3
Normal operation
*
0
1
Data flow from MPR
Notes : 1. BA2,oA12 are reserved for future use (RFU) and must be programmed to 0 during MRS.
2. The predned pattern will be used for read synchronization.
3 . When MPR ntrol is set for normaeration, MR3 A[2]=0, MR3 A[1:0] will be ignored.
ramming
Preliminary Data Sheet E0966E60 (Ver. 6.0)
65
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Burst Length (MR0)
Read and write accesses to the DDR3 are burst oriented, with the burst length being programmable, as shown in the
figure MR0 Programming. The burst length determines the maximum number of column locations that can be
accessed for a given read or write command. Burst length options include fixed BC4, fixed BL8, and on the fly which
allows BC4 or BL8 to be selected coincident with the registration of a read on write command Via A12 (/BC).
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Chop
n casf burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than
for the Bmode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of
rst length beined on the fly via A12(/BC), the internal write operation starts at the same point in time like a
buof 8 wrhis means that during on-the-fly control, the starting point for tWR and tWTR will not be
pulled in by
Burst Type
[Burst Length and Sequen
Starting address
(A2, A1, A0)
Sequential addressing
(decimal)
Interleave addressing
(decimal)
Burst length
Operat
READ
4 (burst chop)
000
001
010
0
100
101
110
111
0VV
1VV
000
001
010
011
100
101
110
111
VVV
0, 1, 2, 3, T, T, T, T
1, 2, 3, 0, T, T, T, T
2, 3, 0, 1, T, T, T, T
3, 0, 1, 2, T, T, T, T
4, 5, 6, 7, T, T, T, T
5, 6, 7, 4, T, T, T, T
64, 5, T, T, T, T
7, 4, 5, 6, T, T, T, T
X, X, X
, X, X
5, 6, 7
1, 2, 3, 0, 5, 6
2, 3, 0, 1, 6
3, 0, 1, 2, 7,
4, 5, 6, 7, 0, 1, 2,
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, T, T, T, T
1, 0, 3, 2, T, T, T, T
2, 3, 0, 1, T, T, T, T
3, 2, 1, 0, T, T, T, T
4, 5, 6, 7, T, T, T, T
5, 4, 7, 6, T, T, T, T
6, 7, 4, 5, T, T, T, T
7, 6, 5, 4, T, T, T, T
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, , 1, 0, 7, 6, 5, 4
5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 0, 3, 2
6, 7, , 2, 3, 0, 1
5, 4, 3
0, 1, 2, 5, 6, 7
WRITE
READ
8
WRITE
Remark: T: Output driver for data and strobes are in high impedance.
V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
X: Don’t Care.
Notes: 1. Page length is a function of I/O organization and column addressing
2. 0...7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
66
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
DLL Enable (MR1)
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon
returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self-
refresh operation and is automatically re-enabled upon exit of self-refresh operation. Any time the DLL is enabled
and subsequently reset, tDLLK clock cycles must occur before a read or synchronous ODT command can be issued
to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to
occur result in a violation of the tDQSCK, tAON or tAOF parameters. During tDLLK, CKE must continuously be
regred h.
DDR3 RAM does not require DLL for any write operation. DDR3 does not require DLL to be locked prior to any
write opetion. DDR3 requires DLL to be locked only for read operation and to achieve synchronous ODT timing.
DDisable
DDR3 DLLd by setting MR1 bit A0 to 1; this will disable the DLL for subsequent operations until
A0 bit set A0 bit for DLL control can be switched either during initialization or later.
The DLL-off s listeelow are an optional feature for DDR3. The maximum clock frequency for DLL-
off mode is 12re is ninimum frequency limit besides the need to satisfy the refresh interval, tREFI.
Due to latency counter and ng restrictions, only one value of /CAS Latency (CL) in MR0 and CAS Write Latency
(CWL) in MR2 are suppoThe DLL-off mode is only required to support setting of both CL = 6 and CWL = 6.
DLL-off mode will affect Read data Clock to Data Strobe relationship (tDQSCK) but not the Data Strobe to Data
relationship (tDQSQ, tQH, HS). Special attention is needed to line up Read data to controller time domain.
Comparing with DLL-on modwhere tDQSCK srom the rising clock edge (AL + CL) cycles after the Read
command, the DLL-off mode tDQSCK starts (Acycles after the read command. Another difference is that
tDQSCK may not be small compared to tCK e larger than tCK) and the difference between tDQSCK
(min.). and tDQSCK (max.) is significantly er -on mode.
The timing relations on DLL-off mode READ operatioshown at following Timing Diagram (CL = 6, BL8):
T0
T1
T2
T3
T5
T6
T7
T8
T9
CK, /CK
Command
READ
A
BA
DQSdiff_DLL-on
RL = AL + CL = 6 (CL = 6, AL = 0)
CL = 6
DQ_DLL-on
A0 CA1 2 CA3 CA4 CA5 CA6 CA7
RL (DLL-off) = AL + (CL - 1) = 5
tDQSCK(DLLf)_m
DQSdiff_DLL-off
DQ_DLL-off
CA0 CA1 CA2 CA3 CA4 5 CA6 CA7
tDQSCK(DLL-off)_max
DQSdiff_DLL-off
DQ_DLL-off
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7
DLL-Off Mode Read Timing Operation
Preliminary Data Sheet E0966E60 (Ver. 6.0)
67
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Switch from DLL “on” to DLL “off” and Required Frequency Change During Self-Refresh
1. Starting from Idle state (all banks pre-charged, all timings fulfilled, and DRAMs On-die Termination resistors,
RTT, must be in high impedance state before MRS to MR1 to disable the DLL.)
2. Set MR1 Bit A0 to “1” to disable the DLL.
3. Wait tMOD.
4. Eelf-Refresh Mode; wait until (tCKSRE) satisfied.
5ange quency, in guidance with Input Clock Frequency Change during Precharge Power-Down section.
t until a table clock is available for at least (tCKSRX) at DRAM inputs. After stable clock, wait tCKSRX
befissuing SRX commnad.
. Starting with tSelf-refresh exit command, ODT must continuously be registered low and CKE must
ontinuoused high until all tMOD timings from any MRS command are satisfied.
8. ait tXRegisters with appropriate values (especially an update of CL, CWL and WR may be
necessand may also be issued after tXS).
9. Wait for M is ready for next command.
Tb
Tc Tc+1Tc+2
Td
Te
Tf Tf+1 Tf+2
Tg Tg+1
Th
CK
/CK
tMOD
tCKSRE
tCKSRX
tXS
tMOD
MRS
SRE N
SRX
MRS
Valid
Command
CKE
KESR
ODT
Cange Frequ
Preliminary Data Sheet E0966E60 (Ver. 6.0)
68
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Switch from DLL “off” to DLL “on” (with required frequency change) During Self-Refresh
1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT)
must be in high impedance state before Self-Refresh mode is entered.)
2. Enter Self-refresh Mode, wait until tCKSRE satisfied.
3. Change frequency, in guidance with Input Clock Frequency Change during Precharge Power-Down section.
4. Wil a stable clock is available for at least (tCKSRX) at DRAM inputs.
5arting th the self-refresh exit command, ODT must continuously be registered low and CKE must
tinuousbe registered high until all tDLLK timing from subsequent DLL Reset command is satisfied.
6. WaS, then set MR1 bit A0 to “0” to enable the DLL.
. Wait tMRD, thet MR0 bit A8 to “1” to start DLL Reset.
8Wait tMRMode Registers with appropriate values (especially an update of CL, CWL and WR may
bneceD is satisfied from any proceeding MRS command, a ZQCL command may also be
issued K.)
9. Wait foDRAM is ready for next command (remember to wait tDLLK after DLL Reset before
applying uiring cked DLL!). In addition, wait also for tZQoper in case a ZQCL command was
issued.
Ta
Tc Tc+1Tc+2
Td
Te
Tf Tf+1Tf+2
Tg
CK
/CK
tCKSRE
tCKSRX
tDLLK
MRS
tXS
tMRD tMRD
SRE N
SRX
MRS
MRS
Valid
Command
CKE
ODTLoff + 1x
ODT
Change Freque
Preliminary Data Sheet E0966E60 (Ver. 6.0)
69
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Additive Latency (MR1)
A posted /CAS read or write command when issued is held for the time of the Additive Latency (AL) before it is
issued inside the device. The read or write posted /CAS command may be issued with or without auto precharge.
The Read Latency (RL) is controlled by the sum of AL and the /CAS latency (CL).
The value of AL is also added to compute the overall Write Latency (WL).
MR) bA4 and A3 are used to enable Additive latency.
A4
A3
0
AL*
0 (posted CAS disabled)
CL − 1
0
1
1
0
CL − 2
1
1
Reserved
Note: AL haL − 1 oL − 2 as per the CL value programmed in the /CAS latency MRS setting.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
70
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Write Leveling (MR1)
For better signal integrity, DDR3 memory module adopts fly by topology for the commands, addresses, control
signals and clocks. The fly by topology has benefits for reducing number of stubs and their length but in other
aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes Controller hard to
maintain tDQSS, tDSS and tDSH specification. Therefore, the controller should support ’write leveling’ in DDR3
SDRAM to compensate the skew.
Wlevelis a scheme to adjust DQS to CK relationship by the controller, with a simple feedback provided by the
. The mory controller involved in the leveling must have adjustable delay setting on DQS to align the rising
edge QS with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK, sampled with the rising
edge of S, through the DQ bus. The controller repeatedly delays DQS until a transition from 0 to 1 is detected.
e DQS delay ed through this exercise would ensure tDQSS, tDSS and tDSH specification. A conceptual
timof this wn as below.
Destination
diock
iff_DQS
DQ
X
0
Push DQS to
capture 0-1 transition
DQ
X
1
Wrig concept
DQS, /DQS driven by the controller during leveling mode must be terminated by the DRAM, based on the ranks
populated. Similarly, the DQ bus driven by the DRAM muso be terminated at the controller.
One or more data bits should carry the leveling feedbto the controller across the DRAM configurations ×4, ×8
and ×16. On a ×16 device, both byte lanes should e levelized independently. Therefore, a separate feedback
mechanism should be available for each byte lane. The upper should provide the feedback of the upper
diff_DQS (diff_DQSU) to clock relationship whereas the its would indicate the lower diff_DQS
(diff_DQSL) to clock relationship.
DRAM Setting for Write Leveling and DRAM Termination Function in
DRAM enters into Write leveling mode if A7 in MR1 set 1. And after ing, DRAM exits from write
leveling mode if A7 in MR1 set 0 (MR1 Setting Involved in the Leveling Proe).
Note that in write leveling mode, only DQS/DQS terminations are activated adeactid via ODT pin, not like
normal operation (refer to the DRAM Termination Function in The Leveling Mode table
[MR1 Setting Involved in the Leveling Procedure]
Function
MR1 bit
A7
Enable
Disable
e
1
Write leveling enable
Output buffer mode (Qoff)
1
0
0
1
A12
Note: 1. Output buffer mode definition is consistent with DDR2
[DRAM Termination Function in The Leveling Mode]
ODT pin@DRAM
De-asserted
Asserted
DQS, /DQS termination
DQs termination
Off
On
Off
Off
Note: In Write Leveling Mode with its output buffer disabled (MR1 [bit7] = 1 with MR1 [bit12] = 1) all RTT_Nom
settings are allowed; in Write Leveling Mode with its output buffer enabled (MR1 [bit7] = 1 with MR1 [bit12] =
0) only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
71
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Write Leveling Procedure
Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. Since the controller levelizes
rank at a time, the output of other rank must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT
after tMOD, time at which DRAM is ready to accept the ODT signal.
Controller may drive DQS low and /DQS high after a delay of tWLDQSEN, at which time DRAM has applied on-die
terminn on these signals. After tWLMRD, controller provides a single DQS, /DQS edge which is used by the
DRto ple CK driven from controller. tWLMRD timing is controller dependent.
samplCK status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after
WLO ming. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read
strobes QS, /DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or
crement DQS setting and launches the next DQS, /DQS pulse after some time, which is controller
dndent.
Once a 0 tetected, the controller locks DQS delay setting and write leveling is achieved for the
device. Thcribes detailed timing diagram for overall procedure and the timing parameters are
shown in b
T2
T1
tWLS
tWLS
tWLH
tWLH
NOP
5
*
CK
/CK
2
3
4
2
3
*
*
*
Command MRS
NO
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tMOD
6
*
ODT
tDQSH (min.)
tDH (min.) tDQSL (min.)
tWLDQSEN
diff_DQS*4
tWLOE
tW
tWLMRD
tWLO
All DQs,
Prime DQ*1
Remaining
DQs
Notes:1. DRAM has the option to drive leveling feedback on a prime all Dback idriven only on one DQ,
the remaining DQs must be driven low as shown in above Figure, and at state through out
the leveling procedure.
2. MRS : Load MR1 to enter write leveling mode.
3. NOP : NOP or deselec
4. diff_DQS is the differential data strobe (DQS, /DQS). Timing reference poire the crossing. DQS is
shown with solid line, /DQS is shown with dotted line.
5. CK, /CK : CK is shown with solid dark line, where as /CK is drawn with dotted line
6. DQS needs to fulfill minimum pulse width requirements tDQSH (min.) and tDQSL n.) as ded for regular
writes; the max pulse width is system dependent.
Timing Details Write leveling Sequence
Preliminary Data Sheet E0966E60 (Ver. 6.0)
72
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Write Leveling Mode Exit
The following sequence describes how Write Leveling Mode should be exited:
1. After the last rising strobe (see T111) edge stop driving the strobe signals (see ~T128). Note: From now on, DQ
pins are in undefined driving mode, and will remain undefined, until tMOD after the respective MR command
(T145).
2. Drive ODT pin low (tIS must be satisfied) and keep it low (see T128).
3. Ae RTT is switched off: disable Write Level Mode via MR command (see T132).
4. er tMis satisfied (T145), any valid commands may be registered. (MR commands may already be issued
er tMRD 136).
T111
T112
T116
T117
T128 T131
T132
T136
T145
CK, /CK
Com
WL_off
1
MRS
Valid
tMOD
Valid
VVaalidlid
tIS
tMRD
ODT
tODTL_off
RTT_DQS-/DQS
DQS-/DQS
RTT_DQ
tWLO + tWLOE
DQ
Result = 1
Timing Details ite leeling Exit
[Related Parameters]
Symbol
Parameter
min.
40
max.
Unit
First DQS pulse rising edge after write leveling mode i
programmed
1
1
tWLMRD
tWLDQSEN
tWLS
*
*
tCK
tCK
tCK
DQS, /DQS delay after write leveling mode is programmed
Write leveling setup time from rising CK, /CK crossing to rising
DQS, /DQS crossing
Write leveling hold time from rising DQS, /DQS crossing to rising
CK, /CK crossing
tWLH
0.15
*
tCK
tWLO
Write leveling output delay
Write leveling output error
0
10
2
ns
ns
tWLOE
⎯
Note: 1. The max values are system dependent.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
73
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
TDQS, /TDQS function (MR1)
TDQS (Termination Data Strobe) is a feature of ×8 DDR3 SDRAM that provides additional termination resistance
outputs that may be useful in some system configurations.
TDQS is not supported in ×4 or ×16 configurations. When enabled via the mode register, the same termination
resistance function is applied to the TDQS and /TDQS pins that are applied to the DQS and /DQS pins.
In contst to the RDQS function of DDR2 SDRAM, TDQS provides the termination resistance function only. The
data function of RDQS is not provided by TDQS.
TDQS DM functions share the same pin. When the TDQS function is enabled via the mode register, the DM
ncn is not pported. When the TDQS function is disabled, the DM function is provided and the /TDQS pin is
not useSee Table TDQS, /TDQS function for details.
he TDQS function is available in ×8 DDR3 SDRAM only and must be disabled via the mode register A11 = 0 in
1 for ×4 anurations.
[TDQS, /TD
A11@MR1
TDQS enable
Disable
0
1
Enable
Notes: 1. If TDQS is enabthe DM function is disabled.
2. When not usTDQS function can be disabled to save termination power
3. TDQS function nly available for ×8 DRAM and must be disabled for ×4 and ×16
[Function matrix]
A11@MR1 (TDQS enable)
DM/T
D
NU/ /TDQS
High-Z
0
1
DQS
/TDQS
Preliminary Data Sheet E0966E60 (Ver. 6.0)
74
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Extended Temperature Usage (MR2)
[Mode Register Description]
Field Bits Description
Description
Auto self-refresh (ASR) (Optional)
when enabled, DDR3 SDRAM automatically
provides self-refresh power management functions
for all supported operating temperature values. If
not enabled, the SRT bit must be programmed to
indicate TC during subsequent self-refresh
operation
0
Manual SR Reference (SRT)
ASR enable (optional)
ASR
SR
6
A7
Self-Refresh Temperature (SRT) Range
If ASR = 0, the SRT bit must be programmed to
indicate TC during subsequent self-refresh
operation
0
l operating temperature range
d (optional) operating temperature range
If ASR = 1, SRT bit must be set to 0
Auto Self-Re- ASR de (optional)
DDR3 SDRAM provides an o Self-Refresh mode (ASR) for application ease. ASR mode is enabled by setting
MR2 bit A6 = 1 and MR2 A7 = 0. The DRAM will manage self-refresh entry in either the Normal or Extended
(optional) Temperature ges. In this mode, the DRAM will also manage self-refresh power consumption when the
DRAM operating temperae changes, lower at low temperatures and higher at high temperatures.
If the ASR option is not suppd by the DRAM, Mbit A6 must be set to 0.
If the ASR mode is not enabled (MR2 bit A6 = RT bit (MR2 A7) must be manually programmed with the
operating temperature range required during ration.
Support of the ASR option does not automallort of the Extended Temperature Range.
Self- Refresh Temperature Range - SRT (optional)
If ASR = 0, the Self-Refresh Temperature (SRT) Range mbe programmed to guarantee proper self-refresh
operation. If SRT = 0, then the DRAM will set an appriate refresh rate for self-refresh operation in the Normal
Temperature Range. If SRT = 1 then the DRAM wiset an appte, potentially different, refresh rate to allow
self-refresh operation in either the Normal or Extended Tempges. The value of the SRT bit can effect
self-refresh power consumption, please refer to the IDD table
For parts that do not support the Extended Temperature Rang7 must be set to 0 and the DRAM should
not be operated outside the Normal Temperature Range.
[Self-Refresh Mode Summary]
MR2
ed openg temperature range
A6
0
A7
0
Self-refresh operation
r self-reh mode
Self-refresh rate appropriate for the Normal Temperature Range
Norm°C to +85
Self-refresh rate appropriate for either the Normal or Extended
Temperature Ranges. The DRAM must support Extended
Temperature Range. The value of the SRT bit can effect self-
refresh power consumption, please refer to the Self- refresh
Current for details.
0
1
1
0
Normal and tended to 5°C)
ASR enabled (for devices supporting ASR and Normal
Temperature Range). Self-refresh power consumption is
temperature dependent
Normal (0°C to +85°C)
ASR enabled (for devices supporting ASR and Extended
Temperature Range). Self-refresh power consumption is
temperature dependent
1
1
0
1
Normal and Extended (0°C to +°C)
Illegal
Preliminary Data Sheet E0966E60 (Ver. 6.0)
75
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Multi Purpose Register (MR3)
The Multi Purpose Register (MPR) function is used to read out predefined system timing calibration bit sequence.
ConceptuaBlock Diof Multi Purpose Register
To enable the MPR, a mode register set (MRS) commamuse issued to MR3 register with bit A2 = 1. Prior to
issuing the MRS command, all banks must be in the state (all banks precharged and tRP/tRPA met). Once the
MPR is enabled, any subsequent READ or READA commands edirected to the multi purpose register. The
resulting operation when a READ or READA command is issd by MR3 bits [A1: A0] when the MPR is
enabled. When the MPR is enabled, only READ or REAs are allowed until a subsequent MRS
command is issued with the MPR disabled (MR3 bit A2=0). mode, self-refresh, and any other non-
READ/READA command are not allowed during MPR enable moe /REunction is supported during MPR
enable mode.
[Functional Description of MR3 Bits for MPR]
MR3
A2
A [1:0]
MPR
MPR-Loc
Function
Notes
Normal operation, no MPR transaction.
Don’t care
(0 or 1)
0
All subsequent reads will come from DRAM array.
All subsequent WRITEs will go to DRAM array.
Enable MPR mode, subsequent READ/READA commands defined by MR3 1:0]
bits.
1
MR3 A [1:0]
1
Note: 1. See Available Data Locations and Burst Order Bit Mapping for Multi Purpose Register table
Preliminary Data Sheet E0966E60 (Ver. 6.0)
76
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
• One bit wide logical interface via all DQ pins during READ operation
⎯ Register Read on ×4:
DQ [0] drives information from MPR.
DQ [3:1] either drive the same information as DQ [0], or they drive 0.
⎯ Register Read on ×8:
DQ [0] drives information from MPR.
DQ [7:1] either drive the same information as DQ [0], or they drive 0.
⎯ Rr Read on ×16:
L [0d DQU [0] drive information from MPR.
QL [7:1] d DQU [7:1] either drive the same information as DQL [0], or they drive 0.
Note: standardization of which DQ is used by DDR3 SDRAM for MPR reads is strongly recommended to ensure
futionality also for AMB2 on DDR3 FB-DIMM.
• Aessinrpose Register reads for all MPR agents:
⎯ BA [2:0
⎯ A [1:0]: ual to ‘00’b. Data read burst order in nibble is fixed
⎯ A [2]:
For BL8, A t be eqto 0.
Burst order is fixed to [,3,4,5,6,7] *1
For Burst Chop 4 cathe burst order is switched on nibble base
A [2] = 0, Burst or0,1,2,3 *1
A [2] = 1, Burst orde,5,6,7 *1
⎯ A [9:3]: don’t care
⎯ A10(AP): don’t care
⎯ A12(/BC): Selects burst chop mode on-twithin MR0
⎯ A11: don’t care
• Regular interface functionality during register reads:
⎯ Support two burst ordering which are switched with Ad A :0] = 00.
⎯ Support of read burst chop (MRS and on-the-fly vi12(/BC).
All other address bits (remaining column address bits including Ank address bits) will be ignored by the
DDR3 SDRAM.
⎯ Regular read latencies and AC timings apply.
⎯ DLL must be locked prior to MPR Reads.
Note: Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned the ected MPR agent.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
77
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Functional Block Diagrams
Figures below provide functional block diagrams for the multi purpose register in ×4, ×8 and ×16 DDR3 SDRAM.
Memory Array
4×8
DQ[3:0]
Read Path
DQS
MPR
/DQS
DM
NibbleLane
Functional Block Dim opose Register in ×4 DDR3 SDRAM
Memory Array
8×8
8×8
64
Copy to
DQ[7:0]
DQ[7:0]
8
Q
Read Path
DQS
MPR
/DQS
M
ByteLane
Functional Block Diagram of Multi Purpose Register in ×8 DDR3 SDRAM
Preliminary Data Sheet E0966E60 (Ver. 6.0)
78
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Memory Array
DQU[7:0]
Read Path
DQSU
/DQSU
8×8
8×8
64
DMU
ByteLaneUpper
8×8
8×
64
Copy to
DQL[7:0]
DQL[7:0]
8
Q
Read Path
DQSL
MPR
/DQSL
DML
ByteLaneLower
Functional Block Diagram of Multi Purpon ×16 DDR3 SDRAM
Preliminary Data Sheet E0966E60 (Ver. 6.0)
79
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Register Address Table
The table below provides an overview of the available data locations, how they are addressed by MR3 A [1:0] during
a MR0 to MR3, and how their individual bits are mapped into the burst order bits during a multi purpose register
read.
[Availale Data Locations and Burst Order Bit Mapping for Multi Purpose Register]
Read
MR
A
3
A [
Burst
Length
Function
Address Burst Order and Data Pattern
A [2:0]
Notes
Burst order 0,1,2,3,4,5,6,7
000
BL8
BC4
BC4
1
1
1
Pre-defined pattern [0,1,0,1,0,1,0,1]
Read predefined
for
Burst order 0,1,2,3,
000
00
Pre-defined pattern [0,1,0,1]
Burst order 4,5,6,7
100
Pre-defined pattern [0,1,0,1]
BL8
C4
BC4
BL8
BC4
BC4
BL8
BC4
BC4
000
000
100
000
000
100
0
100
Burst order 0,1,2,3,4,5,6,7
Burst order 0,1,2,3
1
1
1
1
1
1
1
1
1
1
1
1
01
10
11
RFU
RFU
Burst order 4,5,6,7
Burst order 0,1,2,3,4,5,6,7
Burst order 0,1,2,3
Burst order 4,5,6,7
st order 0,1,2,3,4,5,6,7
order 0,1,2,3,
order 4,5,6,7
Note: 1. Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
Relevant Timing Parameters
The following AC timing parameters are important for operating i Purpose Register: tRP, tMRD, tMOD and
tMPRR.
Besides these timings, all other timing parameters needed fration of the DDR3 SDRAM need to be
observed.
[MPR Recovery Time tMPRR]
Symbol
tMPRR
Description
Multi Purpose Register Recovery Time, defined between enMPR burst and MRS which
reloads MPR or disables MPR function
Preliminary Data Sheet E0966E60 (Ver. 6.0)
80
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Protocol Examples
Protocol Example: Read Out Predetermined Read-Calibration Pattern
Multiple reads from Multi Purpose Register, in order to do system level read timing calibration based on
predetermined and standardized pattern.
Protteps:
• harge l
Wuntil tRP s satisfied
• MRS 3, op-code “A2 = 1 “ and “A[1:0] = 00“
Redirect all suent reads into the Multi Purpose Register, and load Pre-defined pattern into MPR.
• it until tare satisfied (Multi Purpose Register is then ready to be read). During the period
MR3 A2 peration is allowed.
• Read:
⎯ A [1:0] = t order fixed starting at nibble, always 00 here)
⎯ A [2] = ‘0’ burst ois fixed as 0,1,2,3,4,5,6,7)
⎯ A12(/BC) = 1 (use regularst length of 8)
⎯ All other address pins cluding BA [2:0] and A10(AP)): don’t care.
• After RL = AL + CL, DRM bursts out the predefined Read Calibration Pattern.
• Memory controller repeats ese calibration reads ntil read data capture at memory controller is optimized.
• After end of last MPR read but wait until tMPRtisfied.
• MRS MR3, op-code “A2 = 0“ and “A[1:0] = alue are don’t care“
⎯ All subsequent read and write accessel EADs and WRITEs from/to the DRAM array.
• Wait until tMRD and tMOD are satisfied
• Continue with “regular” DRAM commands, like activate a mmory bank for regular read or write access,
T0
T4 T5
T9
T17 T18 T19 T21 T23 T24 T25 T26 T27 T28 T29 T30 T31
T39
CK
/CK
tMRD
tMOD
1
*
Command
PALL
MRS
READ
MRS
tMPRR
NOP
tRP
NOP
NOP
tMOD
3
0
Valid
3
BA
2
*
0
0
id
A[1:0]
2
*
1
0
A[2]
00
Valid
Valid
Valid
A[9:3]
1
0
0
0
0
0
0
0
A10(AP)
A[11]
1
*
A12(/BC)
A[15:13]
Valid
Valid
DQS, /DQS
DQ
RL
Notes: 1. READ with BL8 either by MRS or OTF
2. Memory Control must drive 0 on A[2:0]
VIH or VIL
MPR Readout of Predefined Pattern, BL8 fixed Burst Order, Single Readout
Preliminary Data Sheet E0966E60 (Ver. 6.0)
81
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T4 T5
T9
T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31
T43
CK
/CK
tMRD
tMOD
MRS
tMPRR
1
1
*
*
Command
PALL NOP MRS
tRP
NOP
READ
NOP
READ
NOP
NOP
tMOD
tCCD
3
3
Valid
Valid
2
2
*
*
*
*
[1:0]
[2]
0
1
0
0
0
0
Valid
0
2
2
00
00
0
A[9:
Valid
Valid
Valid
Valid
Valid
Valid
0
0
A10, AP
A[11]
0
0
0
1
1
*
*
A12(/BC)
A[15:13]
Valid
Valid
Valid
Valid
DQS, /DQS
RL
RL
DQ
Notes: 1. READ with BL8 either by MRS or OTF
2. Memory Control must drive 0 on A[2:0]
VIH or VIL
T43
MPR Readout of Predefinexed Burst Order, Back-to-Back Readout
T0
T4 T5
T9
T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31
CK
/CK
tMRD
tMOD
1
1
*
*
Command
PALL NOP MRS
tRP
NOP
READ
NO
READ
MRS
tMPRR
NOP
NOP
tMOD
tCCD
3
0
3
Valid
0
BA
A[1:0]
Valid
Va
2
*
*
0
0
0
1
3
4
*
1
A[2]
00
00
0
Valid
Valid
Valid
Valid
Valid
Valid
A[9:3]
1
0
0
0
0
A10(AP)
A[11]
0
0
1
1
*
*
A12(/BC)
A[15:13]
Valid
Valid
Valid
Valid
DQS, /DQS
DQ
RL
RL
VIr VIL
Notes:1. READ with BC4 either by MRS or OTF
2. Memory Control must drive 0 on A[1:0]
3. A[2] = 0 selects lower 4 nibble bits 0 ... 3
4. A[2] = 1 selects upper 4 nibble bits 4 ... 7
MPR Readout Predefined Pattern, BC4, Lower Nibble Then Upper Nibble
Preliminary Data Sheet E0966E60 (Ver. 6.0)
82
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T4 T5
T9
T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31
T43
CK, /CK
tMRD
tMOD
1
1
*
*
Command
PALL NOP MRS
tRP
NOP
READ
NOP
READ
MRS
tMPRR
NOP
NOP
tMOD
tCCD
3
0
3
Valid
0
[1:0]
Valid
Valid
2
2
*
*
*
0
1
0
0
4
3
*
1
[2]
00
00
0
Valid
Valid
Valid
Valid
Valid
Valid
A[9
0
A10, AP
A[11]
0
0
0
1
1
*
*
A12(/BC)
A[15:13]
Valid
Valid
Valid
Valid
DQS, /DQS
DQ
RL
RL
Notes:1. READ with BC4 either by MRS or OTF
2. Memory Control must drive 0 on A[1:0]
3. A[2] = 0 selects lower 4 nibble bits 0 .
4. A[2] = 1 selects upper 4 nibble bits 7
VIH or VIL
MPR Readout of Predefined Pattern, BC4, Upper Nibble Then Lower Nibble
Preliminary Data Sheet E0966E60 (Ver. 6.0)
83
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Operation of the DDR3 SDRAM
Read Timing Definition
• CK, /CK crossing to DQS, /DQS crossing
• tDQSK; rising edges only of CK and DQS
• tQrg edges of DQS to falling edges of DQS
• L; risindges of / DQS to falling edges of /DQS
tLZ QS), tHZ (DQS) for preamble/postamble (see tHZ (DQS), tLZ (DQS)
RL Measured to this point
CK
/C
tDQmin.)
tDQSCK(min.)
tDQSCK(min.)
tDQSCK(min.)
tLZ(DQS)(min.)
tQSL
tQSH
tRPRE
tRPST
DQS, /DQS
Early strobe
Bit0
Bit
3
Bit4
Bit5
Bit6
Bit7
tDQS(max.)
tmax.)
tQSL
tDQSCK(max.) tDQSCK(max.)
tLZ(DQS)(max.)
tHZ(DQS)(max.)
tQSH
tRPRE
tRPST
DQS, /DQS
Late strobe
Bit0
Bit1
Bit2
Bit5
Bit6
Bit7
Notes: Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(mK(m
Instead, rising strobe edge can vary between tDQSCK(min.) or tDQSCK(max.) wit
Likewise tLZ(DQS)(min.) and tHZ(DQS)(min.) are not tied to tDQSCK(min.) (earl
tLZ(DQS)(max.) and tHZ(DQS)(max.) are not tied to tDQSCK(max.) (late strobe c
The minimum pulse width of read preamble is defined by tRPRE(min.).
The minimum pulse width of read preamble is defined by tRPST(min.).
DDR3 Clock to Data Strobe Relationship
Preliminary Data Sheet E0966E60 (Ver. 6.0)
84
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
• DQS, /DQS crossing to Data Output
• tDQSQ; both rising/falling edges of DQS, no tAC defined
T0
T4
T5
T6
T7
T8
T9
T10
/CK
CK
mand*3
READ
NOP
RL = AL + CL
Bank
Coln
Address
tRPRE
tQH
tQH
tRPST
DQS, /D
tDQSQ(max.)
tDQSQ(max.)
tLZ(DQ)(max.)
tHZ(DQ)(max.)
Dout Dout
n+1
Dout Dout
n+2 n+3
Dout Dout Dout Dout
n+4 n+5 n+6 n+7
DQ*2
n
tLZ(DQ)(min.)
(Last data valid)
Dout Dout
n+1
Dout Dout
n+2 n+3
Dout Dout Dout Dout
n+4 n+5 n+6 n+7
DQ*2
n
(First data no longer valid)
D
t
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
All DQS collectively
Data valid
VIH or VIL
Notes: 1. BL8, RL = 5(AL = 0, CL = 5).
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of ation; other commands may be valid at these times.
4. BL8 setting activated by MR0 bit [A1, [0, 0] and A12 during READ command at T0.
5. Output timings are referenced to VDDQ/2, and DLL o
6. tDQSQ defines the skew between DQS, /DQS to define DQS, /DQS to clock.
7. Early data transitions may not always happen at th
Data transitions of a DQ can vary(either early or la
DDR3 Data Strobe to Datship
tLZ (DQS), tLZ (DQ), tHZ (DQS), tHZ (DQ) Notes
tHZ and tLZ transitions occur in the same access time as valid data transitionsese paeters are referenced to
a specific voltage level which specifies when the device output is no longer drivig tHZ(S) and tHZ(DQ), or begins
driving tLZ(DQS), tLZ(DQ). The figure below shows a method to calculate the point wn device o longer driving
tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signt two rent voltages. The
actual voltage measurement points are not critical as long as the calculation is cont. The parameters
tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as singled ended.
VTT + 2x mV
VTT + x mV
VOH − x mV
VOH − 2x mV
tLZ (DQS), tLZ (DQ
tHZ (DQS), tHZ (DQ)
VTT − x mV
VOL + 2x mV
VOL + x mV
T2
T1
VTT − 2x mV
T1
T2
tHZ (DQS), tHZ (DQ) end point = 2 × T1 - T2
tLZ (DQS), tLZ (DQ) begin point = 2 × T1 - T2
Method for Calculating Transitions and Endpoints
Preliminary Data Sheet E0966E60 (Ver. 6.0)
85
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Read Operation
During read or write command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or
WRITE (auto precharge can be enabled or disabled).
• A12 = 0, BC4 (BC4 = burst chop, tCCD = 4)
• A12 = 1, BL8
A12 wile used only for burst length control, not a column address.
urst Rcommand is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising
dge the clok. The address inputs determine the starting column address for the burst. The delay from the start
of the cmand to when the data from the first cell appears on the outputs is equal to the value of the read latency
RL). The data strooutput (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus.
Tfirst bit osynchronized with the rising edge of the data strobe (DQS). Each subsequent data-out
apprs on se with the DQS signal in a source synchronous manner.
The RL is latency (AL) plus /CAS latency (CL). The CL is defined by the mode register 0 (MR0),
similar to thd DDR-I SDRAMs. The AL is defined by the mode register 1
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
/CK
Command*3
Address*4
READ
NOP
Bank
Col n
tRPST
tRPRE
DQS, /DQS
DQ*2
Dout Dout Dout
n+5 n+6 n+7
Dout
n
CL = 5
RL = AL + CL
VIH or VIL
Notes: 1. BL8, AL = 0, RL = 5, CL = 5
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid ase times.
4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A11 durEAD command at T0.
Burst Read Operation, RL = 5
Preliminary Data Sheet E0966E60 (Ver. 6.0)
86
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12
T13
CK
/CK
Command*3
A4
READ
NOP
Bank
Col n
tRPST
tRPRE
DQS, /S*2
D
Dout Dout Dout Dout Dout Dout Dout Dout
n+1 n+2 n+3 n+4 n+5 n+6 n+7
n
AL = 4
CL = 5
RL = AL + CL
VIH or VIL
Notes: 1. BL8, RL = 9, (CL − 1), CL = 5
2. Dout n = dat from column n.
3. NOP commanre shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activaby either MR0 bit [A1, A[0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0.
Buration, RL = 9
T0
T3
T
T5
T7
T8
T9
T10
T11
T12
T13 T14
CK
/CK
Command*3
READ
READ
NOP
NOP
tCCD
Address*4
Bank
Col n
Bank
Col b
tRPST
tRPRE
DQS, /DQS
DQ*2
Dout Dout Dout Dout Dout Dout Dout Dout Dout DDout Dout Dout Dout Dout
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
b
b+1 b+2 b+b+5 b+6 b+7
RL = 5
RL = 5
VIr VIL
Notes: 1. BL8, RL = 5 (CL = 5, AL = 0).
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at TT4.
READ (BL8) to READ (BL8)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
87
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13 T14
CK
/CK
Command*3
Ass*
READ
READ
NOP
NOP
tCCD
Bank
Col b
Bank
Col n
tRPST
tRPST
tRPRE
tRPRE
DQS, /D
DQ*
Dout Dout Dout Dout
Dout Dout Dout Dout
b+1 b+2 b+3
n
n+1 n+2 n+3
b
RL = 5
RL = 5
VIH or VIL
Notes: 1. BC4, RL = 5 (C, AL = 0).
2. Dout n (or bta-out from column n (or column b).
3. NOP commanre shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activby MR0 bit [A1, A0] = [1, 0or MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0 and T4.
READ (BC4)
T0
T3
T4
T5
T6
T7
8
T9
T10
T11
T12
T13 T14 T15
CK
/CK
Command*3
READ
WRIT
NOP
NOP
tWR
READ to WRIT command delay = RL + tCCD + 2tCK − WL
tBL = 4 clocks
tWTR
Address*4
Bank
Col n
Bank
Col b
tRPRE
tRPST
tWPST
DQS, /DQS
DQ*2
Dout Dout Dout Dout Dout Dout Dout Dout
Din Din Din
Din DDin
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
b
b+b+3 b+4 6 b+7
RL = 5
WL = 5
VIH IL
Notes: 1. BL8, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0).
2. Dout n = data-out from column n, Din b= data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0 and IT comm6.
READ (BL8) to WRITE (BL8)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
88
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13 T14 T15
CK
/CK
Command*3
READ
WRIT
NOP
NOP
tWR
READ to WRIT Command delay = RL + tCCD/2 + 2tCK − WL
tBL = 4 clocks
tWTR
Bank
Col n
Bank
Col b
Ass*
tRPRE
tRPST
tWPRE
tWPST
DQS, /D
DQ*2
Dout Dout Dout Dout
n+1 n+2 n+3
Din Din Din Din
b+1 b+2 b+3
n
b
5
WL = 5
VIH or VIL
Notes: 1. BC4, RL = 5 (CL = 5, AL = L = 5 (CWL = 5, AL = 0).
2. Dout n = data-out from cn n, Din b= data-in from column b.
3. NOP commands are for ease of illustration; other commands may be valid at these times.
4. BC4 setting activatMR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0 and WRIT command T4.
READ (BCo WRITE (BC4) OTF
T0
T4
T5
T7
T8
T9
T10
T11
T12
T13 T14
CK
/CK
Command*3
READ
READ
NOP
NOP
tCCD
Bank
Col n
Bank
Col b
Address*4
tRPST
tRPRE
DQS, /DQS
DQ*2
Dout Dout Dout Dout Dout Dout Dout Dout ut
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
b
b+3
RL = 5
RL = 5
IH or VIL
Notes: 1. RL = 5 (CL = 5, AL = 0).
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T4.
BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0.
READ (BL8) to READ (BC4) OTF
Preliminary Data Sheet E0966E60 (Ver. 6.0)
89
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13 T14
CK
/CK
Command*3
As*
READ
READ
NOP
NOP
tCCD
Bank
Col n
Bank
Col b
tRPST
tRPRE
tRPRE
tRPST
DQS, /D
DQ*
Dout Dout Dout Dout
Dout Dout Dout Dout Dout Dout Dout Dout
b+1 b+2 b+3 b+4 b+5 b+6 b+7
n
n+1 n+2 n+3
b
RL = 5
RL = 5
VIH or VIL
Notes: 1. RL = 5 (CL = 5, 0).
2. Dout n (or bta-out from column n (or column b).
3. NOP commanre shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activd by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0.
BL8 setting activatey MR0 bit [A1, A0] = [0nd A12 = 1 during READ command at T4.
READ (BL8) OTF
T0
T3
T4
T5
T6
7
T8
T9
T10
T11
T12
T13 T14 T15
CK
/CK
Command*3
READ
WRIT
NOP
NOP
tWR
tBL = 4 clocks
READ to WRIT command delay = RL + tCCD/2 + 2tCK − WL
tWTR
Address*4
Bank
Col n
Bank
Col b
tRPST
tWPST
tWPRE
tRPRE
DQS, /DQS
DQ*2
Dout Dout Dout Dout
n+1 n+2 n+3
Din Din Din Din
Din D
Din
n
b
b+1 b+2 b+3 b+4 6 b+7
RL = 5
WL = 5
or VIL
Notes: 1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0).
2. Dout n = data-out from column n , Din b= data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0.
BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T4.
READ (BC4) to WRITE (BL8) OTF
Preliminary Data Sheet E0966E60 (Ver. 6.0)
90
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13 T14 T15
CK
/CK
Command*3
READ
WRIT
NOP
NOP
tWR
READ to WRIT command delay = RL + tCCD + 2tCK − WL
tBL = 4 clocks
tWTR
Bank
Col n
Bank
Col b
As*
tRPRE
tRPST
tWPRE
tWPST
DQS, /D
DQ*2
Dout Dout Dout Dout Dout Dout Dout Dout
Din Din Din Din
b+1 b+2 b+3
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
b
5
WL = 5
VIH or VIL
Notes: 1. RL = 5 (CL = 5, AL = 0), W(CWL = 5, AL = 0).
2. Dout n = data-out from n n, n Din b= data-in from column b.
3. NOP commands are n for ease of illustration; other commands may be valid at these times.
4. BL8 setting activateMR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0.
BC4 setting activated MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T6.
READ (WRITE (BC4) OTF
Preliminary Data Sheet E0966E60 (Ver. 6.0)
91
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Write Timing Definition
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
1
/CK*
CK
3
WRIT
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command*
WL = AL + CWL
k,
4
ress*
tDQSS tDSH
tDSH
tDSH
tDSH
tWPRE (min)
tWPST (min)
tDQSS(min)
D, /DQS
tDQSH
tDQSL tDQSL
tDQSH
tDQSH
tDQSH
tDQSL
tDQSH (min)
tDQSL
tDQSL (min)
tDSS
tDSS
tDSS
tDSS
tDSS
Din
Din
Din
Din
Din
Din
Din
Din
n
2
DQ*
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
tDSH
tDSH
tDSH
tDSH
tWPRE (min)
tWPST (min)
tDQSL (min)
DQS, /DQS
tDQSH
tDQSH
tDQSH
tDQSH
tDQSL
tDQSL
tDQSL
tDQSL
S
tDSS
tDSS
tDSS
tDSS
Din
Din
Din
Din
Din
Din
Din
Din
n
2
DQ*
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
QSS
tDSH
tWPRE (min)
tDSH
tDSH
tDSH
tDQSS(max)
tWPST (min)
DQS, /DQS
tD
QSH
tDQSH
tDQSH
tDQSL
tDQSL
tDQSL (min)
tDQSH (min)
tDSS
tDSS
tDSS
DS
Din
n
Din
D
Din
Din
2
DQ*
n + 1 n 5 n + 6 n + 7
Notes: 1.
BL8, WL = 5 (AL = 0, CWL = 5)
Din n = data-in from column n.
VIH or VIL
2.
3.
NOP commands are shown for ease of illustration; other commands may be valid at se times.
4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 duriRIT command at T0.
5. tDQSS must be met at each rising clock edge.
Write Timing Definition
Preliminary Data Sheet E0966E60 (Ver. 6.0)
92
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Write Operation
During read or write command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or
WRITE (auto precharge can be enabled or disabled).
• A12 = 0, BC4 (BC4 = burst chop, tCCD = 4)
• A12 = 1, BL8
A12 wie used only for burst length control, not a column address.
urst Wrcommand is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of
e ck. The address inputs determine the starting column address. Write latency (WL) is equal to (AL + CWL). A
data stre signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst
ycle must be apto the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS
sification ed for write cycles. The subsequent burst bit data are issued on successive edges of the
DQuntil t4 is completed. When the burst has finished, any additional data supplied to the DQ
pins will bQ Signal is ignored after the burst write operation is complete. The time from the
completion o bank precharge is the write recovery time (tWR).
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12
T13
CK
/CK
Command*3
Address*4
NOP
WRIT
WL = AL + CWL
Bank
Col n
tWPRE
tWPST
DQS, /DQS
DQ*2
Din Din Din Din
n+1 n+2 +7
n
VIH or VIL
Notes: 1. BL8, WL = 5 (AL = 0, CWL = 5)
2. Din n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid these ti
4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A1 during WIT command at T0.
Burst Write Operation, WL = 5
Preliminary Data Sheet E0966E60 (Ver. 6.0)
93
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12
T13
CK
/CK
Command*3
Add
NOP
WRIT
Bank
Col n
tWPST
tWPRE
DQS, /S
DQ*2
Din Din Din Din Din Din Din Din
n+1 n+2 n+3 n+4 n+5 n+6 n+7
n
AL = 4
CWL = 5
WL = AL + CWL
VIH or VIL
Notes: 1. BL8, WL = 9 = (CL − 1), CL = 5, CWL = 5)
2. Din n = data-in m column n.
3. NOP commands shown for ease of illustrati; other commands may be valid at these times.
4. BL8 setting activateMR0 bit [A1, A0] = [MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRITcommand at T0.
Bursration, WL = 9
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Tn Tn+1 Tn+2
CK
/CK
Command*3
Address*4
NOP
WRIT
READ
tWTR*5
Bank
Col n
Bank
Cob
tWPRE
tWPST
DQS, /DQS
DQ*2
Din
n
Din Din Din
n+1 n+2 n+3
WL = 5
= 5
Notes: 1. BC4, WL = 5, RL = 5.
2. Din n = data-in from column n; Dout b = data-out from column b.
VIH or
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 bit [A1, A0] = [1, 0] during WRIT command at T0 and READ command at
5. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after th
last write data shown at T7.
Write to Read Operation
Preliminary Data Sheet E0966E60 (Ver. 6.0)
94
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Tn Tn+1 Tn+2
CK
/CK
Command*3
ess*4
WRIT
PRE
NOP
tWR*5
Bank
Col n
tWPRE
tWPST
DQS, /DQS
DQ*
Din
n
Din Din Din
n+1 n+2 n+3
W= 5
VIH or VIL
Notes: 1. BC4, WL = 5= 5.
2. Din n = dafrom column n.
3. NOP comds are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting vated by MR0 bit [A1, A0] = [1, 0] during WRIT command at T0.
5. The write recotime (tWR) referenced frthe first rising clock edge after the last write data shown at T7.
tWR specifies the t burst write cycle urecharge command can be issued to the same bank .
Wrirge Operation
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11 T12
T13
CK
/CK
Command*3
Address*4
WRIT
NOP
WRIT
NOP
tCCD
tWR
tBL = 4 clocks
tWTR
Bank
Col n
Bank
Col b
tWPRE
tWPST
DQS, /DQS
DQ*2
Din Din Din Din Din Din Din Din Din Din Din Din Din Din
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
b
1 b+2 bb+5 b+6 b+7
WL = 5
WL = 5
Notes: 1. BL8, WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
IL
4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT cmand at T0 d T4.
WRITE (BL8) to WRITE (BL8)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
95
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12
T13
CK
/CK
Command*3
ress*4
NOP
tCCD
NOP
WRIT
WRIT
tWR
tBL = 4 clocks
tWTR
Bank
Col n
Bank
Col b
tWPRE
tWPST
tWPRE
tWPST
S, /DQS
DQ
Din Din Din Din
n+1 n+2 n+3
Din Din Din Din
b+1 b+2 b+3
n
b
WL = 5
WL = 5
Notes: 1. BC4, WL = 5 L = 5, AL = 0)
2. Din n (or bata-in from column n (or column b).
VIH or VIL
3. NOP comds are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting ated by either MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0 and T4.
WRITE 4) to WRITE (BC4)
T0
T1
T2
T3
T7
T8
T9
T10
T11 T12
T13
T14
CK
/CK
Command*3
Address*4
WRIT
READ
OP
NOP
tWTR
Bank
Col n
Bank
Col b
tWPRE
PST
DQS, /DQS
DQ*2
Din Din Din Din Din Din Din Din
n+1 n+2 n+3 n+4 n+5 n+6 n+7
n
WL = 5
RL = 5
Notes: 1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Din n = data-in from column n; DOUT b = data-out from column b.
VIH or VIL
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT cond at T0.
READ command at T13 can be either BC4 or BL8 depending on MR0 bit [A1, A0] and A12 status at T13.
WRITE (BL8) to READ (BC4/BL8)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
96
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12
T13
T14
CK
/CK
Command*3
As*4
WRIT
READ
NOP
tBL = 4 clocks
NOP
tWTR
Bank
Col b
Bank
Col n
tWPRE
tWPST
DQS, /D
DQ*2
Din Din Din Din
n+1 n+2 n+3
n
RL = 5
WL = 5
Notes: 1. CL = 5, 0), WL = 5 (CWL = 5, AL = 0)
2. Din n = data-in fromn n; Dout b = data-out from column b.
VIH or VIL
3. NOP commands hown for ease of illustration; other commands may be valid at these times.
4. BC4 setting aed by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0.
READ comat T13 can be either BC4 or BL8 depending on MR0 bit [A1, A0] and A12 status at T13.
WRITE (BC4) to READ (BC4/BL8)
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11 T12
T13
T14
CK
/CK
Command*3
Address*4
WRIT
WRIT
NOP
tCCD
NOP
tBL = 4 clocks
tWR
tWTR
Bank
Col n
Bank
Col b
tWPRE
tWPST
DQS, /DQS
DQ*2
Din Din Din Din Din Din Din Di
n
n+1 n+2 n+3 n+4 n+5 n+6 n+
WL = 5
WL = 5
Notes: 1. WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
VIH or VIL
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0.
BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T4.
WRITE (BL8) to WRITE (BC4)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
97
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12
T13
T14
CK
/CK
Command*3
As*4
NOP
tCCD
NOP
tBL = 4 clocks
WRIT
WRIT
tWR
tWTR
Bank
Col n
Bank
Col b
tWPRE
tWPST
tWPRE
tWPST
DQS, /D
DQ*2
Din Din Din Din
Din Din Din Din Din Din Din Din
b+1 b+2 b+3 b+4 b+5 b+6 b+7
n
n+1 n+2 n+3
b
WL = 5
WL = 5
Notes: 1. = 5, AL
2. Din n (or b) = data-m column n (or column b).
VIH or VIL
3. NOP commands hown for ease of illustration; other commands may be valid at these times.
4. BC4 setting aed by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0.
BL8 setting ated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T4.
WRITE (BC4) to WRITE (BL8)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
98
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Write Timing Violations
Motivation
Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure
the DRAM works properly.
However it is desirable for certain minor violations, that the DRAM is guaranteed not to "hang up" and error to be
limited hat particular operation.
Fofoling it will be assumed that there are no timing violations w.r.t to the write command itself (including
etc.) anat it does satisfy all timing requirements not mentioned below.
Data Sp and Hold Violations
hould the data to be timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a
we burst, thmight be written to the memory location addressed with this write command.
In thexamTiming Parameters) the relevant strobe edges for write burst A are associated with the
clock edge.5, T7, T7.5, T8, T8.5.
Subsequenlocation might result in unpredictable read data, however the DRAM will work properly
otherwise.
Strobe to Strobe and StrobClock Violations
Should the strobe timing uirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements
(tDSS, tDSH tDQSS) blated for any of the strobe edges associated with a write burst, then wrong data might be
written to the memory locn addressed with the offending write command. Subsequent reads from that location
might result in unpredictable d data, however thRAM will work properly otherwise.
In the example (Figure Write Timing Parametervant strobe edges for write burst A are associated with the
clock edges: T4, T4.5, T5, T5.5, T6, T6.5, T5 and T9. Any timing requirements starting and ending
on one of these strobe edges are T8, T8.5, 10.5, T11, T11.5, T12, T12.5 and T13. Some edges are
associated with both bursts.
T0
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13 T14
CK
/CK
Command*3
WRIT
A
WRIT
B
NOP
NOP
Address*4
/CS
ODTL
BL/2 + 2 ODTL
WL
tDQSS
tDSS
tDSH
tDQSL
PST
tWPRE
tDQSH
DQS, /DQS
DQ*2
tDH
tDS
VIH or VIL
Write Timing Parameters
Preliminary Data Sheet E0966E60 (Ver. 6.0)
99
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Write Data Mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR3 SDRAMs, Consistent with the
implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in
a uni-directional manner, is internally loaded identically to data bits to ensure matched system timing. DM is not
used during read cycles.
T1
in
T2
T3
in
T4
in
T5
in
T6
QS
/DQS
in
in
in
in
Write mask latency = 0
Data Mask Timing
/CK
CK
[tDQSS(min.)]
tWR
WRIT
Command
NOP
WL
tDQSS
DQS, /DQS
DQ
in0
DM
WL
tDQSS
[tDQSS(max.)]
DQS, /DQS
DQ
in0
in2 in3
DM
Data Mask Function, WL = 5, AL = 0 shown
Preliminary Data Sheet E0966E60 (Ver. 6.0)
100
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Precharge
The precharge command is used to precharge or close a bank that has been activated. The precharge command is
triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge
command can be used to precharge each bank independently or all banks simultaneously. Four address bits A10,
BA0, BA1 and BA2 are used to define which bank to precharge when the command is issued.
[Bank lection for Precharge by Address Bits]
A1
BA0
L
BA1
L
BA2
L
Precharged Bank(s)
Bank 0 only
L
H
L
L
L
Bank 1 only
L
H
H
L
L
Bank 2 only
L
L
Bank 3 only
L
H
H
H
H
×
Bank 4 only
L
L
Bank 5 only
L
H
H
×
Bank 6 only
L
H
×
Bank 7 only
H
All banks 0 to 7
Remark: H: VIH, L: VILVIH or VIL
Preliminary Data Sheet E0966E60 (Ver. 6.0)
101
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Auto Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge
command or the auto precharge function. When a read or a write command is given to the DDR3 SDRAM, the /CAS
timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at
the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write Command is
issued, then normal read or write burst operation is executed and the bank remains active at the completion of the
burst ence. If A10 is high when the Read or Write Command is issued, then the auto precharge function is
end. ring auto precharge, a read Command will execute as normal with the exception that the active bank
gin to pharge on the rising edge which is /CAS latency (CL) clock cycles before the end of the read burst.
Auto charge can also be implemented during Write commands. The precharge operation engaged by the Auto
prechargcommand will not begin until the last data of the burst write sequence is properly stored in the memory
ray.
Theature arge operation to be partially or completely hidden during burst read cycles (dependent
upon /CAS oving system performance for random data access. The /RAS lockout circuit internally
delays the on until the array restore operation has been completed so that the auto precharge
command h any rad or write command.
Burst Read witPrecha
If A10 is high when a Reaommand is issued, the Read with Auto precharge function is engaged. The DDR3
SDRAM starts an auto parge operation on the rising edge which is (AL + BL/2) cycles later from the read with
AP command when tR(min.) is satisfied. If tRAS (min.) is not satisfied at the edge, the start point of auto
precharge operation will belayed until tRAS (min.) is satisfied. A new bank active (command) may be issued to
the same bank if the following o conditions are sed simultaneously.
(1) The /RAS precharge time (tRP) has been sathe clock at which the auto precharge begins.
(2) The /RAS cycle time (tRC) from the prevon has been satisfied.
Burst Write with Auto precharge
If A10 is high when a write command is issued, the Write with auto precharge function is engaged. The DDR3
SDRAM automatically begins precharge operation after thmpletion of the burst writes plus write recovery time
(tWR). The bank undergoing auto precharge from thompltion of the write burst may be reactivated if the
following two conditions are satisfied.
(1) The data-in to bank activate delay time (tWR + tRP) has bee.
(2) The /RAS cycle time (tRC) from the previous bank activatioatisfied.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
102
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Auto-Refresh
When /CS, /RAS and /CAS are held low and /WE high at the rising edge of the clock, the chip enters the automatic
refresh mode (REF). All banks of the DDR3 SDRAM must be precharged and idle for a minimum of the precharge
time (tRP) before the auto-refresh command (REF) can be applied. An address counter, internal to the device,
supplies the bank address during the refresh cycle. No control of the external address bus is required once this
cycle has started.
Wheefresh cycle has completed, all banks of the DDR3 SDRAM will be in the precharged (idle) state. A delay
been thauto-refresh command (REF) and the next activate command or subsequent auto-refresh command
be greathan or equal to the auto-refresh cycle time (tRFC).
To allfor improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval irovided. A maximum of 8 refresh commands can be posted to any given DDR3 SDRAM, meaning that
maximum aerval between any refresh command and the next Refresh command is 9 × tREFI.
T1
T2
T3
RP
≥ tRFC
≥ tRFC
CK
Any
Command
NOP
REF
REF
NOP
Command
o-Refresh
Preliminary Data Sheet E0966E60 (Ver. 6.0)
103
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Self-Refresh
The self-refresh command can be used to retain data in the DDR3 SDRAM, even if the rest of the system is powered
down. When in the self-refresh mode, the DDR3 SDRAM retains data without external clocking. The DDR3 SDRAM
device has a built-in timer to accommodate self-refresh operation. The Self-Refresh Entry (SELF) command is
defined by having /CS, /RAS, /CAS and CKE held low with /WE high at the rising edge of the clock.
Before ssuing the self-refresh entry command, the DDR3 SDRAM must be idle with all bank precharge state with
tRP d. Also, on-die termination must be turned off before issuing Self-refresh entry command, by either
rering T pin low “ODTL + 0.5tCK” prior to the self-refresh entry command or using MRS to MR1 command.
the selfresh entry command is registered, CKE must be held low to keep the device in self-refresh mode.
The Dis automatically disabled upon entering Self-refresh and is automatically enabled (including a DLL-Reset)
upon exig self-refresh.
Whthe Ds entered self-refresh mode all of the external control signals, except CKE and /RESET,
are “don’t elf-refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ,
VREFCA at be at valid levels. The DRAM initiates a minimum of one refresh command internally
within tCKEt enterself-refresh mode.
The clock is isablering self-refresh operation to save power. The minimum time that the DDR3
SDRAM must remain in self-sh mode is tCKESR. The user may change the external clock frequency or halt the
external clock tCKSRE clcycles after self-refresh entry is registered, however, the clock must be restarted and
stable tCKSRX clock cs before the device can exit self-refresh operation. To protect DRAM internal delay on
CKE line to block the inpugnals, one NOP (or DESL) command is needed after self-refresh entry.
The procedure for exiting self-refresh requires a of events. First, the clock must be stable tCKSRX prior to
CKE going back high. Once a Self-Refresh EREX, combination of CKE going high and either NOP or
DESL on command bus) is registered, a domust be satisfied before a valid command not requiring
a locked DLL can be issued to the devto alloy internal refresh in progress. Before a command which
requires a locked DLL can be applied, a delay of at least tXSDLL and applicable ZQCAL function requirements
(TBD) must be satisfied.
CKE must remain high for the entire self-refresh eperiod tXSDLL for proper operation except for self-refresh
reentry. Upon exit from self-refresh, the DDR3 SDRAM can be nto Self-refresh mode after waiting at least
tXS period and issuing one refresh command (refresh period oor DESL commands must be registered
on each positive clock edge during the self-refresh exit intervast be turned off during tXSDLL.
The use of Self-refresh mode introduces the possibility that an timed refresh event can be missed when
CKE is raised for exit from self-refresh mode. Upon exit from self-refresh, thSDRrequires a minimum of
one extra refresh command before it is put back into self-refresh mode.
Ta
Tb
Tc Tc+1Tc+2
Td
Te
Tf
Tg Tg+1
Th Th+1
CK, /CK
tCKSRE
tCKSRX
DLL
tRP
tXS
4
2
3
*
*
1
*
Command
Valid alid
d Valid
PALL
SELF NOP
SREX
tCKESR
CKE
ODT
ODTLoff + 0.5 x tCK
Notes: 1. Only NOP or DESL commands.
2. Valid commands not requiring a locked DLL.
3. Valid commands requiring a locked DLL.
4. One NOP or DESL commands.
VIH or VIL
Self-Refresh Entry and Exit Timing
Preliminary Data Sheet E0966E60 (Ver. 6.0)
104
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Power-Down Mode
Power-down is synchronously entered when CKE is registered low (along with NOP or DESL command). CKE is not
allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read / write
operation are in progress. CKE is allowed to go low while any of other operations such as row activation, precharge
or auto precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing those
operations.
TLL shld be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is
ked durpower-down entry, the DLL must be reset after exiting power-down mode for proper read operation
and shronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well
proper DL operation with any CKE intensive operations as long as DRAM controller complies with DRAM
ecifications.
During poks are closed after any in-progress commands are completed, the device will be in
precharge ; if any bank is open after in-progress commands are completed, the device will be in
active powe
Entering poweeactivathe input and output buffers, excluding CK, /CK, ODT, CKE and /RESET. To
protect DRAM internal delay CKE line to block the input signals, multiple NOP or DESL commands are needed
during the CKE switch ond cycle(s) after this timing period are defined as tCPDED. CKE_low will result in
deactivation of commannd address receivers after tCPDED has expired.
[Power-Down Entry Definns]
Status of DRAM
MR0 bit 2
DLL
On
Exit
Relevant Parameters
Active
(A bank or more Open)
Don’t Care
tXP to any valid command
tXP to any valid command. Since it is in
precharge state, commands here will be ACT,
AR, MRS, PRE or PALL .
Precharged
(All banks Precharged)
0
1
Off
On
Slow
ast
tXPDLL to commands who need DLL to operate,
such as READ, READA or ODT control line.
Precharged
(All Banks Precharged)
XP to any valid command
Also the DLL is disabled upon entering precharge power-doexit mode, but the DLL is kept enabled
during precharge power-down for fast exit mode or active powerpoweown mode, CKE low, RESET high
and a stable clock signal must be maintained at the inputs of the DDR3 SDODhould be in a valid state
but all other input signals are “Don’t Care” (If RESET goes low during DRAM will be out of PD
mode and into reset state). CKE low must be maintained until tPD has beower-down duration is limited
by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered high (alg with OP or DESL command).
CKE high must be maintained until tCKE has been satisfied. A valid, executable mand cabe applied with
power-down exit latency, tXP and/or tXPDLL after CKE goes high. Power-down it latenis defined at AC
Characteristics table of this data sheet.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
105
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Timing Diagrams for Proposed CKE with Power-Down Entry, Power-Down Exit
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
Tx
Tx+1
/CK
CK
Command
READ
Valid
NOP
NOP
BA
tCPDED
tRDPDEN
tIS
VIH
CKE
RL = CL + AL = 5 (AL = 0)
tPD
out out out out out out out out
DQ(BL
DQ
0
1
2
3
4
5
6
7
out out out out
0
1
2
3
ower-Dn Entry after Read and Read with Auto Precharge
T0
T1
2
T3
T4
T5
T6
T7
T8
T9
T10 T14 T15
T16 T17 T18 Tn
CK
/CK
Command
NOP
NOP
NOP
WRITA
Valid
BA
tCPDED
tIS
CKE
tWRAPDE
WL=5
tWR*
tPD
in in in in in in
DQ(BL8)
DQ(BC4)
0
1
2
3
4
5
in in in in
0
1
2
3
Ial
ge
Note: tWR is programmed through MRS.
Power-Down Entry After Write with Auto e
Preliminary Data Sheet E0966E60 (Ver. 6.0)
106
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 Tx Tx+1 Tx+2 Tx+3
CK
/CK
Command
WRITE
Valid
NOP
NOP
BA
tCPDED
tIS
CKE
tWRPDEN
WL=5
tWR
tPD
in in in in in in in in
DQ(BL8)
DQ(BC4)
0
1
2
3
4
5
6
7
in in in in
0
1
2
3
Power-Down Entry after Write
T0
Tn Tn+1
Tx
Ty
CK
/CK
tIH
tIH
CKE
tIS
tCPDED
Valid NOP NOP
CKE (min.)
Command
NOP OP NOP Valid NOP NOP NOP NOP
N
Enter power-down mode
Exit pdown
Note: Valid command at T0 is ACT, NOP, DESL or precharge with still ng open after completion of
precharge command.
Active Power-Down Entry and Exit Timing Dim
T0
T1
Tn Tn+1
T
Ty
CK
/CK
tPD
tIH
tIH
CKE
tIS
tCPDED
tIS
tCKE (min.)
Command
NOP NOP
NOP NOP NOP NOP NOP Valid NOP NOP NOP1NOP N
tXP
Enter power-down mode
Exit power-down
Precharge Power-Down (Fast Exit Mode) Entry and Exit
Preliminary Data Sheet E0966E60 (Ver. 6.0)
107
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
Tn Tn+1
Tx
Ty
CK
/CK
tIH
tIH
CKE
tIS
tIS
tPD
tCPDED
tCKE (min.)
NOP NOP NOP NOP NOP NOP Valid NOP Valid NOP NO
tXP
Comman
NOP NOP NOP
tXPDLL
Exit power-down
Enter r-down mode
Parge Power-Down (Slow Exit Mode) Entry and Exit
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
/CK
Command
REF
NOP
NOP
tRPDEN
tIS
CKE
Refresh Command to PoEntry
T0
T1
T2
T3
T4
Tn
Tn+1 Tn
End
CK
/CK
Command
NOP
NOP
ACT
tCPDED
tPD
tACTPDEN
tIS
CKE
Active Command to Power-Down Entry
Preliminary Data Sheet E0966E60 (Ver. 6.0)
108
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
End
CK
/CK
PRE/
PALL
Command
NOP
NOP
tCPDED
tPREPDEN
tIS
C
echarge/Precharge All Command to Power-Down Entry
T1
T2
T3
Tn
Tn+1
NOP
Tn+2
NOP
Tn+3 Tn+4 Tn+5
Tn+6 Tn+7
CK
/CK
Command
S
NOP
NOP
NOP
tCPDED
tMR
tIS
CKE
MRS CommanPower-Down Entry
Preliminary Data Sheet E0966E60 (Ver. 6.0)
109
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Timing Values tXXXPDEN Parameters
Status of DRAM
Idle or Active
Idle or Active
Active
Last Command before CKE_low
Parameter
tACTPDEN
tPRPDEN
Parameter Value
Unit
nCK
nCK
nCK
Activate
1
Precharge
1
READ/READA
tRDPDEN
tWRPDEN
tWRPDEN
tWRAPDEN
tWRAPDEN
tREFPDEN
tMRSPDEN
RL + 4 + 1
Active
WRIT for BL8MRS, BL8OTF, BC4OTF
WRIT for BC4MRS
WRITA for BL8MRS, BL8OTF, BC4OTF
WRITA for BC4MRS
sh
WL + 4 + (tWR/tCK (avg)) *1 nCK
WL + 2 + (tWR/tCK (avg))*1 nCK
WL + 4 + WR*2 + 1
A
tiv
nCK
nCK
nCK
Active
WL + 2 + WR*2 + 1
1
Idle
gister Set
tMOD
Notes: 1. s, for calculation of tWRPDEN, it is necessary to round up tWR / tCK to next integer.
2. as programmed in mode register.
Power-Down Exit Cfication
Case 1:
When CKE registered lor power-down entry, tPD must be satisfied before CKE can be registered hight as
power-down exit.
Case 1a:
After power-down exit, tCKE must be satisfied an be registered low again.
T0
T1
Tn
Tn+1
Tx
Ty
CK
/CK
tIH
tIH
CKE
tIS
tPD
tCPDED
NOP NOP NOP
t
NOP NOP NOP NOP P NOP NOP NOP
N
Command
Exit power-down
Enter power-down
Power-Down Entry/Exit Clarifications (1)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
110
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Case 2:
For certain CKE intensive operations, for example, repeated "PD Exit - Refresh - PD Entry" sequence, the number of
clock cycles between PD Exit and PD Entry may be insufficient to keep the DLL updated. Therefore the following
conditions must be met in addition to tPD in order to maintain proper DRAM operation when Refresh commands is
issued in between PD Exit and PD Entry.
Power-down mode can be used in conjunction with Refresh command if the following conditions are met:
1. tXP ust be satisfied before issuing the command
2. Lmust be satisfied (referenced to registration of PD exit) before next power-down can be entered.
T0 T1
Tn Tn+1
tIH
Tx
Ty
K
/CK
tIH
CK
tIS
DED
tIS
tXPDLL (min.)
tCKE (min.)
tPD
Command
NOP NOP
N
NOP
tXP
REF NOP NOP NOP NOP NOP NOP NOP
er-down
Enter power-d
Power-Down Eny/Exit Clarifications (2)
Case 3:
If an early PD Entry is issued after Refresh command, oPD xit is issued, NOP or DESL with CKE high must be
issued until tRFC from the refresh command is satisfThis means CKE cannot be de-asserted twice within tRFC
window.
T0
T1
Tn
Tx
Ty
CK
/CK
tIH
tIH
CKE
tIS
tIS
tPD
tXPDLL
tCPDED
REF NOP NOP
tCKE (min.)
Command
NOP NOP NOP NOP NOP NOP NOP NONOP Vali
N
tRFC (min.)
Exit power-down
Enter power-down
Note: * Synchronous ODT Timing starts at the end of tXPDLL (min.)
Power-Down Entry/Exit Clarifications (3)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
111
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Input Clock Frequency Change during Precharge Power-Down
Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be “stable” during almost all states of
normal operation. This means once the clock frequency has been set and is to be in the “stable state”, the clock
period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (Spread Spectrum
Clocking) specifications.
The input clock frequency can be changed from one stable clock rate to another stable clock rate under two
cond(1) self-refresh mode and (2) precharge power-down mode. Outside of these two modes, it is illegal to
che the ock frequency. For the first condition, once the DDR3 SDRAM has been successfully placed in to Self-
sh modnd tCKSRE has been satisfied, the state of the clock becomes a don’t care. Once a don’t care,
hangthe clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When
entering d exiting Self-Refresh mode for the sole purpose of changing the clock frequency, the self-refresh entry
d exit specificust still be met as outlined in Self-Refresh section.
Thecond n the DDR3 SDRAM is in Precharge Power-down mode (either fast exit mode or slow
exit mode.) logic low ensuring RTT is in an off state prior to entering Precharge Power-down mode
and CKE mow. A minimum of tCKSRE must occur after CKE goes low before the clock frequency
may changRAM inut clock frequency is allowed to change only within the minimum and maximum
operating frefied foe particular speed grade. During the input clock frequency change, ODT and
CKE must be het stable levels. Once the input clock frequency is changed, stable new clocks must be
provided to the DRAM tCKbefore Precharge Power-down may be exited; after Precharge Power-down is exited
and tXP has expired, thLL must be RESET via MRS. Depending on the new clock frequency additional MRS
commands may need to issued to appropriately set the WR, CL, and CWL with CKE continuously registered high.
During DLL re-lock period, T must remain low. After the DLL lock time, the DRAM is ready to operate with new
clock frequency. This process depicted in the figlock Frequency Change in Precharge Power-Down Mode.
Previous clock frequ
New clock frequency
T0
T1
tIS
Ta
Tc
Tc+1 Td
Td+1
Te
Te+1
/CK
CK
tIH
tCKSRE
SR
CKE
tCPDED
NOP
NOP
NOP
P
Command
Address
MRS
NOP
Valid
Valid
tAOFPD/tAOF
ODT
tD
High-Z
High-Z
DQS, /DQS
DQ
DM
Enter precharge
power-down mode
Exit precharge
power-down mode
Frequency
change
Notes: 1. Applicable for both slow exit and fast exit precharge power-down.
2. tCKSRE and tCKSRX are self-refresh mode specifications but the values
they represent are applicable here.
3. tAOFPD and tAOF must be satisfied and outputs high-z prior to T1;
refer to ODT timing for exact requirements.
Clock Frequency Change in Precharge Power-Down Mode
Preliminary Data Sheet E0966E60 (Ver. 6.0)
112
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
On-Die Termination (ODT)
ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off termination
resistance for each DQ, DQS, /DQS and DM for ×4 and ×8 configuration (and TDQS, /TDQS for ×8 configuration,
when enabled via A11=1 in MR1) via the ODT control pin. For ×16 configuration ODT is applied to each DQU, DQL,
DQSU, /DQSU, DQSL, /DQSL, DMU and DML signal via the ODT control pin. The ODT feature is designed to
improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off
termiresistance for any or all DRAM devices.
DT featuis turned off and not supported in Self-Refresh mode.
A simpunctional representation of the DRAM ODT feature is shown in figure Functional Representation of ODT.
ODT
VDDQ/2
r
y
RTT
CV, ...
Switch
DQ, DQS, DM, TDQS
Functisentation of ODT
The switch is enabled by the internal Owhich uses the external ODT pin and other control
information, see below. The value of T is ed by the settings of Mode Register bits (see MR1
programming figure in the section Programming the Mode Register). The ODT pin will be ignored if the Mode
Register MR1 is programmed to disable ODT and in self-refrh mode.
ODT Mode Register and ODT Truth Table
The ODT Mode is enabled if either of MR1 bits A2 or A6 or n-zero. In this case the value of RTT is
determined by the settings of those bits .
Application: Controller sends WRIT command together with O
• One possible application: The rank that is being written to providinatio
• DRAM turns ON termination if it sees ODT asserted (except ODT is disa
• DRAM does not use any write or read command decode information
• The Termination Truth Table is shown in the Termination Truth Table
[Termination Truth Table]
ODT pin
DRAM Termination State
0
1
OFF
ON, (OFF, if disabled by MR1 bits A2, A6 and A9 in general)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
113
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down
definition, these modes are:
• Active mode
• Idle mode with CKE high
• Active power-down mode (regardless of MR0 bit A12)
• Pree power-down mode if DLL is enabled during precharge power-down by MR0 bit A12.
shronous ODT mode, RTT will be turned on or off ODTLon clock cycles after ODT is sampled high by a rising
clock ee and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency
s tied to te write latency (WL) by: ODTLon = WL – 2; ODTLoff = WL – 2.
ODT LatenDT
In Synchrohe Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the
ODT signanal ODT signal is delayed for a number of clock cycles defined by the Additive Latency
(AL) relative ODT al.
ODTLon = CWL + − 2; ODff = CWL + AL − 2. For details, refer to DDR3 SDRAM latency definitions.
[ODT Latency Table]
Parameter
Symbol
ODTLon
ODTLoff
Value
Unit
nCK
nCK
ODT turn-on Latency
ODT turn-off Latency
– 2 = CWL + AL – 2
= CWL + AL – 2
Synchronous ODT Timing Parameters
In synchronous ODT mode, the following timing parameterapply (see Synchronous ODT Timing Examples (1)):
ODTL, tAON,(min.),max, tAOF,(min.),(max.) Minimum Ron time (tAON min) is the point in time when the
device leaves high impedance and ODT resistance beto turn on. Maximum RTT turn-on time (tAON max) is the
point in time when the ODT resistance is fully on. Botre measured rom ODTLon.
Minimum RTT turn-off time (tAOF min ) is the point in time whestarts to turn-off the ODT resistance.
Maximum RTT turn-off time (tAOF max) is the point in te on-die termination has reached high
impedance. Both are measured from ODTLoff.
When ODT is asserted, it must remain high until ODTH4 is sd. If a command is registered by the
SDRAM with ODT high, then ODT must remain high until ODTH4 (BC4) BLafter the Write command
(see figure Synchronous ODT Timing Examples (2)). ODTH4 and ODTHfrom ODT registered high
to ODT registered low or from the registration of a Write command until Oed low.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
114
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 END
CK
/CK
CKE
ODTH4 (min.)
AL = 3
DT
AL = 3
tODT
ODTLon = CWL + AL – 2
ODTLoff = CWL + AL – 2
CWL – 2
tAON (max.)
tAOF (max.)
tAOF (min.)
tAON (min.)
RT
RTT
Syronous ODT Timing Examples (1): AL=3, CWL = 5;
TLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6
T0 TT2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18
CK
/CK
CKE
Command
ODTH4
ODTH4
ODH4
ODT
ODT= WL – 2
ODTLon =
ODTLoff = WL – 2
ODTLon = WL – 2
tAON (max.)
tAON (min.)
tA)
tAOF (max.)
tAOF (min.)
DRAM_RTT
RTT
T
tAmax.)
tAON (m
Synchronous ODT Timing Examples (2)*: BC4, WL =
ODT must be held high for at least ODTH4 after assertion (T1); ODT must be kept high ODTHBC4) or DTH8
(BL8) after write command (T7). ODTH is measured from ODT first registered high to ODT firsegistered ow, or
from registration of write command with ODT high to ODT registered low. Note that although ODTis satisfied f
ODT registered high at T6 ODT must not go low before T11 as ODTH4 must also be satisfied from the registratof
the write command at T7.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
115
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
ODT during Reads
As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle
before the read preamble by driving the ODT pin low appropriately. RTT may nominally not be enabled until one
clock cycle after the end of the post-amble as shown in the example in the figure below.
Note that ODT may be disabled earlier before the Read and enabled later after the Read than shown in this example
in the figure below.
ODT mt be disabled externally during Reads by driving ODT low.
(exeL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL -2 = 8;
Ooff = CL + AL - 2 = 8)
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 End
K
/C
mmand
Address
RL = AL + CL
ODT
TLoff = WL – 2 = CWL + AL – 2
ODTLon = WL – 2 = CWL + AL – 2
tAOF (max.)
tAOF (min.)
tAON (min.)
tAON (max.)
RTT
RTT
DRAM_RTT
DQS, /DQS
out out out out out out out out
DQ
0
1
2
3
4
5
6
7
Example of T during Reads
Preliminary Data Sheet E0966E60 (Ver. 6.0)
116
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination
strength of the DDR3 SDRAM can be changed without issuing an MRS command. This requirement is supported by
the “Dynamic ODT” feature as described as follows:
Functional Description:
The Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to ’1’. The function and is described as follows:
• Twvalues are available: RTT_Nom and RTT_WR.
⎯ e valfor RTT_Nom is pre-selected via bits A[9,6,2] in MR1
e value fRTT_WR is pre-selected via bits A[10,9] in MR2
• Durinperation without write commands, the termination is controlled as follows:
⎯ Nominal terminn strength RTT_Nom is selected.
⎯ erminatiog is controlled via ODT pin and latencies ODTLon and ODTLoff.
• When a wRIT, WRITA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is
enabled, ontrolled as follows:
⎯ A latenthe wrte command, termination strength RTT_WR is selected.
⎯ A latency for BLxed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected
OTF) after the e comm, termination strength RTT_Nom is selected.
⎯ Termination on/off timicontrolled via ODT pin and ODTLon, ODTLoff.
Table Latencies and Tig Parameters Relevant for Dynamic ODT shows latencies and timing parameters, which
are relevant for the on-die rmination control in Dynamic ODT mode:
When ODT is asserted, it muemain high until O4 is satisfied. If a write command is registered by the SDRAM
with ODT high, then ODT must remain high unt(BC4) or ODTH8 (BL8) after the write command (see the
figure Synchronous ODT Timing Examples (nd ODTH8 are measured from ODT registered high to
ODT registered low or from the registration nd until ODT is registered low.
[Latencies and Timing Parameters Relant for ic ODT]
Definition for all DDR3
Parameters
Symbols
ODTLon
Defined from
efined to
speed bins
Unit
nCK
Registering extl
ODT signal
ODT turn-on Latency
Turning termination on
ODTLon = WL – 2.0
Registering external
ODT signal low
ODT turn-off Latency
ODTLoff
ation off
ODTLoff = WL – 2.0
ODTLcnw = WL – 2.0
nCK
nCK
ODT latency for changing
from RTT_Nom to RTT_WR
Registering external rength from
write command RTT_WR
ODTLcnw
ODT latency for change
from RTT_WR to RTT_Nom
(BC4)
Registering external Change RTT sOcwn4 =
write command RTT_WR to ODTLoff
ODTLcwn4
ODTLcwn8
nCK
nCK
ODT latency for change
from RTT_WR to RTT_Nom
(BL8)
Registering external Change RTT m ODTwn8 =
write command
RTT_WR to RTT_
6 TLoff
Minimum ODT high time after
ODT assertion
ODTH4
ODTH4
ODTH8
tADC
registering ODT high ODT registered low
DTH4 (m= 4
ODmin.) =
ODTH8 (m= 6
0.3ns to 0.7n
nCK
Minimum ODT high time after
Write (BC4)
registering Write with
ODT registered low
ODT high
nCK
Minimum ODT high time after
Write (BL8)
registering Write with
ODT registered low
ODT high
CK
ODTLcnw
RTT valid
ODTLcwn
RTT change skew
tCK
Preliminary Data Sheet E0966E60 (Ver. 6.0)
117
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Mode Register Settings for Dynamic ODT Mode:
The table Mode Register for RTT Selection shows the Mode Register bits to select RTT_Nom and RTT_WR values.
[Mode Register for RTT Selection]
MR1
MR2
RTT_Nom
(RZQ)
RTT_Nom
(Ω)
RTT_WR
(RZQ)
RTT_WR*1
(Ω)
A9
0
6
0
A2
0
A10
0
A9
0
Dynamic ODT OFF: Write does not
affect RTT value
off
off
0
1
1
1
1
0
1
0
0
1
1
0
RZQ/4
60
0
1
RZQ/4
RZQ/2
Reserved
⎯
60
RZQ/2
120
1
0
120
Q/6
40
1
1
Reserved
2*2
ed
served
20
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
30
⎯
Reserved
Reserved
⎯
⎯
Notes: 1. RZQ = 240Ω.
2. If RTT_Nom is ed during WRITEs, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
ODT Timing Diagrams
T0 T1 T2 T3 T4 T5 T6 9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
CK
/CK
ODTLcnw
WRS4
Command
ODTH4
ODTH4
ODT
RTT
ODTLon
ODTLoff
m
tADC .)
tAON (min.)
RTT_Nom
tADC (min.)
RTT_WR
tAOF (min.)
tAOF (max.)
tAON (max.)
tADC (max.)
ODTLcwn4
DQS, /DQS
DQ
in in in in
0
1
2
3
WL
Dynamic ODT: Behavior with ODT Being Asserted Before and after the Write
Note: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. ODTH4 applies to first registering ODT high anthe
registration of the write command. In this example ODTH4 would be satisfied if ODT is low at T8 clocks
after the write command).
Preliminary Data Sheet E0966E60 (Ver. 6.0)
118
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
/CK
Command
ODTH4
ODT
ODTLon
ODTLoff
tAON (min.)
tAOF (min.)
tAOF (max.)
RTT_Nom
T
tAON (max.)
DQS, /DQ
namic T*: Behavior without Write Command; AL = 0, CWL = 5
Note: ODTH4 is defined frODT registered high to ODT registered low, so in this example ODTH4 is satisfied;
ODT registered loT5 would also be legal.
T0
T1
T
T3
T4
T6
T7
T8
T9
T10
T11
CK
/CK
ODTLcnw
ODTLon
Command
ODT
WRS8
ODTH8
ODTLoff
tAON (min.)
tAOF (min.)
tAOF (max.)
RTT_W
RTT
tADC (max.)
ODTLcwn8
DQS, /DQS
DQ
in
0
in
in
in
in
in
n
in
1
2
3
4
5
WL
Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Coand
for Duration of 6 Clock Cycles
Note: Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example ODTH8 = 6 is exactly satisfied.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
119
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
/CK
ODTLcnw
WRS4
Command
ODTH4
RTT
ODTLon
ODTLoff
tAON (min.)
tAOF (min.)
tAOF (max.)
tADC (min.)
RTT_Nom
RTT_WR
tADC (max.)
tADC (max.)
ODTLcwn4
DQS, /DQS
DQ
in
in
in
2
in
0
1
3
WL
Dynamic ODT*: havior with ODT eing Asserted Together with Write Command
for a Duration of 6 Clock Cycles, for BC4 (via MRS or OTF), AL = 0, CWL = 5.
Note: ODTH4 is defined from ODT registregistered low, so in this example ODTH4 is satisfied;
ODT registered low at T5 would abe le
T0
T1
T2
T3
T4
T
T6
T7
T8
T9
CK
/CK
ODTLcnw
ODTH4
Command
ODT
WRS4
ODTLon
tAON (min.)
tAOF (min.)
tmax.)
RTT_WR
RTT
tADC (max.)
ODTLcwn4
DQS, /DQS
DQ
in
0
in
1
in
in
2
3
WL
Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command
for Duration of 4 Clock Cycles
Note: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example ODTH4 = 4 is exactly satisfied.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
120
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Asynchronous ODT Mode
Asynchronous ODT mode is selected when DRAM runs in DLL-on mode, but DLL is temporarily disabled (i.e. frozen)
in precharge power-down (by MR0 bit A12).
Precharge power-down mode if DLL is disabled during precharge power-down by MR0 bit A12.
In asynchronous ODT timing mode, internal ODT command is not delayed by Additive Latency (AL) relative to the
external ODT command.
In asonous ODT mode, the following timing parameters apply (see figure Asynchronous ODT Timings):
tAD (.), (max.), tAOFPD (min.),(max.)
um RTT rn-on time (tAONPD (min.)) is the point in time when the device termination circuit leaves high
mpedce state and ODT resistance begins to turn on. Maximum RTT turn-on time (tAONPD (max.)) is the point in
time whethe ODT resistance is fully on. tAONPD (min.) and tAONPD (max.) are measured from ODT being
mpled high.
Mium RTtAOFPD (min.)) is the point in time when the devices termination circuit starts to turn off
the ODT rm ODT turn-off time (tAOFPD (max.)) is the point in time when the on-die termination
has reachetAOFPD (min.) and tAOFPD (max.) are measured from ODT being sampled low.
CK
/CK
CKE
tIH
tIH
tIS
tIS
ODT
tAOFPD (min.)
RTT
DRAM_RTT
tAONPD (min.)
tAOFPD (max.)
Asynchronous ODT Timings on DDR3 SDwFast ODT Transition: AL is Ignored
In precharge power-down, ODT receiver remains ac, however no read or write command can be issued, as the
respective address/command receivers may be disabled.
[Asynchronous ODT Timing Parameters for All Speed Bin
Symbol
tAONPD
tAOFPD
Parameters
min.
1
max.
Unit
ns
Asynchronous RTT turn-on delay (power-down with DLL fr
Asynchronous RTT turn-off delay (power-down with DLL
9
9
ns
[ODT for Power-Down (with DLL Frozen) Entry and Exit Transition Period]
Description
min.
max.
ODT to RTT turn-on delay
min {ODTLon × tCK + tAON(min.);
max {ODTLon × tCK tAON(.);
tAONPD(min.) }
tAONPD(max.) }
min { (WL − 2.0) × tCK + tAON(min.); max {(WL − 2.0) × tCK + tAON(m
tAONPD(min.) }
tAONPD(max.) }
min { ODTLoff × tCK +tAOF(min.);
tAOFPD(min.) }
max { ODTLoff × tCK + tAOF(ma
tAOFPD(max.) }
ODT to RTT turn-off delay
tANPD
min { (WL − 2.0) × tCK +tAOF(min.); max {(WL − 2.0) × tCK + tAOF(max.);
tAOFPD(min.) }
tAOFPD(max.) }
WL − 1.0
Preliminary Data Sheet E0966E60 (Ver. 6.0)
121
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry
If DLL is selected to be frozen in precharge power-down mode by the setting of bit A12 in MR0 to 0 there is a
transition period around power-down entry, where the DDR3 SDRAM may show either synchronous or
asynchronous ODT behavior.
This transition period ends when CKE is first registered low and starts tANPD before that. If there is a Refresh
command in progress while CKE goes low, then the transition period ends tRFC after the refresh command. tANPD
is equao (WL − 1.0) and is counted (backwards) from the clock cycle where CKE is first registered low.
ODT on during the transition period may result in an RTT change as early as the smaller of tAONPD(min.)
aODTL× tCK + tAON(min.)) and as late as the larger of tAONPD(max.) and (ODTLon × tCK + tAON(max.)).
e-assertn during the transition period may result in an RTT change as early as the smaller of tAOFPD(min.)
and (OLoff × tCK + tAOF(min.)) and as late as the larger of tAOFPD(max.) and (ODTLoff × tCK + tAOF(max.)).
Note thatf AL has a large value, the range where RTT is uncertain becomes quite large.
figure bele three different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state
chae duriperiod; ODT_C shows a state change after the transition period.
REF
NOP NOP
Co
CKE
PD entry transition period
tANPD
ODT
tRFC
ODT_A_sync
Oo
F (max.)
AOF (min.)
RTT
DRAM_RTT_A_sync
ODT_B_tran
ODTLoff + tAOFPD (max.)
tAOFPD (max.)
ODTLoff + tAOFPD (min.)
tAOFPD (min.)
DRAM_RTT_B_tran
ODT_C_async
tAOFPD (max.)
tAOFPD (min.)
RTT
DRAM_RTT_C_async
Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Frozen) Entry
(AL = 0; CWL = 5; tANPD = WL − 1 = 4)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
122
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit
If DLL is selected to be frozen in precharge power-down mode by the setting of bit A12 in MR0 to 0, there is also a
transition period around power-down exit, where either synchronous or asynchronous response to a change in ODT
must be expected from the DDR3 SDRAM.
This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered
high. tANPD is equal to (WL − 1.0) and is counted backward from the clock cycle where CKE is first registered high.
ODT aertion during the transition period may result in an RTT change as early as the smaller of tAONPD(min.)
and n × tCK + tAON(min.)) and as late as the larger of tAONPD(max.) and (ODTLon × tCK + tAON(max.)).
Ode-assion during the transition period may result in an RTT change as early as the smaller of tAOFPD(min.)
d DTLoff CK + tAOF(min.)) and as late as the larger of tAOFPD(max.) and (ODTLoff × tCK + tAOF(max.)).
See Ofor Power-Down (with DLL Frozen) Entry and Exit Transition Period table.
Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. The figure below shows
tthree differDT_C, asynchronous response before tANPD; ODT_B has a state change of ODT during
the nsitioshows a state change of ODT after the transition period with synchronous response.
T5 T7 T9 T11 T13 T15 T17 T19 T21 T23 T25 T27 T29 T31 T33 T35
Com
NOP NOP
CKE
PD exit transition period
tANPD
tXPDLL
ODT_C_async
tAOFPD
tAOFPD (
DRAM_RTT_C_async
ODT_B_tran
RTT
tAOFPD (min.)
ODTLoff + tAOF (min.)
DTLoff + tAOF (max.)
)
DRAM_RTT_B_tran
ODT_A_sync
ODf
tAOF (max.)
tAOF (min.)
RTT
DRAM_RTT_A_sync
Asynchronous to Synchronous Transition during Precharge Power-Down (with DLL zen) E
(CL = 6; AL = CL - 1; CWL = 5; tANPD= WL − 1 = 9)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
123
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Asynchronous to Synchronous ODT Mode during Short CKE high and Short CKE Low Periods
If the total time in precharge power-down state or idle state is very short, the transition periods for power-down entry
and power-down exit may overlap. In this case the response of the DDR3 SDRAM RTT to a change in ODT state at
the input may be synchronous OR asynchronous from the start of the power-down entry transition period to the end
of the PD exit transition period (even if the entry period ends later than the exit period).
If the total time in idle state is very short, the transition periods for power-down exit and power-down entry may
overlapIn this case the response of the DDR3 SDRAM RTT to a change in ODT state at the input may be
syncs OR asynchronous from the start of the power-down exit transition period to the end of the power-down
enransiperiod.
tat in thootom part of figure below it is assumed that there was no refresh command in progress when idle
state wentered.
CK
/CK
Comand
NOP NOP
NOP NOP
CKE
ANPD
tRFC
PD entry transition period
PD exit transition period
tXPDLL
tANPD
hort CKE low transition period
CKE
tA
tXPDLL
tXPDLL
tANPD
short CKE h transition period
Transition Period for Short CKE Cycwith Entry and Exit Period Overlapping
(AL = 0, WL = tANPD = WL − 1 = 4)
Preliminary Data Sheet E0966E60 (Ver. 6.0)
124
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
ZQ Calibration
ZQ calibration command is used to calibrate DRAM RON and ODT values over PVT. DDR3 SDRAM needs longer
time to calibrate RON and ODT at initialization and relatively smaller time to perform periodic calibrations.
ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may
be issued at any time by the controller depending on the system environment. ZQCL command triggers the
calibratin engine inside the DRAM and once calibration is achieved the calibrated values are transferred from
calibengine to DRAM I/O which gets reflected as updated RON and ODT values.
Trst ZQcommand issued after reset is allowed a timing period of tZQinit to perform the full calibration and the
r of vals. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a
timing riod of tZQoper.
ZQCS comand is used to perform periodic calibrations to account for VT variations. A shorter timing window is
vided to peribration and transfer of values as defined by timing parameter tZQCS.
No er acerformed on the DRAM channel by the controller for the duration of tZQinit, tZQoper or
tZQCS. ThDRAM channel helps in accurate calibration of RON and ODT. Once DRAM calibration
is achieved disable ZQ current consumption path to reduce power.
All banks med and P met before ZQCL or ZQCS commands are issued by the controller.
ZQ calibration cds can be issued in parallel to DLL lock time when coming out of self-refresh. Upon self-
refresh exit, DDR3 SDRAM ll not perform an IO calibration without an explicit ZQ calibration command. The
earliest possible time for Calibration command (short or long) after self-refresh exit is tXS.
In dual rank systems tshare the ZQ resistor between devices, the controller must not allow any overlap of
tZQoper or tZQinit or tZQCetween ranks.
CK
Valid
Command
A10
ZQCL
NOPL
ZQCS
NOP/DESL
A10 = H
X
A10 = L
X
Address
CKE
tZQinit or tZQ oper
Hi-Z
tZQCS
H
DQ Bus*2
Activities
Activities
Notes: 1. ODT must be disabled via ODT signal or MRS during calibration p
2. All device connected to DQ bus should be High impedance during calib.
ZQ Calibration
ZQ External Resistor Value and Tolerance
DDR3 SDRAM has a 240Ω, 1% tolerance external resistor connecting from the DDR3 SDZQ piground.
The resister can be used as single DRAM per resistor.
Preliminary Data Sheet E0966E60 (Ver. 6.0)
125
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Package Drawing
78-ball FBGA
Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
9.8 ± 0.1
0.2 S B
INDEX MARK
0.2 S A
0.2
1.20 max.
S
.05
0.1
S
A
78-φ0.45 ± 0.05
B
A
INDEX MARK
1.6 0.8
6.4
ECA-TS2-0159-01
Preliminary Data Sheet E0966E60 (Ver. 6.0)
126
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
96-ball FBGA
Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
9.8 ± 0.1
0.2 S B
INDEX MARK
0.2 S A
S
1.20 max.
S
0.35 ± 0.05
0.1
S
M
S A B
96-φ0.4
0.12
B
A
INDEX MARK
1.6 0.8
6.4
ECA-TS2-0166-01
Preliminary Data Sheet E0966E60 (Ver. 6.0)
127
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDJ5304BASE, EDJ5308BASE, EDJ5316BASE.
Type of Surface Mount Device
EDJ53BASE, EDJ5308BASE: 78-ball FBGA < Lead free (Sn-Ag-Cu) >
ED16BE: 96-ball FBGA < Lead free (Sn-Ag-Cu) >
Preliminary Data Sheet E0966E60 (Ver. 6.0)
128
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
has occurred. Environmental control must be adequate. When it is dry, humidifier
shld be used. It is recommended to avoid using insulators that easily build static
electity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
rk bench and floor should be grounded. The operator should be grounded using
wrist strOS devices must not be touched with bare hands. Similar precautions
need for PW boards with semiconductor MOS devices on it.
2
HASED INPUT PINS FOR CMOS DEVICES
No r CMS devices input pins can be a cause of malfunction. If no
connrovideo the input pins, it is possible that an internal input level may be
generated due to oise, etc., hence causing malfunction. CMOS devices behave
differently than olar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by ng a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND h a resistor, if it is considered to have a possibility of being an output
pin. The unused s must be handin accordance with the related specifications.
3
STATUS BEFORE INITIALIZATIOVICES
Power-on does not necessadefistatus of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devis with reset function have not yet been
initialized. Hence, power-on does not grane output pin levels, I/O settings or
contents of registers. MOS devices are ot initialized until the reset signal is received.
Reset operation must be executed immediately aower-on for MOS devices having
reset function.
CME0107
Preliminary Data Sheet E0966E60 (Ver. 6.0)
129
EDJ5304BASE, EDJ5308BASE, EDJ5316BASE
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escripns of circuits, software and other related information in this document are provided for
strative urposes in semiconductor product operation and application examples. The incorporation of
the circuits, software and information in the design of the customer's equipment shall be done under
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incurred by cumers or third parties arising from the use of these circuits, software and information.
Product ]
e awact is for use in typical electronic equipment for general-purpose applications.
Elpida es every attempt to ensure that its products are of high quality and reliability.
Howevtructed to contact Elpida Memory's sales office before using the product in
aerosp, nuclar power, combustion control, transportation, traffic, safety equipment,
medical or life pport, or other such application in which especially high quality and
reliability is ded or ere its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your applicn so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., cluding the maximum ratings, operating supply voltage range, heat radiation
characteristics, installatconditions and otrelated characteristics. Elpida Memory, Inc. bears no
responsibility for failure damage wheroduct is used beyond the guaranteed ranges and
conditions. Even within the guaranteed conditions, consider normally foreseeable failure
rates or failure modes in semiconductemploy systemic measures such as fail-safes, so
that the equipment incorporating ElpMeproducts does not cause bodily injury, fire or other
consequential damage due to the oation oida Memory, Inc. product.
[Usage environment]
Usage in environments with special characteristics abelow was not considered in the design.
Accordingly, our company assumes no responsibifor los of a customer or a third party when used in
environments with the special characteristics lisbelow.
Example:
1) Usage in liquids, including water, oils, chemicals anents.
2) Usage in exposure to direct sunlight or the outdoorslaces.
3) Usage involving exposure to significant amounts of cas, including sea air, CL2, H2S, NH3,
SO2, and NO .
x
4) Usage in environments with static electricity, or strong electromes radiation.
5) Usage in places where dew forms.
6) Usage in environments with mechanical vibration, impact, or str
7) Usage near heating elements, igniters, or flammable items.
If you export the products or technology described in this document that are rolled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary cedures accordance
with the relevant laws and regulations of Japan. Also, if you export productechnolcontrolled by
U.S. export control regulations, or another country's export control laws or regutioyou must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third pis graed
license to use these products, that third party must be made aware that they are ponsiblor
compliance with the relevant laws and regulations.
M016
Preliminary Data Sheet E0966E60 (Ver. 6.0)
130
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