EM92601AP [ELAN]
DUAL PLL FOR 46/49 MHZ CORDLESS PHONE; 双锁相环46/49 MHZ无绳电话型号: | EM92601AP |
厂家: | ELAN MICROELECTRONICS CORP |
描述: | DUAL PLL FOR 46/49 MHZ CORDLESS PHONE |
文件: | 总6页 (文件大小:56K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EM92600/1A
DUAL PLL FOR 46/49 MHZ CORDLESS PHONE
GENERAL DESCRIPTION
The EM92600/1A series are developed for 46/49 MHz of 10 channels band frequency of cordless telephone
which is used in U.S.A.. These devices are dual phase-locked loop frequency synthesizers contained ROM
counters for receive and transmit loops with two independent phase detect circuits. A common reference
oscillator and reference divider are share by the receive and transmit circuits.
Other features include a lock detect circuit for the transmit loop, illegal code default, a buffered oscillator output
for mixing purposes in the system, 5KHz tone output . The EM92601A is designed for easy MPU interface. It
provides the same features as the EM92600A , but accepts channel programming via a clocked, serial input
instead of parallel BCD inputs. The EM92600A is selected channels via machanical switches of parallel BCD
input.
FEATURES
• Include oscillation circuit with external X-TAL (10.240 MHz).
• Unlock detector.
• 5KHz output for guard tone.
• Standby mode for power saving.
• 2.5 to 5.5V supply range.
• Baseset/Handset changeable.
• Available in 16 pin DIP or SOP.
• SERIES
Part Number
EM92600AP
EM92600AM
EM92601AP
EM92601AM
Package
DIP
SOP
DIP
SOP
Channel Selection
parallel
parallel
serial
serial
PIN ASSIGNMENTS
EM92600A
EM92601A
XTALO
MODE
SB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTALI
XTALO
MODE
SB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTALI
VDD
VDD
RIF
RIF
5K
PDR
5K
PDR
DI
VSS
D0
VSS
CLK
NC
PDT
LD
D1
PDT
LD
D2
EN
TIF
D3
TIF
* This specification are subject to be changed without notice.
4.23.1995
1
EM92600/1A
DUAL PLL FOR 46/49 MHZ CORDLESS PHONE
FUNCTIONAL BLOCK DIAGRAM
V
DD
VSS
XTAL0
VDD
Reference
counter
XTAL1
5K
divide by 2048
VDD
Lock
LD
detector
phase
detector
Phase
detector
PDR
PDT
14 bits divide by N
receive counter
14 bits divide by N
Transmit counter
RIF
TIF
b13-b0
b27-b14
ROM 32*28
& decoder logic
SB
D1
MODE
D0
D2
D3
EM92600A block diagram
VDD
VSS
XTAL0
VDD
Reference
counter
XTAL1
5K
divide by 2048
VDD
Lock
LD
detector
phase
detector
Phase
detector
PDR
RIF
PDT
14 bits divide by N
receive counter
14 bits divide by N
Transmit counter
TIF
b13-b0
b27-b14
4 bits
latch
ROM 32*28
& decoder logic
4 bits
S/R
SB MODE
EN
CLKDI
EM92601A block diagram
PIN DESCRIPTIONS
Symbol
XTALO
Pin No.
Function
O
This ouput generates reference frequency when it is connected to pin 16 with
external OSC of which frequency is 10.240MHz
Base/remote changing. Internal pull down.
MODE
SB
I
I
VDD=base,VSS=remote.
The standby pin is uses to save power when no transmit. Internal pull down.
High: transmit and receive active
Low: receive acts only
5K
O
The signal derived from the reference oscillator. 5KHz output.
* This specification are subject to be changed without notice.
4.23.1995
2
EM92600/1A
DUAL PLL FOR 46/49 MHZ CORDLESS PHONE
Symbol
D0
D1
D2
D3
Di
I/O
Function
I
I
I
I
I
I
The channel selected pin. LSB.(intenal pull down)
The channel selected pin. (internal pull down)
The channel selected pin. (internal pull down)
The channel selected pin. MSB.(internal pull down)
The serial input data pin.
CLK
Clock input. Each low to high transition of the clock shifts one bit of data into
the on-chip shift register.
Not connect.
NC
EN
-
I
The enable pin controls the data transfer from the shift register to the 4-bit latch.
A low to high transition latches the data.
TIF
I
Input to programmable divider of Tx. AC coupling with VCO. Min input voltage
is 200mVpp.
LD
PDT
O
O
Unlock detector output. VDD level: unlock.
Phase detector output for Tx. PDT detects the phase error from Tx PLL and its
output is connected to external low pass filter.
VSS
-
Ground.
PDR
O
Phase detector output for Rx. PDR detects the phase error from Rx PLL and its
output is connected to external low pass filter.
RIF
I
Input of programmable divider for Rx.AC coupling with VCO. Min input voltage
is 200mVpp.
VDD
XTAL1
-
I
Power supply.
To connect crystal ( 10.240MHz ) and capacitor.
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Value
Unit
VDD
DC supply voltage
-0.5 to +6
-0.5 to VDD+0.5
10.0
V
VIN
Input voltage
V
IIN,IOUT
IDD,ISS
TA
DC current drain per pin
DC current drain VDD or VSS pins
Operating temperature range
Storage temperature range
mA
mA
°C
°C
30.0
-30 to +75
-65 to +150
TSTG
* This specification are subject to be changed without notice.
4.23.1995
3
EM92600/1A
DUAL PLL FOR 46/49 MHZ CORDLESS PHONE
DC ELECTRICAL CHARACTERISTICS
(TA= 25°C unless otherwise noted )
Parameter
Sym. Min.
Typ.
Max. Unit
Condition
Operating voltage
Input voltage
VDD
VIL
VIH
VOL
VOH
IIL
2.5
-
-
-
-
-
5.5
0.8
V
V
VDD=3V
VDD=3V
2.2
Output voltage
0.05
V
2.95
Input low current
µA
vIL=0
-36
-0.06
-
-
pin 16,14,9
pin 2~8
Input high current
Output current
IIH
µA
vIH=VDD-0.5V
pin 16,14,9
pin 2~8
VOH=2.6V
VOL=0.4V
VDD=3V, note1
VDD=3V, note2
-
-
-
-
-
-
36
120
IOH
IOL
IDS
IDO
-0.2
0.2
mA
Standby current
Operating current
1.5
3.0
mA
mA
(0.2Vp-p input at RIF,TIF)
3-state leakage current
IOZ
-
±1
µA
VDD=5V
Note 1: XTALin: 10.24MHz ; MODE:VDD; SB:VSS; TIF=20MHz(200 mVp-p); RIF=40MHz(200 mVp-p); others
are open.
Note 2: XTALin: 10.24MHz ; MODE:VDD; SB:VDD; TIF=20MHz(200 mVp-p); RIF=40MHz(200 mVp-p); others are
open.
AC ELECTRICAL CHARACTERISTICS
Parameter
Sym. Min.
Typ.
Max. Unit
Condition
Output rise time
Output fall time
Input rise and fall time
OSC in
Maximum frequency
input =sine wave 0.2Vp-p
TR
TF
TR
200
200
5
nS
nS
µS
VDD=3V
VDD=3V
XTAL1
VDD=3V
XTAL1
TF
FMAX
12
50
50
MHz RIF (VDD=3V)
TIF
Setup time data to clock
Enable to clock
TSU
100
200
EM92601A only
nS
Hold time
clock to data
Recovery time
Enable to clock
Input pulse width
clock and Enable
TH
TREC
TW
80
80
80
nS
nS
nS
EM92601A only
EM92601A only
EM92601A only
* This specification are subject to be changed without notice.
4.23.1995
4
EM92600/1A
DUAL PLL FOR 46/49 MHZ CORDLESS PHONE
TIMING DIAGRAM
D2
th
D1
D3
D0
Data
tsu
tw
Clock
1 st
2 nd
CLK
1 st
CLK
3 rd
CLK
4 th
CLK
CLK
tw
tsu
trec
Enable
Previous
Data Latched
EM92601A Timing
1.6µS
PDT
LD
6.4±0.4mS
Unlock Timing
APPLICATION CIRCUIT
0.455MHz
1ST
2ND
MIX
BPF
MIX
1ST IF
2ND IF
TX
VCO
RX
VCO
BPF
LPF
LPF
9
8
16 15 14
10
13 12 11
10.240
MHz
4
1
2
3
7
5
6
* This specification are subject to be changed without notice.
4.23.1995
5
EM92600/1A
DUAL PLL FOR 46/49 MHZ CORDLESS PHONE
DIVIDE RATIO AND VCO FREQUENCIES
Base
Input
Rx (Fref=5KHz)
Tx=(Fref=5KHz)
(MODE=1)
CH
D3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D2
D1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
FRx (MHz) FVCO(MHz)
N
FTx(MHz) FVCO(MHz)
N
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
2
3
4
5
6
7
8
9
10
49.670
49.845
49.860
49.770
49.875
49.830
49.890
49.930
49.990
49.770
49.970
49.970
49.970
49.970
49.970
49.970
38.975 7795
39.150 7830
39.165 7833
39.075 7815
39.180 7836
39.135 7827
39.195 7839
39.235 7847
39.295 7859
39.275 7855
39.275 7855
39.275 7855
39.275 7855
39.275 7855
39.275 7855
39.275 7855
46.610
46.630
46.670
46.710
46.730
46.770
46.830
46.870
46.930
46.970
46.970
46.970
46.970
46.970
46.970
46.970
46.610
46.630
46.670
46.710
46.730
46.770
46.830
46.870
46.930
46.970
46.970
46.970
46.970
46.970
46.970
46.970
9322
9326
9334
9342
9346
9354
9366
9374
9386
9394
9394
9394
9394
9394
9394
9394
REMOTE
(MODE=0)
Input
Rx (Fref=5KHz)
Tx=(Fref=5KHz)
CH
D3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
D1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
FRx (MHz) FVCO(MHz)
N
FTx(MHz) FVCO(MHz)
N
1
2
3
4
5
6
7
8
9
10
46.610
46.630
46.670
46.710
46.730
46.770
46.830
46.870
46.930
46.970
46.970
46.970
46.970
46.970
46.970
46.970
35.915
35.935
35.975
36.015
36.035
36.075
36.135
36.175
36.235
36.275
36.275
36.275
36.275
36.275
36.275
36.275
7183
7187
7195
7203
7207
7215
7227
7235
7247
7255
7255
7255
7255
7255
7255
7255
49.670
49.845
49.860
49.770
49.875
49.830
49.890
49.930
49.990
49.970
49.970
49.970
49.970
49.970
49.970
49.970
49.670
49.845
49.860
49.770
49.875
49.830
49.890
49.930
49.990
49.970
49.970
49.970
49.970
49.970
49.970
49.970
9934
9969
9972
9954
9975
9966
9978
9986
9998
9994
9994
9994
9994
9994
9994
9994
* This specification are subject to be changed without notice.
4.23.1995
6
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