74F162ASCX [ETC]
Synchronous Up Counter ; 同步加计数器\n
| 型号： | 74F162ASCX |
| 厂家： | 
ETC |
| 描述： | Synchronous Up Counter
|
| 文件： | 总8页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised September 2000
74F160A • 74F162A
Synchronous Presettable BCD Decade Counter
General Description
Features
■ Synchronous counting and loading
■ High-speed synchronous expansion
■ Typical count rate of 120 MHz
The 74F160A and 74F162A are high-speed synchronous
decade counters operating in the BCD (8421) sequence.
They are synchronously presettable for applications in pro-
grammable dividers. There are two types of Count Enable
inputs plus a Terminal Count output for versatility in forming
synchronous multistage counters. The F160A has an asyn-
chronous Master Reset input that overrides all other inputs
and forces the outputs LOW. The F162A has a Synchro-
nous Reset input that overrides counting and parallel load-
ing and allows all outputs to be simultaneously reset on the
rising edge of the clock. The F160A and F162A are high
speed versions of the F160 and F162.
Ordering Code:
Order Number Package Number
Package Description
74F160ASC
74F160ASJ
74F160APC
74F162ASC
74F162APC
M16A
M16D
N16E
M16A
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74F160A
74F162A
© 2000 Fairchild Semiconductor Corporation
DS009485
www.fairchildsemi.com
Logic Symbols
74F160A
74F162A
IEEE/IEC
74F162A
74F160A
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/2.0
50/33.3
50/33.3
CEP
CET
CP
Count Enable Parallel Input
20 µA/−0.6 mA
20 µA/−1.2 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−1.2 mA
20 µA/−0.6 mA
20 µA/−1.2 mA
−1 mA/20 mA
−1 mA/20 mA
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
MR (74F160A) Asynchronous Master Reset Input (Active LOW)
SR (74F162A) Synchronous Reset Input (Active LOW)
P0–P3
PE
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Q0–Q3
TC
Terminal Count Output
www.fairchildsemi.com
2
Functional Description
The 74F160A and 74F162A count modulo-10 in the BCD
(8421) sequence. From state 9 (HLLH) they increment to
state 0 (LLLL). The clock inputs of all flip-flops are driven in
parallel through a clock buffer. Thus all changes of the Q
outputs (except due to Master Reset of the (F160A) occur
as a result of, and synchronous with, the LOW-to-HIGH
transition of the CP input signal. The circuits have four fun-
damental modes of operation, in order of precedence:
asynchronous reset (F160A), synchronous reset (F162A),
parallel load, count-up and hold. Five control inputs—Mas-
ter Reset (MR, F160A), Synchronous Reset (SR, F162A),
Parallel Enable (PE), Count Enable Parallel (CEP) and
Count Enable Trickle (CET)—determine the mode of oper-
ation, as shown in the Mode Select Table. A LOW signal on
MR overrides all other inputs and asynchronously forces all
outputs LOW. A LOW signal on SR overrides counting and
parallel loading and allows all outputs to go LOW on the
next rising edge of CP. A LOW signal on PE overrides
counting and allows information on the Parallel Data (Pn)
The F160A and F162A use D-type edge-triggered flip-flops
and changing the SR, PE, CEP and CET inputs when the
CP is in either state does not cause errors, provided that
the recommended setup and hold times, with respect to the
rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 9. To implement synchronous
multistage counters, the TC outputs can be used with the
CEP and CET inputs in two different ways. Please refer to
the F568 data sheet. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers. In the F160A and F162A
decade counters, the TC output is fully decoded and can
only be HIGH in state 9. If a decade counter is preset to an
illegal state, or assumes an illegal state when power is
applied, it will return to the normal sequence within two
counts, as shown in the State Diagram.
Logic Equations:
inputs to be loaded into the flip-flops on the next rising
edge of CP. With PE and MR (F160A) or SR (F162A)
HIGH, CEP and CET permit counting when both are HIGH.
Conversely, a LOW signal on either CEP or CET inhibits
counting.
Count Enable = CEP × CET × PE
TC = Q0 × Q 1× Q 2 × Q3 × CET
Mode Select Table
State Diagram
Action on the Rising
*SR PE CET CEP
Clock Edge (
)
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
Reset (Clear)
Load (Pn → Qn)
H
H
H
Count (Increment)
No Change (Hold)
No Change (Hold)
X
*For 74’F162A only
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
3-STATE Output
−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
4000V
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
VIL
Input LOW Voltage
0.8
VCD
VOH
Input Clamp Diode Voltage
−1.2
Min
Min
I
I
I
IN = −18 mA
OH = −1 mA
OH = −1 mA
Output HIGH
Voltage
10% VCC
2.5
2.7
V
V
5% VCC
VOL
Output LOW
Voltage
10% VCC
0.5
5.0
7.0
50
Min
Max
Max
Max
0.0
I
OL = 20 mA
IIH
Input HIGH
µA
µA
µA
V
V
IN = 2.7V
IN = 7.0V
Current
IBVI
ICEX
VID
IOD
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
V
VOUT = VCC
I
ID = 1.9 µA
All Other Pins Grounded
IOD = 150 mV
All Other Pins Grounded
4.75
Output Leakage
Circuit Current
V
3.75
µA
0.0
IIL
Input LOW
Current
−0.6
−1.2
−150
55
mA
mA
mA
mA
Max
Max
Max
Max
V
IN = 0.5V (CP, CEP,Pn, MR (F160A))
IN = 0.5V (CET, SR (F162A), PE)
V
IOS
ICC
Output Short-Circuit Current
Power Supply Current
−60
VOUT = 0V
O = HIGH
37
V
www.fairchildsemi.com
4
AC Electrical Characteristics
T
A = +25°C
T
A = −55°C to +125°C
T
A = 0°C to +70°C
CC = +5.0V
L = 50 pF
Max
VCC = +5.0V
V
CC = +5.0V
L = 50 pF
Max
V
Symbol
Parameter
Units
C
L = 50 pF
C
C
Min
90
Typ
120
5.5
Max
Min
75
Min
80
fMAX
Maximum Count Frequency
Propagation Delay, Count
CP to Qn (PE Input HIGH)
Propagation Delay, Load
CP to Qn (PE Input LOW)
Propagation Delay
CP to TC
MHz
ns
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
3.5
3.5
4.0
4.0
5.0
5.0
2.5
2.5
7.5
10.0
8.5
3.5
3.5
4.0
4.0
5.0
5.0
2.5
2.5
9.0
11.5
10.0
10.0
16.5
15.5
9.0
3.5
3.5
4.0
4.0
5.0
5.0
2.5
2.5
8.5
11.0
9.5
7.5
6.0
ns
ns
ns
ns
ns
6.0
8.5
9.5
10.0
10.0
4.5
14.0
14.0
7.5
15.0
15.0
8.5
Propagation Delay
CET to TC
4.5
7.5
9.0
8.5
Propagation Delay
MR to Qn (74F160A)
Propagation Delay
MR to TC (74F160A)
5.5
4.5
9.0
8.0
12.0
10.5
5.5
4.5
14.0
12.5
5.5
4.5
13.0
11.5
tPHL
AC Operating Requirements
T
A = +25°C
T
A = −55°C to +125°C
T
A = 0°C to +70°C
CC = +5.0V
Max
Symbol
Parameter
VCC = +5.0V
VCC = +5.0V
V
Units
Min
4.0
5.0
5.0
5.0
2.0
2.0
Max
Min
5.5
5.5
Max
Min
4.0
5.0
5.0
5.0
2.0
2.0
tS(H)
Setup Time, HIGH or LOW
Pn to CP (74F160A)
Setup Time, HIGH or LOW
Pn to CP (74F162A)
Hold Time, HIGH or LOW
Pn to CP
ns
tS(L)
tS(H)
tS(L)
ns
ns
t
H(H)
2.5
2.5
tH(L)
tS(H)
tS(L)
tH(H)
Setup Time, HIGH or LOW
PE or SR to CP
11.0
8.5
2.0
0
13.5
10.5
2.0
0
11.5
9.5
2.0
0
Hold Time, HIGH or LOW
PE or SR to CP
t
H(L)
tS(H)
tS(L)
Setup Time, HIGH or LOW
CEP or CET to CP
11.0
5.0
0
13.0
6.0
0
11.5
5.0
0
ns
ns
t
t
H(H)
H(L)
Hold Time, HIGH or LOW
CEP or CET to CP
0
0
0
tW(H)
tW(L)
tW(H)
tW(L)
Clock Pulse Width (Load)
HIGH or LOW
5.0
5.0
4.0
6.0
5.0
5.0
5.0
8.0
5.0
5.0
4.0
7.0
Clock Pulse Width (Count)
HIGH or LOW
ns
ns
tW(L)
MR Pulse Width, LOW
(74F160A)
5.0
6.0
5.0
6.0
5.0
6.0
tREC
Recovery Time
MR to CP (74F160A)
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com
8
相关型号：
74F162ASDC
Decade Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, CDIP16, SLIM, CERAMIC, DIP-16
FAIRCHILD
74F162ASJX
Decade Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, PDSO16, 0.300 INCH, EIAJ, PLASTIC, SOP-16
FAIRCHILD
74F162ASJX
Decade Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, PDSO16, 0.300 INCH, EIAJ, PLASTIC, SOP-16
ROCHESTER
74F162ASJX
F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, 0.300 INCH, EIAJ, PLASTIC, SOP-16
TI
74F162ASPC
Decade Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, PDIP16, SLIM, PLASTIC, DIP-16
FAIRCHILD
74F162AVCQR
Decade Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, PDSO16, 0.300 INCH, SOIC-16
FAIRCHILD
74F163AD-T
Binary Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, PDSO16,
YAGEO
©2020 ICPDF网 联系我们和版权申明