74LVX161284AMTDX [ETC]
17-Bit Bus Transceiver ; 17位总线收发器\n
| 型号： | 74LVX161284AMTDX |
| 厂家： | 
ETC |
| 描述： | 17-Bit Bus Transceiver
|
| 文件： | 总9页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1999
Revised November 2000
74LVX161284A
Low Voltage IEEE 161284 Translating Transceiver
General Description
Features
The LVX161284A contains eight bidirectional data buffers
■ Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
with the exception of output slew rate
and eleven control/status buffers to implement
a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard, with the exception of output slew rate,
and is intended to be used in an Extended Capabilities Port
mode (ECP). The pinout allows for easy connection from
the Peripheral (A-side) to the Host (cable side).
■ Translation capability allows outputs on the cable side to
interface with 5V signals
■ All inputs have hysteresis to provide noise margin
Outputs on the cable side can be configured to be either
open drain or high drive (± 14 mA) and are connected to a
separate power supply pin (VCC cable) to allow these out-
■ B and Y output resistance optimized to drive external
cable
■ B and Y outputs in high impedance mode during power
down
puts to be driven by a higher supply voltage than the
A-side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the VCC cable supply to provide proper
■ Inputs and outputs on cable side have internal pull-up
resistors
■ Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
termination and pull-ups for open drain mode.
■ Replaces the function of two (2) 74ACT1284 devices
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A1–A8/B1–B8 transceiver
pins.
Ordering Code
Package
Order Number
Package Description
Number
74LVX161284AMTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
HD
Description
High Drive Enable Input (Active HIGH)
Direction Control Input
Inputs or Outputs
DIR
A1–A8
B1–B8
A9–A13
Y9–Y13
Inputs or Outputs
Inputs
Outputs
A
14–A17
Outputs
C14–C17
PLHIN
PLH
Inputs
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
Host Logic HIGH Input
Host Logic HIGH Output
HLHIN
HLH
© 2000 Fairchild Semiconductor Corporation
DS500204
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Logic Symbol
Truth Table
Inputs
Outputs
DIR
HD
L
L
B1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13 (Note 1)
C14–C17 Data to A14–A17
PLH Open Drain Mode
L
H
L
B1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
A1–A8 Data to B1–B8 (Note 2)
A9–A13 Data to Y9–Y13 (Note 1)
H
C
14–C17 Data to A14–A17
PLH Open Drain Mode
A1–A8 Data to B1–B8
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
H
H
Note 1: Y9–Y13 Open Drain Outputs
Note 2: B1–B8 Open Drain Outputs
Logic Diagram
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2
Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions
Supply Voltage
VCC
−0.5V to +4.6V
Supply Voltage
VCC—Cable
−0.5V to +7.0V
VCC
3.0V to 3.6V
3.0V to 5.5V
0V to VCC
VCC—Cable Must Be ≥ VCC
Input Voltage (VI)—(Note 4)
A1–A13, PLHIN, DIR, HD
B1–B8, C14–C17, HLHIN
B1–B8, C14–C17, HLHIN
VCC—Cable
DC Input Voltage (VI)
Open Drain Voltage (VO)
Operating Temperature (TA)
−0.5V to VCC + 0.5V
−0.5V to +5.5V (DC)
−2.0V to +7.0V*
0V to 5.5V
−40°C to +85°C
*40 ns Transient
Output Voltage (VO)
A1–A8, A14–A17, HLH
B1–B8, Y9–Y13, PLH
B1–B8, Y9–Y13, PLH
−0.5V to VCC +0.5V
−0.5V to +5.5V (DC)
−2.0V to +7.0V*
*40 ns Transient
DC Output Current (IO)
A1–A8, HLH
±25 mA
±50 mA
84 mA
B1–B8, Y9–Y13
PLH (Output LOW)
PLH (Output HIGH)
−50 mA
Input Diode Current (IIK)—(Note 4)
DIR, HD, A9–A13, PLH, HLH, C14–C17
−20 mA
Output Diode Current (IOK
A1–A8, A14–A17, HLH
B1–B8, Y9–Y13, PLH
)
±50 mA
−50 mA
Note 3: Absolute Maximum continuous ratings are those values beyond
which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions is not
implied.
DC Continuous VCC or Ground Current
Storage Temperature
±200 mA
−65°C to +150°C
2000V
Note 4: Either voltage limit or current limit is sufficient to protect inputs.
ESD (HBM) Last Passing Voltage
DC Electrical Characteristics
VCC
(V)
VCC—Cable
(V)
TA = −40°C to +85°C
Symbol
VIK
Parameter
Units
Conditions
Guaranteed Limits
Input Clamp
Diode Voltage
Minimum
3.0
3.0
−1.2
V
Ii = −18 mA
VIH
An, Bn, PLHIN, DIR, HD
3.0–3.6
3.0–3.6
3.0–3.6
3.0–3.6
3.0–3.6
3.0–3.6
3.3
3.0–5.5
3.0–5.5
3.0–5.5
3.0–5.5
3.0–5.5
3.0–5.5
5.0
2.0
2.3
2.6
0.8
0.8
1.6
0.4
0.8
0.2
2.8
2.4
2.0
2.23
3.1
HIGH Level
Input Voltage
Maximum
Cn
V
V
V
HLHIN
VIL
An, Bn, PLHIN, DIR, HD
LOW Level
Input Voltage
Minimum Input
Hysteresis
Cn
HLHIN
+
−
−
−
∆VT
An, Bn, PLHIN, DIR, HD
VT –VT
+
Cn
3.3
5.0
VT –VT
+
HLHIN
An, HLH
3.3
5.0
VT –VT
VOH
Minimum HIGH
Level Output
Voltage
3.0
3.0
I
I
I
I
I
OH = −50 µA
3.0
3.0
OH = −4 mA
OH = −14 mA
OH = −14 mA
OH = −500 µA
Bn, Yn
Bn, Yn
PLH
3.0
3.0
V
3.0
4.5
3.15
3.15
3
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DC Electrical Characteristics (Continued)
VCC
VCC—Cable TA = −40°C to +85°C
Symbol
VOL
Parameter
An, HLH
Units
Conditions
OL = 50 µA
(V)
3.0
3.0
3.0
3.0
3.0
3.0
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
(V)
3.0
3.0
3.0
4.5
3.0
4.5
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Guaranteed Limits
Maximum LOW
Level Output
Voltage
0.2
0.4
I
I
I
I
I
I
OL = 4 mA
OL = 14 mA
OL = 14 mA
OL = 84 mA
OL = 84 mA
Bn, Yn
0.8
V
Bn, Yn
0.77
0.95
0.9
PLH
PLH
RD
RP
IIH
IIL
Maximum Output
Impedance
B1–B8, Y9–Y13
60
(Note 5)(Note 7)
(Note 5)(Note 7)
55
Ω
Ω
Minimum Output
Impedance
B1–B8, Y9–Y13
B1–B8, Y9–Y13,
30
35
Maximum Pull-Up
Resistance
1650
1650
1150
1150
C
14–C17
B1–B8, Y9–Y13
14–C17
A9–A13, PLHIN
Minimum Pull-Up
Resistance
C
Maximum Input
Current in
,
VI = 3.6V
3.6
3.6
1.0
HD, DIR, HLHIN
C14–C17
µA
µA
HIGH State
3.6
3.6
3.6
5.5
50.0
100
VI = 3.6V
VI = 5.5V
C14–C17
Maximum Input
Current in
A9–A13, PLHIN,
3.6
3.6
−1.0
VI = 0.0V
HD, DIR, HLHIN
C14–C17
C14–C17
A1–A8
LOW State
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
5.5
3.6
3.6
5.5
3.6
3.6
5.5
−3.5
−5.0
20
mA
mA
µA
VI = 0.0V
VI = 0.0V
IOZH
Maximum Output
Disable Current
(HIGH)
V
V
V
V
O = 3.6V
O = 3.6V
O = 5.5V
O = 0.0V
B1–B8
50
µA
B1–B8
100
−20
−3.5
−5.0
µA
IOZL
Maximum
A1–A8
µA
Output Disable
Current (LOW)
Power Down
Output Leakage
Power Down
Input Leakage
PowerDown
B1–B8
mA
mA
B1–B8
IOFF
B1–B8, Y9–Y13,
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
100
100
250
250
µA
µA
µA
V
O = 5.5V
PLH
IOFF
C14–C17, HLHIN
VI = 5.5V
(Note 6)
(Note 6)
IOFF—ICC
Leakage to VCC
IOFF—ICC2 Power Down Leakage
to VCC—Cable
µA
ICC
Maximum Supply
Current
3.6
3.6
3.6
5.5
45
70
mA
VI = VCC or GND
VI = VCC or GND
Note 5: Output impedance is measured with the output active LOW and active HIGH (HD = HIGH).
Note 6: Power-down leakage to VCC or VCC—Cable is tested by simultaneously forcing all pins on the cable-side (B1–B8, Y9–Y13, PLH, C14–C17 and HLHIN
to 5.5V and measuring the resulting ICC or ICC—Cable
)
.
Note 7: This parameter is guaranteed but not tested, characterized only.
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4
AC Electrical Characteristics
T
A = −40°C to + 85°C
VCC = 3.0V–3.6V
Figure
Number
Symbol
Parameter
Units
VCC—Cable = 4.5V–5.5V
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
tPHL
A1–A8 to B1–B8
A1–A8 to B1–B8
B1–B8 to A1–A8
B1–B8 to A1–A8
A9–A13 to Y9–Y13
A9–A13 to Y9–Y13
8.5
8.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 1
Figure 2
Figure 3
Figure 3
Figure 1
Figure 2
Figure 3
Figure 3
(Note 8)
Figure 1
Figure 2
Figure 3
Figure 3
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tSKEW
tPHL
tPLH
tPHL
tPLH
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tpEN
14.0
14.0
8.5
8.5
C14–C17 to A14–A17
C14–C17 to A14–A17
LH-LH or HL-HL
PLHIN to PLH
10.0
10.0
2.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
8.5
PLHIN to PLH
8.5
HLHIN to HLH
10.0
12.0
10.0
10.0
10.0
10.0
13.0
10.0
HLHIN to HLH
Output Disable Time
DIR to A1–A8
ns
ns
ns
ns
ns
Figure 4
Figure 5
Figure 6
Figure 2
Figure 2
Output Enable Time
DIR to A1–A8
Output Disable Time
DIR to B1–B8
Output Enable Time
HD to B1–B8, Y9–Y13
Output Disable Time
HD to B1–B8, Y9–Y13
1.0
1.0
8.0
tpDIS
12.0
Note 8: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type:
(i) A1–A8 to B1–B8, A9–A13 to Y9–Y13
(ii) B1–B8 to A1–A8
(iii) C14–C17 to A14–A17
Capacitance
Symbol
Parameter
Input Capacitance
I/O Pin Capacitance
Typ
3
Units
pF
Conditions
CIN
CI/O (Note 9)
V
V
CC = 0.0V (HD, DIR, A9–A13, C14–C17, PLHIN and HLHIN
)
5
pF
CC = 3.3V
Note 9: CI/O is measured at frequency = 1 MHz, per MIL-STD-883B, Method 3012
5
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AC Loading and Waveforms
Pulse Generator for all pulses: Rate ≤1.0 MHz; ZO ≤ 50Ω; tf ≤ 2.5 ns, tr ≤ 2.5 ns.
FIGURE 1. Port A to B and A to Y Propagation Delay Waveforms
FIGURE 2. Port A to B and A to Y Output Waveforms
FIGURE 3. Port B to A, C to A and HLHin to HLH Propagation Delay Waveforms
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6
AC Loading and Waveforms (Continued)
FIGURE 4. tPHZ and tPLZ Test Load and Waveforms, DIR to A1 - A8
FIGURE 5. tPHZ and tPLZ Test Load and Waveforms, DIR to A1 - A8
7
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AC Loading and Waveforms (Continued)
FIGURE 6. tPHZ and tPLZ Test Load and Waveforms,
DIR to B1–B8
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8
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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