AD7885JQ [ETC]
A/D CONVERTER ; A / D转换器\n
| 型号： | AD7885JQ |
| 厂家： | 
ETC |
| 描述： | A/D CONVERTER
|
| 文件： | 总16页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
a
16-Bit, High-Speed Sampling ADCs
AD7884/AD7885
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Monolithic Construction
Fast Conversion: 5.3 s
High Throughput: 166 kSPS
Low Power: 250 mW
V
SS
V
SS
؎3V
F ؎3V S
IN
AGNDS AGNDF AV AV
DD
IN
DD
R3
C1
3k⍀
R2
3k⍀
؎5V
؎5V
S
IN
AD7884
APPLICATIONS
A1
F
R1
SW1
IN
5k⍀
Automatic Test Equipment
Medical Instrumentation
Industrial Control
Data Acquisition Systems
Robotics
D
R
I
O
U
9-BIT
ADC
DB15
DB0
9
LATCH
SW2
R4
T
P
U
T
V
E
R
S
R5
4k⍀
16
16
4k⍀
+
R6
ALU
2k⍀
9
V
REF–
A2
SW3
16-BIT
9
ACCURATE
DAC
CONTROL
TIMER
CS
RD
R7
2k⍀
GENERAL DESCRIPTION
The AD7884/AD7885 is a 16-bit monolithic analog-to-digital
converter with internal sample-and-hold and a conversion time
of 5.3 µs. The maximum throughput rate is 166 kSPS. It uses a
two-pass flash architecture to achieve this speed. Two input
ranges are available: 5 V and 3 V. Conversion is initiated by
the CONVST signal. The result can be read into a microprocessor
using the CS and RD inputs on the device. The AD7884 has a
16-bit parallel reading structure while the AD7885 has a byte reading
structure. The conversion result is in two’s complement code.
R8
2k⍀
V
F
V
S V
V
REF–
CONVST BUSY DGND
GND
REF+
REF+
INV
V
V
SS
؎3V
AGNDS AGNDF AV AV
DD SS
DD
IN
R3
R2
C1
3k⍀
3k⍀
؎5V
؎5V
S
IN
AD7885
A1
F
R1
SW1
IN
5k⍀
The AD7884/AD7885 has its own internal oscillator which controls
conversion. It runs from 5 V supplies and needs a VREF+ of 3 V.
D
R
I
O
U
9-BIT
ADC
DB7
DB0
9
The AD7884 is available in a 40-lead Cerdip package and in a
44-lead PLCC package.
LATCH
+
ALU
SW2
R4
4k⍀
T
P
U
T
V
E
R
S
R5
4k⍀
8
16
R6
2k⍀
9
V
REF–
The AD7885 is available in a 28-lead Cerdip package and the AD7885A
is available in a 44-lead PLCC package.
A2
SW3
16-BIT
9
ACCURATE
DAC
CONTROL
TIMER
CS
RD
R7
2k⍀
HBEN
R8
2k⍀
V
F
V
S V
V
REF–
CONVST BUSY DGND
GND
REF+
REF+
INV
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(VDD = 5 V ؎ 5%, VSS = –5 V ؎ 5%,
VREF+S = 3 V; AGND = DGND = GND = 0 V; fSAMPLE = 166 kHz. All specifications TMIN to TMAX, unless otherwise noted.)
AD7884/AD7885/AD7885A–SPECIFICATIONS
J
A
B
Parameter
Version1, 2, 3 Version1, 2, 3 Versions1, 2, 3 Unit
Test Conditions/Comments
DC ACCURACY
Resolution
Minimum Resolution for Which
No Missing Codes Are Guaranteed 16
Integral Nonlinearity
16
16
16
16
16
Bits
Bits
0.0075
% FSR max
% FSR typ
% FSR max
ppm FSR/°C typ
% FSR typ
% FSR max
ppm FSR/°C typ
% FSR typ
% FSR max
ppm FSR/°C typ
µV rms typ
Typically 0.003% FSR
AD7885AN/BN: 0.1% typ
AD7885BN: 0.2% max
Positive Gain Error
Positive Gain Error
Gain TC4
Bipolar Zero Error
Bipolar Zero Error
Bipolar Zero TC4
Negative Gain Error
Negative Gain Error
Offset TC4
0.1
0.03
0.03
0.05
2
0.05
0.15
8
0.03
0.05
2
2
0.05
2
0.05
8
0.1
8
0.03
AD7885AN/BN: 0.1% typ
AD7885BN: 0.2% max
2
120
2
120
Noise
120
78 µV rms typical in 3 V Input Range
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) Ratio
82
82
–84
–84
–88
84
82
–88
–84
–88
84
82
–88
–84
–88
dB min
dB typ
dB max
dB typ
dB max
Input Signal: 5 V, 1 kHz Sine Wave, Typically 86 dB
Input Signal: 5 V, 12 kHz Sine Wave
Input Signal: 5 V, 1 kHz Sine Wave
Input Signal: 5 V, 12 kHz Sine Wave
Input Signal: 5 V, 1 kHz Sine Wave
Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order Terms
–84
–84
–84
–84
–84
–84
dB typ
dB typ
fA = 11.5 kHz, fB = 12 kHz, fSAMPLE = 166 kHz
fA = 11.5 kHz, fB = 12 kHz, fSAMPLE = 166 kHz
Third Order Terms
CONVERSION TIME
Conversion Time
Acquisition Time
Throughput Rate
5.3
2.5
166
5.3
2.5
166
5.3
2.5
166
µs max
µs max
kSPS max
There is an overlap between conversion and acquisition.
ANALOG INPUT
Voltage Range
5
3
4
5
3
4
5
3
4
Volts
Volts
mA max
Input Current
REFERENCE INPUT
Reference Input Current
5
5
5
mA max
VREF+S = 3 V
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
10
2.4
0.8
10
2.4
0.8
10
V min
VDD = 5 V 5%
VDD = 5 V 5%
Input Level = 0 V to VDD
V max
µA max
pF max
4
Input Capacitance, CIN
10
10
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
DB15–DB0
4.0
0.4
4.0
0.4
4.0
0.4
V min
V max
ISOURCE = 40 µA
ISINK = 1.6 mA
Floating-State Leakage Current
10
10
15
10
15
µA max
pF max
Floating-State Output Capacitance4 15
POWER REQUIREMENTS
VDD
VSS
IDD
5
5
5
V nom
V nom
mA max
mA max
5% for Specified Performance
5% for Specified Performance
Typically 25 mA
–5
35
30
–5
35
30
–5
35
30
ISS
Typically 25 mA
Power Supply Rejection Ratio
∆Gain/∆VDD
∆Gain/∆VSS
86
86
86
86
86
86
dB typ
dB typ
Power Dissipation
325
325
325
mW max
Typically 250 mW
NOTES
1Temperature ranges are as follows: J, A, B Versions: –40°C to +85°C.
2VIN
= 5 V.
3The AD7885AAP has the same specs as the AD7884AP. The AD7885ABP has the same specs as the AD7884BP.
4Sample tested to ensure compliance.
Specifications subject to change without notice.
–2–
REV. D
AD7884/AD7885
TIMING CHARACTERISTICS1, 2
(VDD = +5 V ؎ 5%, VSS = –5 V ؎ 5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4, and 5.)
Limit at 25؇C
Limit at TMIN, TMAX
(A, B, and J Versions) Unit
Parameter
(All Versions)
Conditions/Comments
t1
t2
t3
t4
t52
t63
t7
50
100
0
60
0
57
5
50
40
10
25
60
60
55
55
50
100
0
60
0
57
5
50
40
80
25
60
60
70
70
ns min
CONVST Pulsewidth
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
CONVST to BUSY Low Delay
CS to RD Setup Time
RD Pulsewidth
CS to RD Hold Time
Data Access Time After RD
Bus Relinquish Time After RD
t8
t9
t10
t11
t12
t13
t14
New Data Valid before Rising Edge of BUSY
HBEN to RD Setup Time
HBEN to RD Hold Time
HBEN Low Pulse Duration
HBEN High Pulse Duration
Propagation Delay from HBEN Falling to Data Valid
Propagation Delay from HBEN Rising to Data Valid
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t7, quoted in the Timing Characteristics
is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
I
OL
TO OUTPUT PIN
100pF
2.1V
C
L
200A
I
OH
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
REV. D
–3–
AD7884/AD7885
t1
t1
CONVST
CONVST
CS
t2
t3
t5
t4
tCONVERT
RD
BUSY
t2
t8
tCONVERT
BUSY
DATA
OLD DATA VALID
NEW DATA VALID
t7
t6
HI-Z
HI-Z
DATA
VALID
DATA
Figure 2. AD7884 Timing Diagram, Using CS and RD
Figure 3. AD7884 Timing Diagram, with CS and RD
Permanently Low
t1
CONVST
t10
t9
HBEN
CS
RD
t3
t4
t5
tCONVERT
t2
BUSY
t7
HI-Z
t6
HI-Z
HI-Z
DATA
VALID
DATA
VALID
DATA
DB0–DB7
DB8–DB15
Figure 4. AD7885 Timing Diagram, Using CS and RD
t1
CONVST
t11
t12
HBEN
tCONVERT
t2
BUSY
t8
t13
t14
OLD DATA VALID
(DB8–DB15)
NEW DATA VALID
(DB8–DB15)
NEW DATA VALID
(DB0–DB7)
NEW DATA VALID
(DB8–DB15)
NEW DATA VALID
(DB0–DB7)
DATA
Figure 5. AD7885 Timing Diagram, with CS and RD Permanently Low
–4–
REV. D
AD7884/AD7885
V
REF+ to AGND . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
REF– to AGND . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
ORDERING GUIDE
Linearity
V
VINV to AGND . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Temperature
Range
Error
SNR Package
Model
(% FSR) (dB) Option
AD7884AP –40°C to +85°C
AD7884BP –40°C to +85°C
AD7885AAP –40°C to +85°C
AD7885ABP –40°C to +85°C
AD7884AQ –40°C to +85°C
AD7884BQ –40°C to +85°C
84
84
84
84
84
84
82
84
84
P-44A
P-44A
P-44A
P-44A
Q-40
Q-40
Q-28
Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C
Industrial Cerdip (J, A, B Versions) . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
28-Lead Cerdip
0.0075
0.0075
0.0075
θ
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 50.9°C/W
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 8.3°C/W
AD7885JQ
–40°C to +85°C
AD7885AQ –40°C to +85°C
AD7885BQ –40°C to +85°C
Q-28
Q-28
40-Lead Cerdip
0.0075
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 44.5°C/W
NOTE
44-Lead PLCC
P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip.
θ
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 47.7°C/W
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 17.5°C/W
ABSOLUTE MAXIMUM RATINGS1
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Power Dissipation (Any Package) to 75°C . . . . . . . . 1000 mW
Degradation above 75°C by . . . . . . . . . . . . . . . . . . 10 mW/°C
V
SS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2If the AD7884/AD7885 is being powered from separate analog and digital supplies,
AVSS should always come up before VSS. See Figure 12 for a recommended
protection circuit using Schottky diodes.
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to –7 V
AGND Pins to DGND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
2
AVDD to VD2D . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVSS to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
GND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VINS, VINF to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7884/AD7885 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–5–
AD7884/AD7885
PIN CONFIGURATIONS
PLCC
CERDIP
1
2
V
V
V
S
V
28
27
26
25
24
23
V
INV
1
2
40
39
38
37
36
35
34
33
32
31
INV
REF+
REF–
6
5
4
3
2
1
44 43 42 41 40
V
F
3V
V
S
F
REF–
REF+
IN
REF+
3
PIN 1
IDENTIFIER
DB15
DB14
DB13
DB12
V
REF+
3
5V
S
3V
S
IN
IN
39
38
37
36
35
34
33
32
31
30
5V
F
7
8
DB12
DB11
DB10
DB9
IN
3V
F
4
4
5V
F
IN
DB7
DB6
DB5
AGNDS
AGNDF
IN
5V
S
5
9
5
AGNDS
IN
AV
DD
10
11
5V
F
6
6
AGNDF
IN
AD7885
TOP VIEW
AV
SS
DB8
7
AD7884
22 DB4
7
AV
DD
AGNDS
AGNDF
DB11
DB10
DB9
NC 12
NC
TOP VIEW
8
AV
SS
(Not to Scale) 21
8
DGND
(Not to Scale)
GND
13
14
15
16
17
DGND
AV
DD
9
20
19
18
17
16
15
9
GND
DB3
GND
V
DD
AD7884
TOP VIEW
(Not to Scale)
V
AV
SS
10
11
12
13
14
V
DB7
DB6
10
11
DB8
DB2
SS
SS
V
SS
V
30 DGND
DB1
GND
DD
V
29 DB5
DD
V
GND 12
29
28
27
26
CONVST
CS
DB0
DD
V
DB7
DB6
DB5
13
SS
BUSY
HBEN
18 19 20 21 22 23 24 25 26 27 28
V
14
15
16
17
18
19
20
RD
SS
V
DD
NC = NO CONNECT
25 DB4
DB3
CONVST
CS
24
23 DB2
DB1
RD
V
22
21 DB0
SS
6
5
4
3
2
1
44 43 42 41 40
BUSY
PIN 1
39
38
37
36
35
34
33
32
31
30
5V
F
7
DB7
DB6
NC
IDENTIFIER
IN
AGNDS
AGNDF
8
9
AV
DD
10
11
12
13
14
15
16
17
DB5
DB4
NC
AV
SS
AD7885A
NC
GND
GND
TOP VIEW
(Not to Scale)
DGND
V
DD
V
DB3
DB2
SS
V
SS
V
29 DB1
DD
18 19 20 21 22 23 24 25 26 27 28
NC = NO CONNECT
–6–
REV. D
AD7884/AD7885
PIN FUNCTION DESCRIPTION
Description
AD7884
AD7885
AD7885A
VINV
VINV
VINV
This pin is connected to the inverting terminal of an op amp, as in Figure 6, and allows
the inversion of the supplied 3 V reference.
VREF–
VREF–
VREF–
This is the negative reference input, and it can be obtained by using an external amplifier
to invert the positive reference input. In this case, the amplifier output is connected to
VREF–. See Figure 6.
3 VINS
3 VINF
_
_
3 VINS
3 VINF
This is the analog input sense pin for the 3 volt analog input range on the AD7884 and
AD7885A.
This is the analog input force pin for the 3 volt analog input range on the AD7884 and
AD7885A. When using this input range, the 5 VINF and 5 VINS pins should be tied to
AGND.
–
3 VIN
–
This is the analog input pin for the 3 volt analog input range on the AD7885. When
using this input range, the 5 VINF and 5 VINS pins should be tied to AGND.
5 VINS
5 VINF
5 VINS
5 VINF
5 VINS
5 VINF
This is the analog input sense pin for the 5 volt analog input range on both the AD7884,
AD7885 and AD7885A.
This is the analog input force pin for the 5 volt analog input range on both the AD7884,
AD7885 and AD7885A. When using this input range, the 3 VINF and 3 VINS pins
should be tied to AGND.
AGNDS
AGNDF
AVDD
AVSS
GND
VSS
AGNDS
AGNDF
AVDD
AVSS
GND
VSS
AGNDS
AGNDF
AVDD
AVSS
GND
VSS
This is the ground return sense pin for the 9-bit ADC and the on-chip residue amplifier.
This is the ground return force pin for the 9-bit ADC and the on-chip residue amplifier.
Positive analog power rail for the sample-and-hold amplifier and the residue amplifier.
Negative analog power rail for the sample-and-hold amplifier and the residue amplifier.
This is the ground return for sample-and-hold section.
Negative supply for the 9-bit ADC.
VDD
VDD
VDD
Positive supply for the 9-bit ADC and all device logic.
CONVST
CS
CONVST
CS
CONVST
CS
This asynchronous control input starts conversion.
Chip Select control input.
RD
RD
RD
Read control input. This is used in conjunction with CS to read the conversion result
from the device output latch.
–
HBEN
BUSY
–
DB0–DB7 DB0–DB7
DGND DGND
HBEN
BUSY
–
High Byte Enable. Active high control input for the AD7885. It selects either the high or
the low byte of the conversion for reading.
Busy output. The Busy output goes low when conversion begins and stays low until it is
completed, at which time it goes high.
Sixteen-bit parallel data word output on the AD7884.
Eight-bit parallel data byte output on the AD7885.
Ground return for all device logic.
BUSY
DB0–DB15
–
DGND
V
VREF+
REF+F
VREF+
VREF+
F
S
VREF+
VREF+
F
S
Reference force input.
Reference sense input. The device operates from a 3 V reference.
S
REV. D
–7–
AD7884/AD7885
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
The AD7884/AD7885 is tested using the CCIFF standard where
two input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of different
significance. The second order terms are usually distanced in
frequency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the THD
specification where it is the ratio of the rms sum of the individual
distortion products to the rms amplitude of the fundamental
expressed in dBs.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Bipolar Zero Error
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal (AGND).
Power Supply Rejection Ratio
Positive Gain Error
This is the ratio, in dBs, of the change in positive gain error to
the change in VDD or VSS. It is a dc measurement.
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (+VREF+S – 1 LSB), after Bipolar
Zero Error has been adjusted out.
OPERATIONAL DIAGRAM
Negative Gain Error
An operational diagram for the AD7884/AD7885 is shown in
Figure 6. It is set up for an analog input range of 5 V. If a
3 V input range is required, A1 should drive 3 VINS and
3 VINF with 5 VINS, 5 VINF being tied to system AGND.
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–VREF+S + 1 LSB), after Bipolar
Zero Error has been adjusted out.
Signal to (Noise + Distortion) Ratio
–5V
+5V
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
AV
V
AV
V
SS
DD
DD
SS
5V
5V
S
IN
F
A1
AD817
AD711
IN
V
IN
AD7884/
AD7885
3V
3V
S
IN
DATA
OUTPUTS
F
IN
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
AGNDS
AGNDF
Thus for an ideal 16-bit converter, this is 98 dB.
AD817
Total Harmonic Distortion
A2
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7884/AD7885, it is
defined as:
CONTROL
INPUTS
V
= +5V
2
DD
V
S
F
REF+
AD845, AD817 OR
EQUIVALENT
V22 +V32 +V42 +V52 +V62
V
A3
REF+
6
AD780
THD (dB)= 20 log
V1
10F
V
INV
8
4
AD845, AD817 OR
EQUIVALENT
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
V
A4
REF–
GND DGND
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
NOTE: POWER SUPPLY DECOUPLING NOT SHOWN
Figure 6. AD7884/AD7885 Operational Diagram
The chosen input buffer amplifier (A1) should have low noise
and distortion and fast settling time for high bandwidth applica-
tions. Both the AD711 and the AD845 are suitable amplifiers.
A2 is the force, sense amplifier for AGND. The AGNDS pin
should be at zero potential. Therefore, the amplifier must have a
low input offset voltage and good noise performance. It must
also have the ability to deal with fast current transients on the
AGNDS pin. The AD817 has the required performance and is
the recommended amplifier.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m or n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
If AGNDS and AGNDF are simply tied together to Star
Ground instead of buffering, the SNR and THD are not signifi-
cantly degraded. However, dc specifications like INL, Bipolar
Zero and Gain Error will be degraded.
–8–
REV. D
AD7884/AD7885
The required 3 V reference is derived from the AD780 and
buffered by the high-speed amplifier A3 (AD845, AD817 or
equivalent). A4 is a unity gain inverter which provides the –3 V
negative reference. The gain setting resistors are on-chip and
are factory trimmed to ensure precise tracking of VREF+. Figure
6 shows A3 and A4 as AD845s or AD817s. These have the ability
to respond to the rapidly changing reference input impedance.
The signal at the output of A2 is proportional to the error
between the first phase result and the actual analog input
signal, and is digitized in the second conversion phase. This
second phase begins when the 16-bit DAC and the Residue
Error Amplifier have both settled. First, SW2 is turned off
and SW3 is turned on. Then, the SHA section of the Resi-
due Amplifier goes into hold mode. Next SW2 is turned off
and SW3 is turned on. The 9-bit result is transferred to the
output latch and ALU. An error correction algorithm now
compensates for the offset inserted in the Residue Amplifier
Section and errors introduced in the first pass conversion and
combines both results to give the 16-bit answer.
CIRCUIT DESCRIPTION
Analog Input Section
The analog input section of the AD7884/AD7885 is shown in
Figure 7. It contains both the input signal conditioning and
sample-and-hold amplifier. Note that the analog input is truly
benign. When SW1a goes open circuit to put the SHA into the
hold mode, SW1b is closed. This means that the input resis-
tors, R1 and R2 are always connected to either virtual ground
or true ground.
R4
؎3V SIGNAL
FROM INPUT
SHA
0 TO –3V
SW2
4k⍀
9-BIT
ADC
9
LATCH
+
ALU
R5
16
R6
2k⍀
4k⍀
9
V
REF–
A2
R3
3k⍀
SW3
RESIDUE AMP
+ SHA
C1
R1
16-BIT
9
3V
3V
5V
5V
F
IN
3k⍀
ACCURATE
DAC
R4
4k⍀
TO 9-BIT
ADC
SW1
A1
S
A
IN
+3V
–3V
R2
R5
F
IN
R6
5k⍀
4k⍀
2k⍀
R7
2k⍀
S
IN
R8
SW1
TO RESIDUE
AMPLIFIER A2
B
V
2k⍀
REF–
Figure 7. AD7884/AD7885 Analog Input Section
V
F
V
S
V
REF–
V
REF+
INV
REF+
When the 3 VINS and 3 VINF inputs are tied to 0 V, the
input section has a gain of –0.6 and transforms an input signal
of 5 volts to the required 3 volts. When the 5 VINS and
5 VINF inputs are grounded, the input section has a gain of
–1 and so the analog input range is now 3 volts. Resistors R4
and R5, at the amplifier output, further condition the 3 volts
signal to be 0 volt to –3 volts. This is the required input for the
9-bit A/D converter section.
Figure 8. A/D Converter Section
Timing and Control Section
Figure 9 shows the timing and control sequence for the AD7884/
AD7885. When the part receives a CONVST pulse, the con-
version begins. The input sample-and-hold goes into the hold
mode 50 ns after the rising edge of CONVST and BUSY goes
low. This is the first phase of conversion and takes 3.35 µs to
complete. The second phase of conversion begins when SW2 is
turned off and SW3 turned on. The Residue Amplifier and SHA
section (A2 in Figure 8) goes into hold mode at this point and
allows the input sample-and-hold to go back into sample mode.
Thus, while the second phase of conversion is ongoing, the
input sample-and-hold is also acquiring the input signal for the
next conversion. This overlap between conversion and acqui-
sition allows throughput rates of 166 kSPS to be achieved.
With SW1a closed, the output of A1 follows the input (the
sample-and-hold is in the track mode). On the rising edge of
the CONVST pulse, SW1a goes open circuit, and capacitor C1
holds the voltage on the output of A1. The sample-and-hold is
now in the hold mode. The aperture delay time for the sample-
and-hold is nominally 50 ns.
A/D Converter Section
The AD7884/AD7885 uses a two-pass flash technique in order
to achieve the required speed and resolution. When the CONVST
control input goes from low to high, the sample-and-hold ampli-
fier goes into the hold mode and a 0 V to –3 V signal is presented
to the input of the 9-bit ADC. The first phase of conversion
generates the 9 MSBs of the 16-bit result and transfers these
to the latch and ALU combination. They are also fed back to the
9 MSBs of the 16-bit DAC. The 7 LSBs of the DAC are per-
manently loaded with 0s. The DAC output is subtracted from
the analog input with the result being amplified and offset in
the Residue Amplifier Section.
SECOND
PHASE
CONVST
FIRST PHASE
3.5s
1.8s
BUSY
TACQ
2.5s
HOLD
SAMPLE
INPUT
SHA
FIRST PHASE OF CONVERSION
1ST 9-BIT CONVERSION
DAC SETTLING TIME
RESIDUE AMPLIFIER
SETTLING TIME
SECOND PHASE OF CONVERSION
2ND 9-BIT CONVERSION
ERROR CORRECTION
OUTPUT LATCH UPDATE
Figure 9. Timing and Control Sequence
REV. D
–9–
AD7884/AD7885
To do this the reference noise needs to be less than 35 µV rms.
In the 100 kHz band, the AD780 noise is less than 30 µV rms,
making it a very suitable reference.
USING THE AD7884/AD7885 ANALOG INPUT RANGES
The AD7884/AD7885 can be set up to have either a 3 volts
analog input range or a 5 volts analog input range. Figures 10
and 11 show the necessary corrections for each of these. The
output code is two’s complement and the ideal code table for
both input ranges is shown in Table I.
The buffer amplifier used to drive the device VREF+ should have
low enough noise performance so as not to affect the overall
system noise requirement. The AD845 and AD817 achieve this.
Decoupling and Grounding
Table I. Ideal Output Code Table for the AD7884/AD7885
Analog Input
The AD7884 and AD7885A have one AVDD pin and two VDD
pins. They also have one AVSS pin and three VSS pins. The
AD7885 has one AVDD pin, one VDD pin, one AVSS pin and
one VSS pin. Figure 6 shows how a common +5 V supply should
be used for the positive supply pins and a common –5 V supply
for the negative supply pins.
؎3 V
؎5 V
Digital Output
In Terms of FSR2 Range3
Range4
Code Transitionl
+FSR/2 – 1 LSB
+FSR/2 – 2 LSBs
+FSR/2 – 3 LSBs
2.999908
2.999817
2.999726
4.999847
4.999695
4.999543
011 . . . 111 to 111 . . . 110
011 . . . 110to011 . . . 101
011 . . . 101to011 . . . 100
For decoupling purposes, the critical pins on both devices are
the AVDD and AVSS pins. Each of these should be decoupled to
system AGND with 10 µF tantalum and 0.1 µF ceramic capaci-
tors right at the pins. With the VDD and VSS pins, it is sufficient
to decouple each of these with ceramic 1 µF capacitors.
AGND + 1 LSB
AGND
0.000092
0.000000
0.000153
0.000000
000 . . . 001 to 000 . . . 000
000 . . . 000to111 . . . 111
AGND – 1 LSB
–0.000092 –0.000153 111 . . . 111to111 . . . 110
–(FSR/2 – 3 LSBs) –2.999726 –4.999543 100 . . . 011 to 100 . . . 010
–(FSR/2 – 2 LSBs) –2.999817 –4.999695 100 . . . 010to100 . . . 001
–(FSR/2 – 1 LSB) –2.999908 –4.999847 100 . . . 001 to 100 . . . 000
AGNDS, AGNDF are the ground return points for the on-chip
9-bit ADC. They should be driven by a buffer amplifier as shown
in Figure 6. If they are tied directly together and then to ground,
there will be a marginal degradation in linearity performance.
NOTES
1This table applies for VREF+S = 3 V.
2FSR (Full-Scale Range) is 6 volts for the 3 V input range and 10 volts for the
5 V input range.
The GND pin is the analog ground return for the on-chip lin-
ear circuitry. It should be connected to system analog ground.
31 LSB on the 3 V range is FSR/216 and is equal to 91.5 µV.
41 LSB on the 5 V range is FSR/216 and is equal to 152.6 µV.
The DGND pin is the ground return for the on-chip digital
circuitry. It should be connected to the ground terminal of the
V
DD and VSS supplies. If a common analog supply is used for
Reference Considerations
The AD7884/AD7885 operates from a 3 volt reference. This
can be derived simply using the AD780 as shown in Figure 6.
AVDD and VDD then DGND should be connected to the com-
mon ground point.
Power Supply Sequencing
AVDD and VDD are connected to a common substrate and there
is typically 17 Ω resistance between them. If they are powered
by separate 5 V supplies, then these should come up simulta-
neously. Otherwise, the one that comes up first will have to
drive 5 V into a 17 Ω load for a short period of time. However,
the standard short-circuit protection on regulators like the 7800
series will ensure that there is no possibility of damage to the
driving device.
5V
S
IN
5V
F
A1
IN
V
INV
3V
3V
S
IN
F
IN
AVSS should always come up either before or at the same
time as VSS. If this cannot be guaranteed, Schottky diodes
should be used to ensure that VSS never exceeds AVSS by
more than 0.3 V. Arranging the power supplies as in Figure
6 and using the recommended decoupling ensures that there
are no power supply sequencing issues as well as giving the
specified noise performance.
Figure 10. 5 V Input Range Connection
5V
5V
S
IN
F
IN
3V
S
IN
+5V
+5V
–5V
–5V
HP5082-2810
OR
EQUIVALENT
3V
F
A1
IN
V
INV
AV
V
AV
V
SS
DD
DD
SS
AD7884/AD7885
Figure 11. 3 V Input Range Connections
The critical performance specification for a reference in a 16-bit
application is noise. The reference pk-pk noise should be insig-
nificant in comparison to the ADC noise. The AD7884/AD7885
has a typical rms noise of 120 µV. For example a reasonable
target would be to keep the total rms noise less than 125 µV.
Figure 12. Schottky Diodes Used to Protect Against
Incorrect Power Supply Sequencing
–10–
REV. D
AD7884/AD7885
3000
2000
1000
0
AD7884/AD7885 PERFORMANCE
Linearity
The linearity of the AD7884/AD7885 is determined by the
on-chip 16-bit D/A converter. This is a segmented DAC which
is laser trimmed for 16-bit DNL performance to ensure that
there are no missing codes in the ADC transfer function. Figure
13 shows a typical INL plot for the AD7884/AD7885.
2.0
V
= +5V
DD
V
= –5V
SS
T
= +25؇C
A
1.5
1.0
0.5
0
(X – 2) (X – 1)
(X)
(X + 1) (X + 2) (X + 3)
CODE
Figure 14. Histogram of 5000 Conversions of a DC Input
If the noise in the converter is too high for an application, it can
be reduced by oversampling and digital filtering. This involves
sampling the input at higher than the required word rate and
then averaging to arrive at the final result. The very fast con-
version time of the AD7884/AD7885 makes it very suitable
for oversampling. For example, if the required input bandwidth
is 40 kHz, the AD7884/AD7885 could be oversampled by a
factor of 2. This yields a 3 dB improvement in the effective
SNR performance. The noise performance in the 5 volt input
range is now effectively 85 µV rms and the resultant spread of codes
for 2500 conversions will be four. This is shown in Figure 15.
0
65535
16384
32768
49152
OUTPUT CODE
Figure 13. AD7884/AD7885 Typical Linearity Performance
Noise
In an A/D converter, noise exhibits itself as code uncertainty in
dc applications and as the noise floor (in an FFT, for example)
in ac applications.
1500
1000
500
0
In a sampling A/D converter like the AD7884/AD7885, all
information about the analog input appears in the baseband
from dc to 1/2 the sampling frequency. An antialiasing filter will
remove unwanted signals above fS/2 in the input signal but the
converter wideband noise will alias into the baseband. In the
AD7884/AD7885, this noise is made up of sample-and-hold noise
and A/D converter noise. The sample-and-hold section contrib-
utes 51 µV rms and the ADC section contributes 59 µV rms.
These add up to a total rms noise of 78 µV. This is the input
referred noise in the 3 V analog input range. When operating
in the 5 V input range, the input gain is reduced to –0.6. This
means that the input referred noise is now increased by a factor
of 1.66 to 120 µV rms.
(X – 1)
(X)
(X + 1) (X + 2)
Figure 14 shows a histogram plot for 5000 conversions of a dc
input using the AD7884/AD7885 in the 5 V input range. The
analog input was set as close as possible to the center of a code
transition. All codes other than the center code are due to the
ADC noise. In this case, the spread is six codes.
CODE
Figure 15. Histogram of 2500 Conversions of a DC Input
Using a ×2 Oversampling Ratio
REV. D
–11–
AD7884/AD7885
Dynamic Performance
MICROPROCESSOR INTERFACING
With a combined conversion and acquisition time of 6 µs, the
AD7884/AD7885 is ideal for wide bandwidth signal processing
applications. Signal to (Noise + Distortion), Total Harmonic
Distortion, Peak Harmonic or Spurious Noise and Intermodu-
lation Distortion are all specified. Figure 16 shows a typical
FFT plot of a 1.8 kHz, 5 V input after being digitized by the
AD7884/AD7885.
The AD7884/AD7885 is designed on a high speed process
which results in very fast interfacing timing (Data Access Time
of 57 ns max). The AD7884 has a full 16-bit parallel bus, and
the AD7885 has an 8-bit wide bus. The AD7884, with its paral-
lel interface, is suited to 16-bit parallel machines whereas the
AD7885, with its byte interface, is suited to 8-bit machines.
Some examples of typical interface configurations follow.
AD7884 to MC68000 Interface
0
f
= 1.8kHz, ؎5V SINE WAVE
Figure 18 shows a general interface diagram for the MC68000,
16-bit microprocessor to the AD7884. In Figure 18, conversion
is initiated by bringing CSA low (i.e., writing to the appropriate
address). This allows the processor to maintain control over the
complete conversion process. In some cases it may be more
desirable to control conversion independent from the processor.
This can be done by using an external sampling timer.
IN
f
= 163kHz
SAMPLE
SNR = 87dB
THD = –95dB
–30
–60
–90
A23–A1
ADDRESS BUS
–120
–150
ADDRESS
MC68000
AD7884
DECODE LOGIC
CSB
CSA
2048 POINT FFT
CONVST
CS
DTACK
Figure 16. AD7884/AD7885 FFT Plot
AS
RD
Effective Number of Bits
R/W
The formula for SNR (see Terminology section) is related to
the resolution or number of bits in the converter. Rewriting the
formula, below, gives a measure of performance expressed in
effective number of bits (N).
D15–D0
DB15–DB0
DATA BUS
N = (SNR – 1.76)/6.02
Figure 18. AD7884 to MC68000 Interface
16
Once conversion has been started, the processor must wait until
it is completed before reading the result. There are two ways of
ensuring this. The first way is to simply use a software delay to
wait for 6.5 µs before bringing CS and RD low to read the data.
15
14
13
12
11
10
The second way is to use the BUSY output of the AD7884 to
generate an interrupt in the MC68000. Because of the nature of
its interrupts, the MC68000 requires additional logic (not shown
in Figure 18) to allow it to be interrupted correctly. For full
information on this, consult the MC68000 User’s Manual.
0
20
40
60
80
FREQUENCY – kHz
Figure 17. Effective Number of Bits vs. Frequency
The effective number of bits for a device can be calculated from
its measured SNR. Figure 17 shows a typical plot of effective
number of bits versus frequency for the AD7884. The sampling
frequency is 166 kHz.
–12–
REV. D
AD7884/AD7885
MEMORY READ
MRDC
82288 BUS
CONTROLLER
CS1
CS2
DECODE
CIRCUITRY
CLK
CLK
AD7884
82284 CLOCK
GENERATOR
RD
CS
CONVST
8282 OR
8283
LATCH
A23–A0
DB15
CLK
DB0
BUSY
80286
CPU
–D
D
15
0
IR –IR
0
7
8259A
INTERRUPT
CONTROLLER
8286 OR 8287
TRANSCEIVER
Figure 19. AD7884 Interfacing to Basic iAPX 286 System
AD7884 to 80286 Interface
AD7885 to 8088 Interface
The 80286 is an advanced high performance processor with
special capabilities aimed at multiuser and multitasking systems.
The AD7885, with its byte (8 + 8) data format, is ideal for use
with the 8088 microprocessor. Figure 20 is the interface diagram.
Conversion is started by enabling CSA. At the end of conversion,
data is read into the processor. The read instructions are:
Figure 19 shows an interface configuration for the AD7884 to
such a system. Note that only signals relevant to the AD7884
are shown. For the full 80286 configuration refer to the iAPX
286 data sheet (Basic System Configuration).
MOV AX, C001 Read 8 MSBs of data
MOV AX, C000 Read 8 LSBs of data
In Figure 19 conversion is started by writing to a selected
address and causing it CS2 to go low. When conversion is com-
plete, BUSY goes high and initiates an interrupt. The processor
can then read the conversion result.
5V
MN/MX
A0
A15–A8
ADDRESS BUS
HBEN
ADDRESS
IO/M
DECODE LOGIC
AD7885
CSB CSA
8088
CONVST
CS
RD
RD
STB
8282
ALE
AD7–AD0
DATA BUS
DB7–DB0
Figure 20. AD7885 to 8088 Interface
REV. D
–13–
AD7884/AD7885
AD7884 to ADSP-2101 Interface
Stand-Alone Operation
Figure 21 shows an interface between the AD7884 and the
ADSP-2101. Conversion is initiated using a timer which allows
very accurate control of the sampling instant. The AD7884 BUSY
line provides an interrupt to the ADSP-2101 when conversion
is completed. The RD pulsewidth of the processor can be pro-
grammed using the Data Memory Wait State Control Register.
The result can then be read from the ADC using the follow-
ing instruction:
If CS and RD are tied permanently low on the AD7884, then,
when a conversion is completed, output data will be valid on the
rising edge of BUSY. This makes the device very suitable for
stand-alone operation. All that is required to run the device is an
external CONVST pulse which can be supplied by a sample
timer. Figure 22 shows the AD7884 set up in this mode with the
BUSY signal providing the clock for the 74HC574 3-state latches.
A0
MR0 = DM (ADC)
TIMER
HBEN
where MR0 is the ADSP-2101 MR0 register, and ADC is the
AD7884 address.
CONVST
DB15–DB8
74HC574
CLK
TIMER
AD7884
DMA13–DMA0
ADSP-2101
DMS
ADDRESS BUS
DB7–DB0
74HC574
CLK
ADDRESS
DECODE LOGIC
AD7884
EN
BUSY
CS
CONVST
RD
CS
IRQn
RD
BUSY
RD
Figure 22. Stand-Alone Operation
DMD15–DMD0
DB15–DB0
DATA BUS
Digital Feedthrough from an Active Bus
It is very important when using the AD7884/AD7885 in a
microprocessor-based system to isolate the ADC data bus from
the active processor bus while a conversion is being executed.
This will yield the best noise performance from the ADC.
Latches like the 74HC574 can be used to do this. If the device
is connected directly to an active bus then the converter noise
will typically increase by a factor of 30%.
Figure 21. AD7884 to ADSP-2101 Interface
–14–
REV. D
AD7884/AD7885
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Cerdip
(Q-28)
0.005 (0.13) MIN
28
0.100 (2.54) MAX
15
0.610 (15.49)
0.500 (12.70)
1
14
0.620 (15.75)
0.590 (14.99)
PIN 1
0.015
(0.38)
MIN
1.490 (37.85) MAX
0.225
(5.72)
MAX
0.150
(3.81)
MIN
0.018 (0.46)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
15°
0°
SEATING
PLANE
0.026 (0.66) 0.110 (2.79)
0.014 (0.36) 0.090 (2.29)
0.070 (1.78)
0.030 (0.76)
40-Lead Plastic DIP
(Q-40)
0.005 (0.13) MIN
0.098 (2.49) MAX
40
21
0.620 (15.75)
0.510 (12.95)
PIN 1
1
20
0.63 (16.00)
0.59 (14.93)
2.096 (52.23) MAX
0.070 (1.78)
0.015 (0.38)
0.225 (5.72)
MAX
0.200 (5.08)
0.125 (3.18)
15°
0°
0.018 (0.46)
0.008 (0.20)
SEATING
PLANE
0.026 (0.66)
0.014 (0.36)
0.065 (1.65)
0.045 (1.14)
0.100 (2.54)
BSC
44-Lead PLCC
(P-44A)
0.180 (4.57)
0.165 (4.19)
0.056 (1.42)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.048 (1.21)
0.042 (1.07)
6
40
39
7
PIN 1
IDENTIFIER
0.050
(1.27)
BSC
0.63 (16.00)
0.59 (14.99)
0.021 (0.53)
0.013 (0.33)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
17
29
28
18
0.040 (1.01)
0.025 (0.64)
0.020
(0.50)
R
0.656 (16.66)
0.650 (16.51)
SQ
SQ
0.110 (2.79)
0.085 (2.16)
0.695 (17.65)
0.685 (17.40)
REV. D
–15–
AD7884/AD7885
Revision History
Location
Page
Data Sheet changed from REV. C to REV. D.
Addition of Cerdip package to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
“J” Column added to Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Cerdip added to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Addition of Q-28 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
–16–
REV. D
相关型号：
©2020 ICPDF网 联系我们和版权申明