ADMCF326BN_技术文档

28-Lead Flash Memory

DSP Motor Controller

a

ADMCF326

Three-Phase 16-Bit PWM Generator

TARGET APPLICATIONS

16-Bit Center-Based PWM Generator

Programmable Dead Time and Narrow Pulse Deletion

Edge Resolution to 50 ns

150 Hz Minimum Switching Frequency

Double/Single Duty Cycle Update Mode Control

Programmable PWM Pulsewidth

Special Crossover Function for Brushless DC Motors

Individual Enable and Disable for Each PWM Output

High Frequency Chopping Mode for Transformer

Coupled Gate Drives

External PWMTRIP Pin

Integrated ADC Subsystem

Six Analog Inputs

Acquisition Synchronized to PWM Switching Frequency

Internal Voltage Reference

Washing Machines, Refrigerator Compressors, Fans,

Pumps, Industrial Variable Speed Drives

MOTOR TYPES

AC Induction Motors

Permanent Magnet Synchronous Motors (PMSM)

Brushless DC Motors (BDCM)

FEATURES

20 MIPS Fixed-Point DSP Core

Single Cycle Instruction Execution (50 ns)

ADSP-21xx Family Code Compatible

Independent Computational Units

ALU

Multiplier/Accumulator

Barrel Shifter

9-Pin Digital I/O Port

Multifunction Instructions

Single Cycle Context Switch

Powerful Program Sequencer

Zero Overhead Looping

Conditional Instruction Execution

Two Independent Data Address Generators

Memory Conﬁguration

512 ꢀ 24-Bit Program Memory RAM

512 ꢀ 16-Bit Data Memory RAM

4K ꢀ 24-Bit Program Memory ROM

4K ꢀ 24-Bit Program Flash Memory

Three Independent Programmable Sectors

Security Lock Bit

Bit Conﬁgurable as Input or Output

Change of State Interrupt Support

Two 8-Bit Auxiliary PWM Timers

Synthesized Analog Output

Programmable Frequency

0% to 100% Duty Cycle

Two Programmable Operational Modes

Independent Mode/Offset Mode

16-Bit Watchdog Timer

Programmable 16-Bit Internal Timer with Prescaler

Double Buffered Synchronous Serial Port

Hardware Support for UART Emulation

Integrated Power-On Reset Function Options

28-Lead SOIC and PDIP Packages Available

10K Erase/Program Cycles

FUNCTIONAL BLOCK DIAGRAM

MEMORY BLOCK

ADSP-2100 BASE

ARCHITECTURE

PROGRAM PROGRAM

ROM

4K ꢀ 24

FLASH

4K ꢀ 24

DATA

ADDRESS

16-BIT

THREE-

PHASE

PWM

6

VREF

2.5V

PROGRAM

RAM

512 ꢀ 24

DATA

MEMORY

512 ꢀ 16

GENERATORS

ANALOG

INPUTS

PROGRAM

SEQUENCER

DAG 1 DAG 2

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

ARITHMETIC UNITS

SHIFTER

SERIAL PORT

SPORT 1

2 ꢀ 8-BIT

AUX

PWM

WATCH-

DOG

TIMER

9-BIT

PIO

POR

TIMER

ALU MAC

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

(V_DD= 5 V ꢁ 5%, GND = 0 V, T_A= –40ꢂC to +85ꢂC, CLKIN = 10 MHz, unless

otherwise noted.)

ADMCF326–SPECIFICATIONS

ANALOG-TO-DIGITAL CONVERTER

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Signal Input

0.3

3.5

12

4

+20

20

V

V1, V2, V3, VAUX0, VAUX1, VAUX2

Resolution¹

Bits

mV

ns

µA

Linearity Error²

2

0

Zero Offset²

–20

Channel-to-Channel Comparator Match²

Comparator Delay

600

ADC High Level Input Current²

ADC Low Level Input Current²

10

V_IN= 3.5 V

V_IN= 0.0 V

–10

NOTES

¹Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.

²2.44 kHz sample frequency, V1, V2, V3, VAUX0, VAUX1, VAUX2

Speciﬁcations subject to change without notice.

ELECTRICAL CHARACTERISTICS

Parameter

Min

Typ

Max

Unit

Conditions/Comments

V_IL

V_IH

V_OL

V_OH

I_IL

I_IH

I_OZH

I_OZL

I_IL

I_DD

Low Level Input Voltage

0.8

V

High Level Input Voltage

2

Low Level Output Voltage¹

Low Level Output Voltage ²

High Level Output Voltage

Low Level Input Current³

0.4

0.8

I_OL= 2 mA

I_OH= –0.5 mA

V_IN= 0 V

V_IN= V_DD

V_IN= 0

@ V_DD= Max, V_IN= 0 V

4

–120

–10

V

µA

mA

Low Level Input Current

High Level Input Current⁴

High Level Input Current

90

10

90

High Level Three-State Leakage Current⁵

Low Level Three-State Leakage Current⁵

Low Level PWMTRIP Current

Supply Current (Idle)⁶

–10

41

108

123

Supply Current (Dynamic)⁶

Supply Current Programming⁶

NOTES

¹Output Pins PIO0–PIO8, AH, AL, BH, BL, CH, CL

²XTAL Pin

³Internal Pull-Up, RESET

⁴Internal Pull-Down, PWMTRIP, PIO0–PIO8

⁵Three stateable pins DT1, RFS1, TFS1, SCLK1

⁶Outputs not switching

Speciﬁcations subject to change without notice.

CURRENT SOURCE¹

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Programming Resolution

Default Current²

Tuned Current

3

95

105

Bits

µA

65

95

83

100

ICONST_TRIM = 0x00

NOTES

¹For ADC Calibration

²0.3 V to 3.5 V ICONST Voltage

Speciﬁcations subject to change without notice.

REV. B

–2–

ADMCF326

VOLTAGE REFERENCE

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Voltage Level (V_REF

)

2.40

2.45

2.50

35

2.60

2.55

V

T_A= 25°C to 85°C SOIC

Output Voltage Drift

ppm/°C

Speciﬁcations subject to change without notice.

POWER-ON RESET

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Reset Threshold (V_RST

)

3.2

3.7

4.2

V

mV

ms

Hysteresis (V_HYST

)

100

Reset Active Timeout Period (t_RST

^*2¹⁶CLKOUT Cycles.

)

3.2^*

Speciﬁcations subject to change without notice.

FLASH MEMORY

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Endurance

Data Retention

Program and Erase Operating Temperature

10,000

15

0

Cycles

Years

ꢂC

Cycle = Erase/Program/Verify

85

Read Operating Temperature

–40

+85

ꢂC

Speciﬁcations subject to change without notice.

REV. B

–3–

ADMCF326

TIMING PARAMETERS

Parameter

Min

Max

Unit

Clock Signals

Signal t_CKis deﬁned as 0.5 t_CKIN. The ADMCF326 uses an input clock with a

frequency equal to half the instruction rate; a 10 MHz input clock (equivalent to

100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz). When t_CKvalues are

within the range of 0.5 t_CKINperiod, they should be substituted for all relevant

timing parameters to obtain speciﬁcation value.

Example: t_CKH= 0.5 t_CK– 10 ns = 0.5 (50 ns) – 10 ns = 15 ns.

Timing Requirements:

t_CKIN

t_CKIL

t_CKIH

CLKIN Period

CLKIN Width Low

CLKIN Width High

100

20

150

20

ns

Switching Characteristics:

t_CKL

t_CKH

t_CKOH

CLKOUT Width Low

CLKOUT Width High

CLKIN High to CLKOUT High

0.5 t_CK– 10

0

ns

Control Signals

Timing Requirement:

*

t_RSP

RESET Width Low

5 t_CK

ns

PWM Shutdown Signals

Timing Requirement:

t_PWMTPW

PWMTRIP Width Low

t_CK

*

Applies after Power-Up Sequence is Complete

Speciﬁcations subject to change without notice.

t_CKIN

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

Figure 1. Clock Signals

REV. B

–4–

ADMCF326

Parameter

Min

Max

Unit

Serial Ports

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

100

15

20

ns

DR/TFS/RFS Setup before SCLK Low

DR/TFS/RFS Hold after SCLK Low

SCLK_INWidth

40

Switching Characteristics:

t_CC

CLKOUT High to SCLK_OUT

0.25 t_CK

0

0.25 t_CK+ 20

ns

t_SCDE

t_SCDV

t_RH

SCLK High to DT Enable

SCLK High to DT Valid

TFS/RFS_OUTHold after SCLK High

TFS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

SCLK High to DT Disable

TFS (Alt) to DT Enable

TFS (Alt) to DT Valid

RFS (Multichannel, Frame Delay Zero) to DT Valid

30

0

t_RD

t_SCDH

t_SCDD

t_TDE

t_TDV

t_RDV

25

30

Speciﬁcations subject to change without notice.

CLKOUT

SCLK

t_CC

t_SCK

t_SCP

t_SCSt_SCH

t_SCP

DR

RFS

TFS

IN

t_RD

t_RH

RFS

TFS

OUT

t_SCDD

t_SCDV

t_SCDH

t_SCDE

DT

t_TDE

t_TDV

TFS

(ALTERNATE

FRAME MODE)

t_RDV

RFS

(MULTICHANNEL MODE,

FRAME DELAY 0 [MFD = 0])

Figure 2. Serial Port Timing

REV. B

–5–

ADMCF326

ABSOLUTE MAXIMUM RATINGS*

PIN FUNCTION DESCRIPTIONS

Supply Voltage (V_DD

) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V

No.

Name

Type

Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Flash Memory Erase or Program

Temperature Range (Ambient) . . . . . . . . . . . . 0°C to 85°C

Operating Temperature Range (Ambient) . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280°C

Storage Temperature Range for SOIC Package . . –65°C to +150°C

Storage Temperature Range for PDIP Package . . –40°C to +125°C

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. These are stress ratings only; functional

operation of the device at these or any other conditions greater than those indicated

in the operational sections of this speciﬁcation is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

1

2

3

4

5

6

7

8

PIO6/CLKOUT

PIO5/RFS1

PIO4/DR1A

PIO3/SCLK1

PIO2/DR1B

PIO1/DT1

PIO0/TFS1

CLKIN

XTAL

V_DD

PWMTRIP

V3

V2

I/O

I

O

SUP

I

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

I

V1

PIN CONFIGURATION

VAUX0

VAUX1

VAUX2

ICONST

GND

RESET

CH

CL

BH

BL

AH

1

2

PIO6/CLKOUT

PIO5/RFS1

PIO4/DR1A

PIO3/SCLK1

PIO2/DR1B

PIO1/DT1

PIO0/TFS1

CLKIN

28 PIO7/AUX1

I

O

GND

I

O

I/O

27

26

25

24

23

22

21

20

19

18

17

16

15

PIO8/AUX0

3

AL

AH

BL

BH

CL

CH

4

5

6

ADMCF326

TOP VIEW

(Not to Scale)

7

8

XTAL

9

RESET

GND

V

10

11

12

DD

AL

PIO8/AUX0

PIO7/AUX1

ICONST

VAUX2

VAUX1

VAUX0

PWMTRIP

V3

V2 13

V1 14

ORDERING GUIDE

Temperature

Range

Instruction

Rate

Package

Description

Package

Option

Model

ADMCF326BR

ADMCF326BN

ADMCF326-EVALKIT

–40°C to +85°C

20 MHz

28-Lead Wide Body (SOIC)

28-Lead PDIP

Development Tool Kit

SO-28

N-28

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADMCF326 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. B

–6–

ADMCF326

GENERAL DESCRIPTION

FLASH memory, and 512 × 16-bit data memory RAM. The

user code will be stored and executed from the flash memory.

The program and data memory RAM can be used for dynamic

data storage or can be loaded through the serial port from an

external device as in other ADMCxxx family parts. The program

memory ROM contains a monitor function as well as useful rou-

tines for erasing, programming, and verifying the flash memory.

The ADMCF326 is a low cost, single-chip DSP-based controller,

suitable for permanent magnet synchronous motors, ac induction

motors, and brushless dc motors. The ADMCF326 integrates a

20 MIPS, ﬁxed-point DSP core with a complete set of motor

control and system peripherals that permits fast, efﬁcient devel-

opment of motor controllers.

The DSP core of the ADMCF326 is the ADSP-2171, which is

completely code-compatible with the ADSP-21xx DSP family

and combines three computational units, data address generators

and a program sequencer. The computational units comprise an

ALU, a multiplier/accumulator (MAC), and a barrel shifter.

The ADSP-2171 adds new instructions for bit manipulation,

multiplication (× squared), biased rounding, and global inter-

rupt masking.

The motor control peripherals of the ADMCF326 provide a 12-bit

analog data acquisition system with six analog input channels,

and an internal voltage reference. In addition, a three-phase,

16-bit, center-based PWM generation unit can be used to produce

high accuracy PWM signals with minimal processor overhead.

The ADMCF326 also contains two auxiliary PWM outputs

and nine lines of digital I/O.

Because the ADMCF326 has a limited number of pins, functions

such as the auxiliary PWM and the serial communication port

are multiplexed with the nine programmable input/output (PIO)

pins. The pin functions can be independently selected to allow

maximum flexibility for different applications.

The system peripherals are the power-on reset circuit (POR),

the watchdog timer and a synchronous serial port. The serial

port is conﬁgurable and double buffered, with hardware support

for UART and SCI port emulation.

The ADMCF326 provides 512 × 24-bit program memory RAM,

4K × 24-bit program memory ROM, 4K × 24-bit program

INSTRUCTION

REGISTER

FLASH

PROGRAM

MEMORY

4K ꢀ 24

PM ROM

DM RAM

512 ꢀ 16

4K ꢀ 24

DATA

ADDRESS

GENERATOR

#1

DATA

ADDRESS

GENERATOR

#2

PROGRAM

SEQUENCER

PM RAM

512 ꢀ 24

14

PMA BUS

DMA BUS

PMD BUS

DMD BUS

24

BUS

EXCHANGE

16

CONTROL

LOGIC

TIMER

INPUT REGS

ALU

INPUT REGS

SHIFTER

MAC

TRANSMIT REG

COMPANDING

CIRCUITRY

RECEIVE REG

OUTPUT REGS

16

SERIAL

PORT

R BUS

6

Figure 3. DSP Core Block Diagram

REV. B

–7–

ADMCF326

DSP CORE ARCHITECTURE OVERVIEW

Efﬁcient data transfer is achieved with the use of ﬁve

internal buses:

Figure 3 is an overall block diagram of the DSP core of the

ADMCF326, which is based on the ﬁxed-point ADSP-2171.

The flexible architecture and comprehensive instruction set of

the ADSP-2171 allow the processor to perform multiple operations

in parallel. In one processor cycle (50 ns with a 10 MHz CLKIN),

the DSP core can:

•

Program Memory Address (PMA) Bus

Program Memory Data (PMD) Bus

Data Memory Address (DMA) Bus

Data Memory Data (DMD) Bus

Result (R) Bus

•

Generate the next program address

Fetch the next instruction

Perform one or two data moves

Update one or two data address pointers

Perform a computational operation

Program Memory on the ADMCF326 can either be internal

(on-chip RAM) or external (Flash). Internal program memory

can store both instructions and data, permitting the ADMCF326

to fetch two operands in a single instruction cycle—one from

program memory and one from data memory. Operation from

external program memory is described in detail in the ADSP-

2100 Family User’s Manual, Third Edition.

This all takes place while the processor continues to:

•

Receive and transmit through the serial port

Decrement the interval timer

Generate three-phase PWM waveforms for a power inverter

Generate two signals using the 8-bit auxiliary PWM timers

Acquire four analog signals

The ADMCF326 writes data from its 16-bit registers to the 24-bit

program memory using the PX Register to provide the lower

eight bits. When it reads data (not instructions) from 24-bit pro-

gram memory to a 16-bit data register, the lower eight bits are

placed in the PX Register.

Decrement the watchdog timer

The processor contains three independent computational units:

the arithmetic and logic unit (ALU), the multiplier/accumulator

(MAC), and the shifter. The computational units process 16-bit

data directly and have provisions to support multiprecision com-

putations. The ALU performs a standard set of arithmetic and

logic operations as well as provides support for division primitives.

The MAC performs single-cycle multiply, multiply/add, and

multiply/subtract operations with 40 bits of accumulation. The

shifter performs logical and arithmetic shifts, normalization,

denormalization, and derive-exponent operations. The shifter can

be used to efﬁciently implement numeric format control, including

floating-point representations.

The ADMCF326 can respond to a number of distinct DSP

core and peripheral interrupts. The DSP interrupts comprise

a serial port receive interrupt, a serial port transmit interrupt,

a timer interrupt, and two software interrupts. Additionally,

the motor control peripherals include two PWM interrupts

and a PIO interrupt.

The serial port (SPORT1) provides a complete synchronous

serial interface with optional companding in hardware, and a

wide variety of framed and unframed data transmit and receive

modes of operation. SPORT1 can generate an internal program-

mable serial clock or accept an external serial clock.

A programmable interval counter is also included in the DSP

core and can be used to generate periodic interrupts. A 16-bit

count register (TCOUNT) is decremented every n processor

cycles, where n–1 is a scaling value stored in the 8-bit TSCALE

register. When the value of the counter reaches zero, an interrupt

is generated, and the count register is reloaded from a 16-bit

period register (TPERIOD).

The internal result (R) bus directly connects the computational

units so that the output of any unit may be the input of any unit

on the next cycle.

A powerful program sequencer and two dedicated data address

generators ensure efﬁcient delivery of operands to these compu-

tational units. The sequencer supports conditional jumps and

subroutine calls and returns in a single cycle. With internal loop

counters and loop stacks, the ADMCF326 executes looped code

with zero overhead; no explicit jump instructions are required to

maintain the loop.

The ADMCF326 instruction set provides flexible data moves

and multifunction instructions (one or two data moves within a

computation) that will execute from internal program memory

RAM. The ADMCF326 assembly language uses an algebraic

syntax for ease of coding and readability. A comprehensive set of

development tools supports program development. For further

information on the DSP core, refer to the ADSP-2100 Family

User’s Manual, Third Edition, with particular reference to

the ADSP-2171.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches from data memory and pro-

gram memory. Each DAG maintains and updates four address

pointers (I registers). Whenever the pointer is used to access data

(indirect addressing), it is post-modiﬁed by the value in one of

four modify (M registers). A length value may be associated with

each pointer (L registers) to implement automatic modulo

addressing for circular buffers. The circular buffering feature is

also used by the serial ports for automatic data transfers to and

from on-chip memory. DAG1 generates only data memory

addresses and provides an optional bit-reversal capability. DAG2

may generate either program or data memory addresses but has

no bit-reversal capability.

REV. B

–8–

ADMCF326

Serial Port

INTERRUPT OVERVIEW

The ADMCF326 incorporates a complete synchronous serial port

(SPORT1) for serial communication and multiprocessor com-

munication. The following is a brief list of capabilities of the

ADMCF326 SPORT1. Refer to the ADSP-2100 Family User’s

Manual, Third Edition, for further details.

The ADMCF326 can respond to 16 different interrupt sources

with minimal overhead, ﬁve of which are internal DSP core

interrupts and 11 are from the motor control peripherals. The ﬁve

DSP core interrupts are SPORT1 receive (or IRQ0) and transmit

(or IRQ1), the internal timer, and two software interrupts. The

motor control peripheral interrupts are the nine programmable I/Os

and two from the PWM (PWMSYNC pulse and PWMTRIP).

All motor control interrupts are multiplexed into the DSP core

through the peripheral IRQ2 interrupt. The interrupts are internally

prioritized and individually maskable. A detailed description of the

entire interrupt system of the ADMCF326 is presented later,

following a more detailed description of each peripheral block.

•

SPORT1 is bidirectional and has a separate, double-buffered

transmit and receive section.

SPORT1 can use an external serial clock or generate its own

serial clock internally.

SPORT1 has independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame synchronization signals are active high or inverted,

with either of two pulsewidths and timings.

MEMORY MAP

The ADMCF326 has two distinct memory types: program memory

and data memory. In general, program memory contains user

code and coefﬁcients, while the data memory is used to store

variables and data during program execution. Three kinds of

program memory are provided on the ADMCF326: RAM, ROM,

and flash memory. The motor control peripherals are memory

mapped into a region of the data memory space starting at 0x2000.

The complete program and data memory maps are given in

Tables II and III, respectively.

•

SPORT1 supports serial data-word lengths from three bits to 16

bits and provides optional A-law and µ-law companding ac-

cording to ITU (formerly CCITT) recommendation G.711.

•

SPORT1 receive and transmit sections can generate unique

interrupts on completing a data-word transfer.

SPORT1 can receive and transmit an entire circular buffer of

data with only one overhead cycle per data-word. An interrupt is

generated after a data buffer transfer.

Table II. Program Memory Map

Memory

•

SPORT1 can be conﬁgured to have two external interrupts

(IRQ0 and IRQ1), and the Flag In and Flag Out signals.

The internally generated serial clock may still be used in

this conﬁguration.

Address Range

Type

Function

0x0000–0x002F

0x0030–0x01FF

0x0200–0x07FF

0x0800–0x17FF

0x1800–0x1FFF

0x2000–0x20FF

RAM

Internal Vector Table

User Program Memory

Reserved

Reserved Program Memory

Reserved

User Program Memory

Sector 0

User Program Memory

SPORT1 has two data receive pins (DR1A and DR1B), which

are internally multiplexed onto the one DR1 port of the

SPORT1. The particular data receive pin selected is deter-

mined by a bit in the MODECTRL register.

ROM

FLASH

PIN FUNCTION DESCRIPTION

The ADMCF326 is available in both 28-lead SOIC and PDIP

packages. Table I describes the pins.

0x2100–0x21FF

0x2200–0x2FFF

0x3000–0x3FFF

Sector 1

User Program Memory

Sector 2

Table I. Pin List

No.

Reserved

Pin Group

Name

of

Input/

Pins Output Function

Table III. Data Memory Map

Memory

RESET

1

6

I

I/O

Processor Reset Input

Serial Port 1 Pins (TFS1, RFS1,

DT1, DR1A, DR1B, SCLK1)

Processor Clock Output

External Clock or Quartz

Crystal Connection Point

Digital I/O Port Pins

Auxiliary PWM Outputs

PWM Outputs

PWM Trip Signal

Analog Inputs

Auxiliary Analog Input

ADC Constant Current Source

Power Supply

SPORT1^*

Address Range

Type

Function

CLKOUT^*

CLKIN, XTAL

1

2

O

I, O

0x0000–0x1FFF

0x2000–0x20FF

0x2100–0x37FF

0x3800–0x39FF

0x3A00–0x3BFF

0x3C00–0x3FFF

Reserved

Memory Mapped Registers

Reserved

User Data Memory

Reserved

PIO0–PIO8^*

AUX0–AUX1^*

AH–CL

PWMTRIP

V1, V2, V3

VAUX0–VAUX2

ICONST

9

2

6

1

3

1

I/O

O

I

RAM

Memory Mapped Registers

O

V_DD

GND

Ground

*

Multiplexed pins, individually selectable through PIOSELECT and PIODATA1

Registers.

REV. B

–9–

ADMCF326

FLASH MEMORY SUBSYSTEM

monitor program that is located there checks the boot-from-

flash code. If that code is set, the processor jumps to location

0x2200 in external flash program memory, where it expects to

ﬁnd the user’s application program.

The ADMCF326 has 4K × 24-bit of user-programmable, non-

volatile flash memory. A flash programming utility is provided

with the development tools, which performs the basic device

programming operations: erase, program, and verify.

If the boot-from-flash code is not set, the monitor attempts to

boot from an external device as described in the ADMCF32x

DSP Motor Controller Developer’s Reference Manual

The flash memory array is partitioned into three asymmetrically

sized sectors of 256 words, 256 words, and 3584 words, labeled

Sector 0, Sector 1, and Sector 2, respectively. These sectors are

mapped into external program memory address space.

SYSTEM INTERFACE

Figure 4 shows a basic system conﬁguration for the ADMCF326

with an external crystal.

Four flash memory interface registers are connected to the DSP.

These 16-bit registers are mapped into the register area of data

memory space. They are named Flash Memory Control Register

(FMCR), Flash Memory Address Register (FMAR), Flash

Memory Data Register Low (FMDRL), and Flash Memory Data

Register High (FMDRH). These registers are diagrammed later in

this data sheet. They are used by the flash memory programming

utility. The user program may read these registers, but should not

modify them directly. The flash programming utility provides

a complete interface to the flash memory.

22pF

CLKOUT

XTAL

10MHz

CLKIN

22pF

ADMCF326

RESET

Special Flash Registers

Figure 4. Basic System Conﬁguration

Clock Signals

The flash module has four nonvolatile 8-bit registers called Special

Flash Registers (SFRs) that are accessible independently of the

main flash array via the flash programming utility. These regis-

ters are for general-purpose, nonvolatile storage. When erased,

the Special Flash Registers contain all 0s. To read Special Flash

Registers from the user program, call the read_reg routine con-

tained in ROM. Refer to the ADMCF32x DSP Motor Controller

Developer’s Reference Manual for an example.

The ADMCF326 can be clocked either by a crystal or a TTL-

compatible clock signal. For normal operation, the CLKIN

input cannot be halted, changed during operation, or operated

below the speciﬁed minimum frequency. If an external clock is

used, it should be a TTL-compatible signal running at half

the instruction rate. The signal is connected to the CLKIN pin

of the ADMCF326. In this mode, with an external clock signal,

the XTAL pin must be left unconnected. The ADMCF326 uses

an input clock with a frequency equal to half the instruction

rate; a 10 MHz input clock yields a 50 ns processor cycle (which

is equivalent to 20 MHz). Normally, instructions are executed

in a single processor cycle. All device timing is relative to the

internal instruction rate, which is indicated by the CLKOUT

signal when enabled.

Boot-from-Flash Code

A security feature is available in the form of a code that, when set,

causes the processor to execute the program in flash memory upon

power-up or reset. In this mode, the flash programming utility

and debugger are unable to communicate with the ADMCF326.

Consequently, the contents of the flash memory can neither

be programmed nor read.

The boot-from-flash code may be set via the flash programming

utility, when the user’s program is thoroughly tested and loaded

into flash program memory at address 0x2200. The user’s program

must contain a mechanism for clearing the boot-from-flash code

if reprogramming the flash memory is desired. The only way

to clear boot-from-flash is from within the user program, by calling

the flash_init or auto_erase_reg routines that are included in

the ROM. The user program must be signaled in some way to call

the necessary routine to clear the boot-from-flash code. An example

would be to detect a high level on a PIO pin during start-up initial-

ization and then call the flash_init or auto_erase_routine. The

flash_init routine will erase the entire user program in flash

memory before clearing the boot-from-flash code, thus ensuring

the security of the user program. If security is not a concern, the

auto_erase_reg routine can be used to clear the boot-from-flash

code while leaving the user program intact.

Because the ADMCF326 includes an on-chip oscillator feedback

circuit, an external crystal may be used instead of a clock source, as

shown in Figure 4. The crystal should be connected across the

CLKIN and XTAL pins, with two capacitors as shown in Figure 4.

A parallel-resonant, fundamental frequency, microprocessor-grade

crystal should be used. A clock output signal (CLKOUT) is

generated by the processor at the processor’s cycle rate of twice

the input frequency.

Reset

The ADMCF326 DSP core and peripherals must be correctly

reset when the device is powered up to assure proper initialization.

The ADMCF326 contains an integrated power-on reset (POR)

circuit that provides a complete system reset on power-up and

power-down. The POR circuit monitors the voltage on the

ADMCF326 V_DDpin and holds the DSP core and peripherals

in reset while V_DDis less than the threshold voltage level, V_RST

.

Refer to the ADMCF32x DSP Motor Controller Developer’s Reference

Manual for further instructions and an example of using the

boot-from-flash code.

When this voltage is exceeded, the ADMCF326 is held in reset

for an additional 2¹⁶DSP clock cycles (t_RSTin Figure 5). On

power-down, when the voltage on the V_DDpin falls below

V

_RST–V_HYST, the ADMCF326 will be reset. Also, if the external

FLASH PROGRAM BOOT SEQUENCE

On power-up or reset, the processor begins instruction execu-

tion at address 0x0800 of internal program ROM. The ROM

RESET pin is actively pulled low at any time after power-up, a

complete hardware reset of the ADMCF326 is initiated.

REV. B

–10–

ADMCF326

addition, three control bits of the PWMSEG register permit

crossover of the two signals of a PWM pair for easy control of

ECM or BDCM. In crossover mode, the PWM signal destined

for the high side switch is diverted to the complementary low

side output, and the signal destined for the low side switch is

diverted to the corresponding high side output signal.

V

RST

V

– V

HYST

RST

V

DD

t_RST

RESET

In many applications, there is a need to provide an isolation barrier

in the gate-drive circuits that turn on the power devices of the

inverter. In general, there are two common isolation techniques:

optical isolation using optocouplers, and transformer isolation

using pulse transformers. The PWM controller of the ADMCF326

permits mixing of the output PWM signals with a high frequency

chopping signal to permit an easy interface to such pulse trans-

formers. The features of this gate-drive chopping mode can be

controlled by the PWMGATE Register. There is an 8-bit value

within the PWMGATE Register that directly controls the chopping

frequency. In addition, high frequency chopping can be indepen-

dently enabled for the high side and the low side outputs using

separate control bits in the PWMGATE Register.

Figure 5. Power-On Reset Operation

The ADMCF326 reset sets all internal stack pointers to the

empty stack condition, masks all interrupts, clears the MSTAT

Register and performs a full reset of all of the motor control periph-

erals. Following a power-up, it is possible to initiate a DSP core

and motor control peripheral reset by pulling the RESET pin

low. The RESET signal must meet the minimum pulsewidth

speciﬁcation, t_RSP. Following the reset sequence, the DSP

core starts executing code from the internal PM ROM located

at 0x0800.

DSP Control Registers

The DSP core has a system control register, SYSCNTL, memory

mapped at DM (0x3FFF). SPORT1 is conﬁgured as a serial

port when Bit 10 is set, or as flags and interrupt lines when this

bit is cleared. For proper operation of the ADMCF326, all other

bits in this register must be cleared.

The PWM generator is capable of operating in two distinct modes:

Single Update Mode or Double Update Mode. In Single Update

mode, the duty cycle values are programmable only once per

PWM period, so that the resultant PWM patterns are symmetri-

cal about the midpoint of the PWM period. In the Double Update

Mode, a second updating of the PWM duty cycle values is imple-

mented at the midpoint of the PWM period. In this mode, it is

possible to produce asymmetrical PWM patterns that produce

lower harmonic distortion in three-phase PWM inverters. This

technique also permits the closed-loop controller to change the

average voltage applied to the machine winding at a faster rate,

allowing wider closed-loop bandwidths to be achieved. The operat-

ing mode of the PWM block (Single or Double Update Mode)

is selected by a control bit in MODECTRL Register.

The DSP core has a wait state control register, MEMWAIT,

memory mapped at DM (0x3FFE). The default value of this

resister is 0xFFFF. For proper operation of the ADMCF326,

this register must always contain the value 0x8000.

The conﬁguration of both the SYSCNTL and MEMWAIT Reg-

isters of the ADMCF326 are shown at the end of the data sheet.

THREE-PHASE PWM CONTROLLER

Overview

The PWM generator of the ADMCF326 also provides an internal

signal that synchronizes the PWM switching frequency to the

A/D operation. In Single Update Mode, a PWMSYNC pulse is

produced at the start of each PWM period. In Double Update

Mode, an additional PWMSYNC pulse is produced at the mid-

point of each PWM period. The width of the PWMSYNC pulse

is programmable through the PWMSYNCWT Register.

The PWM generator block of the ADMCF326 is a flexible,

programmable, three-phase PWM waveform generator that can

be programmed to generate the required switching patterns to

drive a three-phase voltage source inverter for ac induction

motors (ACIM) or permanent magnet synchronous motors

(PMSM). In addition, the PWM block contains special functions

that considerably simplify the generation of the required PWM

switching patterns for control of electronically commutated motors

(ECM) or brushless dc motors (BDCM).

The PWM signals produced by the ADMCF326 can be shut

off in a number of different ways. First, there is a dedicated

asynchronous PWM shutdown pin, PWMTRIP, which, when

brought LO, instantaneously places all six PWM outputs in

the LO state. Because this hardware shutdown mechanism is

asynchronous, and the associated PWM disable circuitry does

not use clocked logic, the PWM will shut down even if the DSP

clock is not running. The PWM system may also be shut down

from software by writing to the PWMSWT Register.

The PWM generator produces three pairs of active high PWM

signals on the six PWM output pins (AH, AL, BH, BL, CH, and

CL). The six PWM output signals consist of three high side

drive signals (AH, BH, and CH) and three low side drive signals

(AL, BL, and CL). The switching frequency, dead time, and

minimum pulsewidths of the generated PWM patterns are

programmable using, respectively, the PWMTM, PWMDT, and

PWMPD Registers. In addition, three registers (PWMCHA,

PWMCHB, and PWMCHC) control the duty cycles of the three

pairs of PWM signals.

Status information about the PWM system of the ADMCF326

is available to the user in the SYSSTAT Register. In particular,

the state of PWMTRIP is available, as well as a status bit that

indicates whether operation is in the ﬁrst half or the second half

of the PWM period.

Each of the six PWM output signals can be enabled or disabled

by separate output enable bits of the PWMSEG Register. In

REV. B

–11–

ADMCF326

A functional block diagram of the PWM controller is shown in

Figure 6. The generation of the six output PWM signals on pins

AH to CL is controlled by four important blocks:

Three-Phase Timing Unit

The 16-bit three-phase timing unit is the core of the PWM con-

troller and produces three pairs of pulsewidth modulated signals

with high resolution and minimal processor overhead. There are

four main conﬁguration registers (PWMTM, PWMDT, PWMPD,

and PWMSYNCWT) that determine the fundamental charac-

teristics of the PWM outputs. In addition, the operating mode

of the PWM (Single or Double Update Mode) is selected by Bit 6

of the MODECTRL Register. These registers, in conjunction with

the three 16-bit duty cycle registers (PWMCHA, PWMCHB, and

PWMCHC), control the output of the three-phase timing unit.

•

The three-phase PWM timing unit, which is the core of the

PWM controller, generates three pairs of complemented and

dead-time-adjusted center-based PWM signals.

•

The output control unit allows the redirection of the outputs

of the three-phase timing unit for each channel to either the

high side or low side output. In addition, the output control

unit allows individual enabling/disabling of each of the six

PWM output signals.

PWM Switching Frequency: PWMTM Register

•

The GATE drive unit provides the high chopping frequency

and its subsequent mixing with the PWM signals.

The PWM switching frequency is controlled by the PWM

period register, PWMTM. The fundamental timing unit of

the PWM controller is t_CK= 1/f_CLKOUT,where f_CLKOUT,is the

CLKOUT frequency (DSP instruction rate). Therefore, for a

20 MHz CLKOUT, the fundamental time increment is 50 ns.

The value written to the PWMTM Register is effectively the

number of t_CKclock increments in half a PWM period. The

required PWMTM value is a function of the desired PWM

switching frequency (f_PWM) and is given by:

The PWM shutdown controller manages the two PWM shut-

down modes (via the PWMTRIP pin, and the PWMSWT

Register) and generates the correct RESET signal for the

Timing Unit.

•

The PWM controller is driven by a clock at the same frequency

as the DSP instruction rate, CLKOUT, and is capable of

generating two interrupts to the DSP core. One interrupt is

generated on the occurrence of a PWMSYNC pulse, and

the other is generated on the occurrence of any PWM shut-

down action.

f_CLKOUT

2 × f_PWM

f_CLKIN

f_PWM

PWMTM =

=

Therefore, the PWM switching period, T_S, can be written as:

T_S= 2 × PWMTM × t_CK

PWM DUTY CYCLE

REGISTERS

PWM CONFIGURATION

REGISTERS

PWMTM (15...0)

PWMDT (9...0)

PWMPD (15...0)

PWMSYNCWT (7...0)

MODECTRL (6)

PWMCHA (15...0)

PWMCHB (15...0)

PWMCHC (15...0)

PWMGATE (9...0)

PWMSEG (8...0)

AH

AL

BH

THREE-PHASE

PWM TIMING

UNIT

OUTPUT

CONTROL

UNIT

GATE

DRIVE

UNIT

BL

CH

CL

CLK

SYNC RESET

SYNC

CLK

CLKOUT

PWMSYNC

TO INTERRUPT

CONTROLLER

PWMTRIP

OR

PWMSWT (0)

PWM SHUTDOWN CONTROLLER

Figure 6. Overview of the PWM Controller of the ADMCF326

REV. B

–12–

ADMCF326

For example, for a 20 MHz CLKOUT and a desired PWM

switching frequency of 10 kHz (T_S= 100 µs), the correct value

to load into the PWMTM Register is:

into the output control unit on the rising edge of the PWMSYNC

pulse. In effect, this means that the parameters of the PWM

signals can be updated only once per PWM period at the start of

each cycle. Thus, the generated PWM patterns are symmetrical

about the midpoint of the switching period.

20 × 10⁶

2 × 10 × 10³

PWMTM =

1000 = 0x3E8

In Double Update Mode, there is an additional PWMSYNC pulse

produced at the midpoint of each PWM period. The rising edge

of this new PWMSYNC pulse is again used to latch new values of

the PWM conﬁguration Registers, duty cycle registers, and the

PWMSEG Register. As a result, it is possible to alter both the

characteristics (switching frequency, dead time, minimum pulse-

width and PWMSYNC pulsewidth) and the output duty cycles

at the midpoint of each PWM cycle. Consequently, it is pos-

sible to produce PWM switching patterns that are no longer

symmetrical about the midpoint of the period (asymmetrical

PWM patterns).

The largest value that can be written to the 16-bit PWMTM

Register is 0xFFFF = 65,535, which corresponds to a minimum

PWM switching frequency of:

20 × 10⁶

f_PWM,min

=

= 153 Hz

2 × 65,535

for a CLKOUT frequency of 20 MHz.

PWM Switching Dead Time: PWMDT Register

The second important PWM block parameter that must be

initialized is the switching dead time. This is a short delay time

introduced between turning off one PWM signal (for example

AH) and turning on its complementary signal (AL). This short

time delay is introduced to permit the power switch being turned

off to completely recover its blocking capability before the

complementary switch is turned on. This time delay prevents a

potentially destructive short circuit condition from developing

across the dc link capacitor of a typical voltage source inverter.

In the Double Update Mode, operation in the ﬁrst half or the

second half of the PWM cycle is indicated by Bit 3 of the

SYSSTAT Register. In Double Update Mode, this bit is cleared

during operation in the ﬁrst half of each PWM period (between

the rising edge of the original PWMSYNC pulse and the rising

edge of the new PWMSYNC pulse, which is introduced in

Double Update Mode). Bit 3 of the SYSSTAT Register is set

during the second half of each PWM period. If required, a user

may determine the status of this bit during a PWMSYNC inter-

rupt service routine.

Dead time is controlled by the PWMDT Register. The dead

time is inserted into the three pairs of PWM output signals. The

dead time, T_D, is related to the value in the PWMDT Register by:

The advantages of the Double Update Mode are that lower har-

monic voltages can be produced by the PWM process and wider

control bandwidths are possible. However, for a given PWM

switching frequency, the PWMSYNC pulses occur at twice the

rate in the Double Update Mode. Because new duty cycle values

must be computed in each PWMSYNC interrupt service routine,

there is a larger computational burden on the DSP in the Double

Update Mode.

PWMDT

T_D= PWMDT × 2 × t_CK= 2 ×

f_CLKOUT

Therefore, a PWMDT value of 0x00A (= 10), introduces a 1 µs

delay between the turn-off of any PWM signal (for example AH)

and the turn-on of its complementary signal (AL). The amount

of the dead time can therefore be programmed in increments of

2 t_CK(or 100 ns for a 20 MHz CLKOUT). The PWMDT Register

is a 10-bit Register. For a CLKOUT rate of 20 MHz, its maximum

value of 0x3FF (= 1023) corresponds to a maximum programmed

dead time of:

Width of the PWMSYNC Pulse: PWMSYNCWT Register

The PWM controller of the ADMCF326 produces an internal

PWM synchronization pulse at a rate equal to the PWM switching

frequency in Single Update Mode, and at twice the PWM frequency

in the Double Update Mode. This PWMSYNC synchronizes

the operation of the PWM unit with the A/D converter system.

The width of this PWMSYNC pulse is programmable by the

PWMSYNCWT Register. The width of the PWMSYNC pulse,

T_Dmax= 1023 × 2 × t_CK

= 1023 × 2 × 50 × 10^–9sec

= 102 µs

The dead time can be programmed to zero by writing 0 to the

PWMDT Register.

T_PWMSYNC, is given by:

PWM Operating Mode: MODECTRL and SYSSTAT Registers

The PWM controller of the ADMCF326 can operate in two dis-

tinct modes: Single Update Mode and Double Update Mode.

The operating mode of the PWM controller is determined by

the state of Bit 6 of the MODECTRL Register. If this bit is cleared,

the PWM operates in the Single Update Mode. Setting Bit 6

places the PWM in the Double Update Mode. By default,

following either a peripheral reset or power-on, Bit 6 of the

MODECTRL Register is cleared. This means that the default

operating mode is Single Update Mode.

T_PWMSYNC= t_CK× PWMSYNCWT + 1

(

)

which means that the width of the pulse is programmable from t_CK

to 256 t_CK(corresponding to 50 ns to 12.8 µs for a CLKOUT rate

of 20 MHz). Following a reset, the PWMSYNCWT Register con-

tains 0x27 (= 39) so that the default PWMSYNC width is 2.0 µs.

PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC

Registers

The duty cycles of the six PWM output signals are controlled

by the three duty cycle registers, PWMCHA, PWMCHB, and

PWMCHC. The integer value in the register PWMCHA controls

the duty cycle of the signals on AH and AL. PWMCHB controls

the duty cycle of the signals on BH and BL, and PWMCHC

controls the duty cycle of the signals on CH and CL. The duty

cycle registers are programmed in integer counts of the funda-

mental time unit, t_CK, and deﬁne the desired on-time of the

high side PWM signal produced by the three-phase timing unit

In Single Update Mode, a single PWMSYNC pulse is produced

in each PWM period. The rising edge of this signal marks

the start of a new PWM cycle and is used to latch new values

from the PWM conﬁguration registers (PWMTM, PWMDT,

PWMPD, and PWMSYNCWT) and the PWM duty cycle

registers (PWMCHA, PWMCHB, and PWMCHC) into the

three-phase timing unit. The PWMSEG Register is also latched

REV. B

–13–

ADMCF326

over half the PWM period. The switching signals produced by

the three-phase timing unit are also adjusted to incorporate the

programmed dead time value in the PWMDT Register.

Additionally, it is seen that the dead time is inserted into the

PWM signals in the same way as in the Single Update Mode.

PWMCHA

1

2

The PWM is center-based. This means that in Single Update Mode

the resulting output waveforms are symmetrical and centered in

the PWMSYNC period. Figure 7 presents a typical PWM tim-

ing diagram illustrating the PWM-related registers’ (PWMCHA,

PWMTM, PWMDT, and PWMSYNCWT) control over the

waveform timing in both half cycles of the PWM period. The

magnitude of each parameter in the timing diagram is determined

by multiplying the integer value in each register by t_CK(typically

50 ns). It may be seen in the timing diagram how dead time is

incorporated into the waveforms by moving the switching edges

away from the instants set by the PWMCHA Register.

AH

2 ꢀ PWMDT

2

1

AL

PWMSYNC

PWMSYNCWT + 1

1

PWMSYNCWT + 1

2

SYSSTAT (3)

PWMTM

1

2

Figure 8. Typical PWM Outputs of Three-Phase Timing

Unit in Double Update Mode

PWMCHA

In general, the on-times of the PWM signals in Double Update

Mode are deﬁned by:

AH

2 ꢀ PWMDT

AL

T_AH= PWMCHA + PWMCHA − PWMDT − PWMDT × t

(

)

1

2

1

2

CK

PWMSYNCWT + 1

PWMTM₁+ PWMTM₂− PWMCHA −

PWMSYNC

1

T_AL

=

× t_CK





PWMCHA₂− PWMDT₁− PWMDT₂





SYSSTAT (3)

where the subscript 1 refers to the value of that register during

the ﬁrst half cycle and the subscript 2 refers to the value during

the second half cycle. The corresponding duty cycles are:

PWMTM

Figure 7. Typical PWM Outputs of Three-Phase Timing

Unit in Single Update Mode

T_AH

d_AH

=

−

Each switching edge is moved by an equal amount (PWMDT

× t_CK) to preserve the symmetrical output patterns. The PWMSYNC

pulse, whose width is set by the PWMSYNCWT Register, is also

shown. Bit 3 of the SYSSTAT Register indicates which half cycle

is active. This can be useful in Double Update Mode, as will be

discussed later.

T_S

PWMCHA + PWMCHA₂

PWMTM₁+ PWMTM₂

1

PWMDT + PWMDT₂

PWMTM₁+ PWMTM₂

1

The resultant on-times of the PWM signals shown in Figure 7

may be written as:

T_AL

T_S

d_AL

=

T_AH= 2 × (PWMCHA – PWMDT) × t_CK

T_AL= 2 × (PWMTM – PWMCHA – PWMDT) × t_CK

The corresponding duty cycles are:

PWMTM₁+ PWMTM₂+ PWMCHA

(

1

)

=

PWMTM₁+ PWMTM₂

PWMCHA₂+ PWMDT + PWMDT₂

(

1

)

–

T_AH

T_S

PWMCHA – PWMDT

d_AH

=

PWMTM₁+ PWMTM₂

PWMTM

because for the completely general case in Double Update Mode,

the switching period is given by:

T_ALPWMTM – PWMCHA – PWMDT

d_AL

=

T_S

PWMTM

T_S= PWMTM + PWMTM × t

(

)

1

2

CK

Obviously, negative values of T_AHand T_ALare not permitted

because the minimum permissible value is zero, corresponding

to a 0% duty cycle. In a similar fashion, the maximum value is

T_S, corresponding to a 100% duty cycle.

Again, the values of T_AHand T_ALare constrained to lie between

zero and T_S.

PWM signals similar to those illustrated in Figure 7 and Figure 8

can be produced on the BH, BL, CH, and CL outputs by pro-

gramming the PWMCHB and PWMCHC Registers in a manner

identical to that described for PWMCHA.

The output signals from the timing unit for operation in Double

Update Mode are shown in Figure 8. This illustrates a completely

general case where the switching frequency, dead time, and duty

cycle are all changed in the second half of the PWM period. Of

course, the same value for any or all of these quantities could be

used in both halves of the PWM cycle. However, it can be seen

that there is no guarantee that symmetrical PWM signals will

be produced by the timing unit in this Double Update Mode.

The PWM controller does not produce any PWM outputs until

all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC

Registers have been written to at least once. After these registers

have been written, the counters in the three-phase timing unit

REV. B

–14–

ADMCF326

are enabled. Writing to these registers also starts the main PWM

timer. If during initialization, the PWMTM Register is written

before the PWMCHA, PWMCHB, and PWMCHC Registers,

the ﬁrst PWMSYNC pulse (and interrupt if enabled) will be gener-

ated (1.5 × t_CK× PWMTM) seconds after the initial write to the

PWMTM Register in Single Update Mode. In Double Update Mode,

the ﬁrst PWMSYNC pulse will be generated (t_CK× PWMTM)

seconds after the initial write to the PWMTM Register in Single

Update Mode.

to be less than the value speciﬁed by the PWMPD Register, the

corresponding PWM signal is turned OFF for the entire half

period, and its complementary signal is turned completely ON.

Consider the example where PWMTM = 200, PWMCHA = 5,

PWMDT = 3, and PWMPD = 10 with a CLKOUT of 20 MHz,

while operating in single update mode. For this case, the PWM

switching frequency is 50 kHz and the dead time is 300 ns. The

minimum permissible on-time of any PWM signal over one-half

of any period is 500 ns. Clearly, for this example, the dead-time

adjusted on-time of the AH signal for one-half a PWM period is

(5–3) × 50 ns = 100 ns. Because this is less than the minimum

permissible value, output AH of the timing unit will remain

OFF (0% duty cycle). Additionally, the AL signal will be turned

ON for the entire half period (100% duty cycle).

Effective PWM Resolution

In Single Update Mode, the same values of PWMCHA, PWMCHB,

and PWMCHC are used to deﬁne the on-times in both half

cycles of the PWM period. As a result, the effective resolution of

the PWM generation process is 2 t_CK(or 100 ns for a 20 MHz

CLKOUT) since incrementing one of the duty cycle registers by

one changes the resultant on-time of the associated PWM signals

by t_CKin each half period (or 2 t_CKfor the full period).

Output Control Unit: PWMSEG Register

The operation of the output control unit is managed by the 9-bit

read/write PWMSEG Register. This register sets two distinct

features of the output control unit that are directly useful in the

control of ECM or BDCM.

In Double Update Mode, improved resolution is possible since

different values of the duty cycle registers are used to deﬁne the

on-times in both the ﬁrst and second halves of the PWM period.

As a result, it is possible to adjust the on-time over the whole

period in increments of t_CK. This corresponds to an effective

PWM resolution of t_CKin Double Update Mode (or 50 ns for a

20 MHz CLKOUT).

The PWMSEG Register contains three crossover bits, one for each

pair of PWM outputs. Setting Bit 8 of the PWMSEG Register

enables the Crossover Mode for the AH/AL pair of PWM signals;

setting Bit 7 enables crossover on the BH/BL pair of PWM

signals; and setting Bit 6 enables crossover on the CH/CL pair

of PWM signals. If Crossover Mode is enabled for any pair of

PWM signals, the high side PWM signal from the timing unit

(for example AH) is diverted to the associated low side output

of the output control unit so that the signal will ultimately

appear at the AL pin. Of course, the corresponding low side

output of the timing unit is also diverted to the complementary

high side output of the output control unit so that the signal

appears at Pin AH. Following a reset, the three crossover bits

are cleared so that the Crossover Mode is disabled on all

three pairs of PWM signals.

The achievable PWM switching frequency at a given PWM

resolution is tabulated in Table IV.

Table IV. Achievable PWM Resolution in Single and Double

Update Modes

Resolution Single Update Mode

Double Update Mode

(Bit)

PWM Frequency (kHz) PWM Frequency (kHz)

8

9

10

11

12

39.1

19.5

9.8

4.9

2.4

78.1

39.1

19.5

9.8

The PWMSEG Register also contains six bits (Bits 0 to 5) that

can be used to individually enable or disable each of the six

PWM outputs. If the associated bit of the PWMSEG Register is

set, the corresponding PWM output is disabled regardless of the

value of the corresponding duty cycle register. This PWM output

signal will remain in the OFF state as long as the corresponding

enable/disable bit of the PWMSEG Register is set. The PWM

output enable function gates the crossover function. After a reset,

all six enable bits of the PWMSEG Register are cleared, thereby

enabling all PWM outputs by default.

4.9

Minimum Pulsewidth: PWMPD Register

In many power converter switching applications, it is desirable

to eliminate PWM switching pulses shorter than a certain width.

It takes a ﬁnite time to both turn on and turn off modern

power semiconductor devices. Therefore, if the width of any of the

PWM pulses is shorter than some minimum value, it may

be desirable to completely eliminate the PWM switching for

that particular cycle.

In a manner identical to the duty cycle registers, the PWMSEG

is latched on the rising edge of the PWMSYNC signal so that

changes to this register only become effective at the start of each

PWM cycle in Single Update Mode. In Double Update Mode,

the PWMSEG Register can also be updated at the midpoint of

the PWM cycle.

The allowable minimum on-time for any of the six PWM outputs

for half a PWM period that can be produced by the PWM control-

ler may be programmed using the PWMPD register. The minimum

on-time is programmed in increments of t_CKso that the minimum

on-time produced for any half PWM period, T_MIN, is related to

the value in the PWMPD Register by:

In the control of an ECM, only two inverter legs are switched

at any time, and often the high side device in one leg must be

switched ON at the same time as the low side driver in a second

leg. Therefore, by programming identical duty cycles for two

PWM channels (for example, let PWMCHA = PWMCHB) and

setting Bit 7 of the PWMSEG Register to crossover the BH/BL

pair of PWM signals, it is possible to turn ON the high side

switch of Phase A and the low side switch of Phase B at the

T_MIN= PWMPD × t_CK

A PWMPD value of 0x002 deﬁnes a permissible minimum

on-time of 100 ns for a 20 MHz CLKOUT.

In each half cycle of the PWM, the timing unit checks the on-

time of each of the six PWM signals. If any of the times is found

REV. B

–15–

ADMCF326

same time. In the control of an ECM, one inverter leg (Phase C

in this example) is disabled for a number of PWM cycles. This

disable may be implemented by disabling both the CH and CL

PWM outputs by setting Bits 0 and 1 of the PWMSEG Register.

This is illustrated in Figure 9, where it can be seen that both

the AH and BL signals are identical, because PWMCHA =

PWMCHB, and the crossover bit for Phase B is set. In addition,

the other four signals (AL, BH, CH, and CL) have been disabled

by setting the appropriate enable/disable bits of the PWMSEG

Register. For the situation illustrated in Figure 9, the appropri-

ate value for the PWMSEG Register is 0x00A7. In ECM operation,

because each inverter leg is disabled for certain periods of time,

the PWMSEG Register is changed based upon the position of

the rotor shaft (motor commutation).

enabled by setting Bit 9 of the PWMGATE Register. The high

chopping frequency is controlled by the 8-bit word (GDCLK)

written to Bits 0 to 7 of the PWMGATE Register. The period

and the frequency of this high frequency carrier are:

T_CHOP= 4 × GDCLK + 1 × t_CK

(

)

[

=

]

f_CLKOUT

f_CHOP

4 × GDCLK + 1

(

)

]

[

The GDCLK value may range from 0 to 255, corresponding

to a programmable chopping frequency rate from 19.5 kHz to

5 MHz for a 20 MHz CLKOUT rate. The gate drive features

must be programmed before operation of the PWM controller

and typically are not changed during normal operation of the

PWM controller. Following a reset, by default, all bits of the

PWMGATE Register are cleared so that high frequency chopping

is disabled.

PWMCHA

= PWMCHB

PWMCHA

= PWMCHB

AH

2 ꢀ PWMDT

PWMCHA

AL

BH

BL

2 ꢀ PWMDT

[4 ꢀ (GDCLK+1) ꢀ t_CK

]

CH

CL

PWMTM

Figure 10. Typical PWM signals with high frequency gate

chopping enabled on both high side and low side switches

(GDCLK is the integer equivalent of the value in Bits 0 to 7

of the PWMGATE Register.)

PWMTM

Figure 9. An example of PWM signals suitable for ECM

control. PWMCHA = PWMCHB, BH/BL are a crossover pair.

AL, BH, CH, and CL outputs are disabled. Operation is in

Single Update Mode.

PWM Shutdown

In the event of external fault conditions, it is essential that the

PWM system be instantaneously shut down. Two methods of

sensing a fault condition are provided by the ADMCF326. For

the ﬁrst method, a low level on the PWMTRIP pin initiates

an instantaneous, asynchronous (independent of DSP clock)

shutdown of the PWM controller. This places all six PWM

outputs in the OFF state, disables the PWMSYNC pulse and

associated interrupt signal, and generates a PWMTRIP interrupt

signal. The PWMTRIP pin has an internal pull-down resistor so

that even if the pin becomes disconnected, the PWM outputs will

be disabled. The state of the PWMTRIP pin can be read from

Bit 0 of the SYSSTAT Register.

Gate Drive Unit: PWMGATE Register

The gate drive unit of the PWM controller adds features that

simplify the design of isolated gate drive circuits for PWM

inverters. If a transformer-coupled power device gate drive ampli-

ﬁer is used, the active PWM signal must be chopped at a high

frequency. The PWMGATE Register allows the programming

of this high frequency chopping mode. The chopped active

PWM signals may be required for the high side drivers only,

for the low side drivers only, or for both the high side and

low side switches. Therefore, independent control of this mode

for both high and low side switches is included with two separate

control bits in the PWMGATE Register.

It is possible through software to initiate a PWM shutdown by

writing to the 1-bit read/write PWMSWT Register (0x2061).

Writing to this bit generates a PWM shutdown in a manner

identical to the PWMTRIP pin. Following a PWM shutdown,

it is possible to determine if the shutdown was generated from

hardware or software by reading the same PWMSWT Register.

Reading this register also clears it.

Typical PWM output signals with high frequency chopping

enabled on both high side and low side signals are shown in

Figure 10. Chopping of the high side PWM outputs (AH, BH,

and CH) is enabled by setting Bit 8 of the PWMGATE Register.

Chopping of the low side PWM outputs (AL, BL, and CL) is

REV. B

–16–

ADMCF326

Table V. Fundamental Characteristics of PWM Generation Unit of ADMCF326

16-BIT PWM TIMER

Parameter

Min

Typ

Max

Unit

Counter Resolution

16

100

50

Bits

ns

µs

ns

µs

ns

Hz

Edge Resolution (Single Update Mode)

Edge Resolution (Double Update Mode)

Programmable Dead Time Range

Programmable Dead Time Increments

Programmable Pulse Deletion Range

Programmable Pulse Deletion Increments

PWM Frequency Range

0

100

0

100

150

PWMSYNC Pulsewidth (T_CRST

Gate Drive Chop Frequency Range

)

0.05

0.02

12.5

5

µs

MHz

Restarting the PWM after a fault condition is detected requires

clearing the fault and reinitializing the PWM. Clearing the fault

requires that PWMTRIP returns to a HI state. After the fault has

been cleared, the PWM can be restarted by writing to registers

PWMTM, PWMCHA, PWMCHB, and PWMCHC. After the fault

is cleared and the PWM registers are initialized, internal timing of

the three-phase timing unit will resume, and the new duty cycle

values will be latched on the next rising edge of PWMSYNC.

ICONST_TRIM<2:0>

(CAP RESET)

ICONST

V

C

PWMSYNC (CONVST)

CLK MODECTRL<7>

C

EXTERNAL

CHARGING

CAP

ADC

REGISTERS

GND

V1L

V2L

V3L

COMP

V1

12-BIT

ADC

TIMER

BLOCK

COMP

V2

V3

PWM Registers

ADC REGISTERS

The conﬁguration of the PWM registers is described at the end

of the data sheet. The parameters of the PWM block are tabu-

lated in Table V.

COMP

ADC1

ADC2

ADC3

VAUXL

COMP

ADCAUX

VAUX0

VAUX1

VAUX2

MODECTRL<0..1>

ADC OVERVIEW

4–1

MUX

The ADC of the ADMCF326 is based upon the single slope

conversion technique. This approach offers an inherently

monotonic conversion process within the noise and stability of its

components, and there will be no missing codes.

VREF

Table VI. ADC Auxiliary Channel Selection

MODECTRL (1)

ADCMUX1

MODECTRL (0)

ADCMUX0

Figure 11. ADC Overview

Select

Comparing each ADC input to a reference ramp voltage and

timing the comparison of the two signals performs the conversion

process. The actual conversion point is the time point inter-

section of the input voltage and the ramp voltage (V_C) as shown in

Figure 12. This time is converted to counts by the 12-bit ADC

Timer Block and is stored in the ADC registers. The ramp voltage

used to perform the conversion is generated by driving a ﬁxed

current into an off-chip capacitor, where the capacitor voltage is

VAUX0

VAUX1

VAUX2

Calibration (V_REF

0

1

0

1

0

1

)

The single slope technique has been adapted on the ADMCF326

for four channels that are simultaneously converted. Refer to

Figure 11 for the functional schematic of the ADC. Three of

the main inputs (V1, V2, and V3) are directly connected as

high impedance voltage inputs. The fourth channel has been con-

ﬁgured with a serially-connected 4-to-1 multiplexer. Table VI

shows the multiplexer input selection codes. One of these auxil-

iary multiplexed channels is used to calibrate the ramp against the

internal voltage reference (V_REF).

V_C= I C × t

(

)

Following reset, V_C= 0 at t = 0. This reset and the start of

the conversion process are initiated by the PWMSYNC pulse,

as shown in Figure 12. The width of the PWMSYNC pulse is

controlled by the PWMSYNCWT Register and should be pro-

grammed according to Figure 13 to ensure complete resetting.

In order to compensate for IC process manufacturing tolerances

(and to adjust for capacitor tolerances), the current source of the

ADMCF326 is software programmable. The software setting of the

magnitude of the ICONST current generator is accomplished by

selecting one of eight steps over approximately 20% current range.

REV. B

–17–

ADMCF326

Where T_PWMis equal to the PWM period if operating in Single

Update Mode, or it is equal to half that period if operating in

Double Update Mode. For an assumed CLKOUT frequency

of 20 MHz and PWMSYNC pulsewidth of 2.0 µs, the effective

resolution of the ADC block is tabulated for various PWM

switching frequencies in Table VII.

V

C

CMAX

V1

Table VII. ADC Resolution Examples

V

PWM

Frequency

(kHz)

MODECTRL[7] = 0

MODECTRL[7] = 1

VIL

t

Max

Effective

Resolution

Max

Effective

Resolution

t_VIL

T

CRST

Count

T

–T

CRST

PWM

2.4

4

8

18

25

4095

2480

1230

535

12

4095

2460

1070

760

12

>11

>10

>9

>11

>10

>9

PWMSYNC

380

>8

COMPARATOR

OUTPUT

Charging Capacitor Selection

The charging capacitor value is selected based on the sample

(PWM) frequency desired. A too-small capacitor value will reduce

the available resolution of the ADC by having the ramp voltage

rise rapidly and convert too quickly, not utilizing all possible

counts available in the PWM cycle. Too large a capacitor may not

convert in the available PWM cycle returning 0x000. To select a

charging capacitor, use Figure 14, select the sampling frequency

desired, determine if the current source is to be tuned to a nominal

100 µA or left in the default (0x0 code) trim state, then determine

the proper charge capacitor off the appropriate curve.

Figure 12. Analog Input Block Operation

The ADC system consists of four comparators and a single

timer, which may be clocked at either the DSP rate or half the

DSP rate, depending on the setting of the ADCCNT bit (Bit 7)

of the MODECTRL Register. When this bit is cleared, the timers

count at a slower rate of CLKIN. When this bit is set, they count

at CLKOUT or twice the rate of CLKIN. ADC1, ADC2, ADC3,

and ADCAUX are the registers that capture the conversion

times, which are effectively the timer values, when the associated

comparator trips.

100

200

150

100

TUNED ICONST

10

50

0

DEFAULT ICONST

1

10

100

FREQUENCY – kHz

0

2

4

6

8

10

CHARGING CAPACITOR – nF

Figure 14. Timing Capacitor Selection

Figure 13. PWMSYNCWT Program Value

ADC Resolution

Programmable Current Source

The ADMCF326 has an internal current source that is used to

charge an external capacitor, generating the voltage ramp used

for conversion. The magnitude of the output of the current

source circuit is subject to manufacturing variations and can

vary from one device to the next. Therefore, the ADMCF326

incudes a programmable current source whose output can always

be tuned to within 5% of the target 100 µA. A 3-bit register,

ICONST_TRIM, allows the user to make this adjustment. The

output current is proportional to the value written to the regis-

ter: 0x0 produces the minimum output, and 0x7 produces the

maximum output. The default value of ICONST_TRIM after

reset is 0x0.

The ADC is intrinsically linked to the PWM block through the

PWMSYNC pulse controlling the ADC conversion process.

Because of this link, the effective resolution of the ADC is a

function of both the PWM switching frequency and the rate

at which the ADC counter timer is clocked. For a CLKOUT

period of t_CKand a PWM period of T_PWM, the maximum count of

the ADC is given by:







Max Count = min 4095, T

− T

2 t

(

)



PWM

CRST

CK

for MODECTRL Bit 7 = 1





Max Count = min 4095, T

− T

t

(





CK

PWM

CRST

for MODECTRL Bit 7 = 1

REV. B

–18–

ADMCF326

ADC Reference Ramp Calibration

The auxiliary PWM system of the ADMCF326 can operate in two

different modes: Independent mode or Offset mode. The operating

mode of the auxiliary PWM system is controlled by Bit 8 of the

MODECTRL Register. Setting Bit 8 of the MODECTRL Register

places the auxiliary PWM system in the Independent Mode. In

this mode, the two auxiliary PWM generators are completely

independent, and separate switching frequencies and duty cycles

may be programmed for each auxiliary PWM output. In this mode,

the 8-bit AUXTM0 Register sets the switching frequency of the

signal at the AUX0 output pin. Similarly, the 8-bit AUXTM1

Register sets the switching frequency of the signal at the AUX1 pin.

The fundamental time increment for the auxiliary PWM outputs

is twice the DSP instruction rate (or 2 t_CK) and the correspond-

ing switching periods are given by:

The peak of the ADC ramp voltage should be as close as possible

to 3.5 V to achieve the optimum ADC resolution and signal range.

When the current source is in the default state, the peak of the

ADC ramp slope will be lower than this “3.5 V” target ramp.

When the current source value is increased, the ADC ramp

slope will become closer to the target value. The “tuned” ramp

slope is the one closest to the target ramp.

A simple calibration procedure using the internal 2.5 V reference

voltage allows the selection of the ICONST_TRIM Register

value to reach this:

1. A high quality linear ADC capacitor is selected using Figure 14

for a tuned ICONST.

2. Program PWMSYNCWT to proper count as in Figure 13.

T_{AUX 0}= 2 × AUXTM 0 + 1 × t

(

)

CK

3. The ADC Max Count is calculated, as described in a previ-

ous section.

T_{AUX 1}= 2 × AUXTM1+ 1 × t

(

)

Since the values in both AUXTM0 and AUXTM1 can range from

0 to 0xFF, the achievable switching frequency of the auxiliary PWM

signals may range from 39.1 kHz to 10 MHz for a CLKOUT

frequency of 20 MHz.

4. The target reference conversion is calculated as TARGET =

(Max Count) × (2.5 V/3.5 V).

5. Reset or software sets the ICONST_TRIM Register to zero.

6. Select calibration channel in software on ADC multiplexer.

The on-time of the two auxiliary PWM signals is programmed

by the two 8-bit AUXCH0 and AUXCH1 Registers, according to:

7. The calibration channel value is compared with the target

reference conversion.

T_ON

,

= 2 × AUXTM 0 × t

(

)

AUX 0

CK

8. If this value is greater than the TARGET, the ICONST_TRIM

value is incremented by one, and Step 7 is repeated.

,

= 2 × AUXTM1 × t

(

)

AUX 1

9. If the calibration channel value is less than the TARGET,

the calibration is completed.

so that output duty cycles from 0% to 100% are possible. Duty

cycles of 100% are produced if the on-time value exceeds the

period value. Typical auxiliary PWM waveforms in Independent

Mode are shown in Figure 16(a).

3.5V

TARGET

RAMP

When Bit 8 of the MODECTRL Register is cleared, the auxil-

iary PWM channels are placed in Offset Mode. In Offset Mode,

the switching frequencies of the two signals on the AUX0 and

AUX1 pins are identical and controlled by AUXTM0 in a man-

ner similar to that previously described for Independent Mode.

In addition, the on times of both the AUX0 and AUX1 signals

are controlled by the AUXCH0 and AUXCH1 Registers as be-

fore. However, in this mode the AUXTM1 Register deﬁnes the

offset time from the rising edge of the signal on the AUX0 pin

to that on the AUX1 pin according to:

V

REF

MINIMUM

RAMP

0.3V

T_OFFSET= 2 × AUXTM1+ 1 × t

(

)

CK

Figure 15. Current Ramp

For correct operation in this mode, the value written to the

AUXTM1 Register must be less than the value written to the

AUXTM0 Register. Typical auxiliary PWM waveforms in Offset

Mode are shown in Figure 16(b). Again, duty cycles from 0% to

100% are possible in this mode.

ADC Registers

The conﬁguration of all registers of the ADC System is shown at

the end of the data sheet.

AUXILIARY PWM TIMERS

Overview

In both operating modes, the resolution of the auxiliary PWM

system is eight bits only at the minimum switching frequency

(AUXTM0 = AUXTM1 = 255 in Independent Mode, AUXTM0

= 255 in offset mode). Obviously, as the switching frequency is

increased, the resolution is reduced.

The ADMCF326 provides two variable frequency, variable duty

cycle, 8-bit, auxiliary PWM outputs that are available at the AUX1

and AUX0 pins when enabled. These auxiliary PWM outputs

can be used to provide switching signals to other circuits in a

typical motor control system such as power factor corrected

front end converters or other switching power converters. Alter-

natively, by addition of a suitable ﬁlter network, the auxiliary

PWM output signals can be used as simple single-bit digital-to-

analog converters.

Values can be written to the auxiliary PWM registers at any

time. However, new duty cycle values written to the AUXCH0

and AUXCH1 Registers only become effective at the start of the

next cycle. Writing to the AUXTM0 or AUXTM1 Registers

causes the internal timers to be reset to 0 and new PWM cycles

to begin.

REV. B

–19–

ADMCF326

By default following a reset, Bit 8 of the MODECTRL Register

is cleared, thus enabling Offset Mode. In addition, the registers

AUXTM0 and AUXTM1 default to 0xFF, corresponding to

the minimum switching frequency and zero offset. The on-time

registers AUXCH0 and AUXCH1 default to 0x00.

the SYSSTAT Register may be cleared by writing zero to the

WDTIMER Register. This clears the status bit but does not

enable the watchdog timer.

On reset, the watchdog timer is disabled and is only enabled

when the ﬁrst timeout value is written to the WDTIMER Register.

To prevent the watchdog timer from timing out, the user must

write to the WDTIMER Register at regular intervals (shorter than

the programmed WDTIMER period value). On all but the ﬁrst

write to WDTIMER, the particular value written to the register

is unimportant since writing to WDTIMER simply reloads the

ﬁrst value written to this register.

Auxiliary PWM Interface, Registers and Pins

The registers of the auxiliary PWM system are summarized at

the end of the data sheet.

2 ꢀ (AUXTM0 + 1)

2 ꢀ AUXCH0

PROGRAMMABLE DIGITAL INPUT/OUTPUT

AUX0

The ADMCF326 has nine programmable digital input/output

(PIO) pins that are all multiplexed with other functions. The nine

PIO lines PIO0–PIO8 are multiplexed with the serial port (Pins

PIO0/TFS1 to PIO5/RFS1), the CLKOUT (Pin PIO6/CLKOUT),

and the auxiliary PWM outputs (Pins PIO7/AUX1 and PIO8/

AUX0). When conﬁgured as a PIO, each of these nine pins can

act as an input, output, or an interrupt source.

2 ꢀ (AUXTM1 + 1)

2 ꢀ AUXCH1

AUX1

2 ꢀ AUXCH1

(a) Independent Mode

The operating mode of pins PIO0/TFS1 to PIO7/AUX1 is con-

trolled by the PIOSELECT Register. This 8-bit register has a bit

for each input so that the mode of each pin may be selected indi-

vidually. Bit 0 of PIOSELECT controls the operation of the

PIO0/TFS1 pin. Bit 1 controls the PIO1/DT1 pin, etc. Setting

the appropriate bit in the PIOSELECT Register causes the corre-

sponding pin to be conﬁgured for PIO functionality. Clearing the

bit selects the alternate (SPORT, CLKOUT, or AUXPWM)

mode of the corresponding pin. Following power-on reset, all

bits of PIOSELECT are set such that PIO functionality is

selected. The operating mode of the PIO8/AUX0 pin is selected

by Bit 1 of the PIODATA1 Register. In a manner identical to the

PIOSELECT Register, setting this bit enables PIO functionality

(PIO8) while clearing the bit enables auxiliary PWM func-

tionality (AUX0).

2 ꢀ (AUXTM0 + 1)

2 ꢀ AUXCH0

AUX0

2 ꢀ (AUXTM0 + 1)

AUX1

2 ꢀ AUXCH1

2 ꢀ (AUXTM1 + 1)

(b) Offset Mode

Figure 16. Typical Auxiliary PWM Signals. (All Times in

Increments of t_CK

)

PWM DAC Equation

The auxiliary PWM output can be ﬁltered in order to produce a

low frequency analog signal between 0 V to V_DD. For example, a

2-pole ﬁlter with a 1.2 kHz cutoff frequency will sufﬁciently

attenuate the PWM carrier. Figure 17 shows how the ﬁlter would

be applied.

Once PIO functionality has been selected for any or all of these

nine pins, the direction may be set by the 8-bit PIODIR0 Regis-

ter (for PIO0 to PIO7) and the 1-bit PIODIR1 Register (for PIO8).

Clearing any bit conﬁgures the corresponding PIO line as an

input while setting the bit conﬁgures it as an output. By default,

following a reset, all bits of PIODIR0 and PIODIR1 are cleared

conﬁguring the PIO lines as inputs.

AUXPWM

R1 = R2 = 13kꢃ

C1 = C2 = 10nF

R1

R2

The data of the PIO0 to PIO8 lines is controlled by the

PIODATA0 Register (for PIO0 to PIO7) and Bit 0 of the

PIODATA1 Register (for PIO8). These registers can be used to

read data from those PIO lines conﬁgured as inputs and write data

to those conﬁgured as outputs. Any of the nine pins that have been

conﬁgured for PIO functionality can be made to act as an interrupt

source by setting the appropriate bit of the PIOINTEN0 Register

(for PIO0 to PIO7) or the PIOINTEN1 Register (for PIO8). In

order to act as an interrupt source, the pin must also be conﬁgured

as an input. An interrupt is generated upon a change of state

(low-to-high transition or high-to-low transition) on any input

that has been conﬁgured as an interrupt source. Following a

change of state event on any such input, the corresponding

bit is set in the PIOFLAG0 Register (for PIO0 to PIO7), and

PIOFLAG1 (for PIO8) and a common PIO interrupt is gener-

ated. Reading the PIOFLAG0 and PIOFLAG1 Registers permits

determining the interrupt source. Reading the PIOFLAG0 and

PIOFLAG1 Registers automatically clears all bits of the registers.

C2

C1

Figure 17. Auxiliary PWM Output Filter

WATCHDOG TIMER

The ADMCF326 incorporates a watchdog timer that can per-

form a full reset of the DSP and motor control peripherals in the

event of software error. The watchdog timer is enabled by writing a

timeout value to the 16-bit WDTIMER Register. The timeout

value represents the number of CLKIN cycles required for the

watchdog timer to count down to zero. When the watchdog timer

reaches zero, a full DSP core and motor control peripheral reset

is performed. In addition, Bit 1 of the SYSSTAT Register is set

so that after a watchdog reset, the ADMCF326 can determine

that the reset was due to the timeout of the watchdog timer

and not an external reset. Following a watchdog reset, Bit 1 of

REV. B

–20–

ADMCF326

Table VIII. Auxiliary PWM Timer

AUXILIARY PWM TIMERS

Parameter

Test Conditions

Min

0.039

Typ

Max

Unit

Resolution

PWM Frequency

8

Bits

MHz

10 MHz CLKIN

Following power-on or reset, all bits of PIOINTEN0 and

PIOINTEN1 are cleared so that no interrupts are enabled.

The core interrupts are internally prioritized and individually

maskable. All peripheral interrupts are multiplexed into the DSP

core through the peripheral (IRQ2) interrupt.

Each PIO line has an internal pull-down resistor so that follow-

ing power-on or reset, all nine lines are conﬁgured as input PIOs

and will be read as logic lows if left unconnected.

The PWMSYNC interrupt is triggered by a low-to-high tran-

sition on the PWMSYNC pulse. The PWMTRIP interrupt is

triggered on a high-to-low transition on the PWMTRIP pin, or

by writing to the PWMSWT Register. A PIO interrupt is detected

on any change of state (high-to-low or low-to-high) on the

PIO lines.

Multiplexing of PIO Lines

The PIO0–PIO5 lines are multiplexed on the ADMCF326 with

the functional lines of the serial port, SPORT1. Although the

PIOSELECT Register permits individual selection of the func-

tionality of each pin, certain restrictions apply when using

SPORT1 for serial communications.

The ADMCF326 interrupt control system is conﬁgured and

controlled by the IFC, IMASK, and ICNTL Registers of the

DSP core and by the IRQFLAG register for the PWMSYNC

and PWMTRIP interrupts. PIO interrupts are enabled and

disabled by the PIOINTEN0 and PIOINTEN1 Registers.

In general, when transmitting and receiving data on the DTI and

DRIB pins, respectively, the PIO0/TFS1 and PIO5/RFS1 pins

must also be selected for SPORT (TFS1 and RFS1) functional-

ity even if unframed communication is implemented. Therefore,

when using SPORT1 for any type of serial communication, the

minimal setting for PIOSELECT is 0xD8 (i.e., select DTI, DRIB,

RFS1 and TFS1, select PIO7, PIO6, PIO4, PIO3 as digital I/O).

Table IX. Interrupt Vector Addresses

Interrupt Source

Interrupt Vector Address

PWMTRIP

Peripheral Interrupt (IRQ2)

PWMSYNC

0x002C (Highest Priority)

0x0004

0x000C

0x0008

0x0018

If the serial port communications use an internally generated

SCLK1, the PIO3/SCLK1 pin may be used as a general-purpose

PIO line. When External SCLK Mode is selected, the PIO/SCLK1

pin must be enabled as SCLK1 (PIOSELECT [3] = 0).

PIO

Software Interrupt 1

Software Interrupt 0

SPORT1 Transmit Interrupt (or IRQ1) 0x0020

SPORT1 Receive Interrupt (or IRQ0) 0x0024

When the DRIB data receive line of SPORT1 is selected as

the data receive line (MODECTRL [4] = 1), the PIO4/DRIA

line may be used as a general-purpose PIO pin. When the DRIA

data receive line of SPORT1 is selected as the data receive line

(MODECTRL [4] = 0), the PIO2/DRIB line may be used as

a general-purpose PIO pin.

0x001C

Timer

0x0028 (Lowest Priority)

Interrupt Masking

Interrupt masking (or disabling) is controlled by the IMASK

register of the DSP core. This register contains individual bits

that must be set to enable the various interrupt sources. If any

peripheral interrupt (PWMSYNC, PWMTRIP, or PIO) is to

be enabled, the IRQ2 interrupt enable bit (Bit 9) of the IMASK

Register must be set. The conﬁguration of the IMASK Register

of the ADMCF326 is shown at the end of the data sheet.

The functionality of the PIO6/CLKOUT, PIO7/AUX1, and

PIO8/AUX0 pins may be selected on a pin-by-pin basis as desired.

PIO Registers

The conﬁguration of all registers of the PIO system is shown at

the end of the data sheet.

INTERRUPT CONTROL

Interrupt Conﬁguration

The ADMCF326 can respond to 16 different interrupt sources,

some of which are generated by internal DSP core interrupts

and others from the motor control peripherals. The DSP core

interrupts include the following:

The IFC and ICNTL Registers of the DSP core control and con-

ﬁgure the interrupt controller of the DSP core. The IFC register is

a 16-bit register that may be used to force and/or clear any of

the eight DSP interrupts. Bits 0 to 7 of the IFC register may

be used to clear the DSP interrupts while Bits 8 to 15 can be

used to force a corresponding interrupt. Writing to Bits 11 and 12

in IFC is the only way to create the two software interrupts.

·

A Peripheral (or IRQ2) Interrupt

A SPORT1 Receive (or IRQ0) and a SPORT1 Transmit (or

IRQ1) Interrupt

·

Two Software Interrupts

An Interval Timer Time-Out Interrupt

The ICNTL register is used to conﬁgure the sensitivity (edge

or level) of the IRQ0, IRQ1, and IRQ2 interrupts and to enable/

disable interrupt nesting. Setting Bit 0 of ICNTL conﬁgures the

IRQ0 as edge-sensitive, while clearing the bit conﬁgures it for

level-sensitive. Bit 1 is used to conﬁgure the IRQ1 interrupt.

·

The interrupts generated by the motor control peripherals include:

·

A PWMSYNC Interrupt

Nine Programmable Input/Output (PIO) Interrupts

A PWM Trip Interrupt

REV. B

–21–

ADMCF326

Bit 2 is used to conﬁgure the IRQ2 interrupt. It is recommended

that the IRQ2 interrupt always be conﬁgured as level-sensitive

to ensure that no peripheral interrupts are lost. Setting Bit 4 of

the ICNTL Register enables interrupt nesting. The conﬁgura-

tion of both the IFC and ICNTL Registers is shown at the end

of the data sheet.

9. Contains a status register (SYSSTAT) that indicates the state

of the PWMTRIP pin, the watchdog timer, and the PWM

timer

10. Performs a reset of the motor control peripherals and control

registers following a hardware, software, or watchdog initi-

ated reset

Interrupt Operation

SPORT1 Control

Following a reset, the ROM code on the ADMCF326 must

copy a default interrupt vector table into program memory

RAM from Address 0x0000 to 0x002F. Since each interrupt

source has a dedicated four-word space in this vector table, it is

possible to code short interrupt service routines (ISR) in place.

Alternatively, it may be necessary to insert a JUMP instruction

to the appropriate start address of the interrupt service routine if

more memory is required for the ISR.

Both data receive pins are multiplexed internally into the single

data receive input of SPORT1 as shown in Figure 18. Two con-

trol bits in the MODECTRL Register control the state of the

SPORT1 pins by manipulating internal multiplexers in the

ADMCF326.

ADMCF326

PIO1/DT1

DT1

DR1

PIO4/DR1A

When an interrupt occurs, the program sequencer ensures that

there is no latency (beyond synchronization delay) when pro-

cessing unmasked interrupts. In the case of the timer, SPORT1,

and software interrupts, the interrupt controller automatically

jumps to the appropriate location in the interrupt vector table. At

this point, a JUMP instruction to the appropriate ISR is required.

PIO2/DR1B

PIO0/TFS1

TFS1

RFS1

DSP

CORE

SPORT1

Motor control peripheral interrupts are slightly different. When a

peripheral interrupt is detected, a bit is set in the IRQFLAG Regis-

ter for PWMSYNC and PWMTRIP, or in the PIOFLAG0 or

PIOFLAG1 Registers for a PIO interrupt, and the IRQ2 line

is pulled low until all pending interrupts are acknowledged.

PIO5/RFS1

SCLK1

FL1

PIO3/SCLK1

The DSP software must determine the source of the interrupts

by reading IRQFLAG Register. If more than one interrupt

occurs simultaneously, the higher priority interrupt service routine

is executed. Reading the IRQFLAG Register clears the PWMTRIP

and PWMSYNC bits and acknowledges the interrupt, thus allow-

ing further interrupts when the ISR exits.

UARTEN

DR1SEL

MODECTRL (5 . . . 4)

Figure 18. Internal Multiplexing of SPORT1 Pins

Bit 4 of the MODECTRL Register (DR1SEL) selects between the

two data receive pins. Setting Bit 4 of MODECTRL connects pin

DR1B to the internal data receive port DR1 of SPORT1. Clearing

Bit 4 connects DR1A to DR1.

A user’s PIO interrupt service routine must read the PIOFLAG0

and PIOFLAG1 Registers to determine which PIO port is

the source of the interrupt. Reading registers PIOFLAG0 and

PIOFLAG1 clears all bits in the registers and acknowledges

the interrupt, thus allowing further interrupts after the ISR exits.

Setting Bit 5 of the MODECTRL Register (SPORT1 Mode) con-

ﬁgures the serial port for UART Mode. In this mode, the DR1 and

RFS1 pins of the internal serial port are connected together. Addi-

tionally, setting the SPORT1 Mode bit connects the FL1 flag of

the DSP to the external PIO5/RFS1 pin.

The conﬁguration of all these registers is shown at the end of

the data sheet.

SYSTEM CONTROLLER

The system controller block of the ADMCF326 performs the

following functions:

Flag Pins

The ADMCF326 provides flag pins. The alternate conﬁguration

of SPORT1 includes a Flag In (FI) and Flag Out (FO) pin.

This alternate conﬁguration of SPORT1 is selected by Bit 10 of

the DSP system control register, SYSCNTL at data memory

address 0x3FFF. In the alternate conﬁguration, the DR1 pin

(either DR1A or DR1B depending upon the state of the DR1SEL

bit) becomes the FI pin and the DT1 pin becomes the FO pin.

Additionally, RFS1 is conﬁgured as the IRQ0 interrupt input

and TFS1 is conﬁgured as the IRQ1 interrupt. The serial port

clock, SCLK1, is still available in the alternate conﬁguration.

1. Manages the interface and data transfer between the DSP core

and the motor control peripherals

2. Handles interrupts generated by the motor control peripherals

and generates a DSP core interrupt signal IRQ2

3. Controls the ADC multiplexer select lines

4. Enables PWMTRIP and PWMSYNC interrupts

5. Controls the multiplexing of the SPORT1 pins to select either

DR1A or DR1B data receive pins. It also allows conﬁgura-

tion of SPORT1 as a UART interface.

Development Tools

Users are recommended to obtain the ADMCF326-EVALKIT

from Analog Devices. The tool kit contains everything required

to quickly and easily evaluate and develop applications using the

ADMCF326 and ADMC326 DSP Motor Controllers. Please

contact your ADI sales representative for ordering information.

6. Controls the PWM Single/Double Update Mode

7. Controls the ADC conversion time modes

8. Controls the auxiliary PWM Operation Mode

REV. B

–22–

ADMCF326

Table X. Peripheral Register Map

Bits Used

Address

(HEX)

Name

Function

0x2000

0x2001

0x2002

0x2003

0x2004

0x2005

0x2006

0x2007

ADC1

ADC2

ADC3

[15 . . . 4]

[7 . . . 0]

[15 . . . 0]

[9 . . . 0]

[15 . . . 0]

[8 . . . 0]

[7 . . . 0]

ADC Results for V1

ADC Results for V2

ADC Results for V3

ADC Results for VAUX

PIO0 . . . 7 Pins Direction Setting

PIO0 . . . 7 Pins Input/Output Data

PIO0 . . . 7 Pins Interrupt Enable

PIO0 . . . 7 Pins Interrupt Status

PWM Period

ADCAUX

PIODIR0

PIODATA0

PIOINTEN0

PIOFLAG0

PWMTM

PWMDT

PWMPD

PWMGATE

PWMCHA

PWMCHB

PWMCHC

PWMSEG

AUXCH0

AUXCH1

AUXTM0

AUXTM1

0x2008

0x2009

PWM Dead Time

0x200A

0x200B

0x200C

0x200D

0x200E

0x200F

0x2010

0x2011

0x2012

0x2013

0x2014

PWM Pulse Deletion Time

PWM Gate Drive Conﬁguration

PWM Channel A Pulsewidth

PWM Channel B Pulsewidth

PWM Channel C Pulsewidth

PWM Segment Select

AUX PWM Output 0

AUX PWM Output 1

Auxiliary PWM Frequency Value

Auxiliary PWM Frequency Value/Offset

Reserved

0x2015

0x2016

0x2017

0x2018

MODECTRL

SYSSTAT

IRQFLAG

[8 . . . 0]

[3 . . . 0]

[1 . . . 0]

[15 . . . 0]

Mode Control Register

System Status

Interrupt Status

WDTIMER

Watchdog Timer

0x2019 . . . 43

0x2044

0x2045

0x2046

0x2047

Reserved

PIODIR1

[0]

[1 . . . 0]

[0]

PIO8 Pin Direction Setting

PIO8 Data and Mode Control

PIO8 Pin Interrupt Enable

PIO8 Pin Interrupt Status

Reserved

PIODATA1

PIOINTEN1

PIOFLAG1

[0]

0x2048

0x2049

0x204A . . . 5F

PIOSELECT

[7 . . . 0]

PIO0 to PIO7 Mode Select

Reserved

0x2060

0x2061

PWMSYNCWT

PWMSWT

[7 . . . 0]

[0]

PWMSYNC Pulsewidth

PWM S/W Trip Bit

0x2062 . . . 67

0x2068

Reserved

ICONST_TRIM

[2. . .0]

0x2069 . . . 70

0x2080

0x2081

0x2082

0x2083

Reserved

FMCR

FMAR

FMDRH

FMDRL

[15. . .0]

[11. . .0]

[13. . .0]

[15. . .0]

Flash Memory Control Register

Flash Memory Address Register

Flash Memory Data Register High

Flash Memory Data Register Low

Reserved

0x2084 . . . FF

REV. B

–23–

ADMCF326

Table XI. DSP Core Registers

Bits

Address

Name

Function

0x3FFF

0x3FFE

0x3FFD

0x3FFC

0x3FFB

0x3FFA . . . F3

0x3FF2

0x3FF1

0x3FF0

0x3FEF

SYSCNTL

MEMWAIT

TPERIOD

TCOUNT

TSCALE

[15 . . . 0]

[7 . . . 0]

System Control Register

Memory Wait State Control Register

Interval Timer Period Register

Interval Timer Count Register

Interval Timer Scale Register

Reserved

SPORT1_CTRL_REG

SPORT1_SCLKDIV

SPORT1_RFSDIV

[15 . . . 0]

SPORT1 Control Register

SPORT1 Clock Divide Register

SPORT1 Receive Frame Sync Divide

SPORT1 Autobuffer Control Register

SPORT1_AUTOBUF_CTRL

[15 . . . 0]

REV. B

–24–

ADMCF326

FLASH MEMORY CONTROL REGISTER

15 14 13 12 11 10

9

8

7

6

5

4

3

2

0

1

0

1

0

0x2080

BOOT–FROM–FLASH–CODE

FLASH MEMORY ADDRESS REGISTER

15 14 13 12

11 10

9

8

7

6

5

4

3

2

0

1

0

0x2081

ADDRESS 11–0

RESERVED

ALWAYS READ 0

FLASH MEMORY DATA REGISTER LOW (FMDRL)

15 14 13 12

11 10

9

8

7

6

5

4

3

2

0

1

0

0x2083

0

STATUS 5–0

DATA 7–0

RESERVED

ALWAYS READ 0

FLASH MEMORY DATA REGISTER HIGH (FMDRH)

15 14 13 12

11 10

9

8

7

6

5

4

3

2

0

1

0

0x2082

0

DATA 23–8

MOST SIGNIFICANT BIT IS ON THE LEFT. FOR EXAMPLE, DATA23 IS BIT 15 OF

FMDRH.

Figure 19. Conﬁguration of Flash Memory Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these

bits should always be written as shown.

REV. B

–25–

ADMCF326

PWMTM (R/W)

15 14 13 12

11 10

9

8

7

6

5

4

3

2

1

0

DM (0x2008)

PWMTM

f_PWM

f_CLKOUT

=

2 ꢀ PWMTM

PWMDT (R/W)

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

3

0

2

0

1

0

DM (0x2009)

PWMDT

0

2 ꢀ PWMDT

f_CLKOUT

T

=

SECONDS

D

PWMSEG (R/W)

15 14 13 12 11 10

9

8

7

6

5

0

4

0

3

0

2

1

0

DM (0x200F)

0

A CHANNEL CROSSOVER

B CHANNEL CROSSOVER

CH OUTPUT DISABLE

CL OUTPUT DISABLE

BH OUTPUT DISABLE

0 = NO CROSSOVER

1 = CROSSOVER

C CHANNEL CROSSOVER

0 = ENABLE

1 = DISABLE

BL OUTPUT DISABLE

AH OUTPUT DISABLE

AL OUTPUT DISABLE

PWMSYNCWT (R/W)

1

15 14 13 12 11 10

9

8

0

7

0

6

0

5

1

4

0

3

0

2

1

0

1

DM (0x2060)

0

PWMSYNCWT

PWMSYNCWT + 1

f_CLKOUT

T

=

PWMSYNC, ON

PWMSWT (R/W)

0

15 14 13 12 11 10

9

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2061)

Figure 20. Conﬁguration of PWM Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these

bits should always be written as shown.

REV. B

–26–

ADMCF326

PWMPD (R/W)

15 14 13 12

11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x200A)

PWMPD

0

PWMPD

f_CLKOUT

=

T

SECONDS

MIN

PWMGATE (R/W)

15 14 13 12

11 10

9

8

7

6

5

0

4

0

3

0

2

0

1

0

DM (0x200B)

GDCLK

0

GATE DRIVE CHOPPING FREQUENCY

LOW SIDE GATE CHOPPING

HIGH SIDE GATE CHOPPING

f_CLKOUT

0 = DISABLE

1 = ENABLE

=

f_CHOP

4 ꢀ (GDCLK + 1)

PWMCHA (R/W)

15 14 13 12

11 10

9

8

7

6

5

4

3

2

1

0

DM (0x200C)

PWM CHANNEL A

DUTY CYCLE

PWMCHB (R/W)

15 14 13 12

11 10

9

8

7

6

5

4

3

2

1

0

DM (0x200D)

PWM CHANNEL B

DUTY CYCLE

PWMCHC (R/W)

15

14 13 12

11 10

9

8

7

6

5

4

3

2

1

0

DM (0x200E)

PWM CHANNEL C

DUTY CYCLE

Figure 21. Conﬁguration of Additional PWM Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these

bits should always be written as shown.

REV. B

–27–

ADMCF326

PIODIR0 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2004)

0

0 = INPUT

1 = OUTPUT

PIO0 – PIO7

PIODIR1 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2044)

0

0 = INPUT

1 = OUTPUT

PIO8

PIODATA0 (R/W)

15

14

13

12

11

0

10

0

9

8

7

6

5

4

3

2

1

0

DM (0x2005)

0

0 = LOW LEVEL

1 = HIGH LEVEL

PIO0 – PIO7

PIODATA1 (R/W)

15

0

14

0

13

0

12

0

11 10

9

8

7

6

5

0

4

3

2

0

1

0

DM (0x2045)

PIO8 DATA

0 = LO

1 = HI

0 = AUX0

1 = PIO8

PIO8/AUX0 MODE

PIOSELECT (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

6

5

1

4

1

3

2

1

0

1

0

1

DM (0x2049)

0 = TFS1

1 = PIO0

0 = AUX1

1 = PIO7

0 = DT1

1 = PIO1

0 = CLKOUT

1 = PIO6

0 = DR1B

1 = PIO2

0 = RFS1

1 = PIO5

0 = SCLK1

1 = PIO3

0 = DR1A

1 = PIO4

Figure 22. Conﬁguration of PIO Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these

bits should always be written as shown.

REV. B

–28–

ADMCF326

PIOINTEN0 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

4

0

3

0

2

0

1

0

DM (0x2006)

0 = INTERRUPT DISABLE

1 = INTERRUPT ENABLE

PIO0 – PIO7

PIOINTEN1 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2046)

0 = INTERRUPT DISABLE

1 = INTERRUPT ENABLE

PIO8

PIOFLAG0 (R)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2007)

0

0 = NO INTERRUPT

1 = INTERRUPT FLAGGED

PIO0 – PIO7

PIOFLAG1 (R)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2047)

0 = NO INTERRUPT

1 = INTERRUPT FLAGGED

PIO8

Figure 23. Conﬁguration of Additional PIO Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these

bits should always be written as shown.

REV. B

–29–

ADMCF326

AUXCH0 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2010)

0

T

= 2 ꢀ (AUXCH0) ꢀ t_CK

ON, AUX0

AUXCH1 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2011)

T

= 2 ꢀ (AUXCH1) ꢀ t_CK

ON, AUX1

AUXTM0 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

1

5

1

4

1

3

1

2

1

0

1

0

1

DM (0x2012)

AUX0 PERIOD = 2 ꢀ (AUXTM0 + 1) ꢀ t_CK

AUXTM1 (R/W)

15

0

14

0

13

0

12

0

11 10

9

0

8

7

6

1

5

1

4

1

3

1

2

1

0

1

0

1

DM (0x2013)

AUX1 PERIOD = 2 ꢀ (1 + AUXTM1) ^ꢀt_CK

OFFSET = 2 ꢀ (1 + AUXTM1) ꢀ t_CK

Figure 24. Conﬁguration of AUX Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these

bits should always be written as shown.

REV. B

–30–

ADMCF326

ADC1 (R)

15 14 13 12

11 10

9

8

7

6

5

4

3

0

2

0

1

0

DM (0x2000)

ADC2 (R)

15 14 13 12

11 10

9

8

7

6

5

4

3

0

2

0

1

0

DM (0x2001)

ADC3 (R)

15 14 13 12

11 10

9

8

7

6

5

4

3

0

2

0

1

0

DM (0x2002)

ADCAUX (R)

8

15 14 13 12

11 10

7

6

3

0

2

0

1

0

DM (0x2003)

ICONST_TRIM (R/W)

15 14 13 12

11 10

9

8

7

6

5

0

4

0

3

0

2

0

1

0

DM (0x2068)

0

ICONST MIN = BITS 0 – 2 CLEARED.

ICONST MAX = BITS 0 – 2 SET.

Figure 25. Conﬁguration of Additional AUX Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these

bits should always be written as shown.

REV. B

–31–

ADMCF326

MODECTRL (R/W)

15 14 13 12

11 10

9

8

7

6

5

0

4

3

0

2

0

1

0

DM (0x2015)

0

0 = OFFSET MODE

1 = INDEPENDENT MODE

AUXILIARY

PWM SELECT

ADC MUX CONTROL

00 VAUX0

01 VAUX1

10 VAUX2

11 VAUX3

ADC

COUNTER

SELECT

0 = CLKIN RATE

1 = CLKOUT RATE

PWMTRIP

INTERRUPT

0 = DISABLE

1 = ENABLE

PWMSYNC

INTERRUPT

0 = DISABLE

1 = ENABLE

SPORT1 DATA

RECEIVE SELECT

0 = DR1A

1 = DR1B

SPORT1 MODE

SELECT

0 = SPORT

1 = UART

0 = SINGLE UPDATE MODE

1 = DOUBLE UPDATE MODE

PWM UPDATE

MODE SELECT

SYSSTAT

(R)

15 14 13 12

11 10

9

0

8

7

6

0

5

0

4

3

2

1

0

DM (0x2016)

0

PWMTRIP

PIN STATUS

0 = LOW

1 = HIGH

0 = 1ST HALF OF PWM

CYCLE

1 = 2ND HALF OF PWM

CYCLE

0 = NORMAL

1 = WATCHDOG RESET

OCCURRED

PWM TIMER

STATUS

WATCHDOG

STATUS

IRQFLAG (R)

15 14 13 12

11 10

9

8

7

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2017)

0

PWMTRIP INTERRUPT

0 = NO INTERRUPT

1 = INTERRUPT

OCCURRED

PWMSYNC INTERRUPT

WDTIMER (W)

15 14 13 12

11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2018)

0

Figure 26. Conﬁguration of Status Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these

bits should always be written as shown.

REV. B

–32–

ADMCF326

ICNTL

2

4

0

3

0

1

0

1

0

DSP REGISTER

0 = DISABLE

1 = ENABLE

INTERRUPT NESTING

IRQ0 SENSITIVITY

IRQ1 SENSITIVITY

IRQ2 SENSITIVITY

0 = LEVEL

1 = EDGE

IFC

15 14 13 12 11 10

9

0

8

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DSP REGISTER

0

INTERRUPT FORCE

INTERRUPT CLEAR

IRQ2

TIMER

SPORT1 RECEIVE OR IRQ0

SPORT1 TRANSMIT OR IRQ1

SOFTWARE 0

SOFTWARE 1

SOFTWARE 0

SPORT1 TRANSMIT OR IRQ1

SPORT1 RECEIVE OR IRQ0

TIMER

IRQ2

IMASK (R/W)

15 14 13 12

11 10

9

0

8

7

6

5

0

4

3

0

2

1

0

DSP REGISTER

TIMER

PERIPHERAL (OR IRQ2)

SPORT1 RECEIVE

(OR IRQ0)

0 = DISABLE

(MASK)

1 = ENABLE

0 = DISABLE

(MASK)

1 = ENABLE

SPORT1 TRANSMIT

(OR IRQ1)

SOFTWARE 1

SOFTWARE 0

Figure 27. Conﬁguration of Interrupt Control Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these

bits should always be written as shown.

REV. B

–33–

ADMCF326

SYSCNTL (R/W)

15 14 13 12 11 10

9

8

7

6

5

1

4

1

3

1

2

1

0

1

DM (0x3FFF)

0

1

0

PWAIT

PROGRAM MEMORY

WAIT STATES

0 = DISABLED

1 = ENABLED

SPORT1 ENABLE

0 = FI, FO, IRQ0, IRQ1, SCLK

1 = SERIAL PORT

SPORT1 CONFIGURE

THE ROM MONITOR WRITES 0x8000 TO THIS REGISTER

Figure 28. Conﬁguration of Registers

REV. B

–34–

ADMCF326

OUTLINE DIMENSIONS

28-Lead Standard Small Outline Package [SOIC]

Wide-Body

(R-28)

Dimensions shown in millimeters and (inches)

18.10 (0.7126)

17.70 (0.6969)

28

1

15

14

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

PIN 1

2.65 (0.1043)

2.35 (0.0925)

0.75 (0.0295)

0.25 (0.0098)

ꢀ 45ꢂ

0.30 (0.0118)

0.10 (0.0039)

8ꢂ

0ꢂ

1.27 (0.0500) 0.51 (0.0201) SEATING

1.27 (0.0500)

0.40 (0.0157)

0.32 (0.0126)

0.23 (0.0091)

COPLANARITY

0.10

PLANE

BSC

0.33 (0.0130)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-013AE

28-Lead Plastic Dual-In-Line Package [PDIP]

(N-28)

Dimensions shown in millimeters and (inches)

39.70 (1.5630)

35.10 (1.3819)

28

15

14.73 (0.5799)

12.32 (0.4850)

1

14

PIN 1

1.52 (0.0598)

0.38 (0.0150)

15.87 (0.6248)

15.24 (0.6000)

4.95 (0.1949)

3.18 (0.1252 )

6.35

(0.2500)

MAX

3.81

(0.1500)

MIN

0.38 (0.0150)

0.20 (0.0079)

5.05 (0.1988)

3.18 (0.1252)

1.77

(0.0697)

MAX

2.54

(0.1000)

BSC

SEATING

PLANE

0.56 (0.0220)

0.36 (0.0142)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

ADMC326–Revision History

Location

Page

8/29—Data Sheet changed from REV. A to REV. B.

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8/02—Data Sheet changed from REV. 0 to REV. A.

Edits to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Edits to Figure 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

REV. B

–35–

–36–


型号：	ADMCF326BN
厂家：	ETC
描述：	Controller Miscellaneous - Datasheet Reference 控制器杂项 - 数据表参考\n 外围集成电路光电二极管控制器时钟
文件：	总36页 (文件大小：479K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADMCF326BN [ETC]

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