ADMCF327BN_技术文档

28-LeadFlashMemory

DSPMotorController

a

ADMCF327

Preliminary Technical Data

TARGETAPPLICATIONS

Washing Machines, Refrigerator Compressors, Fans,

Pumps, Industrial Variable Speed Drives

Reluctance Applications

16-Bit Center-Based PWM Generator

Programmable Narrow Pulse Deletion

Edge Resolution to 50 ns

150 Hz Minimum Switching Frequency

Double/Single Duty Cycle Update Mode Control

ProgrammablePWMPulsewidth

MOTORTYPES

Switched Reluctance Motors

FEATURES

20 MIPS Fixed-Point DSP Core

Single Cycle Instruction Execution (50 ns)

ADSP-21xx Family Code Compatible

IndependentComputationalUnits

ALU

Multiplier/Accumulator

Barrel Shifter

MultifunctionInstructions

Single Cycle Context Switch

Powerful Program Sequencer

Zero Overhead Looping

ConditionalInstructionExecution

Two Independent Data Address Generators

MemoryConfiguration

Special Crossover Function

Individual Enable and Disable for Each PWM Output

High Frequency Chopping Mode for Transformer

Coupled Gate Drives

External PWMTRIP Pin

Integrated ADC Subsystem

Six Analog Inputs Plus One Dedicated I_SENSEInput

Acquisition Synchronized to PWM Switching Frequency

Internal Voltage Reference

9-Pin Digital I/O Port

Bit Configurable as Input or Output

Change of State Interrupt Support

Two 8-Bit Auxiliary PWM Timers

Synthesized Analog Output

512 x 24-Bit Program Memory RAM

512 x 16-Bit Data Memory RAM

4K x 24-Bit Program Memory ROM

4K x 24-Bit Program Flash Memory

Three Independent Programmable Sectors

Security Lock Bit

Programmable Frequency

0% to 100% Duty Cycle

Two Programmable Operational Modes

16-Bit Watchdog Timer

Programmable 16-Bit Internal Timer with Prescaler

Double Buffered Synchronous Serial Port

Hardware Support for UART Emulation

Integrated Power-On Reset Function Options

28-Lead SOIC or PDIP Package Options

10K Erase/Program Cycles

Three-Phase 16-Bit PWM Generator for Switched

FUNCTIONAL BLOCK DIAGRAM

MEMORY BLOCK

PROGRAM PROGRAM

ADSP-2100 BASE

ARCHITECTURE

ROM

FLASH

DATA

ADDRESS

GENERATORS

4K ꢀ 24

16-BIT

THREE-

PHASE

PWM

6

VREF

2.5V

PROGRAM

RAM

512 ꢀ 24

DATA

MEMORY

512 ꢀ 16

ANALOG

INPUTS

PROGRAM

SEQUENCER

DAG 1 DAG 2

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

ARITHMETIC UNITS

ALU MAC

SHIFTER

SERIAL PORT

SPORT 1

2 ꢀ 8-BIT

AUX

PWM

WATCH-

DOG

TIMER

9-BIT

PIO

POR

TIMER

REV. PrA

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World WideWeb Site: http://www.analog.com

Analog Devices, Inc., 2000

Fax: 781/326-8703

(V_DD= 5 V

otherwise noted)

ꢁ

5%, GND = 0 V, T_A= –40

ꢂ

C to +85ꢂC, CLKIN = 10 MHz, unless

ADMCF327–SPECIFICATIONS

ANALOG-TO-DIGITALCONVERTER

Parameter

Min

Typ

Max

Unit

Conditions/Comments

SignalInput

0.3

3.5

12

4

+20

20

V

V1, V2, V3, VAUX0, VAUX1, VAUX2

Resolution¹

Bits

mV

ns

LinearityError²

2

0

ZeroOffset²

–20

Channel-to-ChannelComparatorMatch²

ComparatorDelay

600

ADCHighLevelInputCurrent²

ADCLowLevelInputCurrent²

10

µA

V_IN= 3.5 V

V_IN= 0.0 V

–10

NOTES

¹Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.

²2.44 kHz sample frequency, V1, V2, V3, VAUX0, VAUX1, VAUX2.

Specifications subject to change without notice.

ELECTRICALCHARACTERISTICS

Parameter

Min

Typ

Max

Unit

Conditions/Comments

V_IL

V_IH

V_OL

V_OH

I_IL

I_IH

I_OZH

I_OZL

I_IL

I_DD

Low Level Input Voltage

0.8

V

HighLevelInputVoltage

2

Low Level Output Voltage¹

Low Level Output Voltage²

High Level Output Voltage

LowLevelInputCurrent³

0.4

0.8

I_OL= 2 mA

I_OH= –0.5 mA

V_IN= 0 V

V_IN= V_DD

V_IN= 0

@ V_DD= Max, V_IN= 0 V

4

–120

–10

V

µA

mA

LowLevelInputCurrent

HighLevelInputCurrent⁴

HighLevelInputCurrent

90

10

90

HighLevelThree-StateLeakageCurrent⁵

LowLevelThree-StateLeakageCurrent⁵

Low Level PWMTRIP Current

SupplyCurrent(Idle)⁶

–10

32

55

SupplyCurrent(Dynamic)⁶

NOTES

¹Output Pins PIO0–PIO8, AH, AL, BH, BL, CH, CL.

²XTAL Pin.

³Internal Pull-Up, RESET.

⁴Internal Pull-Down, PWMTRIP, PIO0–PIO8.

⁵Three stateable pins DT1, RFS1, TFS1, SCLK1.

⁶Outputs not Switching.

Specifications subject to change without notice.

CURRENTSOURCE¹

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Programming Resolution

Default Current²

Tuned Current

3

95

105

Bits

µA

70

95

83

100

ICONST_TRIM = 0x00

NOTES

¹ForADCCalibration.

²0.3 V to 3.5 V ICONST Voltage.

Specifications subject to change without notice.

–2–

REV. PrA

Preliminary Technical Data

ADMCF327

VOLTAGEREFERENCE

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Voltage Level (V_REF

Output Voltage Drift

)

2.4

2.5

35

2.6

V

T_A= +25°C to +125°C SOIC

ppm/°C

Specifications subject to change without notice.

POWER-ONRESET

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Reset Threshold (V_RST

)

3.2

3.7

4.2

V

Hysteresis (V_HYST

Reset Active Timeout Period (t_RST

)

100

mV

ms

)

3.2¹

NOTES

¹2¹⁶CLKOUTCycles.

Specifications subject to change without notice.

FLASHMEMORY

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Endurance

Data Retention

Program and Erase Operating Temperature

10,000

15

0

Cycles

Years

ꢂC

Cycle = Erase/Program/Verify

85

Read Operating Temperature

–40

+85

ꢂC

Specifications subject to change without notice.

REV. PrA

–3–

Preliminary Technical Data

ADMCF327

TIMINGPARAMETERS

Parameter

Min

Max

Unit

Clock Signals

Signal t_CKis defined as 0.5 t_CKIN. The ADMCF327 uses an input clock with

a frequency equal to half the instruction rate; a 10 MHz input clock (which

is equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz).

When t_CKvalues are within the range of 0.5 t_CKINperiod, they should be

substituted for all relevant timing parameters to obtain specification value.

Example: t_CKH= 0.5 t_CK– 10 ns = 0.5 (50 ns) – 10 ns = 15 ns.

Timing Requirements:

t_CKIN

t_CKIL

t_CKIH

CLKIN Period

CLKIN Width Low

CLKIN Width High

100

20

150

20

ns

Switching Characteristics:

t_CKL

t_CKH

t_CKOH

CLKOUT Width Low

CLKOUT Width High

CLKIN High to CLKOUT High

0.5 t_CK– 10

0

ns

Control Signals

Timing Requirement:

1

t_RSP

RESET Width Low

5 t_CK

ns

PWM Shutdown Signals

Timing Requirement:

t_PWMTPW

PWMTRIP Width Low

t_CK

NOTES

¹Applies after power-up sequence is complete.

Specifications subject to change without notice.

t_CKIN

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

Figure 1. Clock Signals

–4–

REV. PrA

Preliminary Technical Data

ADMCF327

Parameter

Min

Max

Unit

Serial Ports

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

100

15

20

ns

DR/TFS/RFS Setup before SCLK Low

DR/TFS/RFS Hold after SCLK Low

SCLK_INWidth

40

Switching Characteristics:

t_CC

CLKOUT High to SCLK_OUT

0.25 t_CK

0

0.25 t_CK+ 20

ns

t_SCDE

t_SCDV

t_RH

SCLK High to DT Enable

SCLK High to DT Valid

TFS/RFS_OUTHold after SCLK High

TFS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

SCLK High to DT Disable

TFS (Alt) to DT Enable

TFS (Alt) to DT Valid

RFS (Multichannel, Frame Delay Zero) to DT Valid

30

0

t_RD

t_SCDH

t_SCDD

t_TDE

t_TDV

t_RDV

25

30

Specifications subject to change without notice.

CLKOUT

SCLK

t_CC

t_SCK

t_SCP

t_SCS

t_SCH

t_SCP

DR

RFS

IN

TFS

IN

t_RD

t_RH

RFS

OUT

TFS

OUT

t_SCDV

t_SCDD

t_SCDH

t_SCDE

DT

t_TDE

t_TDV

TFS

(ALTERNATE

FRAME MODE)

t_RDV

RFS

(MULTICHANNEL MODE,

FRAME DELAY 0 [MFD = 0])

Figure 2. Serial Port Timing

REV. PrA

–5–

Preliminary Technical Data

ADMCF327

PIN FUNCTION DESCRIPTIONS

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage (V_DD

Input Voltage

Output Voltage Swing

)

–0.3 V to +7.0 V

–0.3 V to V_DD+ 0.3 V

No.

Name

Type

Flash Memory Erase or/Program

Temperature Range (Ambient)

Operating Temperature Range (Ambient)–40°C to +85°C

Storage Temperature Range

Lead Temperature (5 sec)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

PIO6/CLKOUT

PIO5/RFS1

PIO4/DR1A

PIO3/SCLK1

PIO2/DR1B

PIO1/DT1

PIO0/TFS1

CLKIN

XTAL

V_DD

PWMTRIP

V3

V2

V1

VAUX0

VAUX1

VAUX2

ICONST

GND

I/O

I

O

SUP

I

0°C to 85°C

–65°C to +150°C

280°C

*Stressesgreaterthanthoselistedmaycausepermanentdamagetothedevice. These

arestressratingsonly;functionaloperationofthedeviceattheseoranyotherconditions

greater than those indicated in the operational sections of this specification is not

implied.Exposuretoabsolutemaximumratingconditionsforextendedperiodsmay

affectdevicereliability.

1

2

28

27

PIO6/CLKOUT

PIO5/RFS1

PIO4/DR1A

PIO3/SCLK1

PIO2/DR1B

PIO1/DT1

PIO0/TFS1

CLKIN

PIO7/AUX1

PIO8/AUX0

I

26 AL

AH

3

4

5

25

24 BL

O

GND

I

O

6

BH

23

22

21

20

ADMCF327

CL

7

8

TOP VIEW

RESET

CH

CL

BH

BL

AH

AL

(Not to Scale)

CH

XTAL

RESET

9

V

10

19 GND

DD

PW M TRIP

ICONST

11

18

17

VAUX2

VAUX1

VAUX0

V3 12

V2

V1

13

14

16

15

PIO8/AUX0

PIO7/AUX1

I/O

ORDERING GUIDE

Temperature

Range

Instruction

Rate

Package

Description

Package

Option

Model

ADMCF327BR

ADMCF327BN

ADMCF327-EVALKIT

ADMCF327-PB

–40°C to +85°C

20 MHz

28-Lead Wide Body (SOIC)

28-Lead Wide Body (PDIP)

Development Tool Kit

R-28

N-28

Evaluation/Processor Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADMCF327 features proprietary ESD protection circuitry, permanent damage

may occur on devices subjected to high energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

–6–

REV. PrA

Preliminary Technical Data

GENERAL DESCRIPTION

The ADMCF327 is a low cost, single-chip DSP-based

controller, suitable for switched reluctance motor

applications. The ADMCF327 integrates a 20 MIPS,

fixed-point DSP core with a complete set of motor

control and system peripherals that permits fast, effi-

cient development of motor controllers.

ADMCF327

FLASH memory, and 512 x 16-bit data memory RAM.

The user code will be stored and executed from the

flash memory. The program and data memory RAM can

be used for dynamic data storage or can be loaded

through the serial port from an external device as in other

ADMCxxx family parts. The program memory ROM con-

tains a monitor function as well as useful routines for erasing,

programming, and verifying the flash memory.

The DSP core of the ADMCF327 is the ADSP-2171,

which is completely code-compatible with the ADSP-

21xx DSP family and combines three computational

units, data address generators and a program sequencer.

The computational units comprise an ALU, a multi-

plier/accumulator (MAC) and a barrel shifter. The

ADSP-2171 adds new instructions for bit manipulation,

multiplication (x squared), biased rounding and glo-

bal interrupt masking.

The motor control peripherals of the ADMCF327 provide a

12-bit analog data acquisition system with six analog input

channels, and an internal voltage reference. In addition,

a three-phase, 16-bit, center-based PWM generation unit

can be used to produce high accuracy PWM signals with

minimal processor overhead. The ADMCF327 also

contains two auxiliary PWM outputs and nine lines of

digital I/O.

Because the ADMCF327 has a limited number of pins,

functions such as the auxiliary PWM and the serial com-

munication port are multiplexed with the nine program-

mable input/output (PIO) pins. The pin functions can be

independently selected to allow maximum flexibility for

different applications.

The system peripherals are the power-on reset circuit

(POR), the watchdog timer and a synchronous serial

port. The serial port is configurable, and double buff-

ered, with hardware support for UART and SCI port

emulation.

The ADMCF327 provides 512 x 24-bit program memory

RAM, 4K x 24-bit program memory ROM, 4K x 24

bit program

INSTRUCTION

REGISTER

FLASH

PROGRAM

MEMORY

4K ꢀ 24

PM ROM

4K ꢀ 24

DM RAM

512 ꢀ 16

DATA

ADDRESS

GENERATOR

#1

DATA

ADDRESS

GENERATOR

#2

PROGRAM

SEQUENCER

PM RAM

512 ꢀ 24

PMA BUS

DMA BUS

14

24

PMD BUS

DMD BUS

BUS

EXCHANGE

16

CONTROL

LOGIC

TIMER

INPUT REGS

ALU

INPUT REGS

SHIFTER

MAC

TRANSMIT REG

COMPANDING

CIRCUITRY

RECEIVE REG

OUTPUT REGS

16

OUTPUT REGS

SERIAL

PORT

R BUS

6

Figure 3. DSP Core Block Diagram

REV. PrA

–7–

Preliminary Technical Data

DAG2 may generate either program or data memory ad-

dresses but has no bit-reversal capability.

ADMCF327

DSP CORE ARCHITECTURE OVERVIEW

Figure 3 is an overall block diagram of the DSP core of

the ADMCF327, which is based on the fixed-point

ADSP-2171. The flexible architecture and comprehensive

instruction set of the ADSP-2171 allow the processor to

perform multiple operations in parallel. In one processor

cycle (50 ns with a 10 MHz CLKIN) the DSP core can:

Efficient data transfer is achieved with the use of five

internal buses:

• Program memory address (PMA) bus.

• Program memory data (PMD) bus.

• Data memory address (DMA) bus.

• Data memory data (DMD) bus.

• Result (R) bus.

• Generate the next program address.

• Fetch the next instruction.

• Perform one or two data moves.

• Update one or two data address pointers.

• Perform a computational operation.

Program Memory on the ADMCF327 can either be

internal (on-chip RAM) or external (Flash). Internal

program memory can store both instructions and data, per-

mitting the ADMCF327 to fetch two operands in a single

instruction cycle—one from program memory and one

from data memory. Operation from external program

memory is described in detail in the ADSP-2100 Family

User’s Manual, Third Edition.

This all takes place while the processor continues to:

• Receive and transmit through the serial port.

• Decrement the interval timer.

• Generate three-phase PWM waveforms for a power

inverter.

• Generate two signals using the 8-bit auxiliary PWM

timers.

The ADMCF327 writes data from its 16-bit registers to

the 24-bit program memory using the PX register to pro-

vide the lower eight bits. When it reads data (not instruc-

tions) from 24-bit program memory to a 16-bit data

register, the lower eight bits are placed in the PX register.

• Acquire four analog signals.

• Decrement the watchdog timer.

The processor contains three independent computational

units: the arithmetic and logic unit (ALU), the multiplier/

accumulator (MAC) and the shifter. The computational

units process 16-bit data directly and have provisions to

support multiprecision computations. The ALU performs

a standard set of arithmetic and logic operations as well as

providing support for division primitives. The MAC per-

forms single-cycle multiply, multiply/add, and multiply/

subtract operations with 40 bits of accumulation. The

shifter performs logical and arithmetic shifts, normal-

ization, denormalization and derive-exponent operations.

The shifter can be used to efficiently implement numeric

format control, including floating-point representations.

The ADMCF327 can respond to a number of distinct

DSP core and peripheral interrupts. The DSP interrupts

comprise a serial port receive interrupt, a serial port

transmit interrupt, a timer interrupt, and two software

interrupts. Additionally, the motor control peripherals

include two PWM interrupts and a PIO interrupt.

The serial port (SPORT1) provides a complete syn-

chronous serial interface with optional companding in

hardware and a wide variety of framed and unframed data

transmit and receive modes of operation. SPORT1 can

generate an internal programmable serial clock or accept

an external serial clock.

The internal result (R) bus directly connects the computa-

tional units so that the output of any unit may be the input

of any unit on the next cycle.

A programmable interval counter is also included in the

DSP core and can be used to generate periodic interrupts.

A 16-bit count register (TCOUNT) is decremented

every n processor cycles, where n–1 is a scaling value

stored in the 8-bit TSCALE register. When the value of

the counter reaches zero, an interrupt is generated, and the

count register is reloaded from a 16-bit period register

(TPERIOD).

A powerful program sequencer and two dedicated data

address generators ensure efficient delivery of operands to

these computational units. The sequencer supports con-

ditional jumps and subroutine calls and returns in a single

cycle. With internal loop counters and loop stacks, the

ADMCF327 executes looped code with zero overhead; no

explicit jump instructions are required to maintain the

loop.

The ADMCF327 instruction set provides flexible data

moves and multifunction instructions (one or two data

moves within a computation) that will execute from inter-

nal program memory RAM. The ADMCF327 assembly

language uses an algebraic syntax for ease of coding and

readability. A comprehensive set of development tools

support program development. For further information

on the DSP core, refer to the ADSP-2100 Family User’s

Manual, Third Edition, with particular reference to the

ADSP-2171.

Two data address generators (DAGs) provide addresses

for simultaneous dual operand fetches from data memory

and program memory. Each DAG maintains and updates

four address pointers (I registers). Whenever the pointer is

used to access data (indirect addressing), it is post-modi-

fied by the value in one of four modify (M registers). A

length value may be associated with each pointer (L regis-

ters) to implement automatic modulo addressing for

circular buffers. The circular buffering feature is also used

by the serial ports for automatic data transfers to and from

on-chip memory. DAG1 generates only data memory

address and provides an optional bit-reversal capability.

–8–

REV. PrA

Preliminary Technical Data

ADMCF327

Serial Port

INTERRUPT OVERVIEW

The ADMCF327 incorporates a complete synchronous serial

port (SPORT1) for serial communication and multiproces-

sor communication. The following is a brief list of capa-

bilities of the ADMCF327 SPORT1. Refer to the ADSP-2100

Family User’s Manual, Third Edition, for further details.

The ADMCF327 can respond to 16 different interrupt

sources with minimal overhead, five of which are internal

DSP core interrupts and 11 from the motor control periph-

erals. The five DSP core interrupts are SPORT1 receive (or

IRQ0) and transmit (or IRQ1), the internal timer, and two

software interrupts. The motor control peripheral interrupts

are the nine programmable I/Os and two from the PWM

(PWMSYNC pulse and PWMTRIP). All motor control

interrupts are multiplexed into the DSP core through the

peripheral IRQ2 interrupt. The interrupts are internally

prioritized and individually maskable. A detailed description

of the entire interrupt system of the ADMCF327 is pre-

sented later, following a more detailed description of each

peripheral block.

• SPORT1 is bidirectional and has a separate, double-buff-

ered transmit and receive section.

• SPORT1 can use an external serial clock or generate its

own serial clock internally.

• SPORT1 has independent framing for the receive and

transmit sections. Sections run in a frameless mode or

with frame synchronization signals internally or exter-

nally generated. Frame synchronization signals are ac-

tive high or inverted, with either of two pulsewidths and

timings.

MEMORY MAP

The ADMCF327 has two distinct memory types: program

memory and data memory. In general, program memory

contains user code and coefficients, while the data

memory is used to store variables and data during pro-

gram execution. Three kinds of program memory are pro-

vided on the ADMCF327: RAM, ROM, and flash memory.

The motor control peripherals are memory mapped into a

region of the data memory space starting at 0x2000. The

complete program and data memory maps are given in

Tables II and III, respectively.

• SPORT1 supports serial data word lengths from 3 bits to 16

bits and provides optional A-law and µ-law companding

according to ITU (formerly CCITT) recommendation

G.711.

• SPORT1 receive and transmit sections can generate

unique interrupts on completing a data word transfer.

• SPORT1 can receive and transmit an entire circular

buffer of data with only one overhead cycle per data word.

An interrupt is generated after a data buffer transfer.

• SPORT1 can be configured to have two external inter-

rupts (IRQ0 and IRQ1), and the Flag In and Flag Out

signals. The internally generated serial clock may still

be used in this configuration.

Table II. Program Memory Map

Memory

AddressRange

Type

Function

• SPORT1 has two data receive pins (DR1A and DR1B),

which are internally multiplexed onto the one DR1 port

of the SPORT1. The particular data receive pin selected

is determined by a bit in the MODECTRL register.

0x0000–0x002F

0x0030–0x01FF

0x0200–0x07FF

0x0800–0x17FF

0x1800–0x1FFF

0x2000–0x20FF

RAM

Internal Vector Table

User Program Memory

Reserved

Reserved Program Memory

Reserved

User Program Memory

Sector 0

User Program Memory

Sector 1

User Program Memory

Sector 2

ROM

PIN FUNCTION DESCRIPTION

The ADMCF327 is available in a 28-lead SOIC package

and a 28-lead PDIP package. Table I describes the pins.

FLASH

0x2100–0x21FF

0x2200–0x2FFF

0x3000–0x3FFF

Table I. Pin List

Pin Group

Name

# of Input/

Pins Output Function

Reserved

RESET

1

6

I

I/O

ProcessorResetInput

Serial Port 1 Pins (TFS1, RFS1,

DT1,DR1A,DR1B,SCLK1)

ProcessorClockOutput

External Clock or Quartz

CrystalConnectionPoint

Digital I/O Port Pins

AuxiliaryPWMOutputs

PWMOutputs

PWM Trip Signal

AnalogInputs

AuxiliaryAnalogInput

ADCConstantCurrentSource

PowerSupply

Table III. Data Memory Map

Memory

SPORT1¹

CLKOUT¹

CLKIN,XTAL

1

2

O

I, O

AddressRange

Type

Function

0x0000–0x1FFF

0x2000–0x20FF

0x2100–0x37FF

0x3800–0x39FF

0x3A00–0x3BFF

0x3C00–0x3FFF

Reserved

Memory Mapped Registers

Reserved

User Data Memory

Reserved

PIO0–PIO8¹

AUX0–AUX1¹

AH–CL

PWMTRIP

V1, V2, V3

VAUX0–VAUX2

ICONST

9

2

6

1

3

1

I/O

O

I

RAM

Memory Mapped Registers

O

V_DD

GND

Ground

NOTE¹Multiplexedpins,individuallyselectablethroughPIOSELECTand

PIODATA1 registers.

REV. PrA

–9–

Preliminary Technical Data

Refer to the ADMCF32x DSP Motor Controller Developer’s Reference

Manual for further instructions and an example of using

the boot-from-flash code.

ADMCF327

FLASH MEMORY SUBSYSTEM

The ADMCF327 has 4K x 24-bit of user-programmable,

nonvolatile flash memory. A flash programming utility is

provided with the development tools, which performs

the basic device programming operations: erase, pro-

gram, and verify.

FLASH PROGRAM BOOT SEQUENCE

On power-up or reset, the processor begins instruction

execution at address 0x0800 of internal program ROM.

The ROM monitor program that is located there checks

the Boot-from-Flash code. If that code is set, the proces-

sor jumps to location 0x2200 in external flash program

memory, where it expects to find the user’s application

program. If the Boot-from-Flash code is not set, the

monitor attempts to boot from an external device as de-

scribed in the ADMCF32x DSP Motor Controller Developers Refer-

enceManual

The flash memory array is partitioned into three asym-

metrically sized sectors of 256 words, 256 words, and

3584 words, labeled Sector 0, Sector 1, and Sector 2,

respectively. These sectors are mapped into external pro-

gram memory address space.

Four flash memory interface registers are connected to the

DSP. These 16-bit registers are mapped into the register

area of data memory space. They are named Flash Memory

Control Register (FMCR), Flash Memory Address Reg-

ister (FMAR), Flash Memory Data Register Low

SYSTEM INTERFACE

Figure 4 shows a basic system configuration for the

ADMCF327 with an external crystal.

(FMDRL) and Flash Memory Data Register High

(FMDRH). These registers are diagrammed later in this

data sheet. They are used by the flash memory programming

utility. The user program may read these registers, but

should not modify them directly. The flash programming

utility provides a complete interface to the flash memory.

22pF

CLKOUT

XTAL

10MHz

Special Flash Registers

CLKIN

22pF

The flash module has four nonvolatile 8-bit registers called

Special Flash Registers (SFRs) which are accessible inde-

pendently of the main flash array, via the flash program-

ming utility. These registers are for general purpose,

nonvolatile storage. When erased, the Special Flash Reg-

isters contain all 0s. To read Special Flash Registers from

the user program, call the read_reg routine contained in

ROM. Refer to the (ADMCF32x DSP Motor Controller Develop-

ers Reference Manual) for an example.

ADMCF327

RESET

Figure 4. Basic System Configuration

Clock Signals

The ADMCF327 can be clocked either by a crystal or a

TTL-compatible clock signal. For normal operation,

the CLKIN input cannot be halted, changed during op-

eration, or operated below the specified minimum fre-

quency. If an external clock is used, it should be a

TTL-compatible signal running at half the instruction

rate. The signal is connected to the CLKIN pin of the

ADMCF327. In this mode, with an external clock signal,

the XTAL pin must be left unconnected. The ADMCF327

uses an input clock with a frequency equal to half the

instruction rate; a 10 MHz input clock yields a 50 ns pro-

cessor cycle (which is equivalent to 20 MHz). Normally,

instructions are executed in a single processor cycle. All

device timing is relative to the internal instruction rate,

which is indicated by the CLKOUT signal when en-

abled.

Boot-from-Flash Code

A security feature is available in the form of a code that,

when set, causes the processor to execute the program in flash

memory upon power-up or reset. In this mode, the flash

programming utility and debugger are unable to commu-

nicate with the ADMCF327. Consequently, the contents

of the flash memory can neither be programmed nor

read.

The boot-from-flash code may be set via the flash pro-

gramming utility, when the user’s program is thoroughly

tested and loaded into flash program memory at address

0x2200. The user’s program must contain a mechanism for

clearing the boot-from-flash code if reprogramming the

flash memory is desired. The only way to clear boot-

from-flash is from within the user program, by calling the

flash_init or auto_erase_reg routines that are included

in the ROM. The user program must be signaled in some

way to call the necessary routine to clear the boot-from-flash

code. An example would be to detect a high level on a PIO

pin during start-up initialization and then call the

flash_init or auto_erase_routine. The flash_init routine

will erase the entire user program in flash memory be-

fore clearing the boot-from-flash code, thus ensuring the

security of the user program. If security is not a concern,

the auto_erase_reg routine can be used to clear the boot-

from-flash code while leaving the user program intact.

Because the ADMCF327 includes an on-chip oscillator

feedback circuit, an external crystal may be used instead of a

clock source, as shown in Figure 4. The crystal should be

connected across the CLKIN and XTAL pins, with two

capacitors as shown in Figure 4. A parallel-resonant, funda-

mental frequency, microprocessor-grade crystal should be

used. A clock output signal (CLKOUT) is generated by

the processor at the processor’s cycle rate of twice the

input frequency.

Reset

The ADMCF327 DSP core and peripherals must be cor-

rectly reset when the device is powered up to assure proper

initialization. The ADMCF327 contains an integrated

power-on reset (POR) circuit that provides a complete

system reset on power-up and power-down. The POR

–10–

REV. PrA

Preliminary Technical Data

ADMCF327

circuit monitors the voltage on the ADMCF327 V_DDpin

and holds the DSP core and peripherals in reset while V_DD

is less than the threshold voltage level, V_RST. When this

voltage is exceeded, the ADMCF327 is held in reset for

an additional 2¹⁶DSP clock cycles (t_RSTin Figure 5).

On power-down, when the voltage on the V_DDpin

falls below V_RST–V_HYST, the ADMCF327 will be reset.

Also, if the external RESET pin is actively pulled low at

any time after power-up, a complete hardware reset of the

ADMCF327 is initiated.

generated PWM patterns are programmable using, respec-

tively, the PWMTM, PWMDT, and PWMPD registers.

In addition, three registers (PWMCHA, PWMCHB, and

PWMCHC) control the duty cycles of the high side PWM

signals.

Each of the six PWM output signals can be enabled or

disabled by separate output enable bits of the PWMSEG

register. In addition, three control bits of the

PWMSEG register permit crossover of the two signals of

a PWM. In crossover mode, the PWM signal destined for

the high-side switch is diverted to the complementary low

side output, and the signal destined for the low-side switch

is diverted to the corresponding high side output signal.

V

RST

V

› V

HY ST

RST

V

DD

The low side PWM signals from the three-phase timing

unit assume permanently ON states, independent of the

value written to the duty-cycle registers. The duty cycles of

the high side PWM signals from the timing unit are still

determined by the three duty-cycle registers. Using the

crossover feature of the output control unit, it is possible

to divert the permanently ON PWM signals to either the

high side or the low side outputs. This mode is necessary

because in the typical power converter configuration for

switched or variable reluctance motors, the motor winding

is connected between the two power switches of a given

inverter leg. Therefore, in order to build up current in the

motor winding, it is necessary to turn on both switches

at the same time. Typical active HI PWM signals dur-

ing operation in SR mode are shown in Figure 8 for

operation in double update mode. It is clear that the three

low side signals (AL, BL and CL) are permanently ON

and the three high side signals are modulated so that the

corresponding high side power switches are switched

between the ON and OFF states.

t_RST

RESET

Figure 5. Power-On Reset Operation

The ADMCF327 reset sets all internal stack pointers to

the empty stack condition, masks all interrupts, clears the

MSTAT register and performs a full reset of all of the

motor control peripherals. Following a power-up, it is

possible to initiate a DSP core and motor control periph-

eral reset by pulling the RESET pin low. The RESET

signal must meet the minimum pulsewidth specification,

t_RSP. Following the reset sequence, the DSP core starts

executing code from the internal PM ROM located at

0x0800.

DSP Control Registers

The DSP core has a system control register, SYSCNTL,

memory mapped at DM (0x3FFF). SPORT1 is config-

ured as a serial port when Bit 10 is set, or as flags and

interrupt lines when this bit is cleared. For proper opera-

tion of the ADMCF327, all other bits in this register must

be cleared.

In many applications, there is a need to provide an isola-

tion barrier in the gate-drive circuits that turn on the

power devices of the inverter. In general, there are two

common isolation techniques: optical isolation using

optocouplers, and transformer isolation using pulse

transformers. The PWM controller of the ADMCF327

permits mixing of the output PWM signals with a high

frequency chopping signal to permit an easy interface to

such pulse transformers. The features of this gate-drive chop-

ping mode can be controlled by the PWMGATE register.

There is an 8-bit value within the PWMGATE register

that directly controls the chopping frequency.

The DSP core has a wait state control register,

MEMWAIT, memory mapped at DM (0x3FFE). The

default value of this resister is 0xFFFF. For proper

operation of the ADMCF327, this register must always

contain the value 0x8000 (which is the default).

The configuration of both the SYSCNTL and

MEMWAIT registers of the ADMCF327 are shown at the

end of the data sheet.

The PWM generator is capable of operating in two distinct

modes: single update mode or double update mode. In

single update mode, the duty cycle values are program-

mable only once per PWM period, so that the resultant

PWM patterns are symmetrical about the midpoint of the

PWM period. In the double update mode, a second updat-

ing of the PWM duty cycle values is implemented at the

midpoint of the PWM period. In this mode, it is possible

to produce asymmetrical PWM patterns that produce

lower harmonic distortion in three-phase PWM inverters.

This technique also permits the closed-loop controller to

change the average voltage applied to the machine wind-

ing at a faster rate, allowing wider closed-loop band-

widths to be achieved. The operating mode of the PWM

THREE-PHASE PWM CONTROLLER

Switched Reluctance Mode

The PWM generator block of the ADMCF327 is a flex-

ible, programmable, three-phase PWM waveform genera-

tor that can be programmed to generate the required

switching patterns to drive a three-phase voltage source

inverter for a Switched Reluctance Motor.

The PWM generator produces three pairs of active high

PWM signals on the six PWM output pins (AH, AL, BH,

BL, CH, and CL). The six PWM output signals consist of

three high-side drive signals (AH, BH, and CH) and three

low side drive signals (AL, BL, and CL). The switching

frequency, dead time, and minimum pulsewidths of the

REV. PrA

–11–

Preliminary Technical Data

ADMCF327

block (single or double update mode) is selected by a

control bit in MODECTRL register.

• The three-phase PWM timing unit, which is the core of

the PWM controller, generates the PWM output signal for

switched reluctance motor control applications.

The PWM generator of the ADMCF327 also provides an

internal signal that synchronizes the PWM switching fre-

quency to the A/D operation. In single update mode, a

PWMSYNC pulse is produced at the start of each PWM

period. In double update mode, an additional

PWMSYNC pulse is produced at the midpoint of each

PWM period. The width of the PWMSYNC pulse is pro-

grammable through the PWMSYNCWT register.

• The output control unit allows the redirection of the

outputs of the three-phase timing unit for each channel

to either the high side or the low side output. In addi-

tion, the output control unit allows individual enabling/

disabling of each of the six PWM output signals.

• The GATE drive unit provides the high chopping fre-

quency and its subsequent mixing with the PWM sig-

nals.

The PWM signals produced by the ADMCF327 can be

shut off in a number of different ways. First, there is a dedi-

cated asynchronous PWM shutdown pin, PWMTRIP,

which, when brought LO, instantaneously places all six

PWM outputs in the OFF state. Because this hardware

shutdown mechanism is asynchronous, and the associated

PWM disable circuitry does not use clocked logic, the

PWM will shut down even if the DSP clock is not run-

ning. The PWM system may also be shut down from

software by writing to the PWMSWT register.

• The PWM shutdown controller manages the three

PWM shutdown modes (via the PWMTRIP pin, or the

PWMSWT register) and generates the correct RE-

SET signal for the Timing Unit.

• The PWM controller is driven by a clock at the same fre-

quency as the DSP instruction rate, CLKOUT, and is

capable of generating two interrupts to the DSP core.

One interrupt is generated on the occurrence of a

PWMSYNC pulse, and the other is generated on the

occurrence of any PWM shutdown action.

Status information about the PWM system of the

ADMCF327 is available to the user in the SYSSTAT

register. In particular, the state of PWMTRIP is available,

as well as a status bit that indicates whether operation is in

the first half or the second half of the PWM period.

Three-Phase Timing Unit

The 16-bit three-phase timing unit is the core of the

PWM controller and produces three pairs of pulsewidth

modulated signals with high resolution and minimal pro-

cessor overhead. There are four main configuration registers

(PWMTM, PWMDT, PWMPD and PWMSYNCWT)

that determine the fundamental characteristics of the

PWM outputs. In addition, the operating mode of the

A functional block diagram of the PWM controller is

shown in Figure 6. The generation of the six output

PWM signals on pins AH to CL is controlled by four

important blocks:

PWM CONFIGURATION

REGISTERS

PWM DUTY CYCLE

REGISTERS

PWMTM (15...0)

PWMDT (9...0)

PWMPD (15...0)

PWMSYNCWT (7...0)

MODECTRL (6)

PWMCHA (15...0)

PWMCHB (15...0)

PWMCHC (15...0)

PWMGATE (9...0)

PWMSEG (8...0)

AH

AL

BH

THREE-PHASE

PWM TIMING

UNIT

OUTPUT

CONTROL

UNIT

GATE

DRIVE

UNIT

BL

CH

CL

SYNC

CLK

RESET

SYNC

CLK

CLKOUT

PWMSYNC

TO INTERRUPT

CONTROLLER

PWMTRIP

PW M TRIP

OR

PWMSWT (0)

OVER

CURRENT

TRIP

I

SENSE

ANALOG BLOCK

PWM SHUTDOWN CONTROLLER

Figure 6. Overview of the PWM Controller of the ADMCF327

–12–

REV. PrA

Preliminary Technical Data

ADMCF327

PWM (single or double update mode) is selected by Bit 6

of the MODECTRL register. These registers, in conjunction

with the three 16-bit duty cycle registers (PWMCHA, PW-

MCHB and PWMCHC), control the output of the three-

phase timing unit.

used to latch new values from the PWM configuration

registers (PWMTM, PWMPD, and PWMSYNCWT)

and the PWM duty cycle registers (PWMCHA, PWM-

CHB and PWMCHC) into the three-phase timing unit.

The PWMSEG register is also latched into the output

control unit on the rising edge of the PWMSYNC

pulse. In effect, this means that the parameters of the

PWM signals can be updated only once per PWM period

at the start of each cycle. Thus, the generated PWM pat-

terns are symmetrical about the midpoint of the switching

period.

PWM Switching Frequency: PWMTM Register

The PWM switching frequency is controlled by the

PWM period register, PWMTM. The fundamental tim-

ing unit of the PWM controller is t_CK= 1/f_CLKOUTwhere

f_CLKOUTis the CLKOUT frequency (DSP instruction

rate). Therefore, for a 20 MHz CLKOUT, the fundamen-

tal time increment is 50 ns. The value written to the

PWMTM register is effectively the number of t_CKclock

increments in half a PWM period. The required

PWMTM value is a function of the desired PWM

switching frequency (f_PWM) and is given by:

In double update mode, there is an additional PWMSYNC

pulse produced at the midpoint of each PWM period. The

rising edge of this new PWMSYNC pulse is again used to

latch new values of the PWM con•guration registers, duty

cycle registers and the PWMSEG register. As a result, it

is possible to alter both the characteristics (switching

frequency, minimum pulsewidth and PWMSYNC

pulsewidth) and the output duty cycles at the midpoint

of each PWM cycle. Consequently, it is possible to

produce PWM switching patterns that are no longer

symmetrical about the midpoint of the period (asymmetri-

cal PWM patterns).

f_CLKOUT

f_CLKIN

PWMTM =

=

2× f_PWM

f_PWM

Therefore, the PWM switching period, T_S, can be written

as:

T_S= 2 × PWMTM × t_CK

For example, for a 20 MHz CLKOUT and a desired

PWM switching frequency of 10 kHz (T_S= 100 µs), the

correct value to load into the PWMTM register is:

In the double update mode, operation in the first half or

the second half of the PWM cycle is indicated by Bit 3

of the SYSSTAT register. In double update mode, this bit

is cleared during operation in the first half of each PWM

period (between the rising edge of the original

PWMSYNC pulse and the rising edge of the new

PWMSYNC pulse, which is introduced in

double update mode). Bit 3 of the SYSSTAT register is

set during the second half of each PWM period. If re-

quired, a user may determine the status of this bit during a

PWMSYNC interrupt service routine.

20×10⁶

2×10×10³

PWMTM =

1000=0×3E8

The largest value that can be written to the 16-bit

PWMTM register is 0xFFFF = 65,535, which corre-

sponds to a minimum PWM switching frequency of:

20×10⁶

f_PWM,min

=

=153Hz

The advantages of the double update mode are that lower

harmonic voltages can be produced by the PWM process

and wider control bandwidths are possible. However, for

a given PWM switching frequency, the PWMSYNC

pulses occur at twice the rate in the double update mode.

Because new duty cycle values must be computed in each

PWMSYNC interrupt service routine, there is a larger

computational burden on the DSP in the double update

mode.

2×65,535

for a CLKOUT frequency of 20 MHz.

PWM Switching Dead Time: PWMDT Register

In many applications there is a need to insert a short delay,

known as dead time between tuning on its complimentary

PWM signal. However, there is no dead time required in

switched reluctance applications. Therefore, the program-

mable dead time register, PWMDT, is set to a default of

0 on the ADMCF327.

Width of the PWMSYNC Pulse: PWMSYNCWT Register

The PWM controller of the ADMCF327 produces an

internal PWM synchronization pulse at a rate equal to the

PWM switching frequency in single update mode and at

twice the PWM frequency in the double update mode.

This PWMSYNC synchronizes the operation of the

PWM unit with the A/D converter system. The width of

this PWMSYNC pulse is programmable by the PWM-

SYNCWT register. The width of the PWMSYNC pulse,

T_PWMSYNC, is given by:

PWM Operating Mode: MODECTRL and SYSSTAT Reg-

isters

The PWM controller of the ADMCF327 can operate in

two distinct modes: single update mode and double update

mode. The operating mode of the PWM controller is

determined by the state of Bit 6 of the MODECTRL regis-

ter. If this bit is cleared, the PWM operates in the single

update mode. Setting Bit 6 places the PWM in the

double update mode. By default, following either a pe-

ripheral reset or power-on, Bit 6 of the MODECTRL

register is cleared. This means that the default operating

mode is single update mode.

T_PWMSYNC=t_CK× PWMSYNCWT +1

(

)

which means that the width of the pulse is programmable

from t_CKto 256 t_CK(corresponding to 50 ns to 12.8 µs for a

CLKOUT rate of 20 MHz). Following a reset, the

PWMSYNCWT register contains 0x27 (= 39) so that the

default PWMSYNC width is 2.0 µs.

In single update mode, a single PWMSYNC pulse is pro-

duced in each PWM period. The rising edge of this

signal marks the start of a new PWM cycle and is

REV. PrA

–13–

Preliminary Technical Data

ADMCF327

The output signals from the timing unit for operation in

double update mode are shown in Figure 8. This illustrates

a completely general case where the switching frequency,

and duty cycle are all changed in the second half of the

PWM period. Of course, the same value for any or all of

these quantities could be used in both halves of the PWM

cycle. However, it can be seen that there is no guarantee

that symmetrical PWM signals will be produced by the

timing unit in this double update mode.

PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC

Registers

The duty cycles of the three high-side PWM output

signals are controlled by the three duty cycle registers,

PWMCHA, PWMCHB, and PWMCHC. The integer

value in the register PWMCHA controls the duty cycle

of the signals on AH. PWMCHB controls the duty cycle

of the signals on BH and BL, and PWMCHC controls

the duty cycle of the signals on CH. The duty cycle regis-

ters are programmed in integer counts of the fundamental

time unit, t_CK, and define the desired on-time of the high-

side PWM signal produced by the three-phase timing unit

over half the PWM period.

PWMCHA

2

1

AH

The PWM is center-based. This means that in single update

mode the resulting output waveforms are symmetrical and

centered in the PWMSYNC period. Figure 7 presents a

typical PWM timing diagram illustrating the PWM-re-

lated registers’ (PWMCHA, PWMTM, and

AL

PWMSYNC

PWMSYNCWT + 1

2

1

SYSSTAT (3)

PWMTM

1

2

PWMSYNCWT) control over the waveform timing in

both half cycles of the PWM period. The magnitude of

each parameter in the timing diagram is determined by

multiplying the integer value in each register by t_CK(typi-

cally 50 ns). It may be seen in the timing diagram how

dead time is incorporated into the waveforms by moving

the switching edges away from the instants set by the

PWMCHA register.

Figure 8. Typical PWM Outputs of Three-Phase Timing

Unit in Double Update Mode

In general, the on-time of the high-side PWM signals in

double update mode is defined by:

T_AH= PWMCHA +PWMCHA × t

CK

(

)

1

2

PWMCHA

where the subscript 1 refers to the value of that register

during the first half cycle and the subscript 2 refers to the

value during the second half cycle. The corresponding

duty cycles is:

AH

AL

PWMSYNCWT + 1

PWMSYNC

T_AHPWMCHA₁+ PWMCHA₂

d _AH

=

T_S

PWMTM₁+ PWMTM₂

SYSSTAT (3)

PWMTM

because for the completely general case in double update

mode, the switching period is given by:

Figure 7. Typical PWM Outputs of Three-Phase Timing

Unit in Single Update Mode

T = PWMTM + PWMTM

2

t_CK

(

)

S

1

Each switching edge is moved by an equal amount (PWMDTX

Again, the value of T_AHis constrained to lie between zero

and T_S.

x

t_CK) to preserve the symmetrical output patterns. The

PWMSYNC pulse, whose width is set by the PWMSYN-

CWT register, is also shown. Bit 3 of the SYSSTAT reg-

ister indicates which half cycle is active. This can be

useful in double update mode, as will be discussed later.

PWM signals similar to those illustrated in Figure 7 and

Figure 8 can be produced on the BH, BL, CH, and CL

outputs by programming the PWMCHB and PWMCHC

registers in a manner identical to that described for

PWMCHA.

The resultant on-time of the high-side PWM signals

shown in Figure 7 may be written as:

The PWM controller does not produce any PWM outputs

until all of the PWMTM, PWMCHA, PWMCHB, and

PWMCHC registers have been written to at least once.

After these registers have been written, the counters in the

three-phase timing unit are enabled. Writing to these reg-

isters also starts the main PWM timer. If during initializa-

tion, the PWMTM register is written before the

PWMCHA, PWMCHB, and PWMCHC registers, the

first PWMSYNC pulse (and interrupt if enabled) will be

generated (1.5 x t_CKx PWMTM) seconds after the initial

write to the PWMTM register in single update mode. In

double update mode, the first PWMSYNC pulse will be

T_AH=2×PWMCHA× t_CK

The corresponding duty cycles are:

T_AHPWMCHA

d _AH

=

T_S

PWMTM

Obviously, negative values of T_AHare not permitted

because the minimum permissible value is zero, corre-

sponding to a 0% duty cycle. In a similar fashion, the maxi-

mum value is T_S, corresponding to a 100% duty cycle. The

low-side PWM output signals are always in ON state for

switched reluctance applications.

–14–

REV. PrA

Preliminary Technical Data

generated (t_CKx PWMTM) seconds after the initial write

to the PWMTM register in single update mode.

ADMCF327

turned OFF for the entire half period, and its comple-

mentary signal is turned completely ON.

Consider the example where PWMTM = 200, PWMCHA

= 5, PWMDT = 3, and PWMPD = 10 with a CLKOUT

of 20 MHz, while operating in single update mode. For

this case, the PWM switching frequency is 50 kHz. The

minimum permissible on-time of any PWM signal over

one-half of any period is 500 ns. Clearly, for this example,

on-time of the AH signal for one-half a PWM period is

(5) ∞ 50 ns = 1.50 ns. Because this is less than the mini-

mum permissible value, output AH of the timing unit

will remain OFF (0% duty cycle). Additionally, the AL

signal will be turned ON for the entire half period (100%

duty cycle).

Effective PWM Resolution

In single update mode, the same values of PWMCHA,

PWMCHB and PWMCHC are used to define the on-

times in both half cycles of the PWM period. As a result,

the effective resolution of the PWM generation process is

2 t_CK(or 100 ns for a 20 MHz CLKOUT) since

incrementing one of the duty cycle registers by one

changes the resultant on-time of the associated PWM sig-

nals by t_CKin each half period (or 2 t_CKfor the full pe-

riod).

In double update mode, improved resolution is possible

since different values of the duty cycle registers are used

to define the on-times in both the first and second halves

of the PWM period. As a result, it is possible to adjust

the on-time over the whole period in increments of t_CK

This corresponds to an effective PWM resolution of t_CK

in double update mode (or 50 ns for a 20 MHz

CLKOUT).

Output Control Unit: PWMSEG Register

The operation of the output control unit is managed by

the 9-bit read/write PWMSEG register.

.

The PWMSEG register contains three crossover bits, one for

each pair of PWM outputs. Setting Bit 8 of the

PWMSEG register enables the crossover mode for the

AH/AL pair of PWM signals; setting Bit 7 enables cross-

over on the BH/BL pair of PWM signals; and setting Bit

6 enables crossover on the CH/CL pair of PWM signals.

If crossover mode is enabled for any pair of PWM sig-

nals, the high-side PWM signal from the timing unit (for

example AH) is diverted to the associated low-side output

of the output control unit so that the signal will ulti-

mately appear at the AL pin. Of course, the correspond-

ing low-side output of the timing unit is also diverted to

the complementary high-side output of the output con-

trol unit so that the signal appears at Pin AH. Following

a reset, the three crossover bits are cleared so that the

crossover mode is disabled on all three pairs of PWM

signals.

The achievable PWM switching frequency at a given

PWM resolution is tabulated in Table IV.

Table IV. Achievable PWM Resolution in Single and

Double Update Modes

Resolution Single Update Mode

Double Update Mode

(Bit)

PWM Frequency (kHz) PWM Frequency (kHz)

8

9

10

11

12

39.1

19.5

9.8

4.9

2.4

78.1

39.1

19.5

9.8

4.9

Minimum Pulsewidth: PWMPD Register

The PWMSEG register also contains six bits (Bits 0 to 5)

that can be used to individually enable or disable each

of the six PWM outputs. If the associated bit of the

PWMSEG register is set, the corresponding PWM output

is disabled regardless of the value of the corresponding duty

cycle register. This PWM output signal will remain in the

OFF state as long as the corresponding enable/disable bit

of the PWMSEG register is set. The PWM output enable

function gates the crossover function. After a reset, all six

enable bits of the PWMSEG register are cleared, thereby

enabling all PWM outputs by default.

In many power converter switching applications, it is de-

sirable to eliminate PWM switching pulses shorter than a

certain width. It takes a finite time to both turn on

and turn off modern power semiconductor devices.

Therefore, if the width of any of the PWM pulses is

shorter than some minimum value, it may be desir-

able to completely eliminate the PWM switching for

that particular cycle.

The allowable minimum on-time for any of the six PWM

outputs for half a PWM period that can be produced by the

PWM controller may be programmed using the PWMPD

register. The minimum on-time is programmed in incre-

ments of t_CKso that the minimum on-time produced for any

half PWM period, T_MIN, is related to the value in the

PWMPD register by:

In a manner identical to the duty cycle registers, the

PWMSEG is latched on the rising edge of the

PWMSYNC signal so that changes to this register only

become effective at the start of each PWM cycle in single

update mode. In double update mode, the PWMSEG

register can also be updated at the midpoint of the PWM

cycle.

T

_MIN= PWMPD×t_CK

A PWMPD value of 0x002 defines a permissible mini-

mum on-time of 100 ns for a 20 MHz CLKOUT.

Gate Drive Unit: PWMGATE Register

The gate drive unit of the PWM controller adds fea-

tures that simplify the design of isolated gate drive cir-

cuits for PWM inverters. If a transformer-coupled power

device gate drive amplifier is used, the active PWM signal

must be chopped at a high frequency. The PWMGATE

register allows the programming of this high frequency

In each half cycle of the PWM, the timing unit checks the

on-time of each of the six PWM signals. If any of the

times is found to be less than the value specified by the

PWMPD register, the corresponding PWM signal is

REV. PrA

–15–

Preliminary Technical Data

ADMCF327

chopping mode. The chopped active PWM signals may be

programmed for the high-side drivers only, as there is

no chopping required for the low-side switches in switched

reluctance applications. Control of this mode for the high-

side switches is included with a control bit in the PWM-

GATE register.

ing the same PWMSWT register. Reading this register

also clears it.

Restarting the PWM after a fault condition is detected

requires clearing the fault and reinitializing the PWM.

Clearing the fault requires that PWMTRIP returns to a HI

state. After the fault has been cleared, the PWM can be

restarted by writing to registers PWMTM, PWMCHA,

PWMCHB, and PWMCHC. After the fault is cleared and the

PWM registers are initialized, internal timing of the three-

phase timing unit will resume, and the new duty cycle values

will be latched on the next rising edge of PWMSYNC.

Typical PWM output signals with high-frequency chop-

ping enabled on the high-side signals are shown in Fig-

ure 9. Chopping of the high-side PWM outputs (AH, BH

and CH) is enabled by setting Bit 8 of the PWMGATE

register. The high chopping frequency is controlled by

the 8-bit word (GDCLK) written to Bits 0 to 7 of the

PWMGATE register. The period and the frequency of

this high frequency carrier are:

PWM Registers

The configuration of the PWM registers is described at

the end of the data sheet. The parameters of the PWM

block are tabulated in Table V.

T_CHOP4 × GDCLK + 1 × t_CK

(

)

ADC OVERVIEW

f_CLKOUT

4 × GDCLK +1

The ADC of the ADMCF327 is based upon the single

slope conversion technique. This approach offers an

inherently monotonic conversion process and to within the

noise and stability of its components, and there will be no

missing codes.

f_CHOP

=

(

)

The GDCLK value may range from 0 to 255, correspond-

ing to a programmable chopping frequency rate from

19.5 kHz to 5 MHz for a 20 MHz CLKOUT rate. The

gate drive features must be programmed before operation

of the PWM controller and typically are not changed

during normal operation of the PWM controller. Fol-

lowing a reset, by default, all bits of the PWMGATE

register are cleared so that high frequency chopping is dis-

abled.

Table VI. ADC Auxiliary Channel Selection

MODECTRL (1)

ADCMUX1

MODECTRL (0)

ADCMUX0

Select

VAUX0

VAUX1

VAUX2

0

1

0

1

0

1

PWMCHA PWMCHA

Calibration (V_REF

)

AH

The single slope technique has been adapted on the

ADMCF327 for four channels that are simultaneously

converted. Refer to Figure 10 for the functional sche-

matic of the ADC. Three of the main inputs (V1 V2, and

V3) are directly connected as high impedance voltage

inputs. The fourth channel has been con•gured with a

serially-connected 4-to-1 multiplexer. Table VI shows the

multiplexer input selection codes. One of these auxiliary

multiplexed channels is used to calibrate the ramp against the

internal voltage reference (V_REF).

[4

ꢀ (GDCLK+1) ꢀ t_CK]

AL

PWMTM

Figure 9. Typical PWM signals with high frequency chopping

enabled on high-side switches. Low-side PWM signals are

always in “ON” state. For switched reluctance applications

(GDCLK is the integer equivalent of the value in

Bits 0 to 7 of the PWMGATE register.)

PWM Shutdown

In the event of external fault conditions, it is essential that

the PWM system be instantaneously shut down. A low

level on the PWMTRIP pin initiates an instantaneous,

asynchronous (independent of DSP clock) shutdown of

the PWM controller. This places all six PWM outputs in

the OFF state, disables the PWMSYNC pulse and asso-

ciated interrupt signal, and generates a PWMTRIP interrupt

signal. The PWMTRIP pin has an internal pull-down resis-

tor so that even if the pin becomes disconnected, the PWM

outputs will be disabled. The state of the PWMTRIP pin

can be read from Bit 0 of the SYSSTAT register.

In addition, it is possible through software it is possible

through software to initiate a PWM shutdown by writing

to the 1-bit read/write PWMSWT register (0x2061).

Writing to this bit generates a PWM shutdown in a

manner identical to the PWMTRIP pin. Following a

PWM shutdown, it is possible to determine if the shut-

down was generated from hardware or software by read-

–16–

REV. PrA

Preliminary Technical Data

ADMCF327

Table V. Fundamental Characteristics of PWM Generation Unit of ADMCF327

16-BITPWMTIMER

Parameter

Min

Typ

Max

Unit

Counter Resolution

16

100

50

Bits

ns

µs

ns

µs

ns

Hz

Edge Resolution (Single Update Mode)

Edge Resolution (Double Update Mode)

Programmable Dead Time Range

Programmable Dead Time Increments

Programmable Pulse Deletion Range

Programmable Pulse Deletion Increments

PWM Frequency Range

0

100

0

100

150

PWMSYNC Pulsewidth (T_CRST

Gate Drive Chop Frequency Range

)

0.05

0.02

12.5

5

µs

MHz

ICONST_TRIM<2:0>

(CAP RESET)

ICONST

V

C

PWMSYNC (CONVST)

CLK MODECTRL<7>

EXTERNAL

CHARGING

CAP

C

ADC

V

REGISTERS

V

C

CM AX

GND

COMP

V1L

V1

12-BIT

ADC

COMP

V2L

V3L

V2

V3

TIMER

BLOCK

ADC REGISTERS

COMP

ADC1

ADC2

V

VIL

ADC3

VAUXL

COMP

t

ADCAUX

T

t_VIL

CRST

VAUX0

VAUX1

VAUX2

MODECTRL<0..1>

T

›T

CRST

P W M

4 › 1

MUX

PWMSYNC

VREF

COMPARATOR

OUTPUT

Figure 10. ADC Overview

Comparing each ADC input to a reference ramp voltage

and timing the comparison of the two signals performs the

conversion process. The actual conversion point is the

time point intersection of the input voltage and the ramp

voltage (V_C) as shown in Figure 11. This time is converted

to counts by the 12-bit ADC Timer Block and is stored in

the ADC registers. The ramp voltage used to perform the

conversion is generated by driving a •xed current into an

off-chip capacitor, where the capacitor voltage is

Figure 11. Analog Input Block Operation

The ADC system consists of four comparators and a

single timer, which may be clocked at either the DSP rate

or half the DSP rate, depending on the setting of the

ADCCNT bit (Bit 7) of the MODECTRL register. When

this bit is cleared, the timers count at a slower rate of

CLKIN. When this bit is set, they count at CLKOUT or

twice the rate of CLKIN. ADC1, ADC2, ADC3, and

ADCAUX are the registers that capture the conversion

times, which are effectively the timer values, when the asso-

ciated comparator trips.

V_C= (I/C) x t

Following reset, V_C= 0 at t = 0. This reset and the start

of the conversion process are initiated by the

PWMSYNC pulse, as shown in Figure 11. The width

of the PWMSYNC pulse is controlled by the

PWMSYNCWT register and should be programmed

according to Figure 12 to ensure complete resetting. In

order to compensate for IC process manufacturing toler-

ances (and to adjust for capacitor tolerances), the current

source of the ADMCF327 is software programmable. The

software setting of the magnitude of the ICONST current

generator is accomplished by selecting one of eight steps

over approximately 20% current range.

REV. PrA

–17–

Preliminary Technical Data

then determine the proper charge capacitor off the appro-

ADMCF327

200

priate curve.

100

150

100

TUNED ICONST

10

50

0

2

4

6

8

10

DEFAULT ICONST

CHARGING CAPACITOR › nF

Figure 12. PWMSYNCWT Program Value

ADC Resolution

The ADC is intrinsically linked to the PWM block

through the PWMSYNC pulse controlling the ADC

conversion process. Because of this link, the effective

resolution of the ADC is a function of both the PWM

switching frequency and the rate at which the ADC

counter timer is clocked. For a CLKOUT

1

10

100

FREQUENCY › kHz

Figure 13. Timing Capacitor Selection

Programmable Current Source

The ADMCF327 has an internal current source that is

used to charge an external capacitor, generating the volt-

age ramp used for conversion. The magnitude of the

output of the current source circuit is subject to manu-

facturing variations and can vary from one device to the

next. Therefore, the ADMCF327 incudes a programmable

current source whose output can always be tuned to within

5% of the target 100 µA. A 3-bit register,

ICONST_TRIM, allows the user to make this adjustment.

The output current is proportional to the value written to

the register: 0x0 produces the minimum output, and 0x7

produces the maximum output. The default value of

ICONST_TRIM after reset is 0x0.

period of t_CKand a PWM period of T_PWM, the maximum

count of the ADC is given by:

Max Count = min (4095, (T_PWM– T_CRST)/2 t_CK

)

for MODECTRL Bit 7 = 0

Max Count = min (4095, (T_PWM– T_CRST)/t_CK

for MODECTRL Bit 7 = 1

)

Where T_PWMis equal to the PWM period if operating in

single update mode, or it is equal to half that period if

operating in double update mode. For an assumed

CLKOUT frequency of 20 MHz and PWMSYNC

pulsewidth of 2.0 µs, the effective

ADC Reference Ramp Calibration

The peak of the ADC ramp voltage should be as close as

possible to 3.5 V to achieve the optimum ADC resolution

and signal range. When the current source is in the Default

State, the peak of the ADC ramp slope will be lower

than this “3.5 V” target ramp. When the current source

value is increased, the ADC ramp slope will become

closer to the target value. The “tuned” ramp slope is the

one closest to the target ramp.

resolution of the ADC block is tabulated for various

PWM switching frequencies in Table VII.

Table VII. ADC Resolution Examples

PWM

Frequency

(kHz)

MODECTRL[7] = 0

MODECTRL[7] = 1

Max

Effective

Resolution

Max

Effective

Resolution

Count

A simple calibration procedure using the internal 2.5 V refer-

ence voltage allows the selection of the

ICONST_TRIM register value to reach this:

2.4

4

8

18

25

4095

2480

1230

535

12

4095

2460

1070

760

12

>11

>10

>9

>11

>10

>9

1. A high quality linear ADC capacitor is selected using

Figure 14 for a tuned ICONST.

380

>8

2. Program PWMSYNCWT to proper count as in Figure

13.

Charging Capacitor Selection

The charging capacitor value is selected based on the

sample (PWM) frequency desired. A too-small capacitor

value will reduce the available resolution of the ADC by

having the ramp voltage rise rapidly and convert too

quickly, not utilizing all possible counts available in the

PWM cycle. Too large a capacitor may not convert in the

available PWM cycle returning 0x000. To select a charging

capacitor, use Figure 13, select the sampling frequency de-

sired, determine if the current source is to be tuned to a

nominal 100 µA or left in the default (0x0 code) trim state,

3. The ADC Max Count is calculated, as described in a

previous section.

4. The target reference conversion is calculated as TAR-

GET = (Max Count) ∞ (2.5 V/3.5 V).

5. Reset or software sets the ICONST_TRIM register to

zero.

6. Select calibration channel in software on ADC multi-

plexer.

–18–

REV. PrA

Preliminary Technical Data

7. The calibration channel value is compared with the

target reference conversion.

ADMCF327

Since the values in both AUXTM0 and AUXTM1 can

range from 0 to 0xFF, the achievable switching fre-

quency of the auxiliary PWM signals may range from

39.1 kHz to 10 MHz for a CLKOUT frequency of 20

MHz.

8. If this value is greater than the TARGET, the

ICONST_TRIM value is incremented by one, and Step

7 is repeated.

The on-time of the two auxiliary PWM signals is pro-

grammed by the two 8-bit AUXCH0 and AUXCH1 regis-

ters, according to:

9. If the calibration channel value is less than the TAR-

GET, the calibration is completed.

3.5V

T_ON

,

= 2 x (AUXCH0) x t_CK

= 2 x (AUXCH1) x t_CK

AUX0

AUX1

T_ON

TARGET

RAMP

so that output duty cycles from 0% to 100% are possible.

Duty cycles of 100% are produced if the on-time value

exceeds the period value. Typical auxiliary PWM wave-

forms in independent mode are shown in Figure 15(a).

V

REF

MINIMUM

RAMP

When Bit 8 of the MODECTRL register is cleared, the

auxiliary PWM channels are placed in offset mode. In

offset mode, the switching frequency of the two signals on

the AUX0 and AUX1 pins are identical and controlled

by AUXTM0 in a manner similar to that previously

described for independent mode. In addition, the on times

of both the AUX0 and AUX1 signals are controlled by the

AUXCH0 and AUXCH1 registers as before. However, in

this mode the AUXTM1 register defines the offset time

from the rising edge of the signal on the AUX0 pin to that

on the AUX1 pin according to:

0.3V

Figure 14. Current Ramp

ADC Registers

The configuration of all registers of the ADC System is

shown at the end of the data sheet.

T_OFFSET= 2 x (AUXTM1 + 1) x t_CK

AUXILIARY PWM TIMERS

Overview

For correct operation in this mode, the value written to

the AUXTM1 register must be less than the value writ-

ten to the AUXTM0 register. Typical auxiliary PWM

waveforms in offset mode are shown in Figure 15(b).

Again, duty cycles from 0% to 100% are possible in this

mode.

The ADMCF327 provides two variable frequency, vari-

able duty cycle, 8-bit, auxiliary PWM outputs that are avail-

able at the AUX1 and AUX0 pins when enabled. These

auxiliary PWM outputs can be used to provide switch-

ing signals to other circuits in a typical motor control

system such as power factor corrected front-end convert-

ers or other switching power converters. Alternatively, by

addition of a suitable filter network, the auxiliary PWM

output signals can be used as simple single-bit digital-to-

analog converters.

In both operating modes, the resolution of the auxiliary

PWM system is eight bits only at the minimum switch-

ing frequency (AUXTM0 = AUXTM1 = 255 in indepen-

dent mode, AUXTM0 = 255 in offset mode). Obviously,

as the switching frequency is increased, the resolution is

reduced.

The auxiliary PWM system of the ADMCF327 can oper-

ate in two different modes: independent mode or offset

mode. The operating mode of the auxiliary PWM sys-

tem is controlled by Bit 8 of the MODECTRL regis-

ter. Setting Bit 8 of the MODECTRL register places

the auxiliary PWM system in the independent mode. In

this mode, the two auxiliary PWM generators are com-

pletely independent and separate switching frequen-

cies and duty cycles may be programmed for each

auxiliary PWM output. In this mode, the 8-bit AUXTM0

register sets the switching frequency of the signal at the

AUX0 output pin. Similarly, the 8-bit AUXTM1 regis-

ter sets the switching frequency of the signal at the AUX1

pin. The fundamental time increment for the auxiliary

PWM outputs is twice the DSP instruction rate (or 2

t_CK) and the corresponding switching

Values can be written to the auxiliary PWM registers at

any time. However, new duty cycle values written to the

AUXCH0 and AUXCH1 registers only become effective

at the start of the next cycle. Writing to the AUXTM0

or AUXTM1 registers causes the internal timers to be

reset to 0 and new PWM cycles to begin.

By default following a reset, Bit 8 of the MODECTRL

register is cleared, thus enabling offset mode. In addition,

the registers AUXTM0 and AUXTM1 default to 0xFF,

corresponding to the minimum switching frequency and

zero offset. The on-time registers AUXCH0 and

AUXCH1 default to 0x00.

periods are given by:

T_AUX0= 2 x (AUXTM0 + 1) x t_CK

T_AUX1= 2 x (AUXTM1 + 1) x t_CK

REV. PrA

–19–

Preliminary Technical Data

ADMCF327

Table VIII. Auxiliary PWM Timer

AUXILIARYPWMTIMERS

Parameter

TestConditions

Min

0.039

Typ

Max

Unit

Resolution

PWM Frequency

8

Bits

MHz

10 MHz CLKIN

performed. In addition, Bit 1 of the SYSSTAT register is

set so that after a watchdog reset, the ADMCF327 can

determine that the reset was due to the timeout of the

watchdog timer and not an external reset. Following a

watchdog reset, Bit 1 of the SYSSTAT register may be

cleared by writing zero to the WDTIMER register.

This clears the status bit but does not enable the watch-

dog timer.

Auxiliary PWM Interface, Registers and Pins

The registers of the auxiliary PWM system are summa-

rized at the end of the data sheet.

2 ꢀ (AUXTM0 + 1)

2 ꢀ AUXCH0

AUX0

2 ꢀ AUXCH1

On reset, the watchdog timer is disabled and is only

enabled when the first timeout value is written to the

WDTIMER register. To prevent the watchdog timer from

timing out, the user must write to the WDTIMER register

at regular intervals (shorter than the programmed

WDTIMER period value). On all but the first write to

WDTIMER, the particular value written to the register is

unimportant since writing to WDTIMER simply reloads

the first value written to this register.

2 ꢀ (AUXTM1 + 1)

AUX1

2 ꢀ AUXCH1

(a) Independent Mode

2 ꢀ (AUXTM 0 + 1)

2 ꢀ AUXCH 0

PROGRAMMABLE DIGITAL INPUT/OUTPUT

The ADMCF327 has nine programmable digital input/

output (PIO) pins that are all multiplexed with other func-

tions. The nine PIO lines PIO0–PIO8 are multiplexed

with the serial port (Pins PIO0/TFS1 to PIO5/RFS1), the

CLKOUT (pin PIO6/CLKOUT) and the auxiliary PWM

outputs (Pins PIO7/AUX1 and PIO8/AUX0). When con-

figured as a PIO, each of these nine pins can act as an

input, output, or an interrupt source.

AUX0

2 ꢀ (AUXTM0 + 1)

AUX1

2 ꢀ AUXCH 1

2 ꢀ (AUX TM 1 + 1)

(b) Offset Mode

Figure 15. Typical Auxiliary PWM Signals. (All Times in

The operating mode of pins PIO0/TFS1 to PIO7/AUX1

is controlled by the PIOSELECT register. This 8-bit

register has a bit for each input so that the mode of each pin

may be selected individually. Bit 0 of PIOSELECT con-

trols the operation of the PIO0/TFS1 pin. Bit 1 controls

the PIO1/DT1 pin etc. Setting the appropriate bit in the

PIOSELECT register causes the corresponding pin to be

configured for PIO functionality. Clearing the bit selects

the alternate (SPORT, CLKOUT, or AUXPWM) mode

of the corresponding pin. Following power-on reset, all

bits of PIOSELECT are set such that PIO functional-

ity is selected. The operating mode of the PIO8/AUX0

pin is selected by Bit 1 of the PIODATA1 register. In a

manner identical to the PIOSELECT register, setting this

bit enables PIO functionality (PIO8) while clearing the bit

enables auxiliary PWM functionality (AUX0).

Increments of t_CK

)

PWM DAC Equation

The auxiliary PWM output can be filtered in order to

produce a low frequency analog signal between 0 V to

V_DD. For example, a 2-pole filter with a 1.2 kHz cutoff

frequency will sufficiently attenuate the PWM carrier.

Figure 16 shows how the filter would be applied.

AUXPWM

R1 = R2 = 13k ꢃ

C1 = C2 = 10nF

R1

R2

C2

C1

Figure 16. Auxiliary PWM Output Filter

WATCHDOG TIMER

The ADMCF327 incorporates a watchdog timer that can

perform a full reset of the DSP and motor control periph-

erals in the event of software error. The watchdog timer is

enabled by writing a timeout value to the 16-bit

WDTIMER register. The timeout value represents the

number of CLKIN cycles required for the watchdog timer

to count down to zero. When the watchdog timer reaches

zero, a full DSP core and motor control peripheral reset is

Once PIO functionality has been selected for any or all of

these nine pins, the direction may be set by the 8-bit

PIODIR0 register (for PIO0 to PIO7) and the 1-bit

PIODIR1 register (for PIO8). Clearing any bit configures

the corresponding PIO line as an input while setting the

bit configures it as an output. By default, following a re-

set, all bits of PIODIR0 and PIODIR1 are cleared config-

uring the PIO lines as inputs. The data of the PIO0 to

–20–

REV. PrA

Preliminary Technical Data

ADMCF327

PIO8 lines is controlled by the PIODATA0 register

(for PIO0 to PIO7) and Bit 0 of the PIODATA1 reg-

ister (for PIO8). These registers can be used to read data

from those PIO lines con•gured as inputs and write data to

those configured as outputs. Any of the nine pins that have

been configured for PIO functionality can be made to act as

an interrupt source by setting the appropriate bit of the

PIOINTEN0 register (for PIO0 to PIO7) or the

PIO Registers

The configuration of all registers of the PIO system is

shown at the end of the data sheet.

INTERRUPT CONTROL

The ADMCF327 can respond to 16 different interrupt

sources, some of which are generated by internal DSP

core interrupts and others from the motor control periph-

erals. The DSP core interrupts include the following:

PIOINTEN1 register (for PIO8). In order to act as an

interrupt source the pin must also be configured as an input.

An interrupt is generated upon a change of state (low-

to-high transition or high-to-low transition) on any input

that has been configured as an interrupt source. Follow-

ing a change of state event on any such input, the corre-

sponding bit is set in the PIOFLAG0 register (for

PIO0 to PIO7) and PIOFLAG1 (for PIO8) and a com-

mon PIO interrupt is generated. Reading the PIOFLAG0

and PIOFLAG1 registers permits determining the inter-

rupt source. Reading the PIOFLAG0 and PIOFLAG1

registers automatically clears all bits of the registers.

· A Peripheral (or IRQ2) Interrupt.

· A SPORT1 Receive (or IRQ0) and a SPORT1 Trans-

mit (or IRQ1) Interrupt.

· Two Software Interrupts.

· An Interval Timer Time-Out Interrupt.

The interrupts generated by the motor control peripherals

include:

· A PWMSYNC Interrupt.

· Nine Programmable Input/Output (PIO) Interrupts.

· A PWM Trip Interrupt.

Following power-on or reset, all bits of

PIOINTEN0 and PIOINTEN1 are cleared so that no

interrupts are enabled.

The core interrupts are internally prioritized and indi-

vidually maskable. All peripheral interrupts are multiplexed

into the DSP core through the peripheral (IRQ2) inter-

rupt.

Each PIO line has an internal pull-down resistor so that

following power-on or reset all nine lines are con•gured as

input PIOs and will be read as logic lows if left uncon-

nected.

The PWMSYNC interrupt is triggered by a low-to-high

transition on the PWMSYNC pulse. The PWMTRIP

interrupt is triggered on a high-to-low transition on the

PWMTRIP pin, or by writing to the PWMSWT register.

A PIO interrupt is detected on any change of state (high-

to-low or low-to-high) on the PIO lines.

Multiplexing of PIO Lines

The PIO0–PIO5 lines are multiplexed on the

ADMCF327 with the functional lines of the serial port,

SPORT1. Although the PIOSELECT register permits

individual selection of the functionality of each pin, cer-

tain restrictions apply when using SPORT1 for serial

communications.

The ADMCF327 interrupt control system is con•gured

and controlled by the IFC, IMASK, and ICNTL regis-

ters of the DSP core and by the IRQFLAG register for

the PWMSYNC and PWMTRIP interrupts. PIO inter-

rupts are enabled and disabled by the PIOINTEN0 and

PIOINTEN1 registers.

In general, when transmitting and receiving data on the

DTI and DRIB pins, respectively, the PIO0/TFS1 and

PIO5/RFS1 pins must also be selected for SPORT (TFS1

and RFS1) functionality even if unframed communication

is implemented. Therefore, when using SPORT1 for any

type of serial communication, the minimal setting for

PIOSELECT is 0xD8 (i.e., select DTI, DRIB, RFS1 and

TFS1, select PIO7, PIO6, PIO4, PIO3 as digital I/O).

Table IX. Interrupt Vector Addresses

Interrupt Source

InterruptVectorAddress

PWMTRIP

Peripheral Interrupt (IRQ2)

PWMSYNC

0x002C(HighestPriority)

0x0004

0x000C

If the serial port communications use an internally gen-

erated SCLK1, the PIO3/SCLK1 pin may be used as a

general-purpose PIO line. When external SCLK mode is

selected, the PIO/SCLK1 pin must be enabled as SCLK1

(PIOSELECT [3] = 0).

PIO

0x0008

SoftwareInterrupt1

SoftwareInterrupt0

0x0018

0x001C

SPORT1 Transmit Interrupt (or IRQ1) 0x0020

SPORT1 Receive Interrupt (or IRQ0) 0x0024

When the DRIB data receive line of SPORT1 is se-

lected as the data receive line (MODECTRL [4] = 1),

the PIO4/DRIA line may be used as a general-purpose

PIO pin. When the DRIA data receive line of SPORT1 is

selected as the data receive line (MODECTRL [4] = 0),

the PIO2/DRIB line may be used as a general-purpose

PIO pin.

Timer

0x0028(LowestPriority)

Interrupt Masking

Interrupt masking (or disabling) is controlled by the

IMASK register of the DSP core. This register contains

individual bits that must be set to enable the various inter-

rupt sources. If any peripheral interrupt (PWMSYNC,

PWMTRIP, or PIO) is to be enabled, the IRQ2 interrupt

enable bit (Bit 9) of the IMASK register must be set. The

configuration of the IMASK register of the ADMCF327

is shown at the end of the data sheet.

The functionality of the PIO6/CLKOUT, PIO7/AUX1,

and PIO8/AUX0 pins may be selected on a pin-by-pin basis

as desired.

REV. PrA

–21–

Preliminary Technical Data

SYSTEM CONTROLLER

ADMCF327

Interrupt Configuration

The IFC and ICNTL registers of the DSP core control and

configure the interrupt controller of the DSP core. The IFC

register is a 16-bit register that may be used to force and/

or clear any of the eight DSP interrupts. Bits 0 to 7 of

the IFC register may be used to clear the DSP inter-

rupts while Bits 8 to 15 can be used to force a corre-

sponding interrupt. Writing to Bits 11 and 12 in IFC is the

only way to create the two software interrupts.

The system controller block of the ADMCF327 per-

forms the following functions:

1. Manages the interface and data transfer between the

DSP core and the motor control peripherals.

2. Handles interrupts generated by the motor control pe-

ripherals and generates a DSP core interrupt signal

IRQ2.

3. Controls the ADC multiplexer select lines.

The ICNTL register is used to configure the sensitivity

(edge or level) of the IRQ0, IRQ1 and IRQ2 interrupts

and to enable/disable interrupt nesting. Setting Bit 0 of

ICNTL configures the IRQ0 as edge-sensitive, while

clearing the bit configures it for level-sensitive. Bit 1 is

used to configure the IRQ1 interrupt. Bit 2 is used to con-

figure the IRQ2 interrupt. It is recommended that the IRQ2

interrupt always be configured as level-sensitive to ensure

that no peripheral interrupts are lost. Setting Bit 4 of the

ICNTL register enables interrupt nesting. The configura-

tion of both the IFC and ICNTL registers is shown at the

end of the data sheet.

4. Enables PWMTRIP and PWMSYNC interrupts.

5. Controls the multiplexing of the SPORT1 pins to

select either DR1A or DR1B data receive pins. It also

allows configuration of SPORT1 as a UART inter-

face.

6. Controls the PWM single/double update mode.

7. Controls the ADC conversion time modes.

8. Controls the auxiliary PWM operation mode.

9. Contains a status register (SYSSTAT) that indicates

the state of the PWMTRIP pin, the watchdog timer

and the PWM timer.

Interrupt Operation

Following a reset, the ROM code on the ADMCF327

must copy a default interrupt vector table into program

memory RAM from address 0x0000 to 0x002F. Since

each interrupt source has a dedicated four-word space in

this vector table, it is possible to code short interrupt ser-

vice routines (ISR) in place. Alternatively, it may be nec-

essary to insert a JUMP instruction to the appropriate start

address of the interrupt service routine if more memory is

required for the ISR.

10. Performs a reset of the motor control peripherals and

control registers following a hardware, software or

watchdog initiated reset.

SPORT1 Control

Both data receive pins are multiplexed internally into the

single data receive input of SPORT1 as shown in Figure

17. Two control bits in the MODECTRL register con-

trol the state of the SPORT1 pins by manipulating in-

ternal multiplexers in the ADMCF327.

When an interrupt occurs, the program sequencer ensures

that there is no latency (beyond synchronization delay)

when processing unmasked interrupts. In the case of the

timer, SPORT1, and software interrupts, the interrupt

controller automatically jumps to the appropriate location

in the interrupt vector table. At this point, a JUMP instruc-

tion to the appropriate ISR is required.

ADMCF327

PIO1/DT1

DT1

DR1

PIO4/DR1A

PIO2/DR1B

PIO0/TFS1

TFS1

RFS1

DSP

CORE

SPORT1

Motor control peripheral interrupts are slightly different.

When a peripheral interrupt is detected, a bit is set in the

IRQFLAG register for PWMSYNC and PWMTRIP or

in the PIOFLAG0, or PIOFLAG1 registers for a PIO

interrupt, and the IRQ2 line is pulled low until all pend-

ing interrupts are acknowledged.

PIO5/RFS1

SCLK1

FL1

PIO3/SCLK1

The DSP software must determine the source of the inter-

rupts by reading IRQFLAG register. If more than one

interrupt occurs simultaneously, the higher priority inter-

rupt service routine is executed. Reading the IRQFLAG

register clears the PWMTRIP and PWMSYNC bits and

acknowledges the interrupt, thus allowing further interrupts

when the ISR exits.

UARTEN

DR1SEL

MODECTRL (5 . . . 4)

Figure 17. Internal Multiplexing of SPORT1 Pins

Bit 4 of the MODECTRL register (DR1SEL) selects be-

tween the two data receive pins. Setting Bit 4 of

MODECTRL connects pin DR1B to the internal data re-

ceive port DR1 of SPORT1. Clearing Bit 4 connects DR1A

to DR1.

A user’s PIO interrupt service routine must read the

PIOFLAG0 and PIOFLAG1 registers to determine

which PIO port is the source of the interrupt. Reading

registers PIOFLAG0 and PIOFLAG1 clears all bits in

the registers and acknowledges the interrupt, thus allow-

ing further interrupts after the ISR exits.

Setting Bit 5 of the MODECTRL register (SPORT1 Mode)

configures the serial port for UART mode. In this mode, the

DR1 and RFS1 pins of the internal serial port are connected

together. Additionally, setting the SPORT1 Mode bit con-

The configuration of all these registers is shown at the

end of the data sheet.

–22–

REV. PrA

Preliminary Technical Data

ADMCF327

nects the FL1 flag of the DSP to the external PIO5/RFS1

pin.

Flag Pins

The ADMCF327 provides flag pins. The alternate con-

figuration of SPORT1 includes a Flag In (FI) and Flag

Out (FO) pin. This alternate configuration of SPORT1

is selected by Bit 10 of the DSP system control register,

SYSCNTL at data memory address, 0x3FFF. In the

alternate configuration, the DR1 pin (either DR1A or

DR1B depending upon the state of the DR1SEL bit) be-

comes the FI pin and the DT1 pin becomes the FO pin.

Additionally, RFS1 is configured as the IRQ0 interrupt

input and TFS1 is configured as the IRQ1 interrupt. The

serial port clock, SCLK1, is still available in the alternate

configuration.

Development Tools

Users are recommended to obtain the ADMCF327-

EVALKIT from Analog Devices. The tool kit contains

everything required to quickly and easily evaluate and

develop applications using the ADMCF327 and

ADMC326 DSP Motor Controllers. Please contact your

ADI sales representative for ordering information.

REV. PrA

–23–

Preliminary Technical Data

ADMCF327

Table X. Peripheral Register Map

BitsUsed

Address

(HEX)

Name

Function

0x2000

0x2001

0x2002

0x2003

0x2004

0x2005

0x2006

0x2007

ADC1

ADC2

ADC3

[15 . . . 4]

[7 . . . 0]

[15 . . . 0]

[9 . . . 0]

[15 . . . 0]

[8 . . . 0]

[7 . . . 0]

ADC Results for V1

ADC Results for V2

ADC Results for I_SENSE

ADC Results for VAUX

PIO0 . . . 7 Pins Direction Setting

PIO0 . . . 7 Pins Input/Output Data

PIO0 . . . 7 Pins Interrupt Enable

PIO0 . . . 7 Pins Interrupt Status

PWM Period

PWM Pulse Deletion Time

PWM Gate Drive Con•guration

PWM Channel A Pulsewidth

PWM Channel B Pulsewidth

PWM Channel C Pulsewidth

PWM Segment Select

AUX PWM Output 0

AUX PWM Output 1

Auxiliary PWM Frequency Value

Auxiliary PWM Frequency Value/Offset

Reserved

ADCAUX

PIODIR0

PIODATA0

PIOINTEN0

PIOFLAG0

PWMTM

PWMPD

PWMGATE

PWMCHA

PWMCHB

PWMCHC

PWMSEG

AUXCH0

AUXCH1

AUXTM0

AUXTM1

0x2008

0x200A

0x200B

0x200C

0x200D

0x200E

0x200F

0x2010

0x2011

0x2012

0x2013

0x2014

0x2015

0x2016

0x2017

0x2018

MODECTRL

SYSSTAT

IRQFLAG

[8 . . . 0]

[3 . . . 0]

[1 . . . 0]

[15 . . . 0]

Mode Control Register

System Status

Interrupt Status

WDTIMER

Watchdog Timer

0x2019 . . . 43

0x2044

0x2045

0x2046

0x2047

Reserved

PIODIR1

[0]

[1 . . . 0]

[0]

PIO8 Pin Direction Setting

PIO8 Data and Mode Control

PIO8 Pin Interrupt Enable

PIO8 Pin Interrupt Status

Reserved

PIODATA1

PIOINTEN1

PIOFLAG1

[0]

0x2048

0x2049

0x204A . . . 5F

PIOSELECT

[7 . . . 0]

PIO0 to PIO7 Mode Select

Reserved

0x2060

0x2061

PWMSYNCWT

PWMSWT

[7 . . . 0]

[0]

PWMSYNC Pulsewidth

PWM S/W Trip Bit

0x2062 . . . 67

0x2068

Reserved

ICONST_TRIM

[2. . .0]

0x2069 . . . 70

0x2080

0x2081

0x2082

0x2083

Reserved

FMCR

FMAR

FMDRH

FMDRL

[15. . .0]

[11. . .0]

[13. . .0]

[15. . .0]

Flash Memory Control Register

Flash Memory Address Register

Flash Memory Data Register High

Flash Memory Data Register Low

Reserved

0x2084 . . . FF

Table XI. DSP Core Registers

Bits

Address

Name

Function

0x3FFF

0x3FFE

0x3FFD

0x3FFC

0x3FFB

0x3FFA . . . F3

0x3FF2

0x3FF1

0x3FF0

0x3FEF

SYSCNTL

MEMWAIT

TPERIOD

TCOUNT

TSCALE

[15 . . . 0]

[7 . . . 0]

System Control Register

Memory Wait State Control Register

Interval Timer Period Register

Interval Timer Count Register

Interval Timer Scale Register

Reserved

SPORT1_CTRL_REG

SPORT1_SCLKDIV

SPORT1_RFSDIV

[15 . . . 0]

SPORT1 Control Register

SPORT1 Clock Divide Register

SPORT1 Receive Frame Sync Divide

SPORT1 Autobuffer Control Register

SPORT1_AUTOBUF_CTRL

–24–

REV. PrA

Preliminary Technical Data

ADMCF327

FLASH MEMORY CONTROL REGISTER

15

1

14

0

13

0

12

0

11

0

10

9

8

7

6

5

4

3

2

0

1

0

0x2080

BO O T ›F RO M ›F L A S H›C O DE

FLASH MEMORY ADDRESS REGISTER

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0x2081

ADDRESS 11›0

RESERVED

ALWAYS READ 0

FLASH MEMORY DATA REGISTER LOW (FMDRL)

15

0

14

0

13

0

12

11

10

9

8

7

6

5

4

3

2

1

0

0x2083

0

STATUS 5›0

DAT A 7›0

RESERVED

ALWAYS READ 0

FLASH MEMORY DATA REGISTER HIGH (FMDRH)

15

0

14

0

13

0

12

11

10

9

8

7

6

5

4

3

2

1

0

0x2082

0

DA T A 23›8

MOST SIGNIFICANT BIT IS ON THE LEFT. FOR EXAMPLE, DATA23 IS BIT 15 OF FMDRH.

Figure 18. Configuration of Flash Memory Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a

gray field—these bits should always be written as shown.

REV. PrA

–25–

Preliminary Technical Data

ADMCF327

PWMTM (R/W)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DM (0x2008)

PWMTM

f_CLKOUT

f_{PW M}

=

2 ꢀ PWMTM

PWMDT (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

0

6

0

5

0

4

3

2

1

0

PWMDT › DO NOT WRITE

TO THIS REGISTER

PWMSEG (R/W)

15

0

14

0

13

12

11 10

9

8

7

6

5

0

4

3

0

2

1

0

DM (0x200F)

0

A CHANNEL CROSSOVER

B CHANNEL CROSSOVER

CH OUTPUT DISABLE

CL OUTPUT DISABLE

BH OUTPUT DISABLE

0 = NO CROSSOVER

1 = CROSSOVER

C CHANNEL CROSSOVER

0 = ENABLE

1 = DISABLE

BL OUTPUT DISABLE

AH OUTPUT DISABLE

AL OUTPUT DISABLE

PWMSYNCWT (R/W)

1

15

14

0

13

0

12

11

10

9

8

7

0

6

0

5

1

4

3

2

0

1

0

1

DM (0x2060)

PWMSYNCWT

PWMSYNCWT + 1

f_CLKOUT

T

=

PWMSYNC, ON

PWMSWT (R/W)

0

15

0

14 13

12

0

11

0

10

0

9

8

7

0

6

0

5

0

4

3

2

1

0

DM (0x2061)

Figure 19. Configuration of PWM Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray

field—these bits should always be written as shown.

–26–

REV. PrA

Preliminary Technical Data

ADMCF327

PWMPD (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x200A)

PWMPD

f_CLKOUT

=

T

SECONDS

MIN

PWMGATE (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

2

0

1

0

DM (0x200B)

GDCLK

0

GATE DRIVE CHOPPING FREQUENCY

LOW SIDE GATE CHOPPING

HIGH SIDE GATE CHOPPING

f_CLKOUT

0 = DISABLE

1 = ENABLE

=

f_CHOP

4

(GDCLK + 1)

ꢀ

PWMCHA (R/W)

15

14

13

12

11 10

9

8

7

6

5

4

3

2

1

0

DM (0x200C)

PWM CHANNEL A

DUTY CYCLE

PWMCHB (R/W)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DM (0x200D)

PWM CHANNEL B

DUTY CYCLE

PWMCHC (R/W)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DM (0x200E)

PWM CHANNEL C

DUTY CYCLE

Figure 20. Configuration of Additional PWM Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray

field—these bits should always be written as shown.

REV. PrA

–27–

Preliminary Technical Data

ADMCF327

PIODIR0 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2004)

0

0 = INPUT

1 = OUTPUT

PIO0 › PIO7

PIODIR1 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2044)

0

0 = INPUT

1 = OUTPUT

PIO8

PIODATA0 (R/W)

15

14

13

12

0

11

0

10

0

9

8

7

6

5

4

3

2

1

0

DM (0x2005)

0 = LOW LEVEL

1 = HIGH LEVEL

PIO0 › PIO7

PIODATA1 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

6

0

5

4

3

2

0

1

0

DM (0x2045)

PIO8 DATA

0

0 = LO

1 = HI

0 = AUX0

1 = PIO8

PIO8/AUX0 MODE

PIOSELECT (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

6

5

4

1

3

2

1

0

1

0

1

DM (0x2049)

0 = TFS1

1 = PIO0

0 = AUX1

1 = PIO7

0 = DT1

1 = PIO1

0 = CLKOUT

1 = PIO6

0 = RFS1

1 = PIO5

0 = DR1B

1 = PIO2

0 = SCLK1

1 = PIO3

0 = DR1A

1 = PIO4

Figure 21. Configuration of PIO Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray

field—these bits should always be written as shown.

–28–

REV. PrA

Preliminary Technical Data

ADMCF327

PIOINTEN0 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

4

0

3

0

2

0

1

0

DM (0x2006)

0 = INTERRUPT DISABLE

1 = INTERRUPT ENABLE

PIO0 › PIO7

PIOINTEN1 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2046)

0 = INTERRUPT DISABLE

1 = INTERRUPT ENABLE

PIO8

PIOFLAG0 (R)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2007)

0

0 = NO INTERRUPT

1 = INTERRUPT FLAGGED

PIO0 › PIO7

PIOFLAG1 (R)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

0

6

0

5

0

4

3

0

2

0

1

0

DM (0x2047)

0 = NO INTERRUPT

1 = INTERRUPT FLAGGED

PIO8

Figure 22. Configuration of Additional PIO Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray

field—these bits should always be written as shown.

REV. PrA

–29–

Preliminary Technical Data

ADMCF327

AUXCH0 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2010)

0

T

= 2 ꢀ (AUXCH0) ꢀ t_CK

ON, AUX0

AUXCH1 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2011)

T

= 2 ꢀ (AUXCH1) ꢀ t_CK

ON, AUX1

AUXTM0 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

1

5

1

4

1

3

1

2

1

0

1

0

1

DM (0x2012)

AUX0 PERIOD = 2 ꢀ (AUXTM0 + 1) ꢀ t_CK

AUXTM1 (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

1

5

1

4

1

3

1

2

1

0

1

0

1

DM (0x2013)

AUX1 PERIOD = 2 ꢀ (1 + AUXTM1) ꢀ t_CK

OFFSET = 2 ꢀ (1 + AUXTM1) ꢀ t_CK

Figure 23. Configuration of AUX Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray

field—these bits should always be written as shown.

–30–

REV. PrA

Preliminary Technical Data

ADMCF327

ADC1 (R)

15

14

13

12

11 10

9

8

7

6

5

4

3

0

2

0

1

0

DM (0x2000)

ADC2 (R)

15

14

13

12

11

10

9

8

7

6

5

4

3

0

2

0

1

0

DM (0x2001)

ADC3 (R)

15

14

13

12

11

10

9

8

7

6

5

4

3

0

2

0

1

0

DM (0x2002)

ADCAUX (R)

15

14

13

12

11

10

9

8

7

6

5

4

3

0

2

0

1

0

DM (0x2003)

ICONST_TRIM (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

6

5

0

4

0

3

0

2

0

1

0

DM (0x2068)

ICONST MIN = BITS 0 › 2 CLEARED.

ICONST MAX = BITS 0 › 2 SET.

Figure 24. Configuration of Additional AUX Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray

field—these bits should always be written as shown.

REV. PrA

–31–

Preliminary Technical Data

ADMCF327

M O DECT RL (R/W )

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

6

5

0

4

3

0

2

0

1

0

DM (0x2015)

0

=

O FFSET M O DE

AU XILIARY

PW M SE LECT

ADC M U X CO N TRO L

00 VAU X0

1

=

INDEP EN DE N T MO DE

01 VAU X1

10 VAU X2

11 VAU X3

ADC

CO U N T ER

SELE CT

0

=

= CLKIN RAT E

CLKO U T RATE

1

PW M T RIP

IN T ERRUPT

0 = DISABLE

1 = ENABLE

PW M SYN C

IN T ERRUPT

0

1

=

DISABLE

EN ABLE

SPO RT 1 DATA

RECEIVE SELE CT

0

1

=

DR1A

DR1B

SPO RT 1 M O DE

SELE CT

0

1

=

SPO RT

U ART

0

1

=

SIN GLE U PDATE M O DE

DO U BLE U PDATE M O DE

PW M UPDAT E

M O DE SELE CT

SYSSTAT

(R)

15

0

14

0

13

0

12

0

11

0

10

9

8

7

6

0

5

0

4

3

2

1

0

DM (0x2016)

PW M T RIP

0

1

=

LO W

HIG H

PIN STATU S

0

1

=

1ST HALF O F P W M

CYCLE

2N D HA LF O F P W M

CYCLE

0

1

=

N O RM AL

W AT CHDO G RESET

O CCU RRE D

PW M TIM ER

STAT U S

W ATCHDO G

STAT U S

IRQ FLAG (R)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2017)

0

PW M T RIP IN T ERRUPT

PW M SYN C IN TERRU P T

0

1

=

N O IN T ERRU PT

INTE RRU PT

O CCU RRED

W DTIM ER (W )

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2018)

Figure 25. Configuration of Status Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray

field—these bits should always be written as shown.

–32–

REV. PrA

Preliminary Technical Data

ADMCF327

ICNTL

2

4

0

3

0

1

0

1

0

DSP REGISTER

0 = DISABLE

1 = ENABLE

INTERRUPT NESTING

IRQ 0 SENSITIVITY

IRQ 1 SENSITIVITY

IRQ 2 SENSITIVITY

0 = LEVEL

1 = EDGE

IFC

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DSP REGISTER

0

INTERRUPT FORCE

INTERRUPT CLEAR

IRQ 2

TIMER

SPORT1 RECEIVE OR IRQ 0

SPORT1 TRANSMIT OR IRQ 1

SOFTWARE 0

SOFTWARE 1

SOFTWARE 0

SPORT1 TRANSMIT OR IRQ 1

SPORT1 RECEIVE OR IRQ 0

IRQ 2

TIMER

IMASK (R/W)

15

0

14

0

13

0

12

11

10

9

0

8

7

6

5

0

4

3

0

2

1

0

DSP REGISTER

TIMER

PERIPHERAL (OR IRQ 2)

SPORT1 RECEIVE

(OR IRQ 0)

0 = DISABLE

(MASK)

1 = ENABLE

0 = DISABLE

(MASK)

1 = ENABLE

SPORT1 TRANSMIT

(OR IRQ 1)

SOFTWARE 1

SOFTWARE 0

Figure 26. Configuration of Interrupt Control Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray

field—these bits should always be written as shown.

REV. PrA

–33–

Preliminary Technical Data

ADMCF327

SYSCNTL (R/W)

15

0

14

0

13

0

12

0

11

0

10

1

9

8

7

6

0

5

1

4

1

3

1

2

1

0

1

DM (0x3FFF)

0

0 = FI, FO, IRQ0, IRQ1, SCLK

1 = SERIAL PORT

SPORT1 CONFIGURE

0 = DISABLED

1 = ENABLED

SPORT1 ENABLE

MEMWAIT (R/W)

15

1

14

1

13

1

12

1

11

1

10

1

9

1

8

1

7

1

6

1

5

1

4

1

3

1

2

1

0

1

DM (0x3FFE)

1

Figure 27. Configuration of Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray

field—these bits should always be written as shown.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead Wide-Body SOIC

(R-28)

0.7125 (18.10)

0.6969 (17.70)

28

15

1

14

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

0.0098 (0.25)

x 45ꢂ

0.0500 (1.27)

0.0157 (0.40)

8ꢂ

0ꢂ

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0118 (0.30)

0.0040 (0.10)

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

28-Lead PDIP

(N-28)

1.565 (39.70)

1.380 (35.10)

28

15

0.580 (14.73)

0.485 (12.32)

1

14

PIN 1

0.060 (1.52)

0.015 (0.38)

0.625 (15.87)

0.600 (15.24)

0.250

(6.35)

MAX

0.195 (4.95)

0.125 (3.18)

0.150

(3.81)

MIN

0.015 (0.381)

0.008 (0.204)

0.200 (5.05)

0.125 (3.18)

0.100

(2.54)

BSC

0.070

(1.77)

MAX

0.022 (0.558)

0.014 (0.356)

SEATING

PLANE

–34–

REV. PrA


型号：	ADMCF327BN
厂家：	ADI
描述：	IC 0-BIT, 10 MHz, OTHER DSP, PDIP28, PLASTIC, DIP-28, Digital Signal Processor 时钟光电二极管外围集成电路
文件：	总34页 (文件大小：354K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADMCF327BN [ADI]

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