AS4C1M16F5-60TI [ETC]
5V 1M X 16 CMOS DRAM; 5V 1M ×16的CMOS DRAM
| 型号： | AS4C1M16F5-60TI |
| 厂家： | 
ETC |
| 描述： | 5V 1M X 16 CMOS DRAM |
| 文件： | 总21页 (文件大小：475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS4C1M16F5
®
5V 1M×16 CMOS DRAM (fast-page mode)
Features
• 1024 refresh cycles, 16 ms refresh interval
RAS-only or CAS-before-RAS refresh
• Organization: 1,048,576 words × 16 bits
• High speed
-
• Read-modify-write
- 50/60 ns RAS access time
- 20/25 ns fast page cycle time
- 13/17 ns CAS access time
• Low power consumption
• TTL-compatible, three-state DQ
• JEDEC standard package and pinout
- 400 mil, 42-pin SOJ
- 400 mil, 44/50-pin TSOP II
• 5V power supply
• Industrial and commercial temperature available
- Active:
880 mW max (AS4C1M16E0-60)
- Standby: 11 mW max, CMOS DQ
• Fast page mode
Pin arrangement
Pin designation
TSOP II
50
Pin(s)
A0 to A9
RAS
Description
SOJ
VCC
VSS
1
Address inputs
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS
DQ1
DQ2
DQ3
49
48
47
46
45
44
43
42
41
40
DQ16
DQ15
DQ14
DQ13
VSS
DQ12
DQ11
DQ10
DQ9
2
2
DQ16
DQ15
DQ14
DQ13
VSS
3
3
Row address strobe
Input/output
4
4
DQ4
5
5
DQ1 to DQ16
OE
VCC
6
6
DQ5
7
DQ12
DQ11
DQ10
DQ9
NC
7
Output enable
8
DQ6
DQ7
DQ8
8
9
9
WE
Write enable
10
11
12
13
14
15
16
17
18
19
20
21
10
11
NC
NC
NC
WE
LCAS
UCAS
OE
UCAS
LCAS
Column address strobe, upper byte
Column address strobe, lower byte
Power
RAS
NC
A9
NC
A8
NC
NC
WE
RAS
NC
NC
A0
36
35
34
33
32
31
30
29
NC
LCAS
UCAS
OE
15
16
17
18
19
20
21
22
VCC
A0
A7
A1
A6
VSS
Ground
A2
A5
A3
A4
A9
Vcc
VSS
A8
A7
A1
A6
A2
23
24
25
A5
28
27
26
A3
A4
VCC
VSS
Selection guide
Symbol
tRAC
tAA
AS4C1M16F5-50
50
AS4C1M16F5-60
Unit
Maximum RAS access time
60
30
ns
ns
Maximum column address access time
Maximum CAS access time
25
13
tCAC
tOEA
tRC
17
ns
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum fast page mode cycle time
Maximum operating current
13
15
ns
84
104
25
ns
tPC
20
ns
ICC1
ICC5
170
2.0
160
2.0
mA
mA
Maximum CMOS standby current
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Copyright © Alliance Semiconductor. All rights reserved.
AS4C1M16F5
®
Functional description
The AS4C1M16F5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as
1,048,576 words × 16 bits. The AS4C1M16F5 is fabricated using advanced CMOS technology and innovative design
techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The
Alliance 16Mb DRAM family is optimized for use as main memory in personal and portable PCs, workstations, and multimedia
and router switch applications.
The AS4C1M16F5 features high speed page mode operation where read and write operations within a single row (or page)
can be executed at very high speed (15 ns from XCAS)by toggling column addresses within that row. Row and column
addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs respectively. Also, RAS is used
to make the column address latch transparent, enabling application of column addresses prior to xCAS assertion. The
AS4C1M16F5 provides dual UCAS and LCAS for independent byte control of read and write access.
Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:
•
RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data.
•
CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
The AS4C1M16F5 is available in the standard 42-pin plastic SOJ and the 44/50-pin TSOP II packages, respectively. It operates
with a single power supply of 5V 0.5V. The device provides TTL compatible inputs and outputs.
Logic block diagram
Data
DQ
buffers
VCC
Column decoder
Sense amp
DQ1 to DQ16
GND
RAS clock
generator
RAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
OE
1024 × 1024 × 16
Array
CAS clock
generator
UCAS
LCAS
(16,777,216)
Substrate bias
generator
WE clock
generator
WE
Recommended operating conditions
Parameter
Symbol
VCC
Min
4.5
0.0
2.4
–0.5†
0
Nominal
Max
5.5
0.0
VCC
0.8
70
Unit
V
AS4C1M16F5
5.0
0.0
–
Supply voltage
Input voltage
GND
VIH
V
AS4C1M16F5
V
VIL
–
V
Commercial
Industrial
–
Ambient operating temperature
TA
°C
-40
–
85
†
V
min -3.0V for pulse widths less than 5 ns.
IL
Recommended operating conditions apply throughout this document unlesss otherwise specified.
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Absolute maximum ratings
Parameter
Symbol
Vin
Min
-1.0
-1.0
-1.0
-55
–
Max
Unit
Input voltage
+7.0
VCC + 0.5
+7.0
+150
260 × 10
1
V
Input voltage (DQs)
VDQ
V
Power supply voltage
Storage temperature (plastic)
Soldering temperature × time
Power dissipation
VCC
V
TSTG
TSOLDER
PD
°C
oC × sec
–
W
Short circuit output current
Iout
–
50
mA
DC electrical characteristics
-50
-60
Parameter
Symbol Test conditions
0V ≤ Vin ≤ +5.5V,
Pins not under test = 0V
DOUT disabled, 0V ≤ Vout ≤ +5.5V
LCAS, Address cycling;
Min Max Min Max Unit Notes
Input leakage current
IIL
-5
-5
–
+5
+5
-5
-5
–
+5
+5
µA
µA
Output leakage current IOL
Operating power
ICC1
RAS, UCAS,
170
160 mA
2.5 mA
1,2
supply current
tRC=min
TTL standby power
ICC2
RAS
=
UCAS
=
LCAS ≥ VIH
–
–
2.5
–
–
supply current
Average power supply
current, RAS refresh mode ICC3
or CBR
RAS cycling, UCAS
= LCAS ≥ VIH,
170
160 mA
110 mA
1
tRC = min of RAS low after XCAS low.
Fast page mode average
ICC4
RAS = VIL, UCAS or LCAS,
address cycling: tPC = min
–
–
120
2.0
–
–
1, 2
power supply current
CMOS standby power
ICC5
RAS
=
UCAS
=
LCAS = VCC - 0.2V
2.0
mA
supply current
VOH
IOUT = -5.0 mA
IOUT = 4.2 mA
2.4
–
–
2.4
–
–
V
V
Output voltage
VOL
0.4
0.4
CAS before RAS refresh
current
RAS
,
UCAS or LCAS cycling, tRC = min
–
170
–
160 mA
ICC6
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AC parameters common to all waveforms
-50
-60
Symbol
tRC
Parameter
Min
84
30
50
8
Max
–
Min
104
40
60
10
15
12
10
50
5
Max
–
Unit Notes
Random read or write cycle time
RAS precharge time
ns
ns
ns
ns
tRP
–
–
tRAS
tCAS
tRCD
tRAD
tRSH
tCSH
tCRP
tASR
tRAH
tT
RAS pulse width
10K
10K
35
25
–
10K
10K
43
30
–
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS hold time
15
12
10
40
5
ns
ns
ns
ns
ns
ns
ns
6
7
RAS to CAS hold time
–
–
CAS to RAS precharge time
Row address setup time
Row address hold time
Transition time (rise and fall)
Refresh period
–
–
0
–
0
–
8
–
10
1
–
1
50
16
–
50
16
–
ns 4,5
tREF
tCP
–
–
ms
ns
ns
ns
ns
3
CAS precharge time
8
10
30
0
tRAL
tASC
tCAH
Column address to RAS lead time
Column address setup time
Column address hold time
25
0
–
–
–
–
8
10
–
Read cycle
-50
-60
Symbol
tRAC
Parameter
Min
–
Max
50
13
25
–
Min
–
Max
60
17
30
–
Unit Notes
ns
Access time from RAS
6
tCAC
Access time from CAS
–
–
ns 6,13
ns 7,13
ns
tAA
Access time from address
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
–
–
tRCS
0
0
tRCH
0
–
0
–
ns
ns
9
9
0
–
0
–
tRRH
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Write cycle
-50
-60
Symbol
tWCS
tWCH
tWP
Parameter
Min
Max
–
Min
0
Max
–
Unit Notes
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
0
10
10
10
8
ns
ns
ns
ns
ns
ns
ns
11
11
–
10
10
10
10
0
–
–
–
tRWL
tCWL
tDS
–
–
–
–
0
–
–
12
12
tDH
Data-in hold time
8
–
10
–
Read-modify-write cycle
-50
-60
Symbol
tRWC
Parameter
Min
113
67
Max
–
Min
135
77
Max
–
Unit Notes
ns
Read-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
tRWD
–
–
ns
ns
ns
11
11
11
tCWD
tAWD
32
–
35
–
42
–
47
–
Refresh cycle
-50
-60
Symbol
tCSR
Parameter
CAS setup time (CAS-before-RAS
Min
Max
Min
Max
–
Unit Notes
)
5
8
0
–
–
–
5
10
0
ns
ns
ns
3
3
tCHR
CAS hold time (CAS-before-RAS)
RAS precharge to CAS hold time
–
tRPC
–
CAS precharge time
(CBR counter test)
tCPT
10
10
–
ns
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®
Fast page mode cycle
-50
-60
Symbol
tCPA
Parameter
Min
–
Max
Min
–
Max
Unit Notes
Access time from CAS precharge
RAS pulse width
28
35
ns
ns
ns
ns
ns
ns
13
tRASP
tPC
50
30
10
80
54
100K
60
35
10
85
60
100K
Read-write cycle time
–
–
–
–
–
–
–
–
tCP
CAS precharge time (fast page)
Fast page mode RMW cycle
Page mode CAS pulse width (RMW)
tPCM
tCRW
Output enable
-50
-60
Symbol
tCLZ
Parameter
Min
0
Max
–
Min
0
Max
–
Unit Notes
CAS to output in Low Z
RAS hold time referenced to OE
OE access time
ns
ns
ns
ns
ns
ns
ns
ns
8
tROH
tOEA
tOED
tOEZ
8
–
10
–
–
–
13
–
15
–
OE to data delay
13
0
15
0
Output buffer turnoff delay from OE
OE command hold time
OE to output in Low Z
Output buffer turn-off time
13
–
15
–
8
tOEH
tOLZ
10
0
10
0
–
–
tOFF
0
13
0
15
8,10
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Notes
1
2
3
I
, I , and I
are dependent on frequency.
CC1 CC3
CC4
I
and I
depend on output loading. Specified values are obtained with the output open.
CC1
CC4
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4
AC Characteristics assume t = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V (min) ≥ GND and V
IH
T
IL
(max) ≤ V
.
CC
5
6
V
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .
IH
IL
IH
IL
Operation within the t
(max) limit insures that t
(max) can be met. t
(max) is specified as a reference point only. If t
is greater than the
RCD
RAC
RCD
RCD
specified t
(max) limit, then access time is controlled exclusively by t
.
CAC
RCD
7
Operation within the t
(max) limit insures that t
(max) can be met. t (max) is specified as a reference point only. If t
RAD
is greater than the
RAD
RAC
RAD
specified t
(max) limit, then access time is controlled exclusively by t .
AA
RAD
8
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either t or t must be satisfied for a read cycle.
9
RCH
RRH
10
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
is referenced from
OFF
OFF
rising edge of RAS or CAS, whichever occurs last.
t , t , t , t and t are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
WCS WCH RWD CWD
11
AWD
If tWS ≥ t (min) and tWH ≥ t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
WS
WH
cycle. If tRWD ≥ t
(min), t
≥ t
(min) and tAWD ≥ t
(min), the cycle is a read-write cycle and the data out will contain data read from the
RWD
CWD
CWD
AWD
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t or t or t
CAA
CAC
CPA
14
tASC ≥ t to achieve t (min) and t (max) values.
CP PC CPA
15 These parameters are sampled and not 100% tested.
16 These characteristics apply to AS4C1M16F5 5V devices.
AC test conditions
- Access times are measured with output reference levels
of VOH = 2.4V and VOL = 0.4V,
+5V
V
IH = 2.4V and VIL = 0.8V
R1 = 828Ω
- Input rise and fall times: 2 ns
Dout
100 pF*
R2 = 295Ω
*including scope
and jig capacitance
GND
Figure A: Equivalent output load
Falling input
Key to switching waveforms
Rising input
Undefined output/don’t care
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Read waveform
tRC
tRAS
tRCD
tRSH
tRP
RAS
tCSH
tRCS
tCAH
tCAS
tCRP
tASC
UCAS,
LCAS
tRAD
tRAL
tRAH
tASR
Row address
Address
Column address
tRRH
tRCH
tWEZ
WE
OE
tROH
tROH
tOEZ
tRAC
tAA
tOFF (see note 11)
tOEA
tCAC
tREZ
tCLZ
Data out
DQ
tOLZ
Upper byte read waveform
tRC
tRAS
tRP
RAS
tRCD
tRSH
tCSH
tCRP
tCRP
tCAS
UCAS
tRPC
tCRP
LCAS
tRAH
tRAD
tRAL
tASC
tASR
tCAH
Row
Column
Address
tRCH
tRRH
tRCS
WE
OE
tROH
tWEZ
tOEA
tREZ
tOLZ
tRAC
tOEZ
tAA
tCAC
tCLZ
tOFF
Upper DQ
Lower DQ
Data out
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Lower byte read waveform
tRC
tRAS
tRP
RAS
tRCD
tRSH
tCSH
tCRP
tCRP
tCAS
LCAS
tCRP
tRPC
UCAS
tRAH
tRAD
tASC
tRAL
tASR
tCAH
Row
Column
Address
WE
tRCH
tRRH
tRCS
tROH
tWEZ
OE
Upper DQ
tREZ
tOEA
tOLZ
tRAC
tOEZ
tAA
tCAC
tOFF
tCLZ
Data out
Lower DQ
Early write waveform
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
UCAS
,
tRAD
tRAL
LCAS
tASC
tASR
tRAH
tCAH
Row address
Column address
Address
tCWL
tRW L
tWP
tWCS
tWCH
WE
OE
tDH
Data in
tDS
DQ
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Upper byte early write waveform
tRC
tRAS
tRP
RAS
tASR
tRAD
tRAL
tRAH
Row address
Column address
Address
tCAH
tRSH
tASC
tRCD
tCSH
tCAS
tCRP
tCRP
UCAS
tCRP
tRPC
LCAS
tCWL
tWCH
tRWL
tWCS
tWP
WE
OE
tDS
tDH
Data in
Upper DQ
Lower DQ
Lower byte early write waveform
tRC
tRAS
tRP
RAS
tRAD
tRAL
tASR
Row address
tCRP
tRAH
Address
UCAS
Column address
tRPC
tASC
tCAH
tRCD
tCAS
tCSH
tRSH
tCRP
tCRP
LCAS
tRWL
tCWL
tWCH
tWP
tWCS
WE
OE
Upper DQ
tDS
tDH
Data in
Lower DQ
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Write waveform
OE controlled
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
tRAL
UCAS,
LCAS
tRAD
tRAH
tASC
tASR
Row address
tCAH
Column address
Address
tRWL
tCWL
tWP
WE
OE
tOEH
tDS
tOED
tDH
Data in
DQ
Upper byte write waveform
OE controlled
tRC
tRAS
tRP
RAS
tRAD
tRAH
tRAL
tASR
Row address
Column address
tCSH
Address
tRCD
tASC
tRSH
tCAH
tCRP
tCAS
tCRP
UCAS
LCAS
tCRP
tRPC
tCWL
tRWL
tWP
WE
OE
tOEH
tDS
tDH
Upper DQ
Lower DQ
Data in
tOED
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Lower byte write waveform
OE controlled
tRC
tRAS
tRP
RAS
tRAD
tASR
tRAL
tRAH
Address
Row address
Column address
tCAH
tCAS
tRCD
tCSH
tCRP
tACS
tRSH
tCRP
LCAS
tCRP
tRPC
UCAS
tCWL
tRWL
tWP
WE
tOEH
OE
Upper DQ
tDH
tDS
Data in
Lower DQ
Read-modify-write waveform
tRWC
tRAS
tRP
RAS
tCAS
tRSH
tCRP
tRCD
tCSH
UCAS,
LCAS
tAR
tRAL
tRAD
tRAH
tASC
tCAH
tASR
Row address
Column address
tRWD
Address
tRWL
tAWD
tCWL
tWP
tRCS
tCWD
WE
OE
tOEA
tOED
tOEZ
tRAC
tAA
tCAC
tCLZ
tDS
tDH
Data out
Data in
DQ
tOLZ
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Upper byte read-modify-write waveform
tRWC
tRAS
tCSH
tRP
RAS
tRCD
tCAS
tRSH
tCRP
tRPC
tCRP
UCAS
tCRP
LCAS
tRAD
tACS
tASR
tRAL
tCAH
tRAH
Column address
tRWD
Address
Row
tCWL
tRWL
tWP
tAWD
tCWD
tOEA
tRCS
WE
OE
tDH
tDS
tOED
tOLZ
Upper input
tCLZ
tCAC
tAA
Data in
tOEZ
tRAC
Upper output
Data out
tOED
Lower input
Lower output
Lower byte read-modify-write waveform
tRWC
tRAS
tRP
tRPC
RAS
tCRP
UCAS
tCSH
tCAS
tRSH
tRCD
tCRP
tCRP
LCAS
tRAD
tRAL
tASR
tACS
tCAH
tRAH
Row
Column address
tRWD
Address
tCWL
tRWL
tWP
tAWD
tRCS
tCWD
tOEA
WE
OE
tOED
tOLZ
Upper input
Upper output
tDH
tDS
tOED
Lower input
tRAC
Data in
tAA
tCAC
tCLZ
tOEZ
Data out
Lower output
4/11/01; v.0.9.1
Alliance Semiconductor
P. 13 of 21
AS4C1M16F5
®
Fast page mode read waveform
tRASP
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
tCP
tPC
CAS
tAR
tRAD
tRAL
tCAH
Column
tASC
tASR
tRAH
Row
Column
Column
tRCS
Address
tRRH
tRCS
tRCH
tRCH
tOEA
WE
OE
tOEA
tRAC
tOEZ
tOFF
tCLZ
tCAP
tAA
Data out
tCAC
Data out
Data out
I/O
Fast page mode byte write waveform
tRASP
tRP
RAS
tPCM
tCAS
tCSH
tRCD
tRAD
tCP
tCRP
CAS
tRAL
tCAH
tASR
tRAH
tCAH
tCAH
Row
Column
tRWD
Column
tCWL
Column
Address
tRWL
tCWL
tWP
tRCS
tCWD
tAWD
tCWD
tCWD
tAWD
WE
OE
tOEA
tOEZ
tOED
tOEA
tAA
tDH
tRAC
tCAP
tCLZ
tCAC
tDS
tDS
tCLZ
tCAC
tCLZ
tCAC
Data in
Data in
Data out
Data in
I/O
Data out
Data out
4/11/01; v.0.9.1
Alliance Semiconductor
P. 14 of 21
AS4C1M16F5
®
Fast page mode early write waveform
tRASP
tRAH
tRWL
RAS
tCRP
tRCD
tPC
tCAH
tCSH
tASC
tCAS
tCP
tRSH
tWCS
CAS
tRAL
tAR
tASR
tRAD
Address
Row
Column
Column
Column
tCWL
tWP
tWCH
tOEH
WE
OE
tHDR
tOED
tDH
tDS
I/O
Data In
Data in
Data in
CAS before RAS refresh waveform
WE = VIH
tRC
tRP
tRAS
RAS
tRPC
tCHR
tCP
tCSR
UCAS,
LCAS
OPEN
DQ
RAS only refresh waveform
WE
=
OE = VIH or VIL
tRC
tRAS
tRP
RAS
tCRP
tRPC
UCAS,
LCAS
tASR
tRAH
Address
Row address
4/11/01; v.0.9.1
Alliance Semiconductor
P. 15 of 21
AS4C1M16F5
®
Hidden refresh waveform (read)
tRC
tRC
tRAS
tRP
tRAS
tRP
RAS
tCRP
tCHR
tRCD
tRSH
tCRP
CAS
tAR
tRAD
tCAH
tRAH
tASC
Col address
tASR
Row
Address
tRCS
tRRH
WE
OE
tOEA
tRAC
tOFF
tAA
tCAC
tCLZ
tOEZ
Data out
DQ
Hidden refresh waveform (write)
tRC
tRAS
tRP
RAS
tCHR
tCRP
tRCD
tRSH
UCAS,
LCAS
tAR
tRAD
tRAH
tRAL
tASR
tASC
tCAH
Row address
Col address
Address
tRWL
tWCR
tWP
tWCS
tWCH
WE
tDS
tDH
tDHR
Data in
DQ
OE
4/11/01; v.0.9.1
Alliance Semiconductor
P. 16 of 21
AS4C1M16F5
®
CAS before RAS refresh counter test waveform
tRAS
tRSH
tRP
RAS
tCSR
tCPT
tCAS
tCHR
UCAS,
LCAS
tRAL
tASC
tCAH
Address
Col address
tAA
tCAC
tCLZ
tOFF
tOEZ
DQ
WE
OE
Data out
tRRH
tRCH
tRCS
tROH
tOEA
tRWL
tCWL
tWP
tWCH
tWCS
WE
tDH
tDS
DQ
OE
Data in
tRW L
tWP
tRCS
tCWD
tAWD
tCWL
WE
OE
tOEA
tOED
t AA
tDH
tCLZ
tCAC
tOEZ
tDS
Data in
DQ
Data out
4/11/01; v.0.9.1
Alliance Semiconductor
P. 17 of 21
AS4C1M16F5
®
Package dimensions
42-pin SOJ
400 mil
Min Max
0.128 0.148
D
e
A
A1
A2
B
b
c
D
E
E1
E2
e
c
0.025
-
SOJ
E1 E2
0.105 0.115
0.026 0.032
0.015 0.020
0.007 0.013
1.070 1.080
0.370 NOM
0.395 0.405
0.435 0.445
0.050 NOM
Pin 1
E
B
A2
A
A1
Seating
Plane
b
c
50 49 48 47 46 45 44 43 42 41 40
36 35 34 33 32 31 30 29 28 27 26
50-pin TSOP II
Min
Max
(mm)
(mm)
A
A1
A2
b
1.2
TSOP II
He
E
0.05
0.95
1.05
0.45
0.30
c
0.12
0.21
1
2
3
4
5
6
7
8
9
10 11
15 16 17 18 19 20 21 22 23 24 25
d
20.85
10.03
11.56
21.05
10.29
11.96
E
d
He
e
l
0.80 (typical)
0.40 0.60
l
A2
A
0–5°
A1
b
e
4/11/01; v.0.9.1
Alliance Semiconductor
P. 18 of 21
AS4C1M16F5
®
Typical DC and AC characteristics
Normalized access time tRAC
Normalized access time tRAC
Typical access time tRAC
vs. load capacitance CL
vs. supply voltage VCC
1.5
vs. ambient temperature T
a
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
100
90
80
70
60
50
40
30
1.4
Ta = 25°C
1.3
-70
1.2
1.1
1.0
0.9
0.8
-60
-50
4.0
4.5
5.0
5.5
–55
–10
35
80
50
100
150
200 250
6.0
125
Supply voltage (V)
Ambient temperature (°C)
Load capacitance (pF)
Typical supply current ICC
vs. supply voltage VCC
Typical supply current ICC
Typical power-on current IPO
vs. cycle rate 1/tRC
vs. ambient temperature T
a
170
160
150
140
130
120
110
100
170
160
150
140
130
120
110
100
35
30
25
20
15
10
5
-50
-60
-50
-60
0.0
4.0
4.5
5.0
5.5
–55
–10
35
80
2
4
6
8
6.0
125
10
Supply voltage (V)
Ambient temperature (°C)
Cycle rate (MHz)
Typical refresh current ICC3
vs. supply voltage VCC
Typical refresh current ICC3
vs. Ambient temperature Ta
Typical TTL stand-by current ICC2
vs. supply voltage VCC
160
140
120
100
80
160
140
120
100
80
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-50
-60
-50
-60
60
60
40
40
20
4.0
20
0.0
4.5
5.0
5.5
20
40
60
4.0
4.5
5.0
5.5
6.0
6.0
80
Supply voltage (V)
Ambient temperature (°C)
Supply voltage (V)
4/11/01; v.0.9.1
Alliance Semiconductor
P. 19 of 21
AS4C1M16F5
®
Typical TTL stand-by current ICC2
vs. ambient temperature Ta
Typical output sink current IOL
vs. output voltage VOL
Typical output source current IOH
vs. output voltage VOH
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
70
60
50
40
30
20
10
0.0
70
60
50
40
30
20
10
0.0
0
20
40
60
0.0
0.5
1.0
1.5
0.0
1.0
2.0
3.0
80
2.0
4.0
Ambient temperature (°C)
Output voltage (V)
Output voltage (V)
Typical hyper page mode current ICC4
vs. ambient temperature Ta
140
Typical hyper page mode current ICC4
vs. supply voltage VCC
140
120
100
80
120
100
80
-50
-60
-50
-60
60
60
40
40
20
20
0.0
0.0
4.0
0
20
40
60
4.5
5.0
5.5
6.0
80
Ambient temperature (°C)
Supply voltage (V)
Capacitance 15
ƒ = 1 MHz, Ta = Room temperature
Parameter
Symbol
CIN1
Signals
A0 to A9
Test conditions
Max
Unit
Vin = 0V
5
pF
Input capacitance
DQ capacitance
CIN2
RAS
,
UCAS
,
LCAS
,
WE
,
OE
Vin = 0V
7
pF
CDQ
DQ0 to DQ15
Vin = Vout = 0V
7
pF
AS4C1M16F5 ordering information
Package \ RAS access time
50 ns
60 ns
AS4C1M16F5-50JC
AS4C1M16F5-50JI
AS4C1M16F5-60JC
AS4C1M16F5-60JI
Plastic SOJ, 400 mil, 42-pin
TSOP II, 400 mil, 44/50-pin
5V
5V
AS4C1M16F5-50TC
AS4C1M16F5-50TI
AS4C1M16F5-60TC
AS4C1M16F5-60TI
4/11/01; v.0.9.1
Alliance Semiconductor
P. 20 of 21
AS4C1M16F5
®
AS4C1M16F5 part numbering system
AS4
C
1M16E0
–XX
X
X
Package:
Temperature range
DRAM prefix
C = 5V CMOS Device number RAS access time J = 42-pin SOJ 400 mil
T=44/50-pin TSOP II 400 mil
C=Commercial, 0°C to 70°C
I=Industrial, -40°C to 85°C
4/11/01; v.0.9.1
Alliance Semiconductor
P. 21 of 21
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