CS5322/D_技术文档

CS5322

Two-Phase Buck Controller

with Integrated Gate

Drivers and 5-Bit DAC

The CS5322 is a two–phase step down controller which

incorporates all control functions required to power high performance

processors and high current power supplies. Proprietary multi–phase

architecture guarantees balanced load current distribution and reduces

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overall solution cost in high current applications. Enhanced V

control architecture provides the fastest possible transient response,

excellent overall regulation, and ease of use.

28

1

The CS5322 multi–phase architecture reduces output voltage and

input current ripple, allowing for a significant reduction in inductor

values and a corresponding increase in inductor current slew rate. This

approach allows a considerable reduction in input and output capacitor

requirements, as well as reducing overall solution size and cost.

SO–28L

DW SUFFIX

CASE 751F

PIN CONNECTIONS AND

MARKING DIAGRAM

Features

• Enhanced V Control Method

2

1

• 5–Bit DAC with 1.0% Accuracy

• Adjustable Output Voltage Positioning

• 4 On–Board Gate Drivers

• 200 kHz to 800 kHz Operation Set by Resistor

• Current Sensed through Buck Inductors, Sense Resistors, or V–S

Control

28

COMP

R

OSC

CCL

V

FB

V

DRP

CCL1

CS1

CS2

GATE(L)1

GND

GATE(H)1

V

LGND

SS

V

GATE(L)2

GND2

GATE(H)2

CS

REF

PWRGD

CCH1

V

ID0

ID1

ID2

ID3

ID4

LIM

• Hiccup Mode Current Limit

• Individual Current Limits for Each Phase

• On–Board Current Sense Amplifiers

• 3.3 V, 1.0 mA Reference Output

• 5.0 V and/or 12 V Operation

CCL2

I

REF

V

CCH2

• On/Off Control (through Soft Start Pin)

• Power Good Output with Internal Delay

A

= Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

ORDERING INFORMATION

Device

Package

Shipping

CS5322GDW28

27 Units/Rail

SO–28L

CS5322GDWR28

1000 Tape & Reel

Semiconductor Components Industries, LLC, 2001

1

Publication Order Number:

April, 2001 – Rev. 6

CS5322/D

CS5322

300 nH

+12 V

+

+5.0 V

3 ×

16SP270M

1.0 µF

ENABLE

600 nH

61.9 k

1.0 nF

4.12 k

R

+

8 ×

4SP820M

COMP

OSC

CCL

V

FB

DRP

V

CCL1

V

34.8 k

12.7 k

GATE(L)1

CS1

CS2

GND1

GATE(H)1

CS

REF

V

OUT

V

CCH1

PWRGD

LGND

SS

V

ID0

ID1

ID2

12 ×10 µF

V

CCL2

0.1 µF

V

GATE(L)2

ID0

ID1

ID2

V

ID3

ID4

GND2

V

GATE(H)2

I

V

LIM

V

CCH2

REF

V

ID3

ID4

2.80 k

1.0 k

0.1 µF

600 nH

1.0 µF

25.5 k

.01 µF

25.5 k

.01 µF

Figure 1. Application Diagram, 12 V to 1.6 V, 35 A Converter

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CS5322

ABSOLUTE MAXIMUM RATINGS*

Rating

Value

150

Unit

°C

Operating Junction Temperature

Lead Temperature Soldering:

Storage Temperature Range

Reflow: (SMD styles only) (Note 1.)

230 peak

–65 to +150

2.0

°C

ESD Susceptibility (Human Body Model)

kV

1. 60 second maximum above 183°C.

*The maximum package power dissipation must be observed.

ABSOLUTE MAXIMUM RATINGS

Pin Name

Pin Symbol

V

MAX

V

MIN

I

SINK

SOURCE

Power for Logic

V

16 V

20 V

6.0 V

–0.3 V

N/A

50 mA

CCL

Power for GATE(L)1

Power for GATE(L)2

Power GATE(H)1

Power for GATE(H)2

Power Good Output

Soft Start Capacitor

V

N/A

1.5 A, 1.0 µs 200 mA DC

20 mA

CCL1

CCL2

CCH1

CCH2

V

N/A

PWRGD

SS

1.0 mA

Voltage Feedback Compensation

Network

COMP

1.0 mA

Voltage Feedback Input

V

6.0 V

–0.3 V

1.0 mA

FB

Output for Adjusting Adaptive

Voltage Position

V

DRP

Frequency Resistor

Reference Output

R

6.0 V

20 V

–0.3 V

1.0 mA

50 mA

OSC

REF

High–Side FET Drivers

GATE(H)1–2

–0.3 V DC

–2.0 V for 100

ns

1.5 A, 1.0 µs

200 mA DC

1.5 A, 1.0 µs

200 mA DC

Low–Side FET Drivers

GATE(L)1–2

16 V

–0.3 V DC

–2.0 V for 100

ns

1.5 A, 1.0 µs

200 mA DC

1.5 A, 1.0 µs

200 mA DC

Return for Logic

Return for #1 Driver

LGND

GND1

N/A

50 mA

2.0 A, 1.0 µs 200 mA DC

1.0 mA

N/A

0.3 V

6.0 V

–0.3 V

Return for #2 Driver

GND2

N/A

Current Sense for Phases 1–2

Current Limit Set Point

Current Sense Reference

Voltage ID DAC Inputs

CS1–CS2

1.0 mA

I

1.0 mA

LIM

CS

1.0 mA

REF

V

ID0–4

1.0 mA

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CS5322

ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V

< 14 V; 8.0 V < V

< 20 V;

CCH

A

J

CCL

C

= 3.3 nF, C

= 3.3 nF, R

= 32.4 k, C

= 1.0 nF, C = 0.1 µF, C

= 0.1 µF, DAC Code 10000, C = 1.0 µF,

VCC

GATE(H)

GATE(L)

R(OSC)

COMP

SS

REF

I

≥ 1.0 V; unless otherwise specified.)

LIM

Characteristic

Test Conditions

Min

Typ

Max

Unit

Voltage Identification DAC (0 = Connected to V ; 1 = Open or Pull–up to 3.3 V)

SS

Accuracy (all codes)

Measure V = COMP

± 1.0

%

FB

V

ID4

V

ID3

V

ID2

V

ID1

V

ID0

1

–

1.064

1.089

1.114

1.139

1.163

1.188

1.213

1.238

1.262

1.287

1.312

1.337

1.361

1.386

1.411

1.436

1.460

1.485

1.510

1.535

1.559

1.584

1.609

1.634

1.658

1.683

1.708

1.733

1.757

1.782

1.807

1.832

1.00

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

1.25

1.086

1.111

1.136

1.162

1.187

1.212

1.237

1.263

1.288

1.313

1.338

1.364

1.389

1.414

1.439

1.465

1.490

1.515

1.540

1.566

1.591

1.616

1.641

1.667

1.692

1.717

1.742

1.768

1.793

1.818

1.843

1.869

1.50

V

kΩ

V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Input Threshold

V

, V , V , V , V

ID3 ID2 ID1

ID4

ID0

Input Pull–up Resistance

Pull–up Voltage

, V , V , V , V

25

50

100

ID4

ID3

ID2

ID1

ID0

–

3.15

3.30

3.45

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CS5322

ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V

< 14 V; 8.0 V < V

< 20 V;

CCH

A

J

CCL

C

= 3.3 nF, C

= 3.3 nF, R

= 32.4 k, C

= 1.0 nF, C = 0.1 µF, C

= 0.1 µF, DAC Code 10000, C = 1.0 µF,

VCC

GATE(H)

GATE(L)

R(OSC)

COMP

SS

REF

I

≥ 1.0 V; unless otherwise specified.)

LIM

Characteristic

Test Conditions

Min

Typ

Max

Unit

Power Good Output

Power Good Fault Delay

Output Low Voltage

CS

= V

to V

± 15%

25

–

50

0.25

0.1

–11

11

125

0.40

10

µs

V

REF

DAC

= 1.0 V, I

= 4.0 mA

PWRGD

Output Leakage Current

Lower Threshold

= 1.45 V, PWRGD = 5.5 V

–

µA

%

% of Nominal VID Code

–14

8

–8.0

14

Upper Threshold

Voltage Feedback Error Amplifier

V

Bias Current (Note 2.)

9.0

15

10.3

30

11.5

60

µA

1.0 V < V < 1.9 V

FB

COMP Source Current

COMP = 0.5 V to 2.0 V;

V

FB

= 1.8 V; DAC = 00000

COMP Sink Current

15

30

60

µA

COMP = 0.5 V to 2.0 V;

V

FB

= 1.9 V; DAC = 00000

COMP Max Voltage

COMP Min Voltage

Transconductance

2.4

–

2.7

0.1

32

–

0.2

–

V

= 1.8 V COMP Open; DAC = 00000

= 1.9 V COMP Open; DAC = 00000

FB

–

mmho

–10 µA < I

< +10 µA

COMP

Output Impedance

Open Loop DC Gain

Unity Gain Bandwidth

–

60

–

2.5

90

–

MΩ

dB

Note 3.

400

kHz

0.01 µF COMP Capacitor

–

70

–

dB

PSRR @ 1.0 kHz

Soft Start

Soft Start Charge Current

Soft Start Discharge Current

Hiccup Mode Charge/Discharge Ratio

Peak Soft Start Charge Voltage

Soft Start Discharge Threshold Voltage

PWM Comparators

0.2 V ≤ SS ≤ 3.0 V

15

4.0

3.0

3.3

0.20

30

7.5

4.0

0.27

50

13

µA

–

0.2 V ≤ SS ≤ 3.0 V

–

4.2

0.34

V

Minimum Pulse Width

Measured from CSx to GATE(H)

–

350

0.4

515

0.5

ns

V

X

V(V ) = V(CS

) = 1.0 V, V(COMP) = 1.5 V

REF

FB

60 mV step applied between V

and V

CREF

CSX

Channel Start Up Offset

0.3

V(CS1) = V(CS2) = V(V ) = V(CS

) = 0 V;

REF

FB

Measure V(COMP) when GATE(H)1,

GATE(H)2, switch high

GATE(H) and GATE(L)

High Voltage (AC)

Note 3. Measure V

– GATE(L) or

–

0

1.0

V

CCLX

X

V

CCHX

– GATE(H)

X

Low Voltage (AC)

Note 3. Measure GATE(L)

GATE(H)

= 10 V

–

0

0.5

80

V

X or

CCHX

CCLX

X

Rise Time GATE(H)

1.0 V < GATE < 8.0 V; V

35

ns

X

Rise Time GATE(L)

= 10 V

X

2. The V Bias Current changes with the value of R

per Figure 4.

OSC

FB

3. Guaranteed by design. Not tested in production.

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CS5322

ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V

< 14 V; 8.0 V < V

< 20 V;

CCH

A

J

CCL

C

= 3.3 nF, C

= 3.3 nF, R

= 32.4 k, C

= 1.0 nF, C = 0.1 µF, C

= 0.1 µF, DAC Code 10000, C = 1.0 µF,

VCC

GATE(H)

GATE(L)

R(OSC)

COMP

SS

REF

I

≥ 1.0 V; unless otherwise specified.)

LIM

Characteristic

Test Conditions

Min

Typ

Max

Unit

GATE(H) and GATE(L)

Fall Time GATE(H)

8.0 V > GATE > 1.0 V; V

= 10 V

–

35

65

1.2

80

ns

V

X

CCHX

Fall Time GATE(L)

X

CCLX

GATE(H) to GATE(L) Delay

GATE(L) to GATE(H) Delay

GATE Pull–down

GATE(H) < 2.0 V, GATE(L) > 2.0 V

30

–

110

1.6

X

GATE(L) < 2.0 V, GATE(H) > 2.0 V

X

Force 100 µA into GATE Driver with no power

applied to V and V = 2.0 V.

CCHX

CCLX

Oscillator

Switching Frequency

Measure any phase (R

= 32.4 k)

300

150

600

–

400

200

800

1.0

500

250

1000

–

kHz

V

OSC

Note 4. Measure any phase (R

= 63.4 k)

OSC

Note 4. Measure any phase (R

= 16.2 k)

R

Voltage

–

OSC

Phase Delay

165

180

195

deg

Adaptive Voltage Positioning

V

Output Voltage to DAC

Offset

CS1 = CS2 = CS , V = COMP

REF FB

–15

240

2.4

–

15

380

3.8

mV

V/V

DRP

OUT

Measure V

– COMP

DRP

Maximum V

Voltage

(CS1 = CS2) – C

= 50 mV,

310

3.0

DRP

REF

V

FB

= COMP, Measure V

– COMP

DRP

Current Sense Amp to V

Gain

–

DRP

Current Sensing and Sharing

CS Input Bias Current

V(CSx) = V(CS

) = 0 V

–

0.5

0.2

3.15

–

4.0

2.0

µA

V/V

mV

V

REF

CS1–CS2 Input Bias Current

Current Sense Amplifiers Gain

Current Sense Amp Mismatch

REF

2.8

–5.0

0

3.53

5.0

Note 4., 0 ≤ (CSx – CS

) ≤ 50 mV

REF

Current Sense Amplifiers Input

Common Mode Range Limit

Note 4.

–

V

– 2

CCL

Current Sense Input to I

Gain

0.25 V < I

< 1.20 V

LIM

5.0

4.0

–

6.25

10

8.0

V/V

mV/µs

µA

LIM

Current Limit Filter Slew Rate

Bias Current

Note 4.

26

1.0

135

I

0 < I

< 1.0 V

0.1

105

LIM

Single Phase Pulse by Pulse

Current Limit: V(CSx) – V(CS

–

90

mV

)

REF

Current Share Amplifier Bandwidth

Note 4.

1.0

3.2

–

MHz

V

Reference Output

V

REF

Output Voltage

3.3

3.4

0 mA < I(V

) < 1.0 mA

REF

4. Guaranteed by design. Not tested in production.

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CS5322

ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V

< 14 V; 8.0 V < V

< 20 V;

CCH

A

J

CCL

C

= 3.3 nF, C

= 3.3 nF, R

= 32.4 k, C

= 1.0 nF, C = 0.1 µF, C

= 0.1 µF, DAC Code 10000, C = 1.0 µF,

VCC

GATE(H)

GATE(L)

R(OSC)

COMP

SS

REF

I

≥ 1.0 V; unless otherwise specified.)

LIM

Characteristic

Test Conditions

Min

Typ

Max

Unit

General Electrical Specifications

V

Operating Current

V

= COMP (no switching)

–

20

4.0

2.8

2.5

4.4

4.2

200

2.0

1.75

200

24.5

5.5

mA

V

CCL

FB

Operating Current

CCL1

CCL2

CCH1

CCH2

–

5.5

–

4.0

–

3.5

Start Threshold

Stop Threshold

Hysteresis

GATEs switching, Soft Start charging

4.05

3.75

100

1.8

1.55

100

4.7

CCL

GATEs stop switching, Soft Start discharging

GATEs not switching, Soft Start not charging

GATEs switching, Soft Start charging

4.6

V

CCL

300

2.2

mV

V

CCL

Start Threshold

Stop Threshold

Hysteresis

CCH1

GATEs stop switching, Soft Start discharging

GATEs not switching, Soft Start not charging

1.90

300

V

mV

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

SO–28L

PIN SYMBOL

FUNCTION

1

COMP

Output of the error amplifier and input for the PWM

comparators.

2

3

V

Voltage Feedback Pin. To use Adaptive Voltage Positioning

(AVP) select an offset voltage at light load and connect a

FB

resistor between V and V

. The input current of the V

FB

OUT

FB

pin and the resistor value determine output voltage offset for

zero output current. Short V to V for no AVP.

FB

OUT

V

DRP

Current sense output for AVP. The offset of this pin above the

DAC voltage is proportional to the output current. Connect a

resistor from this pin to V to set amount AVP or leave this

FB

pin open for no AVP.

4–5

6

CS1–CS2

Current sense inputs. Connect current sense network for the

corresponding phase to each input.

CS

Reference for Current Sense Amplifiers. To balance input

offset voltages between the inverting and noninverting inputs

of the Current Sense Amplifiers, connect a resistor between

REF

CS

and the output voltage. The value should be 1/3 of

REF

the value of the resistors connected to the CSx pins.

7

PWRGD

Power Good Output. Open collector output goes low when

CS

is out of regulation.

REF

8–12

V

ID4

–V

ID0

Voltage ID DAC inputs. These pins are internally pulled up to

3.3 V if left open.

13

I

Sets threshold for current limit. Connect to reference through

a resistive divider.

LIM

Reference output. Decouple with 0.1 µF to LGND.

Power for GATE(H)2.

14

15

16

17

18

REF

V

CCH2

GATE(H)2

GND2

High side driver #2.

Return for #2 driver.

GATE(L)2

Low side driver #2.

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CS5322

PACKAGE PIN DESCRIPTION (continued)

PACKAGE PIN #

SO–28L

19

PIN SYMBOL

FUNCTION

V

CCL2

Power for GATE(L)2.

20

SS

Soft Start capacitor pin. The Soft Start capacitor controls

both Soft Start time and hiccup mode frequency. The COMP

pin is clamped below Soft Start during Start–Up and hiccup

mode.

21

22

LGND

Return for internal control circuits and IC substrate connection.

V

CCH1

Power for GATE(H)1. UVLO Sense for High Side Driver sup-

ply connects to this pin.

23

24

25

26

27

GATE(H)1

GND1

High side driver #1.

Return #1 drivers.

Low side driver #1.

Power for GATE(L)1.

GATE(L)1

V

CCL1

V

CCL

Power for internal control circuits. UVLO Sense for Logic

connects to this pin.

28

R

A resistor from this pin to ground sets operating frequency

OSC

and V bias current.

FB

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CS5322

−

V

CCL

Start

Stop

+

3.3 V

REF

PWRGD

+

−

REF

4.4 V

4.2 V

−

V

CCH1

Start

Stop

+

V

ID0

ID1

ID2

DAC

+

−

OUT

S

R

PH 1

GATE(H)1

2.0 V

1.8 V

Gate

DAC

Delay

Nonoverlap

V

CCL1

−

PWMC1

V

ID3

V

ID4

+

GATE(L)1

GND1

CO1

+

MAXC1

−

LGND

+

−

+11%

V

CCH2

FAULT

−

+

CO1

0.33 V

S

R

AVPA

PH 2

V

DRP

GATE(H)2

−

+

Gate

Nonoverlap

V

CCL2

−

CS

REF

PWMC2

+

GATE(L)2

GND2

CO2

+

MAXC2

+

−

CO1

CS1

CS2

CSA1

–11%

+

−

FAULT

CO2

0.33 V

−

_CSA2CO2

+

−

×

2

+

Offset

I

LIM

Filter

+

−

I

−

LIM

Current

Source

Gen

EA

+

BIAS

DAC

OUT

SS

Charge

Current

FAULT

S

R

PH 1

+

−

+

−

SS

Discharge

Threshold

SS

Discharge

Current

OSC

+

PH 2

−

R

OSC

V

COMP

SS

FB

Figure 2. Block Diagram

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CS5322

TYPICAL PERFORMANCE CHARACTERISTICS

900

800

700

25

20

15

600

500

400

10

5

300

200

100

0

10

20

30

40

50

60

70

10

20

30

40

50

60

70

80

R

Value, kΩ

R

Value, kΩ

OSC

Figure 3. Oscillator Frequency

Figure 4. V_FBBias Current vs. R_OSCValue

120

100

80

120

100

80

60

40

20

0

20

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

16

Load Capacitance, nF

Figure 5. Gate(H) Rise–time vs. Load Capacitance

measured from 1.0 V to 4.0 V with V_CCat 5.0 V.

Figure 6. Gate(H) Fall–time vs. Load Capacitance

measured from 4.0 V to 1.0 V with V_CCat 5.0 V.

120

100

80

120

100

80

60

40

20

0

20

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

16

Load Capacitance, nF

Figure 7. Gate(L) Rise–time vs. Load Capacitance

measured from 4.0 V to 1.0 V with V_CCat 5.0 V.

Figure 8. Gate(L) Fall–time vs. Load Capacitance

measured from 4.0 V to 1.0 V with V_CCat 5.0 V.

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10

CS5322

APPLICATIONS INFORMATION

FIXED FREQUENCY MULTI–PHASE CONTROL

cycle will terminate earlier providing negative feedback.

The CS5322 provides a Cx input for each phase, but the

CS , V and COMP inputs are common to all phases.

In a multi–phase converter, multiple converters are

connected in parallel and are switched on at different times.

This reduces output current from the individual converters

and increases the apparent ripple frequency. Because several

converters are connected in parallel, output current can ramp

up or down faster than a single converter (with the same

value output inductor) and heat is spread among multiple

components.

REF

FB

Current sharing is accomplished by referencing all phases to

the same V and COMP pins, so that a phase with a larger

FB

current signal will turn off earlier than phases with a smaller

current signal.

Including both current and voltage information in the

feedback signal allows the open loop output impedance of

the power stage to be controlled. When the average output

current is zero, the COMP pin will be only 1/2 of the steady

state ramp height plus the OFFSET above the output

voltage. If the COMP pin is held steady and the inductor

current changes, there must also be a change in the output

voltage. Or, in a closed loop configuration when the output

current changes, the COMP pin must move to keep the same

output voltage. The required change in the output voltage or

COMP pin depends on the scaling of the current feedback

signal and is calculated as

The CS5322 uses a two–phase, fixed frequency,

2

Enhanced V architecture. Each phase is delayed 180° from

the previous phase. Normally Gate(H) transitions high at the

beginning of each oscillator cycle. Inductor current ramps

up until the combination of the current sense signal and the

output ripple trip the PWM comparator and bring Gate(H)

low. Once Gate(H) goes low, it will remain low until the

beginning of the next oscillator cycle. While Gate(H) is

2

high, the enhanced V loop will respond to line and load

transients. Once Gate(H) is low, the loop will not respond

again until the beginning of the next cycle. Therefore,

DV + R CSA Gain DI

S

2

constant frequency Enhanced V will typically respond

The single–phase power stage output impedance is:

within the off–time of the converter.

2

The Enhanced V architecture measures and adjusts

Single Stage Impedance + DVńDI + R CSA Gain.

S

current in each phase. An additional input (Cx) for inductor

The multi–phase power stage output impedance is the

single–phase output impedance divided by the number of

phases. The output impedance of the power stage determines

how the converter will respond during the first few µs of a

transient before the feedback loop has repositioned the

COMP pin.

2

current information has been added to the V loop for each

phase as shown in Figure 9.

SWNODE

C

L

X

R

L

+

CSA

+

The peak output current of each phase can also be

calculated from;

R

S

OFFSET

V

* V

OFFSET

COMP

R

FB

CSA Gain

CS

REF

I

(per phase) +

PWM

pkout

S

COMP

+

V

OUT

Figure 10 shows the step response of a single phase with

the COMP pin at a fixed level. Before T1 the converter is in

normal steady state operation. The inductor current provides

the PWM ramp through the Current Sense Amplifier. The

PWM cycle ends when the sum of the current signal, voltage

signal and OFFSET exceed the level of the COMP pin. At

T1 the output current increases and the output voltage sags.

The next PWM cycle begins and the cycle continues longer

than previously while the current signal increases enough to

V

FB

+

E.A.

+

DAC

OUT

+

COMP

Figure 9. Enhanced V²Feedback and Current

Sense Scheme

make up for the lower voltage at the V pin and the cycle

FB

ends at T2. After T2 the output voltage remains lower than

at light load and the current signal level is raised so that the

sum of the current and voltage signal is the same as with the

original load. In a closed loop system the COMP pin would

move higher to restore the output voltage to the original

level.

The inductor current is measured across R , amplified by

S

CSA and summed with the OFFSET and Output Voltage at

the non–inverting input of the PWM comparator. The

inductor current provides the PWM ramp and as inductor

current increases the voltage on the positive pin of the PWM

comparator rises and terminates the PWM cycle. If the

inductor starts the cycle with a higher current, the PWM

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11

CS5322

considered when setting the I

threshold. If a more

LIM

accurate current sense is required than inductive sensing can

provide, current can be sensed through a resistor as shown

in Figure 9.

SWNODE

Current Sharing Accuracy

V

FB

(V

OUT

)

PCB traces that carry inductor current can be used as part

of the current sense resistance depending on where the

current sense signal is picked off. For accurate current

sharing, the current sense inputs should sense the current at

the same point for each phase and the connection to the

CSA Out

CS

should be made so that no phase is favored. (In some

REF

COMP – Offset

CSA Out + V

cases, especially with inductive sensing, resistance of the

pcb can be useful for increasing the current sense

resistance.) The total current sense resistance used for

calculations must include any pcb trace between the CS

FB

T1

T2

Figure 10. Open Loop Operation

inputs and the CS

input that carries inductor current.

REF

Current Sense Amplifier Input Mismatch and the value of

the current sense element will determine the accuracy of

current sharing between phases. The worst case Current

Sense Amplifier Input Mismatch is 5.0 mV and will

typically be within 3.0 mV. The difference in peak currents

between phases will be the CSA Input Mismatch divided by

the current sense resistance. If all current sense elements are

of equal resistance a 3.0 mV mismatch with a 2.0 mΩ sense

resistance will produce a 1.5 A difference in current between

phases.

Inductive Current Sensing

For lossless sensing, current can be sensed across the

inductor as shown in Figure 11. In the diagram L is the output

inductance and R is the inherent inductor resistance. To

L

compensate the current sense signal the values of R1 and C1

are chosen so that L/R = R1 × C1. If this criteria is met the

L

current sense signal will be the same shape as the inductor

current, the voltage signal at Cx will represent the

instantaneous value of inductor current and the circuit can be

analyzed as if a sense resistor of value R was used as a sense

L

Operation at > 50% Duty Cycle

For operation at duty cycles above 50% Enhanced V will

resistor (R ).

S

2

R1

C1

exhibit subharmonic oscillation unless a compensation

ramp is added to each phase. A circuit like the one on the left

side of Figure 12 can be added to each current sense network

to implement slope compensation. The value of R1 can be

varied to adjust the ramp size.

SWNODE

CS

+

L

+

CSA

OFFSET

R

L

REF

PWM

COMP

+

Switch Node

GATE(L)X

V

OUT

V

FB

E.A.

+

DAC

OUT

COMP

R1

25 k

3 k

CS

Figure 11. Lossless Inductive Current Sensing with

Enhanced V²

X

1.0 nF

0.1 µF

.01 µF

When choosing or designing inductors for use with

inductive sensing tolerances and temperature, effects should

be considered. Cores with a low permeability material or a

large gap will usually have minimal inductance change with

temperature and load. Copper magnet wire has a

temperature coefficient of 0.39% per °C. The increase in

winding resistance at higher temperatures should be

CS

REF

MMBT2222LT1

Existing Current

Sense Circuit

Slope Comp

Circuit

Figure 12. External Slope Compensation Circuit

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12

CS5322

Ramp Size and Current Sensing

Because the current ramp is used for both the PWM ramp

and to sense current, the inductor and sense resistor values

will be constrained. A small ramp will provide a quick

transient response by minimizing the difference over which

the COMP pin must travel between light and heavy loads,

but a steady state ramp of 25 mVp–p or greater is typically

required to prevent pulse skipping and minimize pulse width

jitter. For resistive current sensing, the combination of the

inductor and sense resistor values must be chosen to provide

a large enough steady state ramp. For large inductor values

the sense resistor value must also be increased.

For inductive current sensing, the RC network must meet

the requirement of L/R = R × C to accurately sense the AC

L

and DC components of the current the signal. Again the

values for L and R will be constrained in order to provide

L

a large enough steady state ramp with a compensated current

sense signal. A smaller L, or a larger R than optimum might

L

Figure 13. Inductive Sensing waveform during a Step

be required. But unlike resistive sensing, with inductive

sensing, small adjustments can be made easily with the

values of R and C to increase the ramp size if needed.

with Fast RC Time Constant (50 µs/div)

If RC is chosen to be smaller (faster) than L/R , the AC

L

Current Limit

portion of the current sensing signal will be scaled larger

than the DC portion. This will provide a larger steady state

ramp, but circuit performance will be affected and must be

evaluated carefully. The current signal will overshoot during

transients and settle at the rate determined by R × C. It will

eventually settle to the correct DC level, but the error will

decay with the time constant of R × C. If this error is

excessive it will effect transient response, adaptive

positioning and current limit. During transients the COMP

pin will be required to overshoot along with the current

Two levels of overcurrent protection are provided. Any

time the voltage on a Current Sense pin exceeds CS

by

REF

more than the Single Phase Pulse by Pulse Current Limit, the

PWM comparator for that phase is turned off. This provides

fast peak current protection for individual phases. The

outputs of all the currents are also summed and filtered to

compare an averaged current signal to the voltage on the

I

pin. If this voltage is exceeded, the fault latch trips and

LIM

the Soft Start capacitor is discharged by a 7.5 µA source until

the COMP pin reaches 0.2 V. Then Soft Start begins. The

converter will continue to operate in this mode until the fault

condition is corrected.

signal in order to maintain the output voltage. The V

DRP

will also overshoot during transients and possibly slow the

response. Single phase overcurrent will trip earlier than it

would if compensated correctly and hiccup mode current

limit will have a lower threshold for fast rise step loads than

for slowly rising output currents.

Overvoltage Protection

Overvoltage protection (OVP) is provided as a result of

2

the normal operation of the Enhanced V control topology

with synchronous rectifiers. The control loop responds to an

overvoltage condition within 400 ns, causing the top

MOSFET’s to shut off and the synchronous MOSFET’s to

turn on. This results in a “crowbar” action to clamp the

output voltage and prevent damage to the load. The regulator

will remain in this state until the overvoltage condition

ceases or the input voltage is pulled low.

The waveforms in Figure 13 show a simulation of the

current sense signal and the actual inductor current during a

positive step in load current with values of L = 500 nH, R

L

= 1.6 mΩ, R1 = 20 k and C1 = .01 µF. For ideal current signal

compensation the value of R1 should be 31 kΩ. Due to the

faster than ideal RC time constant there is an overshoot of

50% and the overshoot decays with a 200 µs time constant.

With this compensation the I

pin threshold must be set

LIM

more than 50% above the full load current to avoid

triggering hiccup mode during a large output load step.

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13

CS5322

Transient Response and Adaptive Positioning

between fast and slow positioning is controlled by the ramp

size and the error amp compensation. If the ramp size is too

large or the error amp too slow there will be a long transition

to the final voltage after a transient. This will be most

apparent with lower capacitance output filters.

Note: Large levels of adaptive positioning can cause pulse

width jitter.

For applications with fast transient currents the output

filter is frequently sized larger than ripple currents require in

order to reduce voltage excursions during transients.

Adaptive voltage positioning can reduce peak–peak output

voltage deviations during load transients and allow for a

smaller output filter. The output voltage can be set higher

than nominal at light loads to reduce output voltage sag

when the load current is stepped up and set lower than

nominal during heavy loads to reduce overshoot when the

load current is stepped up. For low current applications a

droop resistor can provide fast accurate adaptive

positioning. However, at high currents the loss in a droop

resistor becomes excessive. For example; in a 50 A

converter a 1.0 mΩ resistor to provide a 50 mV change in

output voltage between no load and full load would dissipate

2.5 Watts.

Lossless adaptive positioning is an alternative to using a

droop resistor, but must respond quickly to changes in load

current. Figure 14 shows how adaptive positioning works.

The waveform labeled normal shows a converter without

adaptive positioning. On the left, the output voltage sags

when the output current is stepped up and later overshoots

when current is stepped back down. With fast (ideal)

adaptive positioning the peak to peak excursions are cut in

half. In the slow adaptive positioning waveform the output

voltage is not repositioned quickly enough after current is

stepped up and the upper limit is exceeded.

Error Amp Compensation

The transconductance error amplifier requires a capacitor

between the COMP pin and GND. Use of values less than 1

nF may result in error amp oscillation of several MHz.

The capacitor between the COMP pin and the inverting

error amplifier input and the parallel resistance of the V

FB

resistor and the V

resistor are used to roll off the error

DRP

amp gain. The gain is rolled off at a high enough frequency

to give a quick transient response, but low enough to cross

zero dB well below the switching frequency to minimize

ripple and noise on the COMP pin.

UVLO

The CS5322 has undervoltage lockout functions

connected to two pins. One, intended for the logic and

low–side drivers, with a 4.4 V turn–on threshold is

connected to the V

pin. A second, for the high side

CCL

drivers, has a 2.0 V threshold and is connected to the V

pin.

CCH1

The UVLO threshold for the high side drivers was chosen

at a low value to allow for flexibility in the part and an input

voltage as low as 3.3 V. In many applications this will be

disabled or will only check that the applicable supply is on

– not that is at a high enough voltage to run the converter.

For the 12 V converter in the application diagram on

IN

page 2, the UVLO pin for the high side driver is pulled up

by the 5.0 V supply (through two diode drops) and the

function is not used. The diode between the Soft Start pin

near GND and prevents start–up while the 12 V supply is off.

In an application where a higher UVLO threshold is

necessary a circuit like the one in Figure 15 will lock out the

converter until the 12 V supply exceeds 9 V.

Normal

Fast Adaptive Positioning

SlowAdaptive Positioning

Limits

Figure 14. Adaptive Positioning

The CS5322 can be configured to adjust the output

voltage based on the output current of the converter. (Refer

to the application diagram on page 2)

+12 V

+5 V

To set the no–load positioning, a resistor is placed

between the output voltage and V pin. The V bias

FB

50 k

Soft Start

current will develop a voltage across the resistor to increase

the output voltage. The V bias current is dependent on the

FB

value of R . See Figure 4.

OSC

During no load conditions the V

pin is at the same

DRP

100 k

voltage as the V pin, so none of the V bias current flows

FB

through the V

resistor. When output current increases

100 k

DRP

the V

pin increases proportionally and the V

DRP

current offsets the V bias current and causes the output

FB

voltage to decrease.

Figure 15. External UVLO Circuit

The V and V

pins take care of the slower and DC

FB

DRP

voltage positioning. The first few µs are controlled primarily

by the ESR and ESL of the output filter. The transition

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CS5322

Soft Start and Hiccup Mode

DESIGN PROCEDURE

A capacitor between the Soft Start pin and GND controls

Soft Start and hiccup mode slopes. A 0.1 µF capacitor with

the 30 µA charge current will allow the output to ramp up at

0.3 V/ms or 1.5 V in 5.0 ms at start–up.

When a fault is detected due to overcurrent or UVLO the

converter will enter a low duty cycle hiccup mode. During

hiccup mode the converter will not switch from the time a

fault is detected until the Soft Start capacitor has discharged

below the Soft Start Discharge Threshold and then charged

back up above the Channel Start Up Offset.

Current Sensing, Power Stage and

Output Filter Components

1. Choose the output filter components to meet peak

transient requirements. The formula below can be

used to provide an approximate starting point for

capacitor choice, but will be inadequate to calculate

actual values.

DV

+ (DIńDT) ESL ) DI ESR

PEAK

Ideally the output filter should be simulated with

models including ESR, ESL, circuit board parasitics

and delays due to switching frequency and converter

response. Typically both bulk capacitance

(electrolytic, Oscon, etc.,) and low impedance

capacitance (ceramic chip) will be required. The bulk

capacitance provides “hold up” during the converter

response. The low impedance capacitance reduces

steady state ripple and bypasses the bulk capacitance

during slewing of output current.

The Soft Start pin will disable the converter when pulled

below 0.3 V.

Layout Guidelines

With the fast rise, high output currents of microprocessor

applications, parasitic inductance and resistance should be

considered when laying out the power, filter and feedback

signal sections of the board. Typically, a multi–layer board

with at least one ground plane is recommended. If the layout

is such that high currents can exist in the ground plane

underneath the controller or control circuitry, the ground

plane can be slotted to reroute the currents away from the

controller. The slots should typically not be placed between

the controller and the output voltage or in the return path of

the gate drive. Additional power and ground planes or

islands can be added as required for a particular layout.

Gate drives experience high di/dt during switching and the

inductance of gate drive traces should be minimized. Gate

drive traces should be kept as short and wide as practical and

should have a return path directly below the gate trace.

Output filter components should be placed on wide planes

connected directly to the load to minimize resistive drops

during heavy loads and inductive drops and ringing during

transients. If required, the planes for the output voltage and

return can be interleaved to minimize inductance between

the filter and load.

2. For inductive current sensing (only) choose the

current sense network RC to provide a 25 mV

minimum ramp during steady state operation.

V

ńV

OUT IN

R + (V * V

IN

)

OUT

F C 25 mV

Then choose the inductor value and inherent

resistance to satisfy L/R = R × C.

L

For ideal current sense compensation the ratio of L and

R

L

is fixed, so the values of L and R will be a

L

compromise typically with the maximum value R

L

limited by conduction losses or inductor temperature

rise and the minimum value of L limited by ripple

current.

3. For resistive current sensing choose L and R to

S

provide a steady state ramp greater than 25 mV.

LńR + (V * V

IN

) T

OUT

ń25 mV

ON

Voltage feedback should be taken from a point of the

output or the output filter that doesn’t favor any one phase.

If the feedback connection is closer to one inductor than the

others the ripple associated with that phase may appear

larger than the ripple associated with the other phases and

poor current sharing can result.

The current sense signal is typically tens of milli–volts.

Noise pick–up should be avoided wherever possible.

Current feedback traces should be routed away from noisy

areas such as switch nodes and gate drive signals. The paths

should be matched as well as possible. It is especially

important that all current sense signals be picked off at

similar points for accurate current sharing. If the current

signal is taken from a place other than directly at the inductor

any additional resistance between the pick–off point and the

inductor appears as part of the inherent inductor resistance

and should be considered in design calculations. Capacitors

for the current feedback networks should be placed as close

to the current sense pins as practical.

S

Again the ratio of L and R is fixed and the values of

L

L and R will be a compromise.

S

4. Calculate the high frequency output impedance

(ConverterZ) of the converter during transients. This

is the impedance of the Output filter ESR in parallel

with the power stage output impedance (PwrstgZ)

and will indicate how far from the original level

(∆VR) the output voltage will typically recover to

within one switching cycle. For a good transient

response ∆VR should be less than the peak output

voltage overshoot or undershoot.

DVR + ConverterZ ESR

PwrstgZ ESR

ConverterZ +

PwrstgZ ) ESR

where:

PwrstgZ + R CSA Gainń2.0

S

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15

CS5322

Multiply the converterZ by the output current step

DV

+ I

OUTFL

R CS to V

Gain

DRP

V(DRP)

size to calculate where the output voltage should

recover to within the first switching cycle after a

transient. If the ConverterZ is higher than the value

required to recover to where the adaptive positioning

is set the remainder of the recovery will be controlled

by the error amp compensation and will typically

recover in 10–20 µs.

where:

R = R or R for one phase;

L

S

I

is the full load output current.

OUTFL

R

+ DV

R

ńDV

V(FB) OUT

V(DRP)

DRP

Calculate Input Filter Capacitor Current Ripple

The procedure below assumes that phases do not overlap

and output inductor ripple current (P–P) is less than the

average output current of one phase.

DVR + DI

OUT

ConverterZ

Make sure that ∆VR is less than the expected peak

transient for a good transient response.

9. Calculate Input Current

5. Adjust L and R or R as required to meet the best

L

S

V

I

OUT

combination of transient response, steady state output

voltage ripple and pulse width jitter.

OUT

Efficiency V

I

IN

+

(

)

IN

10. Calculate Duty Cycle (per phase).

Current Limit

When the sum of the Current Sense amplifiers (V

)

V

ITOTAL

OUT

Efficiency V

Duty Cycle +

(

)

IN

exceeds the voltage on the I

pin the part will enter hiccup

LIM

mode. For inductive sensing the I

set based on the inductor resistance (or current sense

resistor) at max temperature and max current. To set the level

pin voltage should be

LIM

11. Calculate Apparent Duty Cycle.

Apparent Duty Cycle + Duty Cycle # of Phases

12. Calculate Input Filter Capacitor Ripple Current. Use

the chart in Figure 16 to calculate the normalized

of the I

pin:

LIM

6. V

+ R I

CS to I Gain

LIM

I(LIM)

OUT(LIM)

ripple current (K ) based on the reciprocal of

RMS

where:

Apparent Duty Cycle. Then multiply the input current

R is R or R

L

S;

by K

to obtain the Input Filter Capacitor Ripple

RMS

I

is the current limit threshold.

OUT(LIM)

Current.

For the overcurrent to work properly the inductor

time constant (L/R) should be≤ the Current sense RC.

If the RC is too fast, during step loads the current

waveform will appear larger than it is (typically for a

few hundred µs) and may trip the current limit at a

level lower than the DC limit.

Ripple (RMS) + I K

IN

RMS

4.00

3.50

3.00

2.50

2.00

1.50

Adaptive Positioning

7. To set the amount of voltage positioning below the

DAC setting at no load connect a resistor (R

)

V(FB)

1.00

0.50

0.00

between the output voltage and the V pin. Choose

FB

R

V(FB)

as;

15

10

5

0

R

+ NL PositionńV

Bias Current

FB

V(FB)

1/ Apparent Duty Cycle

See Figure 4 for V Bias Current.

8. To set the difference in output voltage between no

load and full load, connect a resistor (R

Figure 16. Normalized Input Filter Capacitor

Ripple Current

FB

)

V(DRP)

between the V

and V pins. R

can be

DESIGN EXAMPLE

DRP

FB

V(DRP)

calculated in two steps. First calculate the difference

between the V and V pin at full load. (The V

Choose the component values for a 12 V to 1.6 V, 35 A

converter with lossless current sensing, adaptive positioning

and a 45 A current limit. The adaptive positioning is chosen

DRP

FB

voltage should be the same as the DAC voltage during

closed loop operation.) Then choose the R to

V(DRP)

30 mV above the nominal V

at no load and 40 mV below

OUT

source enough current across R ( ) for the desired

V FB

the no–load position with 35 A out. The peak output voltage

transient is 70 mV max during a 32 A step current.

change in output voltage.

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CS5322

Current Sensing, Power Stage and

Output Filter Components

Current Limit

V

6.

+ R I

L

I(LIM)

OUT(LIM)

CS to I Gain

1. Assume 1.5 mΩ of output filter ESR.

LIM

2.

V

ńV

OUT IN

+ 2.0 mW 45 A 6.25

+ 562 mV

+ (V * V

)

OUT

R

IN

F C 25 mV

1.6ń12

250 k 0.01 mF 25 mV

+ (12 * 1.6)

+ 22 kW

Adaptive Positioning

7. R

+ NL PositionńV

Bias Current

V(FB)

FB

LńR + .01 mF 20 kW + 200 ms

+ 30 mVń6.0 mA + 5.0 kW

L

Choose R + 2.0 mW

L + 2.0 mW 200 ms + 400 nH

L

8.

+ R I

Current Sense to V

DV

L

OUT

DRP

Gain

DRP

+ 2.0 mW 35 A 3.0

+ 210 mV

3. n/a

4.

PwrstgZ

+ R CSA Gainń2.0

L

+ DV

R

ńDV

V(FB)

+ 2.0 mW 3.15ń2.0 + 3.1 mW

R

DRP

OUT

V(DRP)

+ 210 mV 5.0 kWń40 mV

PwrstgZ ESR

+

ConverterZ

+ 26 kW

PwrstgZ ) ESR

3.1 mW 1.5 mW

3.1 mW ) 1.5 mW

9.

41 A

0.85 12V

1.52 V

0.85 12 V

^ 1.0 mW

I

+ 1.52 V

+ 6.1 A

IN

+ 0.15

10.

DVR + 1.0 mW 32 A + 32 mV

Duty Cycle +

IN

5. n/a

11.

12.

Apparent Duty Cycle + 0.15 2.0 + 0.3

RMS ripple + 6.1 A 1.5 + 9.2 A

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CS5322

ADDITIONAL APPLICATION DIAGRAMS

300 nH

+5.0 V

+

3 ×

1.0 µF

6SP680M

1.0 µF

ENABLE

470 nH

61.9 k

1.0 nF

COMP

R

+

OSC

CCL

8 ×

V

FB

7.5 k

V

CCL1

V

4SP820M

DRP

25.5 k

12.7 k

CS1

CS2

GATE(L)1

GND1

GATE(H)1

CS

V

OUT

REF

V

CCH1

PWRGD

LGND

V

ID0

V

ID1

V

ID2

12 ×10 µF

SS

V

CCL2

V

ID0

0.1 µF

GATE(L)2

GND2

V

ID3

ID4

V

ID1

ID2

I

GATE(H)2

LIM

V

CCH2

REF

V

ID3

4.82 k

0.1 µF

ID4

1.0 µF

470 nH

1.0 k

25.5 k

.01 µF

25.5 k

.01 µF

Figure 17. 5.0 V only to 1.6 V, 35 A

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CS5322

ADDITIONAL APPLICATION DIAGRAMS

300 nH

+5.0 V

+

3 ×

6SP680M

1.0 µF

ENABLE

3.3 nF

4.12 k

10 k

1.2 µH

61.9 k

1.0 nF

R

V

CCL1

COMP

+

3 ×

4SP820M

OSC

V

DRP

CS1

CCL

FB

4.12 k

V

34.8 k

GATE(L)1

GND1

CS2

CS

25.5 k

GATE(H)1

V

OUT

REF

V

PWRGD

CCH1

PWRGD

LGND

V

ID0

V

ID1

V

ID2

3 ×10 µF

SS

V

CCL2

V

ID0

0.1 µF

GATE(L)2

GND2

V

LIM

ID3

ID4

V

ID1

V

ID2

GATE(H)2

I

V

CCH2

REF

V

ID3

2.80 k

1.0 k

0.1 µF

ID4

1.0 µF

1.2 µH

49.9 k

.01 µF

820 Ω

2.0 k

820 Ω

1.0 nF

0.1 µF

2.0 k

GATE(L)2

GATE(L)1

MMBT2222LT1

Figure 18. 5.0 V only to 2.5 V Converter

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19

CS5322

ADDITIONAL APPLICATION DIAGRAMS

300 nH

1.0 µF

+5.0 V

+

+12 V

6SP680M

Q1

Q3

Q2

Q4

1.0 µF

V

OUT

ENABLE

470 nH

61.9 k

1.0 nF

7.5 k

1.0 nF

U1

R

V

COMP

OSC

V

8 ×

4SP820M

CCL

FB

V

CCL1

V

DRP

25.5 k

12.7 k

CS1

CS2

GATE(L)1

GND1

GATE(H)1

CS

PWRGD

REF

V

CCH1

PWRGD

LGND

V

ID0

V

ID1

V

ID2

12 ×10 µF cer

SS

CCL2

V

ID0

V

0.1 µF

GATE(L)2

GND2

V

LIM

ID3

ID4

V

ID1

GATE(H)2

I

V

CCH2

REF

V

ID2

V

Q5

Q7

Q6

ID3

4.32 k

1.0 k

0.1 µF

V

ID4

470 nH

Q8

25.5 k

.01 µF

25.5 k

.01 µF

0.1 µF

Figure 19. 5.0 V only to 1.2 V Bias to 1.6 V, 35 A

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20

CS5322

PACKAGE DIMENSIONS

SOIC

DW SUFFIX

CASE 751F–05

ISSUE F

D

NOTES:

A

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSIONS.

4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS

OF B DIMENSION AT MAXIMUM MATERIAL

CONDITION.

28

15

1

14

MILLIMETERS

B

PIN 1 IDENT

DIM MIN

MAX

2.65

0.29

0.49

0.32

18.05

7.60

A

A1

B

C

D

E

2.35

0.13

0.35

0.23

17.80

7.40

L

0.10

e

1.27 BSC

H

L

10.05

0.41

0

10.55

0.90

8

e

C

q

_

SEATING

PLANE

B

C

q

M

S

B

0.025

C A

PACKAGE THERMAL DATA

Parameter

28 Lead SO Wide

Unit

R

Typical

15

75

°C/W

Θ

JC

JA

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21

CS5322

Notes

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22

CS5322

Notes

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23

CS5322

2

V is a trademark of Switch Power, Inc.

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold

SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment:

CENTRAL/SOUTH AMERICA:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–spanish@hibbertco.com

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada

Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

Toll–Free from Mexico: Dial 01–800–288–2872 for Access –

then Dial 866–297–9322

ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support

Phone: 1–303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

Toll Free from Hong Kong & Singapore:

Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

001–800–4422–3781

EUROPE: LDC for ON Semiconductor – European Support

German Phone: (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET)

Email: ONlit–german@hibbertco.com

French Phone: (+1) 303–308–7141 (Mon–Fri 2:00pm to 7:00pm CET)

Email: ONlit–french@hibbertco.com

Email: ONlit–asia@hibbertco.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: 81–3–5740–2700

Email: r14525@onsemi.com

English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT)

Email: ONlit@hibbertco.com

ON Semiconductor Website: http://onsemi.com

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

For additional information, please contact your local

Sales Representative.

*Available from Germany, France, Italy, UK, Ireland

CS5322/D

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24


型号：	CS5322/D
厂家：	ETC
描述：	Two-Phase Buck Controller with Integrated Gate Drivers and 5-Bit DAC 两相降压控制器，集成栅极驱动器和5位DAC\n 驱动器栅极栅极驱动控制器
文件：	总24页 (文件大小：175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CS5322/D [ETC]

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