CXG1144EN [ETC]
High Power DPDT Switch with Logic Control ; 大功率双刀双掷开关与逻辑控制\n型号: | CXG1144EN |
厂家: | ETC |
描述: | High Power DPDT Switch with Logic Control
|
文件: | 总7页 (文件大小:60K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CXG1144EN
High Power DPDT Switch with Logic Control
Description
10 pin VSON (Plastic)
The CXG1144EN is a high power DPDT switch
MMIC.This IC can be used in wireless communication
systems, for example, CDMA handsets with GPS.
The CXG1144EN can be operated by one CMOS
control line. The Sony's J-FET process is used for low
insertion loss and on-chip logic circuit.
Features
• Low insertion loss: 0.30dB @900MHz,
0.45dB @1900MHz
• High linearity: IIP3 (Typ.) = 65dBm
• 1 CMOS compatible control line
• Small package size: 10-pin VSON
Applications
• Dual-band cellular handsets
• CDMA with GPS, dual-band CDMA
Structure
GaAs J-FET MMIC
Absolute Maximum Ratings (Ta = 25°C)
• Bias voltage
VDD
Vctl
7
V
V
• Control voltage
5
• Operating temperature Topr
• Storage temperature Tstg
–35 to +85
–65 to +150
°C
°C
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E02748-PS
CXG1144EN
Block Diagram andTerminal Arrangement Figure
GND (recommended)
6
7
5
4
3
2
1
RF3
GND
GND
RF4
RF2
GND
GND
RF1
CTL
F2
F3
F1
8
F4
9
V
DD
Logic
10
DD
V
GND (recommended)
TruthTable
CTL
ON state
OFF state
F1
F2
F3
F4
L
RF1 – RF2, RF3 – RF4
RF2 – RF3, RF4 – RF1
RF2 – RF3, RF4 – RF1
RF1 – RF2, RF3 – RF4
ON OFF ON OFF
OFF ON OFF ON
H
Pin Description 1
Pin No. Symbol
Description
1
2
CTL
RF1
GND
GND
RF2
RF3
GND
GND
RF4
VDD
Control signal input
RF signal input
GND
3
4
GND
5
RF signal output
RF signal input
GND
6
7
8
GND
9
RF signal output
Power supply input
10
– 2 –
CXG1144EN
Pin Description 2
Pin No. Symbol
Equivalent circuit
1
Logic
1
CTL
10
F1 to F4
10
VDD
DC Bias Condition
(Ta = 25°C)
Item
Vctl (H)
Vctl (L)
VDD
Min.
2.0
0
Typ.
3.0
—
Max.
3.6
Unit
V
0.4
V
2.7
3.0
3.6
V
– 3 –
CXG1144EN
Electrical Characteristics
(Ta = 25°C, VDD = 3.0V)
Item
Symbol
IL
Condition
Min.
Typ.
0.30
0.45
21
Max. Unit
900MHz
1.9GHz
900MHz
1.9GHz
0.55
0.70
dB
dB
Insertion loss
18
14
dB
Isolation
VSWR
ISO.
VSWR
2fo
16
dB
50Ω
1.2
–75
–75
–75
–75
65
—
1
–60
–60
–60
–60
dBc
dBc
dBc
dBc
dBm
dBm
dBm
µs
3
1
3
2
4
Harmonics
Input IP3
3fo
55
55
32
IIP3
65
1dB compression input power P1dB
VDD = 2.8V
35
Switching speed
Bias current
TSW
IDD
1
5
VDD = 3.0V
55
200
100
µA
Control current
Ictl
Vctl (H) = 3V
40
µA
Condition
1
Pin = 25dBm, 0/3V control, VDD = 3.0V, 900MHz
2
3
4
Pin = 25dBm (900MHz) +25dBm (901MHz), 0/3V control, VDD = 3.0V
Pin = 25dBm, 0/3V control, VDD = 3.0V, 1.9GHz
Pin = 25dBm (1.9GHz) +25dBm (1.901GHz), 0/3V control, VDD = 3.0V
– 4 –
CXG1144EN
Electrical Characteristics Measurement Circuit
GND (recommended)
6
7
5
4
3
2
1
RF3
RF2
C
RF (100pF)
C
RF (100pF)
GND
GND
8
GND
GND
9
RF1
RF4
CRF (100pF)
CRF (100pF)
Rctl (1kΩ)
10
V
DD
CTL
Cbypass (100pF)
Cbypass (100pF)
GND (recommended)
When using this IC, the following external components should be used:
Rctl:
This resistor is used to improve ESD performance. 1kΩ is recommended.
This capacitor is used for RF de-coupling and must be used for all applications.
100pF is recommended.
CRF:
Cbypass: This capacitor is used for DC line filtering. 100pF is recommended.
– 5 –
CXG1144EN
Typical Characteristics
Frequency vs. Insertion loss
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
Frequency [GHz]
Frequency vs. Isolation
0
5
10
15
20
25
30
35
40
45
50
0
0.5
1.0
1.5
2.0
Frequency [GHz]
– 6 –
CXG1144EN
Package Outline
Unit: mm
10PIN VSON(PLASTIC)
+ 0.1
0.8 – 0.05
0.6
2.5
0.05
S
A
S
6
10
PIN 1 INDEX
1
5
B
x2
0.4
0.8
0.35 ± 0.1
S
0.15
B
x4
0.15
AB
S
A
B
0.05 M
S
Solder Plating
0.13 ± 0.025
+ 0.09
0.14 – 0.03
TERMINAL SECTION
1) The dimensions of the terminal section apply to the
NOTE:
ranges of 0.1mm and 0.25mm from the end of a terminal.
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
COPPER ALLOY
0.013g
SONY CODE
VSON-10P-01
EIAJ CODE
JEDEC CODE
PACKAGE MASS
LEAD SPECIFICATIONS
ITEM
LEAD MATERIAL
LEAD TREATMENT
SPEC.
COPPER ALLOY
Sn-Bi 2.5%
LEAD TREATMENT THICKNESS 5-18µm
Sony Corporation
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