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CY26187-1 [ETC]

Clocks and Buffers ; 时钟和缓冲器\n
CY26187-1
型号： CY26187-1
厂家： ETC    ETC
描述：

Clocks and Buffers
时钟和缓冲器\n

时钟
文件： 总6页 (文件大小：90K)
中文：  中文翻译
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PRELIMINARY  
CY26187-1  
Broadcom Reference Design  
Clock Generator  
2CY26187-1-1CY2295  
Features  
Benefits  
• Integrated phase-locked loop  
• Low skew, low jitter, high accuracy outputs  
• 3.3V Operation  
Highest performance PLL tailored for multimedia applications  
Meets critical timing requirements in complex system designs  
Enables system and application compatibility  
Broadcom Reference  
Part Number  
Outputs  
Design  
Input Frequency  
Output Frequencies  
CY26187-1  
2
SDK5680  
25 MHz  
1 copy of 142 MHz, 1 copy 35.5 MHz (3.3V)  
Logic Block Diagram - CY26187-1  
CLK_OUT_1  
CLK_OUT_2  
OUTPUT  
MULTIPLEXER  
AND  
XIN  
Q
OSC.  
Φ
XOUT  
VCO  
DIVIDERS  
P
PLL  
OE  
VSS  
VDD  
Pin Configuration  
CY26187-1  
8-pin SOIC  
XOUT  
1
8
7
6
5
XIN  
2
3
4
CLK_OUT_1  
CLK_OUT_2  
VDD  
AVDD  
OE  
AVSS  
Cypress Semiconductor Corporation  
Document #: 38-07130 Rev. *A  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised December 14, 2002  
PRELIMINARY  
CY26187-1  
Pin Summary CY26187-1  
Name  
Pin Number  
Description  
XIN  
1
2
3
4
5
6
7
8
25-MHz Reference Crystal Input  
Analog Voltage Supply  
Output Enable (0 = off; 1 = on)  
Ground  
AVDD  
OE  
AVSS  
VDD  
Voltage Supply  
CLK_OUT_2  
CLK_OUT_1  
XOUT[1]  
35.5-MHz Clock Out  
142-MHz Clock Out  
Reference Crystal Output  
Absolute Maximum Conditions  
Parameter  
VDD  
Description  
Min.  
–65  
Max.  
7.0  
Unit  
V
Supply Voltage  
TS  
Storage Temperature[2]  
Junction Temperature  
Digital Inputs  
125  
°C  
°C  
V
TJ  
125  
VSS – 0.3  
VDD + 0.3  
VDD + 0.3  
2000  
Digital Outputs referred to VDD  
Electro-Static Discharge  
VSS – 0.3  
V
V
Recommended Operating Conditions  
Parameter  
VDD  
Description  
Min.  
3.135  
0
Typ.  
Max.  
3.465  
70  
Unit  
V
Operating Voltage  
3.3  
TA  
Ambient Temperature  
°C  
CLOAD  
fREF  
Max. Load Capacitance  
CY26187-1 Reference Frequency  
15  
pF  
25  
MHz  
Power-up time for all VDD's to reach minimum  
specified voltage (power ramps must be monotonic)  
tPU  
0.05  
500  
ms  
DC Electrical Characteristics  
Parameter  
IOH  
Description  
Output High Current  
Output Low Current  
Input Capacitance  
Input Leakage Current  
Supply Current  
Conditions  
VOH = VDD – 0.5, VDD = 3.3V  
VOL = 0.5, VDD = 3.3V  
Min.  
Typ.  
Max.  
Unit  
mA  
mA  
pF  
12  
12  
24  
24  
IOL  
CIN  
IIZ  
7
5
µA  
IDD  
Sum of core and output current  
35  
mA  
AC Electrical Characteristics (VDD = 3.3V)[3]  
Parameter  
Description  
Output Duty Cycle  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Clock Jitter  
Conditions  
Min.  
45  
Typ.  
50  
Max.  
Unit  
%
Duty Cycle is defined in Figure 1, 50% of VDD  
Output Clock Rise Time, 20% - 80% of VDD  
Output Clock Fall Time, 80% - 20% of VDD  
Peak-to-Peak period jitter  
55  
t3  
0.8  
0.8  
1.4  
1.4  
V/ns  
V/ns  
ps  
t4  
t9  
300  
3
t10  
PLL Lock Time  
ms  
Document #: 38-07130 Rev. *A  
Page 2 of 6  
PRELIMINARY  
CY26187-1  
Notes:  
1. Float XOUT pin if XIN is driven by reference clock (as opposed to crystal).  
2. Rated for 10 years.  
3. Not 100% tested  
Document #: 38-07130 Rev. *A  
Page 3 of 6  
PRELIMINARY  
CY26187-1  
.
Test Circuit  
AV  
DD  
CLK out  
CLOAD  
0.1 µF  
0.1 µF  
OUTPUTS  
VDD  
GND  
t3  
t4  
t1  
t2  
80%  
20%  
50%  
CLK  
CLK  
Figure 2. Rise and Fall Time Definitions  
Figure 1. Duty Cycle Definition; DC = t2/t1  
Ordering Information  
Broadcom Reference  
Design  
Ordering Code Package Name Package Type  
CY26187SC-1 S8 8-Pin SOIC  
Operating Range Operating Voltage  
Commercial 3.3V  
SDK5680  
Document #: 38-07130 Rev. *A  
Page 4 of 6  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
PRELIMINARY  
CY26187-1  
Package Diagram  
8-Lead (150-Mil) SOIC S8  
51-85066-A  
Document #: 38-07130 Rev. *A  
Page 5 of 6  
PRELIMINARY  
CY26187-1  
Document Title: CY26187-1 Broadcom Reference Design Clock Generator  
Document Number: 38-07130  
Issue  
Date  
Orig. of  
REV.  
**  
ECN NO.  
110095  
Change Description of Change  
02/19/02  
12/14/02  
CKN  
RBI  
New data sheet  
Power up requirements added to Operating Conditions Information  
*A  
121871  
Document #: 38-07130 Rev. *A  
Page 6 of 6  

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