E670-EDGE670 [ETC]
500 MHz Window Comparator ; 500 MHz的窗口比较器\n
| 型号： | E670-EDGE670 |
| 厂家： | 
ETC |
| 描述： | 500 MHz Window Comparator
|
| 文件： | 总12页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Edge670
500 MHz
Window Comparator
PRELIMINARY
HIGH-PERFORMANCE PRODUCTS – ATE
Features
Description
The Edge670 is a monolithic ATE pin electronics
comparator manufactured in a high-performance
complementary bipolar process. In automatic test
equipment, the Edge670 offers a window comparator
suitable for very fast, bidirectional channels in Memory,
VLSI, and Mixed-Signal test systems.
• 11V Common Mode Range
• Input Tracking > 6 V/ns with < ±25 ps
dispersion
• Low Leakage (<1 µA)
• Input Power Down Mode
(for extremely low leakage operation (<250 nA))
• Small footprint (32 pin TQFP)
The 670 is capable of tracking very fast edges and
passing sub-ns pulses over an 11V common mode range
while maintaining excellent timing accuracy. The
differential digital outputs are adjustable to
accommodate ECL levels, PECL levels, or custom levels
to interface directly with a CMOS ASIC.
The Edge670 is pin compatible with the Edge672, except
no load is present.
Functional Block Diagram
QA*
CVA
–
QA
IPD
QB
+
VINP
+
–
QB*
CVB
PECL
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Revision 3 / July 20, 2001
1
Edge670
HIGH-PERFORMANCE PRODUCTS – ATE
PRELIMINARY
PIN Description
Pin Name
Pin #
Description
Comparator
19
VINP
Analog voltage input for the window comparator. The VINP connects to both
of the non-inverting (+) inputs of the comparators.
4, 5
8, 7
QA / QA*
QB / QB*
Differential output pins from the window comparator.
15, 16
CVA, CVB
Analog input pins used to set the high and low levels for the window
comparator.
14
IPD
TTL compatible input which activates the input power down mode of the
window comparator.
Power
6, 18
VEE
3, 9, 17, 20
10
Negative power supply.
VCC
Positive power supply.
GND
Device ground.
PECL
11
Analog power supply which sets the comparator output levels.
Test Pins
12
13
CATHODE
ANODE
Cathode and anode ends of a series string of diodes used to monitor the die
temperature.
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Edge670
HIGH-PERFORMANCE PRODUCTS – ATE
PRELIMINARY
PIN Description (continued)
25
32
1
N/C
N/C
N/C
VCC
QA
N/C
N/C
N/C
VCC
VINP
VEE
VCC
QA*
VEE
QB*
QB
17
9
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Edge670
HIGH-PERFORMANCE PRODUCTS – ATE
PRELIMINARY
Circuit Description
Hysteresis
Window Comparator
Hysteresis is a measure of the change in threshold
voltage as a function of the comparator output state
(see Figure 2). Typically, hysteresis is used to prevent
multiple comparator output transitions due to slow input
slew rates in a noisy environment. These slower inputs
remain in the transition region for longer periods of time,
allowing any noise present to cause repeated threshold
crossings.
Introduction
The Edge670 has two comparators connected on-chip
as a window comparator to determine whether the DUT
is in a high, low, or indeterminate state.
Power Supply Sequencing
The Edge670 is designed with 4 mV of hysteresis. This
hysteresis is non-adjustable and requires no external
support. The amount of hysteresis was chosen to allow
stable and reliable transitions in most system
environments, without noticeably affecting the
comparator performance.
The following sequence should be used when powering
up the Edge670.
1. VEE
2. VCC
3. Analog Inputs (VINP, CVA, CVB)
Actual Threshold Voltage
2 mV
Functionality
4 mV
The VINP pin is tied to the positive inputs of both
comparators (see Figure 1).
Programmed Threshold
Voltage
Input Condition
VINP > CVA
VINP < CVA
VINP > CVB
VINP < CVB
Output Condition
QA = High; QA* = Low
QA = Low; QA* = High
QB = High; QB* = Low
QB = Low; QB* = High
Figure 2. Hysteresis
The effects of hysteresis are visible in two categories -
offset voltage and propagation delay. The amount of
hysteresis must be large enough to overcome the system
noise floor, yet small enough not to increase offset
voltage effects significantly.
QA*
QA
CVA
–
+
Input Protection
VINP
+
QB
The VINP pin has an internal 50Ω series resistor and
two over-voltage diodes capable of shunting up to 100
mA (see Figure 3) and, therefore, requires no external
protection circuitry. The over-voltage input range that
the comparator can withstand is determined by the power
supply rails and the following equations:
–
QB*
CVB
Figure 1. Comparator Functionality
Thresholds
VEE – .7 – (100 mA * 50Ω) < VINP <
VCC + .7 + (100 mA * 50Ω)
CVA and CVB are the two comparator threshold levels.
These inputs are high impedance voltage controlled
inputs that determine at which VINP input voltage the
comparator will change states.
or
VEE – 5.7V < VINP < VCC + 5.7V.
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Edge670
HIGH-PERFORMANCE PRODUCTS – ATE
PRELIMINARY
Circuit Description (continued)
two modes. With IPD = low, the comparator is in its
normal high speed mode, supporting maximum AC
performance.
VCC
With IPD = high, the comparator is in Power Down Mode.
The input bias current decreases to < 100 nA. The
comparator still functions, but can track edges only up
to 25 mV/ns.
–
+
50
VINP
+
Thermal Monitor
–
The Edge670 includes an on-chip thermal monitor
accessible through the CATHODE and ANODE. These
nodes connect to five diodes in series (see Figure 4)
and may be used to accurately measure the junction
temperature at any time.
VEE
Figure 3. Input Protection
An external bias current of 100 µA is injected through
the string, and the measured voltage corresponds to a
specific junction temperature with the following equation:
For a wider protected input range, an additional external
series resistor may be added.
Comparator PECL Output Capability
Tj[°C] = {(ANODE - CATHODE)/5 - .7} / (-.00208).
PECL is a variable analog voltage power supply that
determines the common mode voltage of the comparator
digital outputs. With PECL connected to ground, the
Edge670 generates standard differential ECL outputs.
However, the outputs will track the PECL input, and
remaining one diode drop below it as PECL is varied
between ground and +5V. By setting PECL appropriately,
a fully differential comparator output may interface
directly to a CMOS ASIC without any translators.
ANODE
Bias Current
Temperature coefficient = –10 mV/ C
˚
Input Power Down
The Edge670 comparator has a mechanism where it can
drastically reduce the input bias current flowing into the
VINP pin, while still maintaining a functional comparator.
In this mode, however, the comparator slows down
significantly and can no longer track fast edges, in
particular, fast falling edges.
CATHODE
Figure 4. Thermal Diode String
The IPD pin is a TTL compatible input which controls the
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Edge670
HIGH-PERFORMANCE PRODUCTS – ATE
PRELIMINARY
Circuit Description (continued)
Delay Dispersion
Given a constant temperature and voltage environment Propagation delay dispersion is defined as the maximum
(within the bounds of the recommended operating deviation of the propagation delay taken at the eight
conditions), the propagation delay dispersion (TSD) measurement points (see Figure 10) for 1V and 3V input
indicates how much variation in propagation delay time signals described below. The parameters of interest are:
can be expected for one comparator over a wide range
of input conditions. Thus, the propagation delay of a
comparator can be described as:
• Slew rate
• Edge direction
• Overdrive
Tpd ± TSD
• Common mode voltage.
where TPD is the nominal delay that will vary with
temperature and voltage, and part to part. In many ATE Low dispersion numbers indicate the accuracy of a
applications, Tpd is calibrated or compensated for on a system under a variety of input conditions, and are an
channel-by-channel basis. TSD includes factors that important figure of merit for any comparator.
normally may be difficult to calibrate, and therefore
directly impact overall system timing accuracy.
While not production tested, the Edg670 is designed
specifically to exhibit low dispersion. The typical Edge670
will show less than 25 ps Tpd dispersion.
3 V
2.7 V
3V / NS
SLEW RATE
INPUT
THRESHOLD
LEVELS
3 V
1V / NS
SLEW RATE
.3 V
0 V
-0.8 V
-1.0 V
3V / NS
SLEW RATE
INPUT
THRESHOLD
LEVELS
1V
1V / NS
SLEW RATE
-1.6 V
-1.8 V
Figure 10. Dispersion Measurement Conditions
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Edge670
HIGH-PERFORMANCE PRODUCTS – ATE
PRELIMINARY
Package Information
32-Pin TQFP
7mm x 7 mm
TOP VIEW
PIN Descriptions
4
D
D / 2
b
3
e
E
4
N / 4 TIPS
E / 2
SEE DETAIL "A"
0.20
C
A – B
D
4 X
BOTTOM VIEW
5
7
D1
D1 / 2
E1 / 2
E1
5
7
0.20
H
A – B
D
4 X
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Edge670
HIGH-PERFORMANCE PRODUCTS – ATE
PRELIMINARY
Package Information (continued)
DETAIL "A"
DETAIL "B"
0
MIN.
3
0.08 / 0.20 R.
–
S
e / 2
0.05
DATUM
PLANE
A1
A2
0.25
– H –
GAUGE PLANE
C.08
R. MIN.
0 – 7
b
0.20 MIN.
1.00 REF.
L
SECTION C–C
ddd
M
C
A – B
S
D S
9
8 PLACESꢀ
11 / 13
WITH LEAD FINISH
b
A
– H –ꢀ
2
0.05
/ / 0.10
C
Leadꢀ
Cross Section
ccc
– C –ꢀ
0.09 / 0.20
0.09 / 0.16
M
SEE DETAIL "B"
b
1
BASE METAL
JEDEC VARIATION
Notes:
1.
2.
All dimensions and tolerances conform to ANSI Y14.5-1982.
Datum plane -H- located at mold parting line and coincident
with lead, where lead exits plastic body at bottom of parting
line.
Datums A-B and -D- to be determined at centerline between
leads where leads exit plastic body at datum plane -H-.
To be determined at seating plane -C-.
AC
Sym
Min
Nom
Max
Note
A
A1
A2
D
1.60
0.15
1.45
0.05
1.35
0.10
1.40
3.
4.
5.
6.
7.
8.
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
0.60
4
Dimensions D1 and E1 do not include mold protrusion.
“N” is the total # of terminals.
D1
E
7, 8
4
These dimensions to be determined at the datum plane -H-.
Package top dimensions are smaller than bottom dimensions
and top of package will not overhang bottom of package.
Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 mm total in excess of the b
dimension at maximum material condition. Dambar cannot be
located on the lower radius or the foot.
E1
L
7, 8
0.45
0.15
0.75
9.
M
N
32
0.80 BSC
0.37
e
10. Controlling dimension: millimeter.
11. Maximum allowable die thickness to be assembled in this
package family is 0.30 millimeters.
12. This outline conforms to JEDEC publication 95, registration
MO-136, variations AC, AE, and AF.
b
0.30
0.30
0.45
0.40
0.10
0.20
9
b1
ccc
ddd
0.35
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Edge670
HIGH-PERFORMANCE PRODUCTS – ATE
PRELIMINARY
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Positive Power Supply
Negative Power Supply
VCC
VEE
8.5
-8.5
13.0
0
11.5
-5.2
16.7
3.3
12.0
-4.5
17.0
5.0
V
V
V
V
Total Analog Supply
VCC - VEE
PECL
Comparator Output Positive Supply
Absolute Maximum Ratings
Parameter
Symbol
Min
Typ
Max
Units
Positive Supply (Relative to GND)
Negative Supply (Relative to GND)
Total Power Supply
VCC
VEE
0
+13.0
0
V
V
V
V
-9.0
VCC - VEE
PECL
+20.0
+6.0
Comparator Output Positive Supply
0
0
Digital Output Currents
QA, QA*, QB, QB*
50
mA
Comparator Input to Threshold
VINP - CVA
VINP - CVB
-13
-13
+13
+13
V
V
Analog Voltages
CVA, CVB
VEE
VCC
V
Ambient Operating Temperature
Storage Temperature
TA
TS
TJ
-55
-65
+145
+150
+150
+160
oC
oC
oC
oC
Junction Temperature
Process Temperature (<30 hours)
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at these, or any other conditions
beyond those listed in the operational sections of this specification are not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
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Edge670
HIGH-PERFORMANCE PRODUCTS – ATE
PRELIMINARY
DC Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Threshold Voltage
CVA, CVB
VINP
VEE + 2.9
VEE + 2.9
-11
VCC - 2.9
VCC - 2.9
+11
V
V
V
Input Voltage Range
Input Differential Voltage
VINP - CVA, B
Threshold Input Current
IPD Pin Input Current
-50
+50
+10
µA
µA
-150
VINP Input Current (Note 1)
Normal Operation IPD = 0
IPD Mode IPD = 1
IBIAS
IBIAS
-1
-250
+1
+250
µA
nA
Offset Voltage
VOS
-50
+50
mV
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Comparator Hysteresis
CMRR
PSRR
60
60
4
dB
dB
mV
Digital Output Swing
|QA - QA*|
|QB - QB*|
600
600
700
700
1,000
1,000
mV
mV
Power Supply
Positive Supply Current
Negative Supply Current
PECL Supply Current (Note 2)
ICC
IEE
IDD
30
40
55
44
60
16
60
80
95
mA
mA
mA
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
Note 1: Tested at +7V and –1V.
Note 2: Assumes no digital output current
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Edge670
HIGH-PERFORMANCE PRODUCTS – ATE
PRELIMINARY
AC Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Propagation Delay (Notes 1, 2)
Tpd
1.0
2.0
4.0
ns
Propagation Delay Dispersion (Note 2)
800 mV
3V
5V
-100
-100
-100
< 25
< 25
< 25
+100
+100
+100
ps
ps
ps
Input Slew Rate Tracking (Note 2)
IPD = 0
IPD = 1
5.0
25
6.0
V/ns
mV/ns
Input Capacitance
Cin
1.5
pF
ps
ns
Output Rise and Fall Times (20% to 80%)
Minimum Pulse Width (Note 2)
Tr, Tf
250
1.5
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
Note 1:
Note 2:
Assumes normal operating mode of IPD = 0.
Guaranteed by characterization. This parameter is not production tested
Ordering Information
Model Number
Package
E670CTF
32 pin 7 mm x 7 mm TQFP
(670 Die (Comparator Only))
EVM670CTF
Edge670 Evaluation Board
Contact Information
Semtech Corporation
High-Performance Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
2000 Semtech Corp.
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Edge670
HIGH-PERFORMANCE PRODUCTS – ATE
PRELIMINARY
Revision History
Current Revision: July 20, 2001
Previous Revision: March 5, 2001
Page #
4
Section Name
Previous Revision
Current Revision
Add: Power Supply Sequencing
Circuit Description
Section
Current Revision: March 5, 2001
Previous Revision: August 12, 2000
Page #
5
Section Name
Previous Revision
Current Revision
Update Figure 3
Circuit Description
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