FMS9875KGC100X [ETC]
;
| 型号： | FMS9875KGC100X |
| 厂家： | 
ETC |
| 描述： | 转换器 |
| 文件： | 总29页 (文件大小：482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FMS9875
GBR YP P Graphics Digitizer
B R
Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL
The ADC sampling clock can be derived from either an
external source or from incoming horizontal sync using the
Features
• 108/140 Ms/s conversion rate
• RGB and YPBPR clamps
• 444 and 422 output timing
• Adjustable Gain and offset
• Internal Reference Voltage
• I2C/SMBus compatible Serial Port
• 100-pin package
internal PLL. Setup and control is via registers accessible
through an SMBus/I2C compatible serial port.
Input amplitude range is 500–1000mV with either DC or AC
coupling. AC coupled inputs can be clamped to program-
mable midpoint/bottom levels or to external reference levels
using either internal or externally generated clamp timing.
Common to the three channels are clamp pulses, a bandgap
reference voltage and clocks derived from the HSYNC PLL
or an external clock source. Digital data output levels are
2.5–3.3V CMOS compliant.
Applications
• YPBPR Digitizers
• Projectors
• TV sets
Power is derived from a single +3.3 Volt power supply. Package
is a low cost 100-lead MQFP. Performance specifications are
guaranteed over 0°C to 70°C.
Description
As a fully integrated graphics interface, the FMS9875 can
digitize RGB orYPBPR video signals at resolutions up to
1280 x 1024 with 75 Hz refresh rate. Compatible video
formats include NTSC-601, PAL-601, SMPTE 293M,
SMPTE 296M and SMPTE 274M.
Product Number
FMS9875KAC100
FMS9875KAC140
Speed
108 Ms/s
140 Ms/s
Block Diagram
GYIN
Gain &
Offset
Bottom
Clamp
DGY7-0
A/D
GYREF
Bottom/
Midpoint
Clamp
BPIN
Gain &
Offset
444/422
A/D
A/D
DBP7-0
DRP7-0
BPREF
Bottom/
Midpoint
Clamp
RPIN
Gain &
Offset
444/422
RPREF
ICLAMP
VREFIN
Reference
VREFOUT
SCK
CLAMP
INVSCK
XCK
ICLAMP
Timing
Generator
DCK
DCK
HSOUT
HS
PXCK
HSIN
COAST
LPF
PLL
SDA
SCL
A0
A1
SYNC
Stripper
ACSIN
DCSOUT
Control
PWRDN
REV. 1.2.15 1/14/02
PRODUCT SPECIFICATION
FMS9875
A/D conversion range can be matched to the amplitude of the
incoming video signal by programming Gain Registers
GGY, GBP and GRP, which vary sensitivity (LSB/volt) over
a 2:1 range. Incoming video signal amplitudes varying from
0.5 to 1.0 volt can be accommodated.
Architectural Overview
Three separate digitizer channels are controlled by common
timing signals derived from the Timing Generator. A/D clock
signals can be derived from either a PLL or an external clock
XCK. With the PLL selected, A/D clocks track the incoming
horizontal sync signal connected to the HSIN input. Setup is
controlled by registers that are accessible through the serial
interface.
Input offset voltage of each converter is programmable in 1
LSB steps through the 6-bit OSGY, OSBP and OSRP regis-
ters. Range of adjustment is equivalent to –31 to +32 LSB.
Conversion Channels
A/D Converter
Typical RGB or YPBPR input signals, GYIN, BPIN, and
RPIN are ground referenced with 700mV amplitude. If a
sync signal is embedded then the usual format is sync on
green or Y with the sync tip at ground, the black level
elevated to 300mV and peak green at 1000mV. Either type
of input can be accepted by using the clamp function with
AC coupling.
Each A/D converter digitizes the analog input into 8-bit data
words. Latency is 5–51/2 clock cycles, depending upon the
state of the INVSCK pin.
VREFIN is the source of reference voltage for the three A/D
converters. VREFIN can be connected to either the internal
bandgap voltage, VREFOUT or an external voltage.
Clamps
Output Data Configuration
AC coupled input video signals must be level shifted to
match the signal and A/D converter reference levels during
the back porch (see Figure 1). Y/G inputs should be clamped
to the A/D converter lower reference level. PBPR signals
should be clamped to the A/D converter midrange level
(nominally 350 mV), which is 50% of full scale (nominally
700 mV).
For RGB outputs, data format is unsigned binary: 00
corresponds to the lowest input; FF corresponds to the
highest input.
For YPBPR outputs, the data format is:
• Y (0 to 700mV input): unsigned binary.
• PBPR ( 350mV input): twos-complement or offset binary.
+350 mV
PBIN, PRIN
Output data format is:
-350 mV
+700 mV
• 24-bit YPBPR444
• 16-bit YPBPR422
YGIN
With 422 sampling, PBPR samples are coincident with even
samples of Y, beginning with 0.
ICLAMP
HSOUT, L-to-H transition identifies the first sample.
Figure 1. Clamping to the back-porch
Timing and Control
Clamp pulses, ICLAMP, are derived from internal Timing
and Control logic or from the external CLAMP input. Clamp
timing is common to the three input channels.
Timing and Control logic encompasses the Timing Generator,
PLL and Serial Interface.
Timing Generator
With the A/D range set to 700mV ground referenced, clamp
levels are:
All internal clock and synchronization signals are generated
by the Timing Generator. Master Clock source is either the
PLL or the external clock input, XCK. Register bit, XCKSEL
selects the Master Clock source. Two clocks are generated.
• RGB: 000mV
• Y: 000mV
• PBPR: +350mV
Sampling clock, SCK is supplied to all three A/D converters.
Phase of SCK (relative to HSIN) can be adjusted in 32 11.25
degree phase increments using the 5-bit PHASE register.
Clamp levels can be set through the registers or through the
YGREF, BPREF and RPREF pins.
Output data clocks, DCK and DCK are provided for
synchronizing data transfer from the digitizer outputs.
DCK and DCK are slaved to SCK.
Gain and Offset
Gain and Offset registers serve two functions: 1) Adjustment
of contrast and brightness by setting RGB values in tandems.
2) Matching the gain and offsets between channels, by
setting RGB values individually to obtain the same output
levels at zero and full-scale.
Incoming horizontal sync HSIN is propagated by the Timing
and Control to HSOUT with a delay that aligns the leading
edge with the output data.
2
REV. 1.2.15 1/14/02
FMS9875
PRODUCT SPECIFICATION
Phase Locked Loop
VCO frequency to be maintained. Missing horizontal sync
pulses during the vertical interval can cause tearing at the top
of a picture, if COAST is not used.
With a horizontal sync signal connected to the HSIN input
pin, the PLL generates a high frequency internal clock sig-
nal, PXCK that is fed to the Timing and Control logic. Fre-
quency of PXCK is set by the register programmable PLL
divide ratio, PLLN.
Two pixels per clock mode is set by programming the PLL
to half the pixel rate. By toggling the INVCK pin between
frames, even and odd pixels can be read on alternate frames.
COAST is an input that disables the PLL lock to the horizon-
tal sync input, HSIN. If HSIN is to be disregarded for a
period such as the vertical sync interval, COAST allows the
Serial Interface
Registers are accessed through an I2C/SMBus compatible
serial port. Four serial addresses are pin selectable.
Pin Assignments
100-Lead MQFP (KG)
DYG (7)
DYG (6)
DYG (5)
DYG (4)
76
77
78
79
50
49
48
47
VDDO
GND
NC
NC
DYG (3)
DYG (2)
DYG (1)
DYG (0)
GND
80
81
82
83
84
46
45
44
43
42
NC
NC
NC
NC
GND
VDDO
DCK
DCK
85
86
87
88
89
90
91
92
41
40
39
38
37
36
35
34
GND
GND
VDDP
GND
VDDP
GND
LPF
HSOUT
DCSOUT
GND
VDDO
GND
XCK
GND
GND
VDDA
93
94
95
33
32
31
VDDP
GND
COAST
30
29
28
27
26
HSIN
GND
GND
VDDP
VDDP
PWRDNB
REFOUT
REFIN
96
97
98
99
VDDA
VDDA
100
REV. 1.2.15 1/14/02
3
PRODUCT SPECIFICATION
FMS9875
Pin Descriptions
Pin Name
Pin No. Type/Value Pin Function Description
Converter Channels
YGIN, BPIN, RPIN 3, 9, 15
Input
Input
Analog Inputs. RGB or YPBPR.
YGREF, BPREF
,
4, 10, 16
Clamp Reference Inputs. Voltage reference inputs for YG, BP and
RPREF
RP clamps.
DYG7-0
76–83
63–70
51–58
Output
Output
Output
Luminance/Green Channel Data Output.
PB/Blue Channel Data Output.
DPB7-0
DPR7-0
PR/Red Channel Data Output.
Timing Generator
CLAMP
21
20
Input
Input
External Clamp Input.
INVSCK
Invert Sampling Clock. Inverts SCK, the internal clock sampling the
analog inputs. Supports Alternate Pixel Sampling mode for capture
pixel rates up to 216Ms/s.
XCK
34
Input
External Clock input. Enabled if register bit, XCKSEL = H.
Replaces PXCK clock generated by PLL. If unused, connect to
ground through a 10kΩ resistor.
DCK
DCK
86
87
Output
Output
Output Data Clock. Clock for strobing output data to external logic.
Output Data Clock Inverted. Inverted clock for strobing output data
to external logic.
HSOUT
88
Output
Horizontal Sync Output. Reconstructed HSYNC delayed by
FMS9875 latency with leading edge synchronized to start of data
output. Polarity is always active HIGH.
Phase Locked Loop
HSIN
30
31
Schmitt
Input
Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V
source should be clamped at 3.3V or current limited, to prevent
overdriving ESD protection diodes.
COAST
PLL COAST. Extraneous or missing horizontal sync pulses can be
ignored by asserting the COAST input. With COAST asserted, the
HSIN signal is ignored by the PLL without affecting PXCK and the
derived clocks: SCK, DCK and DCK. With register bit, COASTPOL = 1:
COAST = L: PLL locked to HSIN.
COAST = H: PLL VCO input floats with HSIN disregarded
COAST polarity may be inverted using the COASTPOL register bit.
LPF
35
Passive
PLL Low Pass Filter. Connect recommended PLL filter to LPF pin.
(see Schematic, PLL Filter)
Sync Stripper
ACSIN
2
Analog Composite Sync Input. Input to sync stripper with 150mV
threshold.
DCSOUT
Control
SDA
89
Digital Composite Sync Output. Output from sync stripper.
22
23
24
25
96
Bi-directional Serial Port Data. Bi-directional data (I2C/SMBUS).
SCL
Input
Input
Input
Input
Serial Port Clock. Clock input (I2C/SMBUS).
Address bit 0. Lower bit of serial port address.
Address bit 1. Upper bit of serial port address.
A0
A1
PWRDN
Power Down/Output Control. Powers down the FMS9875 with
outputs high impedance.
4
REV. 1.2.15 1/14/02
FMS9875
PRODUCT SPECIFICATION
Pin Descriptions
Pin
Name
Pin No.
Pin Function Description
Power and Ground
VDDA
VDDP
5, 7, 11, 13, 17, 19, 95, 99, 100
26, 27, 33, 37, 39
ADC Supply Voltages. Provide a quiet noise free voltage.
PLL Supply Voltage. Most sensitive supply voltage.
Provide a very quiet noise free voltage.
VDDO
GND
50, 60, 62, 72, 85, 91
Digital Output Supply Voltage. Decouple judiciously to
avoid propagation of switching noise.
1, 6, 8, 12, 14, 18, 28, 29, 32, 36, 38, 40, Ground. Returns for all power supplies. Connect ground
41, 42, 49, 59, 61, 71, 84, 90, 92, 93, 94 pins to a solid ground-plane.
VREFIN
98
Voltage Reference Input. Common reference input to
RGB converters. Connect to VREFOUT, if internal
reference is used.
VREFOUT
97
Voltage Reference Output. Internal band-gap reference
output. Tie to ground through a 0.1µF capacitor.
Addressable Memory
Register Map
Name
Address
Function
Default (hex)
PLLN11-4
00
PLL divide ratio, MSBs. PLLN + 1 = total number of
69 (1693)
pixels per horizontal line.
PLLCTRL
01
PLL Control Register.
D0 (1693)
1. Lower four bits of PLL divide ratio.
2. PLL Subdivide phase.
3. PLL Subdivide ratio.
GGY7-0
02
Gain, green/luminance channel. Adjustable from 70 to
80
140%.
GBP7-0
GRP7-0
03
04
05
Gain, blue/PB channel. Adjustable from 70 to 140%.
Gain, red/PR channel. Adjustable from 70 to 140%.
80
80
80
OSGY5-0
Offset, green/luminance channel. OSR5-0 is stored in
the six upper register bits 7-2. Default value is decimal 32.
OSGY5–0
X X
OSBP5-0
OSRP5-0
CD7-0
06
07
08
Offset, blue/PB channel. OSR5-0 is stored in the six
upper register bits 7-2. Default value is decimal 32.
80
80
80
OSBP5–0
X X
Offset, red/PR channel. OSR5-0 is stored in the six upper
register bits 7-2. Default value is decimal 32.
OSRP5–0
X X
Clamp delay. Delay in pixels from trailing edge of
horizontal sync.
CW7-0
09
0A
Clamp width. Width of clamp pulse in pixels.
80
F4
CONFIG 1
Configuration Register No. 1
REV. 1.2.15 1/14/02
5
PRODUCT SPECIFICATION
FMS9875
Name
Address
Function
Default (hex)
PHASE7-0
0B
Sampling clock phase. PHASE4-0 stored in upper
register bits 7-3. PHASE sets the sampling clock phase in
11.25° increments. Default value is decimal 16.
80
PHASE4–0
X X X
PLLCTRL
CONFIG 2
0C
0D
0E
0F
PLL Control.
24
00
00
00
Configuration Register No. 2.
Clamp Control Register.
Reserved.
Register Definitions
PLL Control Register (01)
Bit no.
Name
Type Description
1-0
SUBDIV1-0
R/W
PLL Subdivide ratio. Selects the ratio of the divider following the PLL.
00: divide-by 1
01: divide-by 2
10: divide-by 4
11: reserved
SUBDIV1–0
X X X X X X
2
PLLFAZ
R/W
PLL Sub-divider Phase. Selects the phase of the divide-by-2 output.
(Invalid for other outputs)
3
–
R/W
R/W
Reserved.
7-4
PLLN3-0
PLL divide ratio, LSBs. PLLN + 1 = total number of pixels per horizontal line.
PLLN3–0
X X X X
Configuration Register 1 (0A)
Bit no.
Name
Type Description
0
1
XCKSEL
R/W
R/W
R/W
R/W
R/W
External Clock Select. Select internal clock source.
0: Internal PLL
1: XCK input.
2
3
4
5
XCLAMPOL
XCLAMP
External Clamp Polarity. Select clamp polarity.
0: Active L.
1: Active H.
External Clamp Select. Select clamp source.
0: Internally generated by PLL referenced to HSIN.
1: External CLAMP input.
COASTPOL
HSPOL
Coast Polarity. Select COAST input polarity.
0: Active L.
1: Active H.
HSIN Polarity. Select horizontal sync input polarity. PLL is locked to selected
edge:
0: Falling edge.
1: Rising edge.
6
7
—
—
R
R
1:
1:
6
REV. 1.2.15 1/14/02
FMS9875
PRODUCT SPECIFICATION
PLL Configuration Register (0C)
Bit no.
1-0
Name
—
Type Description
4-2
IPUMP2-0
R/W
Charge Pump Current. Selects Charge Pump current (µA).
000: 50
001: 100
010: 150
011: 250
100: 350
101: 500
110: 750
111: 1500
6-5
7
FVCO1-0
R/W
R/W
VCO Frequency Range. Selects VCO frequency range (MHz).
00: 10–40
01: 10–70
10: 20–120
11: 20–150
—
Reserved.
0: Run.
1: (reserved).
Configuration Register 2 (0D)
Bit no.
Name
—
Type Description
0
3-1
4
—
R
Reserved. Set to 0.
REV
Revision Number. Die revision number.
OUTPHASE R/W
Output Data Phase. In the alternate pixel mode, selects either odd (1, 3, 5, …)
or even (2, 4, 6 ….) samples following the HSYNC leading edge to be emitted
from output data ports.
0: Even samples
1: Odd samples
5
6
7
TWOS
PRFIRST
422
R/W
R/W
R/W
PBPR Data Output Format.
0: Offset binary.
1: Two’s complement.
PBPR Data Output Timing.
0: PB data first, PR data second.
1: PR data first, PB data second.
Output Data Format.
0: 444
1: 422 with PBPR multiplexed onto the DBP7-0 output.
REV. 1.2.15 1/14/02
7
PRODUCT SPECIFICATION
FMS9875
Clamp Control Register (0E)
Bit no.
1-0
Name
—
Type Description
—
Reserved. Set to 00.
3-2
RPLEVEL
R/W
RP Clamp. Clamps R or PR input to selected level.
00: Clamp to internal 0 V.
01: Clamp to external voltage at RPREF input.
10: Clamp to internal mid-scale.
11: Clamp to high impedance.
5-4
7-6
BPLEVEL
GYLEVEL
R/W
R/W
BP Clamp. Clamps B or PB input to selected level.
00: Clamp to internal 0 V.
01: Clamp to external voltage at BPREF input.
10: Clamp to internal mid-scale.
11: Clamp to high impedance.
GY Clamp.
00: Clamp to internal 0 V.
01: Clamp to external voltage at YGREF input.
10: Clamp to internal mid-scale.
11: Clamp to high impedance.
8
REV. 1.2.15 1/14/02
FMS9875
PRODUCT SPECIFICATION
A plot of output codes versus input voltage has a staircase-
like shape. With FMS9875 Gain and Offset register values
set to match a nominal 700 mV input, Tables 1 and 2 show
the output codes in deciminal and binary, corresponding to
the mid-point input voltages of each step.
Functional Description
There are two major sections within the FMS9875:
1. Analog-to-digital Converter Channels, one for each
channel, GY, RP, BP and the voltage reference.
Note:
2. Timing and Control comprising the PLL, Timing
Generator, Sync Stripper and Serial Interface.
1. The midpoint of code 000 lies 1/2 of one code-size
below the 000/001 transition.
A/D Converter Channels
Each of the RGB/YPBPR channels consists of:
2. The midpoint of code 255 lies 1/2 of one code-size
above the 254/255 transition.
1. A clamp to set the lower reference of each G/Y, B and R
channel or the midpoint reference of the PB and PR
channels.
3. For AC coupled inputs, during the blanking period:
a) Y, G, B and R inputs should be clamped to the
FMS9875 bottom reference.
2. Gain and offset stages to match the A/D converter range
to input signal levels.
b) PB and PR inputs should be clamped to the FMS9875
mid-range level. (Half the range plus the offset
voltage)
3. An Analog-to-Digital Converter to digitize the analog
input.
Table 1.YP P and GBR Decimal Output Coding
B
R
PB, PR
Two’s Complement
Input (mV)
700
Y, G, B, R
255
Offset Binary
255
254
127
126
697.25
254
351.37
348.63
345.88
128
127
126
128
127
126
000
255
254
2.75
0
001
000
001
000
129
128
Table 2.YP P and GBR Binary Output Coding
B
R
Input (mV)
PB, PR
Offset Binary Two’s Complement
350 mV ref. 0 mV ref.
Y, G, B, R
1111 1111
1111 1110
700
350
1111 1111
1111 1110
0111 1111
0111 1110
697.25
347.25
351.37
348.63
345.88
1.37
-1.37
-4.12
1000 0000
0111 1111
0111 1110
1000 0000
0111 1111
0111 1110
0000 0000
1111 1111
1111 1110
2.75
0
-347.25
-350
0000 0001
0000 0000
0000 0001
0000 0000
1000 0001
1000 0000
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9
PRODUCT SPECIFICATION
FMS9875
Analog Inputs
2. External voltages levels connected to the GYREF, BPREF
and RPREF inputs. Nominal values are 0 mV for Y and
350 mV for PB and PR. Clamp Control Register bits
should be set as follows:
Input signal range is 500 to 1000mV to support conversion of
single-ended signals with a typical amplitude of 700mV p-p.
With the clamp active, each input can accommodate compos-
ite sync, a negative 300mV excursion.
Table 4. External Clamp Setup
Inputs are optimized for a source resistance of 37.5 to 75Ω.
To reduce noise sensitivity, the 400MHz input bandwidth
may be reduced by adding a small series inductor prior to the
75Ω terminating resistor. See Applications Section.
GYLEVEL
BPLEVEL
RPLEVEL
GBR
01
01
01
YPBPR
Clamps
External clamp levels should be established to match the
incoming signals. For example, with 650 mV peak-to-peak
PBPR signals, the mid-point should be set to 325 mV.
If the incoming signals are not ground referenced, a clamp
must be used to establish the incoming video range. Prior to
each A/D converter, each channel includes a clamp that
allows capacitively coupled input levels to be matched to the
A/D converter reference level when the clamp pulse is active.
Source of the clamp timing is determined by the XCLAMP
register bit.
Internal clamp timing is generated by the Timing and
Control Block. Position and width of the internal clamp
pulse, ICLAMP are programmable through registers CD and
CW. External clamp input is selected by register bit
XCLAMP and the external clamp polarity selected through
register bit XCLAMPOL. To disable the clamp for DC
coupled inputs, set XCLAMP = 1 with either of these
conditions:
Clamping levels depend upon the incoming signal format:
1. RGB. All signals must be clamped to the A/D converter
lower reference voltage, which is ground.
1. XCLAMPOL = 0 with input CLAMP = H.
2. XCLAMPOL = 1 with input CLAMP = L.
2. YPBPR. The Y signal must be clamped to ground.
PBPR signals must be clamped to the mid-level of the
A/D converter range, to establish the zero level of the
signed PBPR signals.
Best performance will be achieved with the clamp set active
for most of the black signal level interval between the trailing
edge of horizontal sync and the start of active video. Insufficient
clamping can cause brightness changes at the top of the image
and slow recovery from large changes in Average Picture
Level (APL). Recommended clamp delay value, CD is 0x10
to 0x20 for most standard video sources.
With 700 mV incoming signal levels, nominal clamp levels
are 0 mV for ground and 350 mV for mid-level. Offset and
gain control can be used to trim input levels to match the
clamp voltages.
Clamps levels can be derived from either of two sources:
1. Internal Voltages:
Analog-to-Digital Converter
Figure 2 is a block diagram of the ADC core with gain and
offset functions. G7-0, OS5-0, VIN and D7-0 generically refer
to the gain and offset register values, analog input and paral-
lel data output of any RGB channel.
a) Y and GBR signals are clamped to the A/D converter
lower reference voltage that can be adjusted by the
Offset register value.
b) PBPR signals are clamped to the A/D mid-scale v
oltage, which cannot be adjusted by the Offset
control. Instead, the data output is forced to code
128 during the clamping period.
Clamp Control Register bits should be set as follows:
Table 3. Internal Clamp Setup
GYLEVEL
BPLEVEL
RPLEVEL
GBR
00
00
00
10
00
10
YPBPR
10
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FMS9875
PRODUCT SPECIFICATION
VREF
G7-0
Gain
Register
D/A
IBIAS + IOFFSET
OS5-0
Current
D/A
Offset
Register
A/D Core
VIN
+
Track &
Hold
-
D7-0
A/D
RLEVEL
SCK
Figure 2. A/D Converter Architecture
Within the A/D converter core are the following elements:
Voltage offset from the common mode voltage at the invert-
ing input of the Track and Hold is:
1. Differential track and hold.
255 + G7–0
---------------------------- --------
500
255
VOS = ( OS5–0 – 31) •
•
•
•
2. Differential analog-to-digital converter.
255
D/A converter gain tracks A/D gain with 1 LSB of offset
corresponding to 1LSB of gain. Increasing the offset of a
video signal increases brightness of the picture. Data output
from the A/D converter is:
Setting the gain register value G7-0 (GRP7-0, GGY7-0, GBP7-0),
establishes the gain D/A converter voltage which is the upper
A/D reference voltage. Increasing the gain register value
reduces the output level. Conversion range is defined by the gain
setting according to Table 5.
D7–0 = S • VIN – ( OS5–0 – 31 )
•
Table 5. Gain Calibration
Impact of the offset values OSGY5-0, OSBP5-0, and OSRP5-0
is shown in Table 6.
G7-0
0
Conversion Range (mV)
500
700
102
255
Table 6. Offset Calibration
1000
OS5-0
0
Equivalent Offset (bits)
-31d
0
A/D Converter sensitivity is:
31
255
255
500
----------------------------
255 + G7 – 0
S = -------- •
LSB ⁄ mV
•
63
32d
Sampling Clock PHASE Adjustment
Offset is set through the Track and Hold, which translates the
ground referenced input to a differential voltage centered
around A/D common mode bias voltage.
Bandwidth of TV video is typically well below the horizon-
tal sampling rate. Consequently, PHASE has little impact on
images sampled in theYPBPR format or RGB signals derived
from a video source. By contrast, PC-generated image
quality is strongly impacted by the PHASE4-0 value. If
PHASE is not set correctly, any section of an image
consisting of vertical lines may exhibit tearing.
The 6-bit Offset D/A converter injects a current into RLEVEL
with two components:
1. IBIAS to establish the A/D common mode voltage.
2. IOFFSET to set the offset from the common mode level.
Figure 3 shows how an analog input, VIN is sampled by the
rising edge of SCK after a delay PHASE from the rising
edge of either PXCK or XCK. SCK can be delayed up to 32
steps in 11.25° increments by adjusting the register value,
PHASE4-0
.
REV. 1.2.15 1/14/02
11
PRODUCT SPECIFICATION
FMS9875
PHASE
PXCK/XCK
SCK
VIN
Sn
DCK
DA
Figure 3. Internal Sampling Clock, SCK Timing
Output data and clocks: DCK and DCK are delayed in tan-
dem with SCK relative to PXCK or XCK. There is a 5-51/2
clock latency between the data sample Sn and the corre-
amplitude modulation of the digitized data, D7-0, due to the
sampling clock jitter. To avoid corruption of the image, set-
ting the value PHASE7-0 is critical. PHASE4-0 should be
trimmed to position the sampling edge of SCK within the
zone of serendipity.
sponding data out DA7-0
.
Ideally, incoming pixels (PC generated) would be trape-
zoidal with fast rise-times and the sampling edge of the A/D
clock, SCK would be positioned along the level section of
the incoming pixel waveform as shown in Figure 4. There is
a narrow zone of uncertainly where sampling during pixel
rise time would cause an error in the value of the A/D data
output, D7-0, which is shown as a value, 0-255.
Zones of Uncertainty
RIN, GIN, BIN
SCK
D7-0
Zones of Uncertainty
RIN, GIN, BIN
SCK
Figure 6. Improper Pixel Sampling
Voltage References
An on-chip voltage reference is generated from a bandgap
source. VREFOUT is the buffered output of this source that
can be connected to VREFIN to supply a voltage reference
that is common to the three converter channels.
D7-0
Figure 4. Ideal Pixel Sampling
V
REFIN, with a nominal voltage of 1.25V, is the source of the
In practice, high-resolution pixels have relatively long rise-
times. As shown in Figure 5, there are narrow zones of seren-
dipity when the pixel amplitude is level. Samples are valid in
these zones.
differential reference voltages for each A/D converter.
Reference voltages supplied to the differential inputs of the
comparators in the A/D converters are derived from VREFIN
.
Digital Data Outputs
Zones of Serendipity
Input horizontal sync HSIN and outgoing data, D[7..0] are
resynchronized to the internal delayed sample clock, SCK.
Output timing relationships are defined in Figure 7. Latency of
the first pixel, N varies according to the mode:
RIN, GIN, BIN
SCK
1. Normal.
2. Alternate pixel sampling.
D7-0
Data transitions on the falling edge of the DCK clock. Pixel
data should be sampled on the rising edge of the DCK clock.
Figure 5. Acceptable Pixel Sampling
Levels are 3.3 volt CMOS. PWRDN = L sets the outputs
high-impedance. PWRDN = H enables the outputs.
Referring to Figure 6, when the sample clock, SCK has some
jitter, if the sampling edge occurs anywhere within the zone
of uncertainty where the pixel rise time is steep, there will be
12
REV. 1.2.15 1/14/02
FMS9875
PRODUCT SPECIFICATION
HSIN
PHASE
N
PXCK/XCK
SCK
GBRIN/YPBPRIN
DCK
P0
DCK
tSKEW
D0
D[7..0]
HSOUT
Figure 7. Output Timing
Figures 8 through 12 depict data output timing relative to the
sampling clock and inputs for all modes. Timing is referenced
to the leading edge of HSIN when the first sample is taken at
the rising edge of SCK. Register bit OUTPHASE, determines
if odd or even samples are directed to the data ports.
HS is the internal sync pulse generated from HSIN. SCK is
the internal A/D converter sampling clock.
Pixel sampling is referenced to the rising edge of HSIN.
Data outputs are delayed by 5 to 5.5 pixels. To allow for
clamping, start-of-active-video (SAV) can begin any time
after the falling edge of HSIN. End-of-active-video (EAV)
follows SAV any time before the next HSIN pulse.
Note the timing of the HSOUT waveform:
1. HSOUT is always active HIGH.
2. Leading edge of HSOUT is aligned to the leading or
trailing edge (selected by the HSPOL register bit) of
HSIN delayed by 5 to 5.5 pixels
3. Leading edge is aligned with DCK.
4. Trailing edge is linked to HSIN.
5. If HSIN does not terminate before mid-line, HSOUT is
forced low. A 50% duty cycle indicates that HSPOL is
incorrectly set.
GBRIN
HSIN
PXCK
HS
P0
P1
P2
P3
P4
P5
P6
P7
5 PIXEL DELAY
SCK
DCK
D0 D1 D2 D3 D4 D5 D6 D7
DGBR7-0
HSOUT
Figure 8. GBR Mode
REV. 1.2.15 1/14/02
13
FMS9875
PRODUCT SPECIFICATION
YPBPRIN
HSIN
PXCK
HS
P0
P1
P2
P3
P4
P5
P6
P7
5 PIXEL DELAY
SCK
DCK
DGY7-0
Y0
Y1 Y2 Y3
Y4 Y5 Y6
Y7
DBP7-0
DRP7-0
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7
HSOUT
Figure 9. YP P 444 Mode
B
R
YPBPRIN
P0
P1
P2
P3
P4
P5
P6
P7
HSIN
PXCK
HS
5 PIXEL DELAY
SCK
DCK
DGY7-0
DBP7-0
Y0
Y1 Y2 Y3
Y4 Y5 Y6
Y7
PB0 PR0 PB2 PR2 PB4 PR4 PB6 PR6
HSOUT
Figure 10. YP P 422 Mode
B
R
P0 P1 P2 P3 P4 P5 P6 P7
RGBIN
HSIN
PXCK
HS
5.5 PIXEL DELAY
SCK
DCK
D7-0
D1
D3
D5
D7
HSOUT
Figure 11. RGB Alternate Pixel Sampling Mode, (Even Pixels)
REV. 1.2.15 1/14/02
14
FMS9875
PRODUCT SPECIFICATION
P2
P0 P1
P3 P4 P5 P6 P7
RGBIN
HSIN
PXCK
HS
5 PIXEL DELAY
SCK
DATACK
D7-0
D0
D2
D4
D6
HSOUT
Figure 12. RGB Alternate Pixel Sampling Mode, (Odd Pixels)
On one frame, along each line, even pixels are sampled. On
the other, odd pixels are sampled.
Alternate Pixel Sampling Mode
A logic H on the INVSCK pin inverts the sampling phase of
SCK. In the Alternate Pixel Sampling Mode:
Alternate Pixel Sampling is similar to interlacing used in
broadcast video, except that the columns of pixels are inter-
laced instead of lines.
1. The PLL is run at half rate. SCK, DCK and DCK are
half rate.
2. CKINV is toggled between frames.
E1 E1 E1 E1 E1 E1 E1
O1 O1 O1 O1 O1 O1 O1
E1 E1 E1 E1 E1 E1 E1
O1 O1 O1 O1 O1 O1 O1
E1 E1 E1 E1 E1 E1 E1
O1 O1 O1 O1 O1 O1 O1
O E O E O E O E O E O E
O E O E O E O E O E O E
O E O E O E O E O E O E
O E O E O E O E O E O E
O E O E O E O E O E O E
O E O E O E O E O E O E
O E O E O E O E O E O E
O E O E O E O E O E O E
O E O E O E O E O E O E
O E O E O E O E O E O E
O E O E O E O E O E O E
O1E1O1E1O1E1O1E1O1E1O1E1O1E1
O1E1O1E1O1E1O1E1O1E1O1E1O1E1
O1E1O1E1O1E1O1E1O1E1O1E1O1E1
O1E1O1E1O1E1O1E1O1E1O1E1O1E1
O1E1O1E1O1E1O1E1O1E1O1E1O1E1
O1E1O1E1O1E1O1E1O1E1O1E1O1E1
O1E1O1E1O1E1O1E1O1E1O1E1O1E1
O1E1O1E1O1E1O1E1O1E1O1E1O1E1
Figure 14. Odd Pixels from Frame 1
Figure 13. Odd and Even Pixels in a Frame
O1E2 O1 E2O1E2O1E2 O1E2O1E2
O3E2 O3E2 O3E2 O3E2 O3E2 O3E2
O3E2 O3E2 O3E2 O3E2 O3E2 O3E2
O3E2 O3E2 O3E2 O3E2 O3E2 O3E2
O3E2 O3E2 O3E2 O3E2 O3E2 O3E2
O3E2 O3E2 O3E2 O3E2 O3E2 O3E2
O3E2 O3E2 O3E2 O3E2 O3E2 O3E2
O3E2 O3E2 O3E2 O3E2 O3E2 O3E2
O3E2 O3E2 O3E2 O3E2 O3E2 O3E2
O3E2 O3E2 O3E2 O3E2 O3E2 O3E2
O3E2 O3E2 O3E2 O3E2 O3E2 O3E2
O3E2 O3E2 O3E2 O3E2 O3E2 O3E2
O1E2O1 O1 O1 O1
E2 E2 E2 E2O1E2
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
O1E2 O1 E2O1E2O1E2 O1E2O1E2
O1E2 O1 E2O1E2O1E2 O1E2O1E2
O1E2 O1 E2O1E2O1E2 O1E2O1E2
O1E2 O1 E2O1E2O1E2 O1E2O1E2
O1E2 O1 E2O1E2O1E2 O1E2O1E2
O1E2 O1 E2O1E2O1E2 O1E2O1E2
O1E2 O1 E2O1E2O1E2 O1E2O1E2
O1E2 O1 E2O1E2O1E2 O1E2O1E2
O1E2 O1 E2O1E2O1E2 O1E2O1E2
O1E2 O1 E2O1E2O1E2 O1E2O1E2
O1E2 O1 E2O1E2O1E2 O1E2O1E2
O1E2 O1 E2O1E2O1E2 O1E2O1E2
E2
E2 E2 E2 E2O1E2
O1 O1 O1 O1 O1
E2 E2 E2 E2 E2O1E2
O1 O1 O1 O1 O1
E2 E2 E2 E2 E2O1E2
O1 O1 O1 O1 O1
E2 E2 E2 E2 E2O1E2
O1 O1 O1 O1 O1
E2 E2 E2 E2 E2O1E2
O1 O1 O1 O1 O1
E2 E2 E2 E2 E2O1E2
O1 O1 O1 O1 O1
E2 E2 E2 E2 E2O1E2
O1 O1 O1 O1 O1
E2 E2 E2 E2 E2O1E2
O1 O1 O1 O1 O1
E2 E2 E2 E2 E2 E2
O1
O1 O1 O1 O1 O1
E2
E2 E2 E2 E2 E2
O1
O1 O1 O1 O1 O1
Figure 13. Even Pixels from Frame 2
Figure 14. Subsequent Output
Combining Frames 2 and 3
Figure 15. Combined Frames
2 and 3
REV. 1.2.15 1/14/02
15
PRODUCT SPECIFICATION
FMS9875
Reference for the PLL is the horizontal sync input, HSIN
with polarity selected by the HSPOL bit.
Timing and Control
Timing and Control logic encompasses the PLL, Timing
Generator and Sync Stripper.
Frequency of the HSIN input is multiplied by the value PLLN
+ 1 derived from the PLLN11-4 and PLLN3-0 registers. PLLN
+ 1 should equal the number of pixels per horizontal line
including active and blanked sections. Typically blanking is
20–30% of active pixels. Divide ratios from 2–4095 are
supported. SCK, DCK and DCK run at a rate PLLN + 1
times the HSIN frequency.
Phase Locked Loop
VDDP
C2
R
C1
HSIN
Θi
The PLL consists of a phase comparator, charge pump VCO
and ÷N counter, with the charge pump connected through the
LPF pin to an external filter. These elements must be pro-
grammed to match the incoming video source to be captured.
IP VZ
Phase
Detector
Charge
Pump
VCO Θo
Sub-
divider
KV
Θ
o/N
Divider
SCK
(DCK)
Values of IPUMP and FVCO for common video standards
timing are shown in Table 7. Timing of many computer video
outputs does not comply with VESA recommendations.
PLLN should be optimized to avoid vertical noise bars on the
displayed image.
Two clock types originate in the PLL:
1. Data clocks DCK and DCK.
2. Internal sampling clock SCK.
Modes marked 2X are 2X-oversampled modes where the
number of samples per horizontal line is doubled. To select
this mode, the Phase-locked Loop Divide Ratio value must
changed from PLL1x to:
DCK and DCK are used to strobe data from the FMS9875 to
following digital circuits. SCK is the ADC sample clock
which has adjustable phase controlled through the PHASE
register. DCK and DCK are phase aligned with SCK.
PLL2x = 2 • (PLL1x + 1) – 1
Table 7. Recommended IPUMP and FVCO values for Standard Display Formats
Test
Rank
Refresh
Rate
Horizontal
Frequency Sample Rate FVCO
Standard
NTSC-601
PAL-601
Resolution
720 x 483i (1X)
720 x 583i (1X)
720 x 483i (2X)
720 x 583i (2X)
720 x 483p
IPUMP
101
SUBDIV
1-0
1-0
2-0
C
C
C
C
C
C
C
30 Hz
25 Hz
30 Hz
25 Hz
60 Hz
60 Hz
30 Hz
15.734 kHz
15.625 kHz
15.734 kHz
15.625 kHz
31.4685 kHz
45.00 kHz
13.5 MHz
13.5 MHz
27 MHz
00
00
00
00
00
01
01
2
101
NTSC-601
PAL-601
101
1
2
1
27 MHz
101
SMPTE 293M
SMPTE 296M
SMPTE 274M
VGA
27 MHz
111
1280 x 720p
1920 x 1080i
640 X 480
74.25 MHz
74.25 MHz
111
33.750 kHz
111
C
C
C
60 Hz
75 Hz
85 Hz
31.5 kHz
37.5 kHz
43.3 kHz
25.175 MHz
31.500 MHz
36.000 MHz
01
01
01
110
110
110
2
1
1
1
SVGA
XGA
C
C
CT
800 X 600
1024 X 768
1280 X 1024
60 Hz
75 Hz
85 Hz
37.9 kHz
46.9 kHz
53.7 kHz
40.000 MHz
49.500 MHz
56.250 MHz
01
01
01
110
110
110
C
C
C
60 Hz
75 Hz
85 Hz
48.4 kHz
60.0 kHz
68.3 kHz
65.000 MHz
78.750 MHz
94.500 MHz
10
10
11
110
110
110
SXGA
C
CT
CT
60 Hz
72 Hz
75 Hz
64.0 kHz
78.1 kHz
80.0 kHz
108.000 MHz
135.000 MHz
135.000 MHz
11
11
11
110
111
111
Notes:
1. VESA Monitor Timing Standards and Guidelines, September 17, 1998 and others.
2. Frame refresh rate is twice the field refresh rate for interlace (i) formats and equal to the field rate for progressive (p) formats.
3. When SUBDIV = 2, VCO runs at 2x sample rate.
1-0
16
REV. 1.2.15 1/14/02
FMS9875
PRODUCT SPECIFICATION
Values of IPUMP and FVCO are set through the PLL
Configuration Register (0x0C). Recommended external filter
components are shown in Figure 16. RF quality 10%
ceramic capacitors with X7R dielectric are recommended.
1. Use 2X over-sampling. For example with NTSC-601,
the 1X sample rate should be 13.5 MHz. If the divide
ratio is increased from 858 (PLLN = 857) to 1716
(PLLN = 1715), the sampling rate is 27 MHz.
2. Use 1X sampling by doubling the VCO frequency, then
dividing the PLL frequency by two. For example, with
NTSC-601, the divide ratio is doubled to 1716
VDDP
C1
0.18µF
(PLLN = 1715), then the sub-divide ratio is set to two
(SUBDIV1-0 = 01) to reduce the sampling rate from
27 MHz to 13.5 MHz with 858 pixels per line.
C2
0.018µF
R1
1.5K
LPF
COAST
When COAST is active, PLL lock to HSIN is disabled, while
the VCO frequency is retained. VCO frequency remains
stable over several lines without updates from HSIN.
COAST can be connected directly to the vertical sync signal
or supplied by the graphics controller. If 1/2H pulses are
present within HSIN, the COAST period must encompass all
1/2H pulses. COAST polarity may be inverted using the
COASTPOL register bit. In the description below, the setting
COASTPOL = H is used.
Figure 16. Schematic, PLL Filter.
Loop performance is established by setting:
1. VCO frequency range through FVCO1-0. (see Table 8)
2. Charge Pump Current through IPUMP2-0. (see Table 9)
3. External loop filter component values.
Table 8. VCO Frequency Bands
Operation of COAST is depicted in Figure 17. HSOUT
polarity is always positive. When COAST = L, HSOUT
tracks HSIN (shown with postive polarity in Figure 1):
FVCO2-0 Frequency Range (MHz) KVCO (MHz/V)
00
01
10
11
10–40
10–70
35
60
80
95
1. HSOUT rising edge tracks HSIN delayed by a few pixels.
20–120
20–150
2. HSOUT falling edge tracks the trailing edge of HSIN
with no delay.
Table 9. Charge Pump Current Levels
When COAST = H, the PLL flywheels, disregarding the
incoming HSIN references, while the HSOUT waveform
depends upon the state of HSIN.
IPUMP2-0
000
Current (µA)
50
100
150
250
350
500
750
1500
1. If HSIN = H:
001
a.) HSOUT rising edge remains locked to the PLL.
010
b.) HSOUT trailing edge falls after 50% of the HSOUT
period has expired.
011
100
2. HSIN transitions:
101
a.) HSOUT rising edge remains locked to the PLL.
110
b.) HSOUT falling edge is terminated by the trailing
edge of HSIN.
111
3. If HSIN = L, then HSOUT = L
Setting PHASE4-0 selects the sampling phase of SCK rela-
tive to PXCK in 32 steps of 11.25°. Phase of the output data,
DCK and DCK is slaved to the SCK phase.
RMS Clock jitter is less than 2% of pixel period in all operat-
ing modes.
At frequencies below 80 MHz, the percentage jitter begins to
rise. Increased jitter at low frequencies can be counteracted
in either of two ways:
REV. 1.2.15 1/14/02
17
PRODUCT SPECIFICATION
FMS9875
HSIN
Trailing edge terminates HSOUT
COAST
HSOUT
50% Timeout
Figure 17.
Timing Generator
Timing and Control logic generates:
Serial Interface
Register access is via a 2-wire I2C/SMBus compatible inter-
face. As a slave device, the 7-bit address is selected by the
A1-0 pins (see Table 10). Serial port pins SDA and SCL com-
municate with the host SMBus/I2C controller which act as a
master.
1. Internal sampling clock, SCK.
2. Output data clocks, DCK and DCK.
3. Output horizontal sync, HSOUT
.
Since the serial control port is design to interface with 3.3V
logic, the pins must be protected, if SDA and SCL signals
originate from 5V logic. Series connected 150Ω resistors are
recommended. (See Applications Section)
4. Internal clamp pulse, ICLAMP.
With HSPOL set correctly, ICLAMP delay follows the trail-
ing edge of horizontal sync in (HSIN). Delay is set by the
CD register. Width of ICLAMP is set by the CW register.
Range of CD and CW values is 1–255 pixels.
Table 10. Serial Interface Address Codes
A1-0
00
7-Bit Address
Sync Stripper
4C
4D
4E
4F
Some video signals include embedded composite sync rather
than separate horizontal and vertical sync signals, typically
sync on green. Composite sync is extracted from Composite
Video at the ACSIN pin.
01
10
11
When the ACSIN signal falls below a 150mV ground refer-
enced threshold, sync is detected. Composite Sync Output,
DCSOUT reflects the ACSIN sync timing with non-inverted
CMOS digital levels.
Two signals comprise the bus: clock (SCL) and bi-directional
data (SDA). When receiving and transmitting data through
the serial interface, the FMS9875 acts as a slave, responding
only to commands by the I2C/SMBus master.
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA may change only when SCL = L. An SDA transition
while SCL = H is interpreted as a start or stop signal.
Power Down
PWRDN = L minimizes FMS9875 power consumption.
Data outputs become high impedance. Clocks generation is
stopped. Register contents are retained. Sync stripping and
the internal voltage reference function.
18
REV. 1.2.15 1/14/02
FMS9875
PRODUCT SPECIFICATION
SDA
tBUFF
tSTAH
tDHO
tDSU
tSTASU
tSTOSU
tDAL
SCL
tDAH
Figure 18. Serial Bus: Read/Write Timing
SDA
SCL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ACK
Figure 19. SerialBus: Typical Byte Transfer
SDA
SCL
A6
A5
A4
A3
A2
A1
A0
R/W\
ACK
Figure 20. Serial Bus: Slave Address with Read/Write Bit
There are five steps within an I2C/SMBus cycle:
Data Transfer via Serial Interface
If a slave device, such as the FMS9875 does not acknowl-
edge the master device during a write sequence, SDA
remains HIGH so the master can generate a stop signal. Dur-
ing a read sequence, if the master device does not acknowl-
edge by bringing SDA = L, the FMS9875 interprets SDA =
H as “end of data.” SDA remains HIGH so the master can
generate a stop signal.
1. Start signal
2. Slave address byte
3. Pointer register address byte
4. Data byte to read or write
5. Stop signal
When the Serial Bus interface is inactive, SCL = H and SDA
= H. Communications are initiated by sending a start signal
(Figure 18, left waveform) that is a HIGH-to-LOW transition
on SDA while SCL is HIGH. A start signal alerts all slaved
devices that a data transfer sequence is imminent.
To write data to a specific FMS9875 control register, three
bytes are sent:
1. Write the slave address byte with bit R/W = L.
2. Write the pointer byte.
3. Write to the control register indexed by the pointer.
After a start signal, the first eight bits of data comprise a seven
bit slave address followed a single R/W bit (Read = H, Write
= L) to set the direction of data transfer: read from; or write
to the slave device. If the transmitted slave address matches
the address of the FMS9875 which set by the state of the
ADD pin, the FMS9875 acknowledges by pulling SDA
LOW on the 9th SCL pulse (see Figure 20). If the addresses
do not match or the register being accessed is 0x0F, the
FMS9875 does not acknowledge.
After each byte is written, the pointer auto-increments to
allow multiple data byte transfers within one write cycle.
Data is read from the control registers of the FMS9875 in a simi-
lar manner, except that two data transfer operations are required:
1. Write the slave address byte with bit R/W = L.
2. Write the pointer byte.
3. Write the slave address byte with bit R/W = H
4. Read the control register indexed by the pointer.
For each byte of data read or written, the MSB is the first bit
of the sequence.
REV. 1.2.15 1/14/02
19
PRODUCT SPECIFICATION
FMS9875
After each byte is read, the pointer auto-increments to allow
multiple data byte transfers within one read cycle.
Read from one register
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte (= base address)
4. Stop signal (optional)
5. Start signal
6. Slave Address byte (R/W bit = HIGH)
7. Data byte from base address
8. Stop signal
Preceding each slave write, there must be a start cycle.
Following the pointer byte there should be a stop cycle.
After the last read, there must be a stop cycle comprising
a LOW-to-HIGH transition of SDA while SCL is HIGH.
(see Figure 18, right waveform)
A repeated start signal occurs when the master device driv-
ing the serial interface generates a start signal without first
generating a stop signal to terminate the current communica-
tion. This is used to change the mode of communication
(read, write) between the slave and master without releasing
the serial interface lines.
Read from four registers
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte (= base address)
4. Stop signal (optional)
5. Start signal
Serial Interface Read/Write Examples
6. Slave Address byte (R/W bit = HIGH)
7. Data byte from base address
8. Data byte from (base address + 1)
9. Data byte from (base address + 2)
10. Data byte from (base address + 3)
11. Stop signal
Examples below show how serial bus cycles can be linked
together for multiple register read and write access cycles.
For sequential register accesses, each ACK handshake ini-
tiates further SCL clock cycles from the master to transfer
the next data byte.
Write to one register
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte
4. Data byte to base address
5. Stop signal
Write to four consecutive registers
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte
4. Data byte to base address
5. Data byte to (base address + 1)
6. Data byte to (base address + 2)
7. Data byte to (base address + 3)
8. Stop signal
20
REV. 1.2.15 1/14/02
FMS9875
PRODUCT SPECIFICATION
Absolute Maximum Ratings
(beyond which the device may be damaged)1
Parameter
Power Supply Voltages
VCC (Measured to GND)
Digital Inputs
Min
Typ
Max
Unit
-0.5
4
V
Applied voltage (Measured to GND)2
Forced current 3, 4
-0.3
-5.0
VDDA
5.0
V
mA
Analog Inputs
Applied Voltage (Measured to GND)2
Forced current 3, 4
-0.5
VDDA
10.0
V
-10.0
mA
Digital Outputs
Applied voltage (Measured to GND)2
Forced current 3, 4
Forced current 3, 4
-0.5
-6.0
-8.0
V
mA
6.0
8.0
1
mA
Short circuit duration (single output in HIGH state to ground)
Temperature
second
Junction
150
300
220
150
150
°C
°C
°C
°C
V
Lead Soldering (10 seconds)
Vapor Phase Soldering (1 minute)
Storage
-65
Electrostatic Discharge5
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
5. EIAJ test method.
Operating Conditions
Parameter
VDDA
Min
3.0
3.0
2.2
0
Nom
3.3
Max
3.6
3.6
3.6
70
Units
ADC Power Supply Voltage
PLL Power Supply Voltage
Output Power Supply Voltage
Ambient Temperature, Still Air
A/D analog input range, min.
A/D analog input range, max.
V
V
VDDP
3.3
VDDO
TA
3.3
V
°C
VTMAX
VTMIN
550
mV p-p
mV p-p
875
Test Rank Definitions
Rank
P
D
C
T
Production tested at 70°C.
Guaranteed by design over full temperature range.
Guaranteed by characterization and design over full temperature range.
Target specification, pending characterization.
REV. 1.2.15 1/14/02
21
PRODUCT SPECIFICATION
FMS9875
Electrical Characteristics1
Test
Parameter
Temp.
Rank
Min
Typ Max
Unit
Power Supply Currents
IDDA
IDDD
IDDP
PD
Supply current, ADC
Supply current2, Digital Output
Supply current, PLL
25°C
25°C
25°C
Full
P
P
220
50
mA
mA
mA
mW
mA
mW
P
50
Power dissipation
D
1100
30
IPD
Power-down current
Full
PC
D
PDD
Powered-down disspation
Full
100
Digital Inputs/Outputs
CI
Input Capacitance
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
D
PC
PC
D
3
pF
µA
µA
V
IIH
Input Current, HIGH
-2
-2
+2
+2
IIL
Input Current, LOW
VIH
VIL
Input Voltage, HIGH
VDDD–0.8
Input Voltage, LOW
D
0.8
V
IOHD
IOHC
IOLD
IOLC
VOH
VOL
Output Current, HIGH, data
Output Current, HIGH, clock
Output Current, LOW, data
Output Current, LOW, clock
Output Voltage, HIGH (IOH = max.)
Output Voltage, LOW (VDD3) (IOL = max.)
D
4
8
4
8
mA
mA
mA
mA
V
D
D
D
D
VDDO–0.1
VDDD–0.8
D
0.1
V
Serial Bus I/O
VSMIH Input Voltage, HIGH
Full
Full
Full
Full
Full
D
D
D
D
D
V
V
VSMIL
Input Voltage, LOW
0.8
VSMOL Output Voltage, LOW (ISMOL = max.)
ISMOH Output Current, HIGH
0.1
V
1
µA
mA
ISMOL
Output Current, HIGH
4
Analog Inputs
IB
Input bias current
Input Offset Voltage3
Full
Full
Full
PC
D
1
µA
mV
mV
EOS
-75
0
+75
VACSIN Analog Composite Sync Threshold
C
125
150 175
Reference Output
VREF
Output Voltage
Full
Full
PC
C
1.15
1.25 1.38
50
V
Temperature Coefficient
ppm/°C
Notes:
1. Unless otherwise stated, 0 to 70°C
2. DCK, DCK load = 15 pF; data load = 5 pF.
3. With Gain = 102.
22
REV. 1.2.15 1/14/02
FMS9875
PRODUCT SPECIFICATION
Switching Characteristics
Test
Temp. Rank Min. Typ. Max. Unit
Parameter
Analog-to-Digital Converters
Conversion rate
FMS9875KAC100
FMS9875KAC140
Full
Full
CT
CT
10
10
108
140
2
Ms/s
ns
tSKEW
Timing Generator
HSIN input frequency
DCK Clock to Data Out Skew
-0.5
Full
Full
C
15
110
12
kHz
Maximum PLL clock rate
FMS9875KAC100
FMS9875KAC140
CT
108
140
MHz
Minimum PLL clock rate
Sampling phase tempco
Full
Full
PC
C
MHz
20
ps/°C
Serial Bus Interface
tDAL
tDAH
SCL Pulse Width, LOW
Full
Full
Full
Full
Full
Full
Full
Full
C
C
C
C
C
C
C
C
4.7
4.0
4.0
4.7
4.0
4.7
250
0
µs
µs
µs
µs
µs
µs
ns
ns
SCL Pulse Width, HIGH
tSTAH
tSTASU
tSTOSU
tBUFF
tDSU
SDA Start Hold Time
SCL to SDA Setup Time (Stop)
SCL to SDA Setup Time (Start)
SDA Stop Hold Time Setup
SDA to SCL Data Setup Time
SDA to SCL Data Hold Time
tDHO
A/D Converter Performance Characteristics
Test
Parameter
Temp.
Rank
Min.
Typ.
Max.
Unit
Analog to Digital Converter
ELI
Integral Linearity Error
Differential Linearity Error
Missing Codes
Input full scale matching1
Offset adjustment range
Offset Register Value to Zero Offset
Gain tempco
Full
Full
PC
PC
PC
PC
D
-2.0
-1.0
2.0
1.0
0
LSB
LSB
ELD
Full
Full
2.5
25
6
%FS
%FS
LSB
ppm/°C
MHz
ns
Full
OSZ
BW
Full
C
4
32
59
25°C
25°C
25°C
25°C
C
300
400
2
Analog bandwidth, full power
Transient response
D
C
tOV
Over-voltage recovery time
C
1.5
ns
Notes
1. Without offset trim. (OSGY = OSBP = OSRP = 32.)
REV. 1.2.15 1/14/02
23
PRODUCT SPECIFICATION
FMS9875
PLL Performance Characteristics
Test
Parameter
Temp.
Rank
Min.
Typ.
Max.
Unit
Clock Input
tJPP
Peak-to-peak PLL Jitter
MHz
31.5
49.5
78.75
108
25°C
C
ps
6000
3117
1493
892
135
750
tJRMS RMS Jitter
MHz
31.5
49.5
78.75
108
25°C
C
ps
873
488
245
148
122
135
tJ2PP
Peak-to-peak jitter with
subdivide ratio equal
to 2.
MHz
31.5
49.5
MHz
31.5
49.5
25°C
25°C
C
C
ps
ps
1600
1700
tJ2RMS RMS jitter with subdivide
ratio equal to 2.
330
203
Notes
1. In Figures 21-23, the dashed curve is with subdivide ratio = 2.
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
1400
1200
1000
800
600
400
200
0
0
20
40
60
80 100 120 140 160
0
20
40
60
80 100 120 140 160
VCO Frequency, MHz
VCO Frequency, MHz
Figure 21. Pixel Clock Peak-to-Peak Jitter
Figure 22. Pixel Clock RMS Jitter
5%
4%
3%
2%
1%
0
0
20
40
60
VCO Frequency, MHz
Figure 23. Pixel Clock % RMS Jitter
80 100 120 140 160
24
REV. 1.2.15 1/14/02
FMS9875
PRODUCT SPECIFICATION
By adjusting the values in the gain (GRP, GGY, GBP) and
offset (OSRO, OSGY, OSBP) registers, the input conversion
range can be matched to the incoming analog signals.
Applications Information
For additional applications information see Applications
Notes available from the factory.
AC Coupled Digitizer
Shown in Figure 24 is an implementation of a video digitizer
with AC coupled YPBPRinputs. Horizontal sync input.
To minimize component count, use of the following on-chip
circuits is recommended:
1. ADC sampling clock.
2. Clamp.
Output data is three channel 24-bit pixels with a maximum
rate of 140Ms/s. Data is clocked out on the negative edge of
DCK. HSOUT is delayed HSIN.
3. Voltage reference
Optimum PLL Configuration Register (address 0x0C)
settings for typical modes are listed in Table 7. Unless
otherwise indicated, all modes are compliant with VESA or
SMPTE specifications. For unlisted modes, values should be
adjusted to optimize performance.
Control is through the serial port with 150Ω resistors
inserted to allow interfacing with 5V logic. If the serial bus is
operates with 3.3V levels, these resistors are unnecessary.
VPLL
VADC
VDIG
C1
Y
.047uF
U1
C2
R1
75
FMS9875
PB
75
NC9
74
.047uF
26
27
33
37
39
VDDP
VDDP
VDDP
VDDP
VDDP
NC8
73
NC7
48
F
R2
75
NC6
47
NC5
46
NC4
45
NC3
44
3
9
YGIN
BPIN
RPIN
YGREF
BPREF
RPREF
CKINV
CLAMP
SDA
NC2
43
F
NC1
RN1 100
YDATA [7..0]
15
4
76
77
78
79
80
81
82
83
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
PR
DYG7
DYG6
DYG5
DYG4
DYG3
DYG2
DYG1
DYG0
R3
75
C3
.047uF
10
16
20
21
22
23
24
25
30
31
34
35
R4
F
SDA
RN2 100
PBATA [7..0]
PRATA [7..0]
INVSCK
CLAMP
150
R5
63
64
65
66
67
68
69
70
16
15
14
13
12
11
10
9
1
DPB7
DPB6
DPB5
DPB4
DPB3
DPB2
DPB1
DPB0
2
3
4
5
6
7
8
SCL
150
SCL
A0
A1
A0
RN3 100
VPLL
51
52
53
54
55
56
57
58
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
A1
DPR7
DPR6
DPR5
DPR4
DPR3
DPR2
DPR1
DPR0
C4
R6
3.3k
HSIN
HSIN
COAST
XCK
0.039uF
C 5
R7
47
LPF
86
87
88
89
97
DCK
DCK
DCK
0.0039uF
2
96
98
ACSIN
PWRDN
REFIN
R8
47
DCK
HSOUT
DCSOUT
REFOUT
F
REFOUT
C6
0.1uF
Figure 24. Schematic, VGA Digitizer, AC Coupled RGB
REV. 1.2.15 1/14/02
25
PRODUCT SPECIFICATION
FMS9875
Digital I/O
Printed Wiring Board Design Guidelines
Recommendations:
Recommended strategy is to mount the FMS9875 over a
ground plane with carefully routed analog inputs and digital
outputs. All connections should be treated as transmission
lines to ensure that reflections due to mismatches are mini-
mized and ground return currents do not interfere with critical
signals.
1. Route digital I/O signals clear of analog inputs.
2. Terminate clock lines to reduce reflections. Treat clock
lines as transmission lines.
3. Scale the HSIN input to 3.3V, using a resistor network
or a series 1 kΩ resistor.
Analog Inputs
4. Limit Serial Port inputs voltages applied to SDA and
SDL pins with 150Ω resistors connected directly to the
pins.
Recommendations:
1. Keep analog trace lengths short to minimize crosstalk.
5. If necessary, to reduce reflections, EMI or spikes add a
2. Terminate analog inputs with 75Ω resistors, placed
50–200Ω resistor at each data output pin.
close to the FMS9875 analog inputs, RIN, GIN and BIN
By matching transmission line impedances, reflections
will be minimized.
.
6. If necessary, to reduce reflections, EMI or spikes add a
50–200Ω resistor at each data output pi.
3. Layout traces as 75Ω transmission lines.
7. To minimize noise within the FMS9875, restrict the
capacitive load at the digital outputs to < 10pF.
4. Avoid running analog traces near digital traces. Due to
the wide input bandwidth (400MHz) digital noise can
easily leak into analog inputs or cause excessive PLL
jitter.
Power and Ground
A schematic of the recommended power distribution is
shown in Figure 26. Note that:
5. If necessary, limit bandwidth by adding a ferrite bead in
series with each RGB input as shown in Figure 25. A
Fair-Rite #2508051217Z0 is recommended.Alternatively,
bandwidth reduction using a shunt 10pF capacitor may
reduce snow (intensity noise) caused by HF noise riding
on the RGB input. Mismatches, reflections and noise
may cause ringing or distortion of the incoming video
signals.
1. Analog and digital circuits are layed out over a common
solid ground plane.
2. Each FMS9875 pin is decoupled with a 0.1µF capacitor.
3. A group of pins may be de-coupled through a common
capacitor if no pin is more than 5 mm from the capacitor.
4. A separate regulated supply is used for the phase-locked
6. Locate the PLL filter close to the FMS9875 package and
clear of other signals.
loop power supply, VDDP
.
5. Capacitors are attached to each PLL pin or pin-pair.
7. Bypass the reference with a 0.1µF capacitor to ground.
C1
47nF
L1
BEAD
RIN, GIN, BIN
R,G,B INPUT
R1
75
C2
10pF
Figure 25. RGB Input Filter Options
26
REV. 1.2.15 1/14/02
FMS9875
PRODUCT SPECIFICATION
Pins 26, 27
C1
0.01µF
Pin 33
C2
0.1µF
Pin 37
Pin 39
C3
0.01µF
U1
RC1117-3.3
L1
BEAD
VPLL
C5
2
4
3
OUT
PowerInput
IN
ADJ/GND
C4
0.1µF
OUT
C6
C7
+
10µF
1
0.1µF
10µF
L2
BEAD
VADC Pins
C8
C9
C10 C11 C12 C13 C14
C15
+ C24
10µF
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
U2
RC1117-3.3
L3
BEAD
2
4
3
VDD Pins
OUT
OUT
IN
ADJ/GND
1
C16 C17 C18 C19 C20 C21 C22
C23
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
+
C25
0.1µF
10µF
Figure 26. Recommended Power Distribution
Physical placement of PLL power supply decoupling
components is critical. Bearing in mind the following
suggestions:
with 700mV input, adjust GGY, GBP and GRP so that
each RGB data output D7-0 = (same value), typically
240 decimal. Average values during calibration to
minimize the impact of noise.
1. All components should be placed in close proximity to
the FMS9875 pins.
4. In theYPBPR mode, theY-channel calibration procedure
is the same as for GBR. PBPR channels must be
calibrated differently. If the internal mid-scale clamp is
used, Offset is automatically preset. Only the Gain need
be adjusted to accomodate the swing from peak blue to
peak orange on the PB channel; and peak red to peak
cyan onthe PR channel. Average values during calibra-
tion to minimize the impact of noise.
2. Routing through vias should be avoided, if possible.
3. Each VDDP/GND pin pair: 26&27/28, 33/32, 37/38, and
39/40 should be decoupled with a either a 0.01 or 0.1 µF
capacitor (see Figure 24).
4. Use Fair-rite 274 301 9447 bead.
5. Clamp registers, CD and CW, should be programmed to
maximize the period of the clamp during the backporch,
while not encroaching into the sync or active video
periods.
Firmware
Best performance can be achieved by correctly setting the
FMS9875 registers. Here are some recommendations:
6. PHASE must be trimmed to minimize onscreen snow
(intensity noise) when a vertical grill pattern is
displayed.
1. For analog video, the sampling rate is usually 2X–3X
the video bandwidth. PLLN and PHASE are not critical.
2. For PC video, set the value of PLLN equal to the num-
ber of pixels to be sampled minus one. With this setting,
the number of samples per horizontal line equals the
number of pixels. If PLLN + 1 does not equal the num-
ber of pixels, there will be irregular intensities on text
and an interference pattern on a vertical grill pattern.
7. FVCO must be set to encompass the incoming
frequency range.
8. IPUMP must be set to minimize intensity noise.
9. To ensure correct power-on defaults, program all regis-
ters including Test Register 0x0F, which must be set to
0x00 for normal operation. Note that unlike registers
0x00 through 0x0D, register 0x0F does not acknowl-
edge. The ACK bit remains H instead of being pulled L.
3. In the GBR mode, calibrate Offset and Gain by first set-
ting each input to 0mV. Then adjust OSGY, OSBP, and
OSRP to set each RGB data output D7-0 = 0x00. Next
REV. 1.2.15 1/14/02
27
PRODUCT SPECIFICATION
FMS9875
Mechanical Dimensions
100-Lead MQFP (KG) Package
Notes:
Millimeters
Symbol
Notes
3, 5
4
1. All dimensions and tolerances conform to ANSI Y14.5M-1994.
Min.
Typ.
Max
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable mold protrusion is 0.254mm per side.
A
—
—
2.82
0.15
3.00
—
A1
A2
D
3. "N" is the number of terminals, 25 per side.
2.62
2.77
2.67
4. Dimension "b" does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm in excess of the "b"
dimension at the maximum material condition.
17.20 BSC
14.00 BSC
12.00 BSC
0.88
D1
D2
L
0.73
0.17
1.03
0.27
N
100
0.50 BSC
e
b
—
.40 Min.
0° Min.
0.13 R Min.
Datum Plane
.13/.30 R
e
0–7°
D2
L
D1/2
1.60 Ref.
Lead Detail
D
A2
See Lead Detail
Base Plane
A
-C-
B
Seating Plane
A1
LEAD COPLANARITY
ccc
C
28
REV. 1.2.15 1/14/02
PRODUCT SPECIFICATION
FMS9875
Ordering Information
Product Number
FMS9875KGC100
FMS9875KGC100X
Temperature Range
Screening
Commercial
Commercial
Package
Package Marking
0°C to 70°C
0°C to 70°C
100 Lead MQFP
9875KGC100
9875KGC100
100 Lead MQFP with
Tape and Reel
FMS9875KGC140
FMS9875KGC140X
0°C to 70°C
0°C to 70°C
Commercial
Commercial
100 Lead MQFP
9875KGC140
9875KGC140
100 Lead MQFP with
Tape and Reel
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
1/14/02 0.0m 004
Stock#DS30009875
2001 Fairchild Semiconductor Corporation
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