FTA20N60A [ETC]
SMPS Power Supply; SMPS电源
| 型号： | FTA20N60A |
| 厂家： | 
ETC |
| 描述： | SMPS Power Supply |
| 文件： | 总9页 (文件大小：511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FTA20N60A
销售电话：13641469108廖先生
QQ:543158798
Pb
N-Channel MOSFET
Applications:
Lead Free Package and Finish
VDSS
RDS(ON) (Typ.)
ID
20 A
• Adaptor
• TV Main Power
• SMPS Power Supply
• LCD Panel Power
600 V
0.35
D
Features:
• RoHS Compliant
• Low ON Resistance
• Low Gate Charge
• Peak Current vs Pulse Width Curve
G
G
D
S
TO-220F
Ordering Information
S
PART NUMBER
PACKAGE
TO-220F
BRAND
Packages
Not to Scale
FTA20N60A
FTA20N60A
TC=25
Parameter
o
C unless otherwise specified
Absolute Maximum Ratings
Symbol
FTA20N60A
600
Units
VDSS
Drain-to-Source Voltage
Continuous Drain Current
(NOTE *1)
(NOTE *2)
V
ID
20.0
ID@ 100 Co
IDM
Continuous Drain Current
Pulsed Drain Current, VGS@ 10V
Power Dissipation
Figure 3
Figure 6
60
A
W
o
W/ C
PD
o
Derating Factor above 25 C
2.00.48
VGS
EAS
Gate-to-Source Voltage
± 30
V
Single Pulse Avalanche Engergy
L=10 mH
1000
mJ
IAS
Pulsed Avalanche Rating
Peak Diode Recovery dv/dt
Figure 8
5.0
A
dv/dt
(NOTE *3)
V/ns
Maximum Temperature for Soldering
Leads at 0.063 in (1.6 mm) from Case for 10 seconds
Package Body for 10 seconds
TL
TPKG
300
260
oC
Operating Junction and Storage
Temperature Range
TJ and TSTG
-55 to 150
* Drain Current Limited by Maximum Junction Temperature
Caution: Stresses greater than those listed in the “Absolute Maximum Ratings” Table may cause permanent damage to the device.
Thermal Resistance
Symbol
Parameter
Junction-to-Case
Junction-to-Ambient
FTA20N60A
Units
Test Conditions
Drain lead soldered to water cooled heatsink, PD ad-
R
2.08
100
JC
JA
o
justed for a
oC/W
peak junction temperature of +150 C.
1 cubic foot chamber, free air.
R
Page 1 of 9
FTA20N60A REV. B. Apr. 2010
©2010 InPower Semiconductor Co., Ltd.
OFF Characteristics
Symbol
TJ=25 Counless otherwise specified
Parameter
Min.
600
Typ.
--
Max.
--
Units
V
Test Conditions
BVDSS
Drain-to-Source Breakdown Voltage
VGS=0V, ID=250μA
o
BreakdownVoltage Temperature
Coefficient, Figure 11.
Reference to 25 C,
ID=250μA
o
--
--
0.51
--
--
10
BVDSS / TJ
V/ C
VDS=600V, VGS=0V
VDS=480V, VGS=0V
IDSS
IGSS
Drain-to-Source Leakage Current
μA
nA
--
--
250
o
TJ=125 C
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
--
--
--
--
100
VGS=+30V
VGS= -30V
-100
TJ=25
o
C unless otherwise specified
ON Characteristics
Symbol
Parameter
Min.
--
Typ.
Max.
0.45
4.0
Units
Test Conditions
VGS=10V, ID=9.0A
(NOTE *4)
VDS=VGS, ID=250 A
Static Drain-to-Source On-Resistance
Figure 9 and 10.
RDS(ON)
VGS(TH)
gfs
0.35
--
Gate Threshold Voltage, Figure 12.
Forward Transconductance
2.0
--
V
S
VDS=15V, ID=10A
(NOTE *4)
15
--
Dynamic Characteristics
Symbol
Essentially independent of operating temperature
Parameter
Min.
--
Typ.
2830
245
Max.
Units
pF
Test Conditions
Ciss
Input Capacitance
Output Capacitance
--
--
VGS=0V
VDS=25V
Coss
--
f =1.0MHz
Figure 14
Crss
Reverse Transfer Capacitance
--
17
--
Qg
Total Gate Charge
--
--
55
14
--
--
VDD=300V
ID=18A
Qgs
Gate-to-Source Charge
nC
Qgd
Figure 15
Gate-to-Drain (“Miller”) Charge
--
21
--
Resistive Switching Characteristics
Symbol Parameter
Essentially independent of operating temperature
Min.
--
Typ.
40
Max.
Units
Test Conditions
VDD=300V
ID=18A
td(ON)
Turn-on Delay Time
Rise Time
--
--
--
trise
--
75
ns
td(OFF)
tfall
Turn-Off Delay Time
--
150
VGS=10V
RG=25
Fall Time
--
80
--
Page 2 of 9
FTA20N60A REV. B. Apr. 2010
©2010 InPower Semiconductor Co., Ltd.
o
Source-Drain Diode Characteristics
Symbol Parameter
Tc=25 C unless otherwise specified
Min.
--
Typ.
Max.
Units
A
Test Conditions
IS
Continuous Source Current (Body Diode)
Maximum Pulsed Current (Body Diode)
Diode Forward Voltage
--
--
20
80
1.5
--
Integral pn-diode
in MOSFET
ISM
A
--
--
--
--
VSD
IS=20A, VGS=0V
VGS=0V
--
V
ns
trr
Reverse Recovery Time
615
5.8
Qrr
Reverse Recovery Charge
--
IF=20A, di/dt=100 A/μs
nC
Notes:
*1. TJ = +25 oC to +150 oC.
*2. Repetitive rating; pulse width limited by maximum junction temperature.
*3. ISD= 20 A, di/dt < 100 A/μs, VDD < BVDSS, TJ=+150 oC.
*4. Pulse width < 380μs; duty cycle < 2%.
Page 3 of 9
FTA20N60A REV. B. Apr. 2010
©2010 InPower Semiconductor Co., Ltd.
Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case
Duty Factor
1.000
50%
20%
10%
Thermal
Impedan0c.1e00
(Normalized)
5%
2%
1%
PDM
0.010
t1
t2
JC,
Z
0.001
NOTES:
DUTY FACTOR: D=t1/t2
single pulse
PEAK TJ=PDM x Z JC x R JC+TC
0.0001
10E-6
100E-6
1E-3
10E-3
100E-3
1E+0
10E+0
1E-6
tp, Rectangular Pulse Duration (s)
Figure 3. Maximum Continuous Drain Current
vs Case Temperature
Maximum Power Dissipation
vs Case Temperature
Figure 2.
75
20
PD, Power
60
Dissipation (W)
ID, Drain
15
Current (A)
45
10
30
15
5
0
0
75
TC, Case Temperature (oC)
125
75
100
125
150
25
50
100
150
25
50
o
TC, Case Temperature ( C)
Figure 5. Typical Drain-to-Source ON Resistance
vs Gate Voltage and Drain Current
Figure 4. Typical Output Characteristics
20
2.1
PULSE DURATION = 250 μS
DUTY FACTOR = 0.5%
MAX, TC = 25 oC
PULSE DURATION = 10 μS
DUTY FACTOR = 0.5% MAX
TC = 25 oC
15V
VG
S=
RDS(ON),
Drain-to-Source
ON Resistance (
1.4
VGS = 7.0V
VGS = 6.5V
ID, Drain
15
Current (A)
ID = 40A
ID = 20A
ID = 10A
ID = 5.0A
10
VGS = 6.0V
0.7
VGS = 5.5V
VGS = 5.0V
5
0
0.0
4
3
18
0
12
15
8
10
12
6
9
6
14
VDS, Drain-to-Source Voltage (V)
VGS, Gate-to-Source Voltage (V)
Page 4 of 9
FTA20N60A REV. B. Apr. 2010
©2010 InPower Semiconductor Co., Ltd.
Figure 6. Maximum Peak Current Capability
1000
TRANSCONDUCTANCE
MAY LIMIT CURRENT IN
THIS REGION
FOR TEMPERATURES
ABOVE 25 oC DERATE PEAK
CURRENT AS FOLLOWS:
=
IDM, Peak
100
Current (A)
–---------------------
10
VGS = 10V
1
10E-6
100E-6
1E-3
10E-3
100E-3
1E+0
10E+0
tp, Pulse Width (s)
Unclamped Inductive
Switching Capability
Figure 7. Typical Transfer Characteristics
Figure 8.
25
100
PULSE DURATION = 380 μs
DUTY CYCLE = 0.5% MAX
VDS = 30 V
ID,
IAS, Avalanche
Current (A)
Drain-to-Sourc
20
e Current (A)
STARTING TJ = 25 oC
10
1
15
10
5
STARTING TJ = 150 oC
+150 oC
+25 oC
-55 oC
If R= 0: tAV= (L×IAS)/(1.3BVDSS-VDD)
If R 0: tAV= (L/R) ln[IAS×R)/(1.3BVDSS-VDD)+1]
R equals total Series resistance of Drain circuit
0.1
1E-6
0
7
4
5
6
7
100E-6
tAV, Time in Avalanche (s)
1E-3
10E-3
10E-6
VGS, Gate-to-Source Voltage (V)
Figure 9. Typical Drain-to-Source ON
Resistance vs Drain Current
Figure 10. Typical Drain-to-Source ON Resistance
vs Junction Temperature
1.8
2.75
PULSE DURATION = 10 μs
DUTY CYCLE = 0.5% MAX
TC=25°C
2.50
RDS(ON),
1.5
RDS(ON),
Resistance
2.25
Drain-to-Source
Drain-to-Source
(Normalized)
2.00
ON Resistance
1.2
( )
1.75
1.50
1.25
1.00
0.75
0.9
0.6
V= 10V
GS
PULSE DURATION = 10 μs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 10.0A
0.3
0.50
0.0
0
0.25
-75
-50
75
TJ, Junction Temperature (oC)
100
150
5
10
15
25
-25
0
25
50
125
20
30
ID, Drain Current (A)
Page 5 of 9
FTA20N60A REV. B. Apr. 2010
©2010 InPower Semiconductor Co., Ltd.
Figure 11. Typical Breakdown Voltage vs
Junction Temperature
Figure 12. Typical Threshold Voltage vs
Junction Temperature
1.2
1.1
1.15
BVDSS,
Drain-to-Source
VGS(TH),
Breakdown
Threshold Voltage
1.10
Voltage
1.0
(Normalized)
(Normalized)
1.05
1.00
0.95
0.90
0.9
0.8
0.7
0.6
VGS = 0V
ID = 250 μA
VGS = VDS
ID = 250 μA
0.5
-75
-25
0
25
50
75
100
125
150
-75
-50
-25
0
25
50
75
100
125
150
-50
TJ, Junction Temperature (oC)
TJ, Junction Temperature (oC)
Figure 14. Typical Capacitance vs
Drain-to-Source Voltage
Figure 13.
Maximum Forward Bias Safe
Operating Area
100.0
10000
10μs
Ciss
ID, Drain
C, Capacitance
1000
100μ
1ms
Current (A)
(pF)
10.0
Coss
100
1.0
0.1
10ms
DC
VGS = 0V, f = 1MHz
Ciss = Cgs + Cgd
Coss Cds + Cgd
Crss = Cgd
OPERATION IN THIS AREA
MAY BE LIMITED BY R
10
DS(ON)
Crss
TJ = MAX RATED
TC = 25 oC
1
1
10
100
1000
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
VDS, Drain Voltage (V)
Figure 15.
Typical Gate Charge
vs Gate-to-Source Voltage
Figure 16. Typical Body Diode Transfer
Characteristics
60
12
VGS,
Gate-to-Source
Voltage (V)
ISD, Reverse
Drain Current
50
(A)
10
VDS = 150V
VDS = 300V
VDS = 480V
40
8
6
30
20
10
+150 oC
+25 oC
4
2
ID = 18A
50
VGS = 0V
1.2
0
0
0
0.2
0.4
0.6
0.8
1.0
10
20
30
40
60
1.4
QG , Total Gate Charge (nC)
VSD, Source-to-Drain Voltage (V)
Page 6 of 9
FTA20N60A REV. B. Apr. 2010
©2010 InPower Semiconductor Co., Ltd.
Test Circuits and Waveforms
VDS
ID
ID
VDS
VGS
VGS
Miller
Region
VDD
D.U.T.
VGS(TH)
1 mA
Qgs
Qgd
Qg
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveform
VDS
RL
90%
10%
VDS
VGS
VDD
RG
D.U.T.
VGS
td(OFF) tfall
td(ON)
trise
Figure 19. Resistive Switching Test Circuit
Figure 20. Resistive Switching Waveforms
Page 7 of 9
FTA20N60A REV. B. Apr. 2010
©2010 InPower Semiconductor Co., Ltd.
Test Circuits and Waveforms
di/dt adj.
Current
Pump
di/dt = 100A/μA
ID
Double Pulse
D.U.T.
VDD
Qrr
L
trr
ID
Figure 22. Diode Reverse Recovery Waveform
Figure 21. Diode Reverse Recovery Test Circuit
BVDSS
Series Switch
(MOSFET)
L
IAS
BVDSS
VDD
VDD
0
D.U.T.
Commutating
Diode
tAV
VGS
50
IAS
VGS
tp
I AS 2 L
E AS
2
Figure 23. Unclamped Inductive Switching Test Circuit
Figure 24. Unclamped Inductive Switching Waveforms
Page 8 of 9
FTA20N60A REV. B. Apr. 2010
©2010 InPower Semiconductor Co., Ltd.
Disclaimers:
InPower Semiconductor Co., Ltd (IPS) reserves the right to make changes without notice in order to improve reliability, function
or design and to discontinue any product or service without notice. Customers should obtain the latest relevant information before
orders and should verify that such information is current and complete. All products are sold subject to IPS’s terms and conditions
supplied at the time of order acknowledgement.
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reliability and quality control are used to the extent IPS deems necessary to support this warrantee. Except where agreed upon
by contractual agreement, testing of all parameters of each product is not necessarily performed.
InPower Semiconductor Co., Ltd does not assume any liability arising from the use of any product or circuit designs described
herein. Customers are responsible for their products and applications using IPS’s components. To minimize risk, customers must
provide adequate design and operating safeguards.
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modification or alteration. Reproduction of this information with any alteration is an unfair and deceptive business practice.
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Life Support Policy:
InPower Semiconductor Co., Ltd’s products are not authorized for use as critical components in life support devices or
systems without the expressed written approval of InPower Semiconductor Co., Ltd.
As used herein:
1. Life support devices or systems are devices or systems which:
a. are intended for surgical implant into the human body,
b. support or sustain life,
c. whose failure to perform when properly used in accordance with instructions
for used provided in the labeling, can be reasonably expected to result in significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Page 9 of 9
FTA20N60A REV. B. Apr. 2010
©2010 InPower Semiconductor Co., Ltd.
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