GM71VS65403ALT-5 [ETC]
x4 EDO Page Mode DRAM ; X4 EDO页模式DRAM\n
| 型号： | GM71VS65403ALT-5 |
| 厂家： | 
ETC |
| 描述： | x4 EDO Page Mode DRAM
|
| 文件： | 总25页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GM71V65403A
GM71VS65403AL
16,777,216 WORDS x 4 BIT
CMOS DYNAMIC RAM
LG Semicon Co.,Ltd.
Description
Pin Configuration
32 SOJ / TSOP II
The GM71V(S)65403A/AL is the new generation
dynamic RAM organized 16,777,216 words by 4bits.
The GM71V(S)65403A/AL utilizes advanced CMOS
Silicon Gate Process Technology as well as
advanced circuit techniques for wide operating
margins, both internally and to the system user.
System oriented features include single power supply
of 3.3V+/-10% tolerance, direct interfacing
capability with high performance logic families such
as Schottky TTL.
1
2
3
32
31
VSS
IO3
VCC
IO0
IO1
NC
30
IO2
NC
4
5
29
28
27
26
NC
NC
NC
6
7
VSS
VCC
/CAS
The GM71V(S)65403A/AL offers Extended Data
Out(EDO) Mode as a high speed access mode.
8
9
25
24
/OE
NC
/WE
/RAS
Features
10
A0
23 A11
* 16,777,216 Words x 4 Bit
* Extended Data Out (EDO) Mode Capability
* Fast Access Time & Cycle Time
22
11
12
A10
A1
A2
A3
A9
A8
21
20
13
14
15
(Unit: ns)
A4
A5
19
18
A7
A6
t
RAC
50
t
AA
t
CAC
t
RC
t
HPC
84
20
25
25
30
13
15
GM71V(S)65403A/AL-5
GM71V(S)65403A/AL-6
16
VSS
17
VCC
104
60
(Top View)
*Power dissipation
- Active : 684mW/612mW(MAX)
- Standby : 1.8 mW ( CMOS level : MAX )
0.54mW ( L-Version : MAX)
*EDO page mode capability
*Access time : 50ns/60ns (max)
*Refresh cycles
- RAS only Refresh
§Â
4096 cycles/64
(GM71V65403A)
§Â
4096 cycles/128 (GM71VS65403AL)(L_Version)
*CBR & Hidden Refresh
§Â
4096 cycles/64
(GM71V65403A)
§Â
4096 cycles/128
*4 variations of refresh
-RAS-only refresh
(GM71VS65403AL)( L-Version )
-CAS-before-RAS refresh
-Hidden refresh
-Self refresh (L-Version)
*Single Power Supply of 3.3V+/-10 % with a built-in VBB generator
*Battery Back Up Operation ( L-Version )
1
GM71V65403A
GM71VS65403AL
LG Semicon
Pin Description
Pin
Function
Address Inputs
Pin
WE
Function
A0-A11
A0-A11
RAS
Write Enable
I/O0 - I/O3
VCC
Data Input / Output
Power (+3.3V)
Ground
Refresh Address Inputs
Row Address Strobe
Column Address Strobe
Output Enable
VSS
CAS
OE
NC
No Connection
Ordering Information
Type No.
Access Time
Package
400 Mil
32Pin
Plastic SOJ
§À
§À
GM71V(S)65403A/ALJ-5
GM71V(S)65403A/ALJ-6
50
60
400 Mil
32Pin
Plastic TSOP II
§À
§À
GM71V(S)65403A/ALT-5
GM71V(S)65403A/ALT-6
50
60
Absolute Maximum Ratings*
Symbol
Parameter
Storage Temperature (Plastic)
Rating
Unit
TSTG
-55 to 125
C
-0.5 to VCC + 0.5
(MAX ; 4.6V)
Voltage on any Pin Relative to VSS
VT
V
VCC
IOUT
PT
Voltage on VCC Relative to VSS
Short Circuit Output Current
Power Dissipation
-0.5 to 4.6
V
50
mA
W
1.0
*Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
VCC
Parameter
Supply Voltage
Typ
Max
3.6
0
Min
3.0
0
Unit
V
Notes
1,2
2
3.3
0
VSS
Supply Voltage
V
Vcc+0.3
0.8
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
-
V
V
1
1
-0.3
-
TA
Ambient Temperature under Bias
70
C
0
-
2
GM71V65403A
GM71VS65403AL
LG Semicon
DC Electrical Characteristics: (VCC = 3.3V+/-10%, TA = 0 ~ 70C)
Symbol
Parameter
Min Max Unit Note
VOH
Output Level
Output Level Voltage (IOUT = -2mA)
2.4
0
VCC
V
V
VOL
ICC1
Output Level
Output Level Voltage (IOUT = 2mA)
0.4
Operating Current (tRC = tRC min)
50ns
60ns
-
-
190
170
mA
mA
1,2
Standby Current (TTL interface)
Power Supply Standby Current
(RAS, CAS= VIH, DOUT = High-Z)
ICC2
ICC3
-
2
50ns
60ns
-
-
190
170
RAS-Only Refresh Current
( tRC = tRC min)
mA
2
50ns
60ns
-
-
-
110
100
0.5
ICC4
ICC5
Extended Data Out page Mode Current
(RAS = VIL, CAS, Address Cycling: tHPC = tHPC min)
mA 1,3
mA
CMOS interface
(RAS, CAS>=VCC-0.2V, DOUT = High-Z)
Standby Current(L_Version)
-
300
uA
4
160
140
ICC6
CAS-before-RAS Refresh Current
(tRC = tRC min)
50ns
60ns
-
-
mA
Battery Back Up Operating Current(Standby with CBR)
(tRC=31.25us,tRAS=300ns,Dout=High-Z)
uA
ICC7
ICC8
-
500
4, 5
Standby Current (CMOS)
Power Supply Standby Current
RAS = VIH, CAS = VIL , DOUT = Enable
-
5
mA
uA
1
5
ICC9
II(L)
IO(L)
Self Refresh Current
(RAS, CAS <=0.2V,Dout=High-Z)
-
400
5
Input Leakage Current, Any Input
(0V<=VIN<=Vcc)
-5
-5
uA
uA
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<=Vcc)
5
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, tHPC.
4. VIH>=VCC-0.2V, 0V<=VIL<=0.2V
5. L-Version
3
GM71V65403A
GM71VS65403AL
LG Semicon
Capacitance (VCC = 3.3V+/-10%, TA = 25C)
Symbol
CI1
Parameter
Typ
Max
Unit
§Ü
Note
1
-
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-in,Data-Out)
5
7
7
§Ü
CI2
-
-
1
§Ü
CI/O
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS, CAS = VIH to disable DOUT.
AC Characteristics (VCC = 3.3V+/-10%, TA = 0 ~ 70C, Notes 1, 2,19)
Test Conditions
Input rise and fall times : 2ns
Input level : VIL/VIH = 0.0/3.0V
Input timing reference levels : VIL/VIH = 0.8/2.0V
Output timing reference levels : VOL/VOH = 0.8/2.0V
Output load : 1 TTL gate+CL (100pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
GM71V(S)65403A/AL-5 GM71V(S)65403A/AL-6
Symbol
Parameter
Notes
Unit
Min
84
Min
Max
Max
104
-
-
-
-
§À
§À
§À
§À
§À
§À
§À
§À
t
RC
RP
Random Read or Write Cycle Time
RAS Precharge Time
30
40
t
8
-
10000
10000
-
10
60
10
0
-
CAS Precharge Time
tCP
50
10000
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tODD
tDZO
t
DZC
RAS Pulse Width
10000
8
0
CAS Pulse Width
-
-
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
10
0
8
-
-
0
-
10
8
-
-
§À
§À
3
4
14
12
17
12
10
13
35
5
37
25
-
45
30
-
§À
§À
§À
§À
40
5
-
-
-
CAS Hold Time
-
CAS to RAS Precharge Time
OE to DIN Delay Time
OE Delay Time from DIN
15
13
0
-
-
-
-
§À
§À
§À
5
0
0
-
6
6
7
-
0
CAS Delay Time from DIN
TransitionTime (Rise and Fall)
Refresh Period
50
tT
2
-
2
-
§À
§Â
§Â
50
64
4096
cycles
4096
tREF
64
-
-
Refresh Period ( L-Version )
128
128
cycles
4
GM71V(S)65403A/AL
LG Semicon
Read Cycles
GM71V(S)65403A/AL-5
GM71V(S)65403A/AL-6
Symbol
Parameter
Notes
Unit
Min
Max
50
Max
60
Min
§À
§À
-
-
-
-
Access Time from RAS
tRAC
CAC
8,9
13
15
Access Time from CAS
9,10,17
t
§À
§À
-
-
25
13
-
-
30
15
-
Access Time from Column Address
Access Time from OE
t
AA
9,11,17
9
t
OAC
RCS
0
0
§À
§À
§À
§À
§À
0
Read Command Set-up Time
-
t
12
12
0
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
Column Address to CAS Lead Time
Output Buffer Turn-off Delay Time from CAS
Output Buffer Turn-off Delay Time from OE
-
-
-
-
t
RCH
RRH
0
0
t
30
18
25
15
-
-
-
t
RAL
CAL
OFF
OEZ
CDD
-
t
§À
§À
§À
-
13
13
-
-
-
15
15
t
13,21
13
-
t
13
13
-
-
5
CAS to DIN Delay Time
RAS to DIN Delay Time
15
15
t
§À
-
t
RDD
§À
§À
15
-
-
-
WE to DIN Delay Time
13
-
t
WDD
13,21
13
Output Buffer Turn-off Delay Time from RAS
13
13
15
15
t
OFR
§À
§À
§À
tWEZ
-
3
-
Output Buffer Turn-off Delay Time from WE
Output Data Hold Time
3
21
-
-
-
-
-
-
-
-
tOH
Output Data Hold Time from RAS
3
3
tOHR
21
50
3
§À
§À
§À
Read Command Hold Time from RAS
Output data hold time from OE
CAS to Output in Low - Z
60
3
tRCHR
-
-
t
OHO
0
0
tCLZ
5
GM71V(S)65403A/AL
LG Semicon
Write Cycles
Symbol
GM71V(S)65403A/AL-5 GM71V(S)65403A/AL-6
Notes
Parameter
Unit
Min
0
Min
0
Max
Max
-
-
-
-
-
14
§À
§À
§À
§À
§À
§À
§À
t
WCS
WCH
WP
RWL
CWL
Write Command Set-up Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
8
10
10
17
10
0
-
-
-
-
-
-
t
8
t
13
8
t
-
-
t
Write Command to CAS Lead Time
Data-in Set-up Time
15
15
0
t
DS
10
8
-
Data-in Hold Time
tDH
Read-Modify-Write Cycles
GM71V(S)65403A/AL-5
GM71V(S)65403A/AL-6
Notes
Parameter
Symbol
Unit
Min
116
67
Min
Max
Max
140
-
-
-
-
-
-
Read-Modify-Write Cycle Time
§À
§À
§À
§À
§À
t
RWC
RWD
CWD
AWD
OEH
79
34
49
15
-
-
14
14
t
RAS to WE Delay Time
30
t
CAS to WE Delay Time
42
14
-
-
t
Column Address to WE Delay Time
OE Hold Time from WE
13
t
Refresh Cycles
GM71V(S)65403A/AL-5
GM71V(S)65403A/AL-6
Notes
Symbol
Unit
Parameter
Min
Min
Max
Max
CAS Set-up Time
(CAS-before-RAS Refresh Cycle)
§À
-
-
5
tCSR
5
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
8
0
-
-
-
-
10
0
§À
§À
t
CHR
WRP
WE setup time
(CAS-before-RAS Refresh Cycle)
t
WE hold time
(CAS-before-RAS Refresh Cycle)
§À
§À
8
5
-
-
10
5
-
-
t
WRH
RPC
RAS Precharge to CAS Hold Time
t
6
GM71V(S)65403A/AL
LG Semicon
Extended Data Out Mode Cycles
GM71V(S)65403A/AL-6
GM71V(S)65403A/AL-5
Notes
Unit
Symbol
Parameter
Min
20
8
Min
Max
Max
25
-
-
tHPC
EDO Page Mode Cycle Time
§À
-
20
10
-
-
§À
-
tWPE
Write pulse width during CAS Precharge
EDO Mode RAS Pulse Width
100000
-
tRASP
100000
16
§À
§À
§À
§À
§À
§À
Access Time from CAS Precharge
-
35
-
9,17
28
-
-
tACP
35
10
tRHCP
28
8
RAS Hold Time from CAS Precharge
tCOL
-
-
-
-
CAS Hold Time Referred OE
CAS to OE set-up Time
5
-
5
tCOP
35
tRCHP
28
-
Read Command Hold Time from CAS
Precharge
t
DOH
OEP
§À
§À
Output Data Hold Time from CAS Low
OE Precharge Time
3
8
-
-
-
-
3
9,22
t
10
EDO Page Mode Read-Modify-Write cycle
GM71V(S)65403A/AL-6
GM71V(S)65403A/AL-5
Notes
Symbol
Parameter
Unit
Min
57
Min
68
Max
Max
EDO Read-Modify-Write Cycle Time
-
-
-
-
§À
§À
tHPRWC
CPW
45
54
14
EDO Page Mode Read-Modify-Write Cycle
CAS Precharge to WE Delay Time
t
Self Refresh Cycles (L_Version)
GM71V(S)65403A/AL-5
GM71V(S)65403A/AL-6
Symbol
Parameter
Notes
Unit
Min
100
90
Min
100
110
-50
Max
Max
us
-
-
-
-
-
-
tRASS
26
26
RAS Pulse Width(Self-Refresh)
RAS Precharge Time(Self-Refresh)
CAS Hold Time(Self-Refresh)
§À
§À
t
RPS
CHS
-50
t
7
GM71V(S)65403A/AL
LG Semicon
Notes:
AC measurements assume tT = 2§ .À
1.
2.
AC initial pause of 200 § Áis required after power up followed by a minimum of eight
initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-before-
RAS refresh)
Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only: if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
3.
4.
5.
Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only: if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH(min) and VIL (max).
8. Assumes that tRCD¡ ÂtRCD(max) and tRAD¡ ÂtRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD¡ tÃRCD(max) and tRCD + tCAC(max) ¡ ÃtRAD + tAA(max).
11.
12.
Assumes that tRAD ¡ tÃRAD (max) and tRCD + tCAC(max)¡ tÂRAD + tAA(max).
Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD, and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only: if tWCS ¡ tÃWCS(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if
tRWD ¡ tÃRWD(min), tCWD¡ tÃCWD(min), tAWD¡ tÃAWD(min) and tCPW¡ tÃCPW(min), the cycle is a read-
modify-write and the data output will contain data read from the selected cell: if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
15.
tDS and tDH are referred to CAS leading edge in early write cycles and to WE leading edge in
delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in extended data out mode cycles.
Access time is determined by the longest among tAA, tCAC and tCPA.
17.
18.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
19.
When output buffers are enabled once, sustain the low impedance state until valid daa is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
8
GM71V(S)65403A/AL
LG Semicon
tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read
20.
21.
cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix
cycle (1),(2) } minimum value of CAS cycle t HPC(tCAS + t CP + 2t T) becomes greater than the
specified tHPC(min) value.
The value of CAS cycle time of mixed EDO page mode is shown in
EDO page mode mix cycle (1) and (2).
Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH, and between tOFR and tOFF.
tDOH defines the time at which the output level go cross.
reference level.
V OL=0.8V, VOH=2.0V of output timing
22.
23.
Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
§Â period on the condition a and b below.
a. Enter self refresh mode within 15.6 us after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us
after exiting from self refresh mode.
In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
24.
25.
26.
27.
For L_Version, it is available to apply each 128 §Â and 31.2 us instead of 64 §Â and 15.6us at
note 23.
At tRASS£¾100 us , self refresh mode is activated, and not active at t RASS £¼10us. It is undefined
within the range of 10 us £¼tRASS £¼100 us . for tRASS £¾10 us , it is necessary to satisfy tRPS.
XXX: H or L ( H : VIH(min)< =VIN< =VIH(max), L: VIH(min)< =VIN< =VIH(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
9
GM71V(S)65403A/AL
LG Semicon
Timing Waveforms
t
RC
t
RAS
t
RP
RAS
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
T
CAS
t
RAD
t
RAL
CAL
t
t
ASR
t
RAH
t
ASC
t
CAH
ADDRESS
ROW
COLUMN
t
RRH
t
RCHR
t
RCS
t
RCH
WE
t
CAC
t
WEZ
t
AA
t
OFF
t
CLZ
High-Z
DOUT
DOUT
t
OFR
OHR
t
RDD
t
RAC
t
t
t
OH
t
WDD
OEZ
OHO
CDD
t
t
DZC
t
High-Z
DIN
OE
t
DZO
t
ODD
t
OAC
FIGURE 1. READ CYCLE
10
GM71V(S)65403A/AL
LG Semicon
t
RC
t
RAS
t
RP
RAS
t
RSH
t
T
t
RCD
t
CAS
t
CRP
t
CSH
CAS
t
ASR
t
RAH
t
ASC
t
CAH
ADDRESS
ROW
COLUMN
t
WCS
t
WCH
WE
t
DS
t
DH
DIN
DIN
High-Z
DOUT
FIGURE 2. EARLY WRITE CYCLE
11
GM71V(S)65403A/AL
LG Semicon
t
RC
t
RAS
t
RP
RAS
CAS
t
RSH
t
T
t
RCD
t
CAS
t
CRP
t
CSH
t
ASR
t
RAH
t
CAH
t
ASC
ADDRESS
ROW
COLUMN
t
CWL
t
RWL
t
RCS
t
WP
WE
t
DZC
t
DH
t
DS
High-Z
DIN
DIN
t
t
ODD
t
OEH
t
DZO
t
OEP
OE
t
OEZ
CLZ
High-Z
INVALID
OUTPUT
DOUT
*18
FIGURE 3. DELAYED WRITE CYCLE
12
GM71V(S)65403A/AL
LG Semicon
t
RWC
t
RAS
t
RP
RAS
CAS
t
T
t
RCD
t
CAS
t
CRP
t
RAD
t
RAH
t
ASR
t
CAH
t
ASC
ADDRESS
ROW
COLUMN
t
CWL
t
CWD
t
RCS
t
AWD
t
RWL
t
RWD
t
WP
WE
t
t
AA
t
RAC
t
DH
t
DS
t
DZC
CAC
High-Z
DIN
DIN
t
ODD
t
OEH
t
CLZ
High-Z
DOUT
DOUT
t
OAC
t
t
OEZ
OHO
t
OEP
t
DZO
OE
*18
FIGURE 4. READ MODIFY WRITE CYCLE
13
GM71V(S)65403A/AL
LG Semicon
t
RC
t
RAS
t
RP
RAS
CAS
t
T
t
CRP
t
RPC
t
CRP
t
ASR
t
RAH
ADDRESS
ROW
t
OFR
t
OFF
High-Z
DOUT
FIGURE 5. RAS ONLY REFRESH CYCLE
t
RC
t
RC
t
RP
t
RAS
t
RP
t
RAS
t
RP
RAS
CAS
tT
t
RPC
t
RPC
t
CRP
t
CP
t
CSR
t
CHR
t
CP
t
CSR
t
CHR
t
WRP
t
WRH
t
WRP
t
WRH
WE
ADDRESS
t
OFR
t
OFF
High-Z
DOUT
FIGURE 6. CAS BEFORE RAS REFRESH CYCLE
14
GM71V(S)65403A/AL
LG Semicon
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RP
RAS
CAS
tT
t
CHR
t
RSH
t
RCD
t
CRP
t
CAS
t
RAD
t
RAL
t
ASR
t
RAH
t
CAH
t
ASC
ADDRESS
ROW
COLUMN
t
RCH
t
RCS
t
RRH
WE
t
WDD
t
DZC
t
CDD
t
RDD
High-Z
DIN
t
DZO
t
OAC
t
ODD
OE
t
t
CAC
t
t
t
t
t
OEZ
AA
WEZ
t
RAC
OHO
OFF
OH
t
CLZ
DOUT
DOUT
t
OFR
t
OHR
FIGURE 7. HIDDEN REFRESH CYCLE
15
GM71V(S)65403A/AL
LG Semicon
tRASP
tRP
tHPC
RAS
tCRP
tRHCP
tHPC
tHPC
tT
tCSH
tCP
tCP
tCP
tRSH
CAS
tCAS
tCAS
tCAS
tCAS
tRCHR
tRCHP
t
RRH
tRCS
tRCH
tRCH
WE
tRAL
tWDD
t
WPE
tCAH
tCAH
tCAH
tRAH
tCAH
tASR
tASC
tASC
tASC
tASC
ADDRESS
ROW
COLUMN
COLUMN
COLUMN
COLUMN
tCAL
tCAL
tCAL
t
RDD
CDD
tCAL
tDZC
t
High-Z
DIN
t
COL
tDZO
t
COP
OEP
tOEP
tODD
t
OE
t
tOOHFRR
t
OEZ
t
ACP
t
OAC
CAC
tOEZ
t
OHO
t
t
ACP
t
AA
t
OHO
AA
t
CAC
t
tCAC
tCAC
tOFF
t
WEZ
AA
tAA
t
OEZ
tOH
t
OAC
tOAC
t
t
DOH
tRAC
t
OHO
t
ACP
High-Z
DOUT
DOUT 1
DOUT 2
DOUT 2
DOUT 3
DOUT 4
FIGURE 8. EXTENDED DATA OUT PAGE MODE READ CYCLE(1)
16
GM71V(S)65403A/AL
LG Semicon
tRASP
tRP
tHPC
RAS
tCRP
tRHCP
tHPC
tHPC
tT
tCSH
tCP
tCP
tCP
tRSH
CAS
tCAS
tCAS
tCAS
tCAS
tRCHP
t
RRH
tRCS
tRCH
WE
tRAL
tWDD
tCAH
tCAH
tCAH
tRAH
tCAH
tASR
tASC
tASC
tASC
tASC
ADDRESS
ROW
COLUMN1
COLUMN2
COLUMN3
COLUMN4
tCAL
tCAL
tCAL
t
RDD
CDD
tCAL
tDZC
t
High-Z
DIN
t
COL
tDZO
t
COP
OEP
tOEP
tODD
t
OE
t
tOOHFRR
t
OEZ
t
ACP
t
OAC
tOEZ
t
OHO
t
t
ACP
t
AA
t
OHO
AA
tCAC
t
CAC
tCAC
tCAC
tOFF
tAA
tAA
t
OEZ
tOH
t
OAC
tOAC
t
DOH
tDOH
tRAC
t
ACP
t
OHO
High-Z
DOUT
DOUT 1
DOUT 2
DOUT 2
DOUT 3
DOUT 4
FIGURE 8. EXTENDED DATA OUT PAGE MODE READ CYCLE(2)
17
GM71V(S)65403A/AL
LG Semicon
t
RP
t
RASP
RAS
tT
t
HPC
t
CSH
t
RSH
t
CRP
t
RCD
t
CAS
t
CP
t
CAS
t
CP
t
CAS
CAS
t
ASR
t
CAH
t
ASC
t
ASC
t
ASC
t
RAH
t
CAH
t
CAH
ADDRESS
ROW
COLUMN 1
COLUMN 2
COLUMN N
t
WCS
t
WCS
t
WCH
t
WCH
t
WCS
t
WCH
WE
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
D
D
IN
D
IN 1
D
IN 2
DIN N
High-Z*
OUT
FIGURE 10. EXTENDED DATA OUT MODE EARLY WRITE CYCLE
18
GM71V(S)65403A/AL
LG Semicon
tRP
tRASP
RAS
tCP
tCP
tCRP
tT
tCSH
tHPC
tRSH
tRCD
tCAS
tCAS
tCAS
CAS
tASC
tASR
tASC
tASC
tRAD
tRAH
tCAH
tCAH
tCAH
ADDRESS
ROW
COLUMN 1
COLUMN 2
COLUMN N
tCWL
tCWL
tCWL
t
RWL
t
RCS
t
RCS
DZC
t
RCS
WE
tWP
tWP
t
WP
t
DZC
tDS
tDS
tDS
t
tDZC
tDH
tDH
tDH
DIN
DIN 1
DIN 2
DIN N
tDZO
tDZO
tDZO
tODD
tODD
tODD
tOEH
tOEH
tOEH
OE
tOEP
tOEP
tCLZ
tCLZ
tCLZ
tOEZ
tOEZ
tOEZ
High-Z
INVALID
INVALID
INVALID
DOUT
DOUT
DOUT
DOUT
*18
FIGURE 11. EXTENDED DATA OUT MODE DELAYED WRITE CYCLE
19
GM71V(S)65403A/AL
LG Semicon
tRP
tRASP
RAS
t
HPRWC
tCRP
tT
t
RSH
tCP
tCP
tRCD
tCAS
tCAS
t
CAS
CAS
tRAD
tASR
tASC
tASC
tASC
tRAH
tCAH
tCAH
tCAH
ADDRESS
ROW
COLUMN 1
COLUMN 2
COLUMN N
t
CPW
t
CPW
AWD
CWD
t
RWD
AWD
CWD
tCWL
tCWL
t
CWL
t
AWD
t
t
t
t
t
CWD
t
RWL
tRCS
tRCS
tRCS
WE
tWP
tWP
tWP
tDZC
tDS
tDS
tDS
tDZC
tDZC
tDH
tDH
tDH
High-Z
DIN
OE
DIN 1
DIN 2
DIN N
tDZO
tDZO
t
OEP
t
OEP
t
OEP
t
DZO
tODD
tODD
tOEH
tOEH
tOEH
tODD
t
OEZ
t
OEZ
tOEZ
t
OHO
tOHO
t
OHO
t
t
OAC
CAC
AA
t
OAC
CAC
t
OAC
CAC
t
t
t
AA
t
t
AA
tACP
t
ACP
tRAC
tCLZ
tCLZ
tCLZ
DOUT 1
DOUT 2
DOUT N
High-Z
DOUT
*18
FIGURE 12. EXTENDED DATA OUT MODE READ MODIFY WRITE CYCLE
20
GM71V(S)65403A/AL
LG Semicon
tRP
tRASP
RAS
tT
tCP
tCP
tCP
tCRP
tCAS
tCAS
tCAS
tCAS
CAS
tRCD
tCSH
tWP
t
RSH
RAL
tWCS
tWCH
tRRH
tRCS
tRCH
tCPW
t
WE
tAWD
tASC
tASC
tASC
tRAH
tASC
tCAH
tCAH
tCAH
tASR
tCAH
COLUMN
4
COLUMN
1
COLUMN
3
COLUMN
2
ROW
ADDRESS
t
RDD
tDS
tCAL
tCAL
tDH
tDS
t
CDD
tDH
High - Z
DIN 1
DIN 3
Din
tWDD
tODD
tOEP
OE
t
CAC
t
t
CAC
t
OFR
t
CAC
t
WEZ
t
DOH
t
OEZ
AA
tOAC
t
OEZ
t
OFF
tOAC
tAA
tAA
t
OHO
tOH
tACP
t
ACP
tACP
High - Z
DOUT 2
DOUT
4
Dout
DOUT 3
*20
FIGURE 13. EXTENDED DATA OUT MODE MIX CYCLE (1)
21
GM71V(S)65403A/AL
LG Semicon
tRP
tRASP
RAS
tT
tCSH
tCRP
tCP
tCP
tCP
tCAS
tCAS
tCAS
tCAS
CAS
tRCD
t
RCHR
t
RRH
t
RSH
RAL
tWCH
tWP
t
RCH
tRCS
t
RCH
t
WCS
tCPW
t
WE
tASC
tASC
tASC
tASC
tRAH
tCAH
tCAH
tCAH
tCAH
tASR
COLUMN
3
COLUMN
4
COLUMN
2
COLUMN
1
ROW
ADDRESS
t
CAL
tCAL
t
CAL
tCAL
t
t
RDD
tDS
tDS
t
DH
t
DH
CDD
High - Z
Din
DIN 2
DIN 3
tODD
tWDD
tODD
tCOL
tOEP
tOEP
OE
t
COP
t
CAC
t
CAC
t
CAC
t
t
WEZ
t
t
t
AA
t
AA
OAC
OAC
tOEZ
OEZ
t
AA
OAC
RAC
t
OEZ
t
OFF
OH
OFR
OAC
t
t
t
t
t
tOHO
ACP
t
High - Z
DOUT 3
DOUT 1
DOUT 4
Dout
tOHO
*20
FIGURE 14. EXTENDED DATA OUT MODE MIX CYCLE (2)
22
GM71V(S)65403A/AL
LG Semicon
t
RP
t
RASS
t
RPS
RAS
t
RPC
t
T
t
CHS
t
CRP
t
CSR
t
CP
CAS
t
WRP
t
WRH
WE
t
OFR
t
OFF
High-Z
DOUT
*23, 24, 25, 26
FIGURE 15. SELF REFRESH CYCLE
23
GM71V(S)65403A/AL
LG Semicon
SOJ 32 pin PKG Dimension
Unit: mm
0.64 MIN
1.16 MAX
2.09 MIN
3.01 MAX
20.95 MIN
21.38 MAX
1.165 MAX
0.33 MIN
0.53 MAX
1.27
0.33 MIN
0.49 MAX
0.10
24
GM71V(S)65403A/AL
LG Semicon
TSOPII 32 PIN Package Dimension
0.40 MIN
Unit: mm
¡ £
20.95 MIN
21.35 MAX
0.60 MAX
0 ~ 5
NORMAL TYPE
0.145
0.125
0.05
0.04
0.80
1.15 MAX
0.42 0.08
0.40 0.06
1.27
0.08 MIN
0.18 MAX
0.10
Dimension including the plating thickness
Base material dimension
25
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