HD74HC668/HD74HC669 [ETC]
;
ETC 
HD74HC668/HD74HC669
Synchronous UP/Down Decade Counter
Synchronous Up/Down 4-bit binary Counter
ADE-205-520 (Z)
1st. Edition
Sep. 2000
Description
This synchronous presettable decade counter features an internal carry look-ahead for cascading in high-
speed counting applications. Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each other when so instructed by the count-
enable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that
are normally associated with asynchronous (ripple-clock) counters.
A buffered clock input triggers the four master-slave flip-flops on the rising (positive going) edge of the
clock waveform. This counter is fully programmable; that is, the outputs may each be preset to either level.
The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is
synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree
with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count enable inputs and a carry
output. Both count enable inputs (P and T) must be low to count. The direction of the count is determined
by the level of the up/down input. when the input is high, the counter counts up; when low, it counts down.
Input T is fed forward to enable the carry output. The carry output thus enabled will produce a low-level
output pulse with a duration approximately equal to the high portion of the QA output when counting up
and approximately equal to the low portion of the QA output when counting down. This low level overflow
carry pulse can be used to enable successive cascaded stages. Transitions at the enable P or T inputs are
allowed regardless of the level of the clock input. All inputs are diode-clamped to minimize transission-
line effects, thereby simplifying system design. This counter features a fully independent clock circuit.
Changes at control inputs (enable P, Enable T, load, up/down) that will modify the operating mode have no
effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting)
will be dictated solely by the conditions meeting the stable setup and hold times.
Features
•
•
•
•
High Speed Operation
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
HD74HC668/HD74HC669
•
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Pin Arrangement
HD74HC668
U/D
CK
A
1
2
3
4
5
6
7
8
16 VCC
Ripple
carry
15
output
14 QA
B
13 QB
Data
inputs
Outputs
C
12 QC
D
11 QD
Enable
P
10 Enable T
GND
9
Load
(Top view)
2
HD74HC668/HD74HC669
HD74HC669
U/D
CK
A
1
2
3
4
5
6
7
8
16 VCC
Ripple
carry
output
15
14 QA
13 QB
12 QC
11 QD
B
Data
inputs
Outputs
C
D
Enable
Enable
10
9
T
P
GND
Load
(Top view)
3
HD74HC668/HD74HC669
Logic Diagram
HD74HC668
L
T
Q
QA
U/D
IN
Q
CK
DA
Load
L
Enable P
Enable T
T
Q
QB
IN
Q
CK
DB
L
T
Q
QC
IN
Q
CK
DC
VCC
L
T
Q
QD
IN
Q
CK
DD
RCO
CK
4
HD74HC668/HD74HC669
HD74HC669
T
Q
QA
U/D
IN
Q
DA
Load
Enable P
Enable T
T
Q
QB
IN
Q
DB
T
Q
QC
IN
Q
DC
T
Q
QD
IN
Q
DD
RCO
VCC
CK
5
HD74HC668/HD74HC669
Timing Chart
HD74HC668
Load
A
B
Data
inputs
C
D
Clock
U/D
Enable P and T
QA
QB
QC
QD
Ripple
carry
output
7
8
9
0
1
2
2
2
1
0
9
8
7
Count up
Inhibit
Count down
Load
6
HD74HC668/HD74HC669
HD74HC669
Load
A
B
Data
inputs
C
D
Clock
U/D
P and T
QA
QB
QC
QD
Ripple
carry
output
13
14
15
0
1
2
2
2
1
0
15
14
13
Count up
Inhibit
Count down
Load
7
HD74HC668/HD74HC669
DC Characteristics
Ta = –40 to
Ta = 25°C
+85°C
Item
Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Input voltage
VIH
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
1.5
—
—
—
—
0.5
1.5
3.15
4.2
—
—
V
V
V
3.15 —
—
4.2
—
—
—
—
—
—
—
—
VIL
0.5
1.35
1.8
—
1.35 —
1.8
—
—
—
—
—
—
Output voltage
VOH
1.9 2.0
4.4 4.5
5.9 6.0
4.18 —
5.68 —
1.9
4.4
5.9
4.13
5.63
—
Vin = VIH or VIL IOH = –20 µA
—
—
—
IOH = –4 mA
IOH = –5.2 mA
—
VOL
—
—
—
—
—
—
—
0.0 0.1
0.0 0.1
0.0 0.1
0.1
0.1
0.1
0.33
0.33
V
Vin = VIH or VIL IOL = 20 µA
—
—
—
—
—
—
0.26 —
0.26 —
±0.1 —
4.0
IOL = 4 mA
IOL = 5.2 mA
Input current
Iin
±1.0 µA
40 µA
Vin = VCC or GND
Quiescent supply ICC
current
—
Vin = VCC or GND, Iout = 0 µA
8
HD74HC668/HD74HC669
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = –40 to
+85°C
Ta = 25°C
Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Item
Maximum clock
Frequency
fmax
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
80
16
14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
—
—
—
4
MHz
27
32
21
25
Propagation delay tPLH
200 —
250 ns
Clock to Ripple carry out
Clock to Q
time
tPHL
40
34
—
—
50
43
tPLH
tPHL
225 —
280 ns
45
38
—
—
56
48
tPLH
tPHL
150 —
190 ns
Enable T to Ripple carry out
U/D to Ripple carry out
30
26
—
—
38
33
tPLH
tPHL
200 —
250 ns
40
34
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
43
—
Pulse width
Setup time
tw
100
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
17
tsu
tsu
tsu
tsu
100 —
125
25
Data to Clock
20
17
—
—
21
150 —
190
38
Enable P, T to Clock
Loadk to Clock
U/D to Clock
30
26
—
—
33
150 —
190
38
30
26
—
—
33
150 —
190
38
30
26
—
—
33
9
HD74HC668/HD74HC669
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont)
Ta = –40 to
Ta = 25°C
+85°C
Item
Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Hold time
th
2.0
4.5
6.0
2.0
4.5
6.0
—
5
—
—
—
—
5
—
—
—
75
15
13
10
5
—
—
—
95
19
16
10
ns
ns
pF
5
5
5
5
Output rise/fall
time
tTLH
tTHL
—
—
—
—
—
—
—
—
—
5
Input capacitance Cin
10
HD74HC668/HD74HC669
Package Dimensions
Unit: mm
19.20
20.00 Max
16
1
9
8
1.3
1.11 Max
7.62
+ 0.13
– 0.05
0.25
2.54 ± 0.25
0.48 ± 0.10
0° – 15°
Hitachi Code
DP-16
JEDEC
EIAJ
Mass (reference value)
Conforms
Conforms
1.07 g
Unit: mm
10.06
10.5 Max
9
8
16
1
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0° – 8°
1.27
0.70 ± 0.20
*0.42 ± 0.08
0.40 ± 0.06
0.15
M
0.12
Hitachi Code
JEDEC
FP-16DA
—
EIAJ
Conforms
0.24 g
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
11
HD74HC668/HD74HC669
Unit: mm
9.9
10.3 Max
9
16
1
8
1.27
+ 0.10
6.10
– 0.30
1.08
0.635 Max
0° – 8°
+ 0.67
0.60
– 0.20
*0.42 ± 0.08
0.40 ± 0.06
0.15
0.25
M
Hitachi Code
JEDEC
EIAJ
FP-16DN
Conforms
Conforms
0.15 g
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
12
HD74HC668/HD74HC669
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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For further information write to:
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Hitachi Europe Ltd.
Electronic Components Group.
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Maidenhead
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(Taipei Branch Office)
4/F, No. 167, Tun Hwa North Road,
Hung-Kuo Building,
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Telex : 23222 HAS-TP
URL : http://www.hitachi.com.tw
Copyright Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
Colophon 2.0
13
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