HUFA75229P3 [ETC]
TRANSISTOR | MOSFET | N-CHANNEL | 50V V(BR)DSS | 44A I(D) | TO-220AB ; 晶体管| MOSFET | N沟道| 50V V( BR ) DSS | 44A I( D) | TO- 220AB\n型号: | HUFA75229P3 |
厂家: | ETC |
描述: | TRANSISTOR | MOSFET | N-CHANNEL | 50V V(BR)DSS | 44A I(D) | TO-220AB
|
文件: | 总9页 (文件大小:195K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HUFA75229P3
Data Sheet
December 2001
44A, 50V, 0.022 Ohm, N-Channel UltraFET
Power MOSFET
Features
• 44A, 50V
This N-Channel power MOSFET is
manufactured using the innovative
UltraFET® process. This advanced
• Low On-Resistance, r
= 0.022Ω
DS(ON)
• Temperature Compensating PSPICE® Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
Ordering Information
PART NUMBER
PACKAGE
BRAND
75229P
G
HUFA75229P3
TO-220AB
NOTE: When ordering use the entire part number.
S
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUFA75229P3 Rev. B
HUFA75229P3
o
Absolute Maximum Ratings
T = 25 C, Unless Otherwise Specified
C
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
50
50
V
V
V
DSS
Drain to Gate Voltage (R
= 20kΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±20
GS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
44
A
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Figure 5
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Figure 6, 14, 15
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
90
0.6
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 175
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250µA, V = 0V (Figure 11)
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
Gate to Source Threshold Voltage
Zero Gate Voltage Drain Current
I
50
-
-
-
4
DSS
GS(TH)
D
GS
= V , I = 250µA (Figure 10)
V
V
V
V
V
2
V
GS
DS
DS
GS
DS D
I
= 45V, V
= 40V, V
= ±20V
= 0V
-
-
1
µA
µA
nA
Ω
DSS
GS
GS
o
= 0V, T = 150 C
-
-
250
±100
0.022
105
-
C
Gate to Source Leakage Current
Drain to Source On Resistance
Turn-On Time
I
-
-
GSS
r
I
= 44A, V
= 10V (Figure 9)
= 30V, I 44A,
D
0.017
0.020
-
DS(ON)
D GS
t
V
R
R
-
-
-
-
-
-
-
-
-
ns
ON
DD
= 0.68Ω, V = 10V,
L
GS
Turn-On Delay Time
Rise Time
t
12
58
33
33
-
ns
d(ON)
= 9.1Ω
GS
(Figures 18, 19)
t
-
ns
r
Turn-Off Delay Time
Fall Time
t
-
ns
d(OFF)
t
-
ns
f
Turn-Off Time
t
100
75
43
2.5
ns
OFF
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Q
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
DD
= 30V,
44A,
60
35
2.0
nC
nC
nC
g(TOT)
GS
GS
GS
I
D
Q
g(10)
g(TH)
R
= 0.68Ω
L
I
= 1.0mA
Q
g(REF)
(Figures 13, 16, 17)
Input Capacitance
C
V
= 25V, V
GS
= 0V,
-
-
-
-
-
1060
-
-
pF
pF
pF
ISS
OSS
RSS
DS
f = 1MHz
(Figure 12)
Output Capacitance
C
C
405
Reverse Transfer Capacitance
95
-
-
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
(Figure 3)
TO-220
1.66
62
C/W
θJC
θJA
o
R
-
C/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
72
UNITS
V
V
I
I
I
= 44A
-
-
-
-
-
-
SD
SD
SD
SD
t
= 44A, dI /dt = 100A/µs
SD
ns
rr
Reverse Recovered Charge
Q
= 44A, dI /dt = 100A/µs
SD
120
nC
RR
©2001 Fairchild Semiconductor Corporation
HUFA75229P3 Rev. B
HUFA75229P3
Typical Performance Curves
1.2
1.0
0.8
50
40
30
20
0.6
0.4
0.2
0
10
0
0
25
50
75
100
125
o
150
175
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
T , CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
PEAK T = P
x Z
x R
+ T
JC C
J
DM
JC
θ
θ
0.01
-5
10
-4
10
-3
10
-2
-1
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
400
200
100
o
T = 25 C
C
FOR TEMPERATURES
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
T
= MAX RATED
J
o
o
T
= 25 C
C
175 - T
I = I
C
25
150
100µs
10
1ms
100
40
V
= 10V
GS
10ms
OPERATION IN THIS
AREA MAY BE
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
LIMITED BY r
BV
MAX = 50V
DS(ON)
DSS
1
-5
-4
-3
10
-2
-1
0
1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
10
10
10
10
10
10
V
t, PULSE WIDTH (s)
DS
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUFA75229P3 Rev. B
HUFA75229P3
Typical Performance Curves (Continued)
100
80
60
40
20
300
V
= 20V
= 10V
= 8V
If R = 0
GS
t
= (L)(I )/(1.3*RATED BV
- V
)
DD
V
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
DSS
GS
V
GS
t
AV
- V ) +1]
DD
AS DSS
V
= 7V
GS
V
= 6V
= 5V
GS
100
o
STARTING T = 25 C
J
V
GS
o
STARTING T = 150 C
J
PULSE DURATION = 250µs
o
T
= 25 C
C
10
0.001
0
0.01
t
0.1
1
10
0
1
V
2
3
4
5
, TIME IN AVALANCHE (ms)
, DRAIN TO SOURCE VOLTAGE (V)
AV
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
2.5
2.0
100
PULSE TEST
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 250µs, V = 10V, I = 44A
GS D
o
-55 C
80
60
40
20
0
o
175 C
1.5
1.0
0.5
o
V
= 15V
25 C
DD
-80
-40
0
40
80
120
160
200
0
1.5
3.0
4.5
6.0
7.5
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.0
1.2
1.1
1.0
0.9
0.8
V
= V , I = 250µA
DS
I
= 250µA
GS
D
D
0.8
0.6
0.4
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUFA75229P3 Rev. B
HUFA75229P3
Typical Performance Curves (Continued)
10
1500
V
= 30V
DD
V
= 0V, f = 1MHz
GS
8
6
4
2
0
1200
900
600
300
0
C
ISS
WAVEFORMS IN
DESCENDING ORDER:
C
C
OSS
RSS
I
I
I
= 44A
= 27A
= 11A
D
D
D
0
5
10
15
20
25
30
35
0
10
20
30
40
50
Q , GATE CHARGE (nC)
g
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
©2001 Fairchild Semiconductor Corporation
HUFA75229P3 Rev. B
HUFA75229P3
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
-
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
g(TOT)
R
DD
L
V
DS
V
= 20V
GS
V
Q
GS
g(10)
+
-
V
DD
V
= 10V
V
GS
GS
DUT
V
= 2V
GS
I
0
G(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
©2001 Fairchild Semiconductor Corporation
HUFA75229P3 Rev. B
HUFA75229P3
PSPICE Electrical Model
SUBCKT HUFA75229P3 2 1 3 ;
rev 6/19/97
CA 12 8 1.72e-9
CB 15 14 1.52e-9
CIN 6 8 9.61e-10
LDRAIN
DPLCAP
5
DRAIN
2
10
RLDRAIN
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
-
50
EBREAK 11 7 17 18 58.13
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
+
-
17
DBODY
RDRAIN
6
8
EBREAK 18
ESG
-
EVTHRES
+
16
21
+
-
EVTEMP 20 6 18 22 1
19
8
MWEAK
LGATE
EVTEMP
+
RGATE
GATE
6
-
18
22
MMED
1
IT 8 17 1
9
20
MSTRO
8
RLGATE
LDRAIN 2 5 1e-9
LGATE 1 9 2.86e-9
LSOURCE 3 7 2.69e-9
LSOURCE
CIN
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
S2A
RBREAK
12
15
13
14
13
17
18
8
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
RGATE 9 20 1.52
RLDRAIN 2 5 10
RLGATE 1 9 26.9
RLSOURCE 3 7 28.6
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RSOURCE 8 7 RSOURCEMOD 13.85e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*135),3.5))}
.MODEL DBODYMOD D (IS = 7.50e-13 RS = 5.05e-3 TRS1 = 2.21e-3 TRS2 = 1.02e-6 CJO = 1.51e-9 TT = 4.05e-8 M = 0.5)
.MODEL DBREAKMOD D (RS = 2.14e- 1TRS1 = 9.62e- 4TRS2 = 1.23e-6)
.MODEL DPLCAPMOD D (CJO = 13.5e-1 0IS = 1e-3 0N = 10 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 2.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.52)
.MODEL MSTROMOD NMOS (VTO = 3.80 KP = 70.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.91 KP = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 15.2 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.05e- 3TC2 = 1.94e-7)
.MODEL RDRAINMOD RES (TC1 = 8.04e-2 TC2 = 1.37e-4)
.MODEL RSLCMOD RES (TC1 = 4.83e-3 TC2 = 1.16e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -3.43e-3 TC2 = -1.63e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.35e- 3TC2 = 1.16e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.90 VOFF= -4.90)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.90 VOFF= -7.90)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.50 VOFF= 2.50)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.50 VOFF= -0.50)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUFA75229P3 Rev. B
HUFA75229P3
SPICE Thermal Model
JUNCTION
7
REV 16 June 97
HUFA75229P3
RTHERM1
CTHERM1
CTHERM1 7 6 4.90e-7
CTHERM2 6 5 4.90e-4
CTHERM3 5 4 1.96e-3
CTHERM4 4 3 7.90e-3
CTHERM5 3 2 1.85e-1
CTHERM6 2 1 2.70
6
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 7 6 1.10e-2
RTHERM2 6 5 3.30e-2
RTHERM3 5 4 1.64e-1
RTHERM4 4 3 7.90e-1
RTHERM5 3 2 3.60e-1
RTHERM6 2 1 1.60e-1
5
4
3
2
1
CASE
©2001 Fairchild Semiconductor Corporation
HUFA75229P3 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
â
SMART START™
STAR*POWER™
Stealth™
VCX™
FAST
ACEx™
Bottomless™
CoolFET™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
FASTr™
FRFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
CROSSVOLT™
DenseTrench™
DOME™
POP™
Power247™
PowerTrenchâ
QFET™
EcoSPARK™
E2CMOSTM
TinyLogic™
QS™
EnSignaTM
TruTranslation™
UHC™
QT Optoelectronics™
Quiet Series™
SILENTSWITCHERâ
FACT™
FACT Quiet Series™
UltraFETâ
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OFANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
相关型号:
HUFA75307T3ST_NL
Power Field-Effect Transistor, 2.6A I(D), 55V, 0.09ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE PACKAGE-4
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明