HWD2108 [ETC]
Dual 105 mW Headphone Amplifier; 双105毫瓦耳机放大器
| 型号： | HWD2108 |
| 厂家： | 
ETC |
| 描述： | Dual 105 mW Headphone Amplifier |
| 文件： | 总18页 (文件大小：935K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Audio Power Amplifier
HWD2108
Dual 105 mW Headphone Amplifier
General Description
The HWD2108 is a dual audio power amplifier capable of
delivering 105mW per channel of continuous average power
into a 16Ω load with 0.1% (THD+N) from a 5V power supply.
Key Specifications
n THD+N at 1kHz at 105mW continuous average output
power into 16Ω
n THD+N at 1kHz at 70mW continuous average output
0.1% (typ)
power into 32Ω
n Output power at 0.1% THD+N at 1kHz into 32Ω 70mW
(typ)
0.1% (typ)
audio power amplifiers were designed specifically to
provide high quality output power with a minimal amount of
external components using surface mount packaging. Since
the HWD2108 does not require bootstrap capacitors or snub-
ber networks, it is optimally suited for low-power portable
systems.
Features
n LLP, MSOP, and SOP surface mount packaging
n Switch on/off click suppression
n Excellent power supply ripple rejection
n Unity-gain stable
The unity-gain stable HWD2108 can be configured by external
gain-setting resistors.
n Minimum external components
Applications
n Headphone Amplifier
n Personal Computers
n Portable electronic devices
Typical Application
*Refer to the Application Information Section for information concerning proper selection of the input and output coupling capacitors.
FIGURE 1. Typical Audio Amplifier Application Circuit
1
Connection Diagrams
LLP Package
Top View
Order Number HWD2108LD
SOP & MSOP Package
Top View
Order Number HWD2108M, HWD2108MM
Typical Application
2
Absolute Maximum Ratings (Note 3)
If Military/Aerospace specified devices are required,
please contact the CSMSC Semiconductor Sales Office/
Distributors for availability and specifications.
θJC (MSOP)
θJA (MSOP)
θJC (SOP)
θJA (SOP)
θJC (LLP)
θJA (LLP)
56˚C/W
210˚C/W
35˚C/W
170˚C/W
Supply Voltage
6.0V
−65˚C to +150˚C
−0.3V to VDD + 0.3V
Internally limited
3500V
15˚C/W
Storage Temperature
Input Voltage
117˚C/W (Note 9)
150˚C/W (Note 10)
θJA (LLP)
Power Dissipation (Note 4)
ESD Susceptibility (Note 5)
ESD Susceptibility (Note 6)
Junction Temperature
Soldering Information (Note 1)
Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
Thermal Resistance
Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX
Supply Voltage
250V
150˚C
−40˚C ≤ T ≤ 85˚C
A
2.0V ≤ VDD ≤ 5.5V
Note 1: See AN-450 “Surface Mounting and their Effects on Product Reli-
ability” for other methods of soldering surface mount devices.
215˚C
220˚C
Electrical Characteristics (Notes 2, 3)
The following specifications apply for VDD = 5V unless otherwise specified, limits apply to TA = 25˚C.
Symbol
Parameter
Conditions
HWD2108
Units
(Limits)
Typ (Note Limit (Note
7)
8)
2.0
5.5
3.0
16.5
50
VDD
Supply Voltage
V (min)
V (max)
IDD
Supply Current
VIN = 0V, IO = 0A
1.2
6
mA (max)
Ptot
Total Power Dissipation
Input Offset Voltage
Input Bias Current
VIN = 0V, IO = 0A
VIN = 0V
mW (max)
VOS
Ibias
10
10
0
mV (max)
pA
V
VCM
Common Mode Voltage
4.3
67
70
0.1
.3
V
GV
Io
Open-Loop Voltage Gain
Max Output Current
Output Resistance
Output Swing
RL = 5kΩ
dB
mA
Ω
<
THD+N 0.1 %
RO
VO
RL = 32Ω, 0.1% THD+N, Min
RL = 32Ω, 0.1% THD+N, Max
Cb = 1.0µF, Vripple = 100mVPP
f = 100Hz
V
4.7
89
PSRR
Power Supply Rejection Ratio
Channel Separation
,
dB
Crosstalk
THD+N
RL = 32Ω
75
dB
Total Harmonic Distortion + Noise f = 1 kHz
RL = 16Ω,
0.05
66
%
dB
VO =3.5VPP (at 0 dB)
RL = 32Ω,
0.05
66
%
VO =3.5VPP (at 0 dB)
dB
SNR
fG
Signal-to-Noise Ratio
Unity Gain Frequency
Output Power
VO = 3.5Vpp (at 0 dB)
Open Loop, RL = 5kΩ
THD+N = 0.1%, f = 1 kHz
RL = 16Ω
105
5.5
dB
MHz
Po
105
70
mW
mW
RL = 32Ω
60
THD+N = 10%, f = 1 kHz
RL = 16Ω
150
90
3
mW
mW
pF
RL = 32Ω
CI
Input Capacitance
3
Electrical Characteristics (Notes 2, 3) (Continued)
The following specifications apply for VDD = 5V unless otherwise specified, limits apply to TA = 25˚C.
Symbol
Parameter
Conditions
HWD2108
Units
(Limits)
Typ (Note Limit (Note
7)
8)
CL
Load Capacitance
Slew Rate
200
pF
SR
Unity Gain Inverting
3
V/µs
Electrical Characteristics (Notes 2, 3)
The following specifications apply for VDD = 3.3V unless otherwise specified, limits apply to TA = 25˚C.
Symbol Parameter Conditions Conditions
Typ (Note Limit (Note
Units
(Limits)
7)
1.0
7
8)
IDD
VOS
Po
Supply Current
VIN = 0V, IO = 0A
mA (max)
mV (max)
Input Offset Voltage
Output Power
VIN = 0V
THD+N = 0.1%, f = 1 kHz
RL = 16Ω
40
28
mW
mW
RL = 32Ω
THD+N = 10%, f = 1 kHz
RL = 16Ω
56
38
mW
mW
RL = 32Ω
Electrical Characteristics (Notes 2, 3)
The following specifications apply for VDD = 2.6V unless otherwise specified, limits apply to TA = 25˚C.
Symbol Parameter Conditions Conditions
Typ (Note Limit (Note
Units
(Limits)
7)
0.9
5
8)
IDD
VOS
Po
Supply Current
VIN = 0V, IO = 0A
mA (max)
mV (max)
Input Offset Voltage
Output Power
VIN = 0V
THD+N = 0.1%, f = 1 kHz
RL = 16Ω
20
16
mW
mW
RL = 32Ω
THD+N = 10%, f = 1 kHz
RL = 16Ω
31
22
mW
mW
RL = 32Ω
Note 2: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
, θ , and the ambient temperature T . The maximum
A
JMAX JA
allowable power dissipation is P
= (T
− T ) / θ . For the HWD2108, T
= 150˚C, and the typical junction-to-ambient thermal resistance, when board
JMAX
DMAX
JMAX
A
JA
mounted, is 210˚C/W for package MUA08A and 170˚C/W for package M08A.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: Machine Model, 220 pF–240 pF discharged through all pins.
Note 7: Typicals are measured at 25˚C and represent the parametric norm.
Note 8: Tested limits are guaranteed to CSMSC’s AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are guaranteed by design, test,
or statistical analysis.
Note 9: The given θ is for an HWD2108 packaged in an LDA08B with the Exposed-DAP soldered to a printed circuit board copper pad with an area equivalent to
JA
that of the Exposed-DAP itself.
Note 10: The given θ is for an HWD2108 packaged in an LDA08B with the Exposed-DAP not soldered to any printed circuit board copper.
JA
4
External Components Description (Figure 1)
Components
Functional Description
The inverting input resistance, along with Rf, set the closed-loop gain. Ri, along with Ci, form a high
pass filter with fc = 1/(2πRiCi).
1. Ri
The input coupling capacitor blocks DC voltage at the amplifier’s input terminals. Ci, along with Ri,
create a highpass filter with fC = 1/(2πRiCi). Refer to the section, Selecting Proper External
Components, for an explanation of determining the value of Ci.
The feedback resistance, along with Ri, set closed-loop gain.
2. Ci
3. Rf
This is the supply bypass capacitor. It provides power supply filtering. Refer to the Application
Information section for proper placement and selection of the supply bypass capacitor.
This is the half-supply bypass pin capacitor. It provides half-supply filtering. Refer to the section,
Selecting Proper External Components, for information concerning proper placement and selection
of CB.
4. CS
5. CB
This is the output coupling capacitor. It blocks the DC voltage at the amplifier’s output and forms a high
pass filter with RL at fO = 1/(2πRLCO)
6. CO
7. RB
This is the resistor which forms a voltage divider that provides 1/2 VDD to the non-inverting input of the
amplifier.
Typical Performance
Characteristics
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
5
Typical Performance Characteristics (Continued)
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
6
Typical Performance Characteristics (Continued)
THD+N vs Output Power
THD+N vs Output Power
THD+N vs Output Power
THD+N vs Output Power
THD+N vs Output Power
THD+N vs Output Power
7
Typical Performance Characteristics (Continued)
THD+N vs Output Power
THD+N vs Output Power
Output Power vs
Load Resistance
THD+N vs Output Power
Output Power vs
Load Resistance
Output Power vs
Load Resistance
8
Typical Performance Characteristics (Continued)
Output Power vs
Supply Voltage
Output Power vs
Power Supply
Output Power vs
Power Supply
Clipping Voltage vs
Supply Voltage
Power Dissipation vs
Output Power
Power Dissipation vs
Output Power
9
Typical Performance Characteristics (Continued)
Power Dissipation vs
Output Power
Channel Separation
Channel Separation
Noise Floor
Open Loop
Power Supply Rejection Ratio
Frequency Response
10
Typical Performance Characteristics (Continued)
Open Loop
Open Loop
Frequency Response
Frequency Response
Supply Current vs
Supply Voltage
Frequency Response vs
Output Capacitor Size
Frequency Response vs
Output Capacitor Size
Frequency Response vs
Output Capacitor Size
11
Typical Performance Characteristics (Continued)
Typical Application
Typical Application
Frequency Response
Frequency Response
12
POWER SUPPLY BYPASSING
Application Information
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically
use a 10µF in parallel with a 0.1µF filter capacitors to stabi-
lize the regulator’s output, reduce noise on the supply line,
and improve the supply’s transient response. However, their
presence does not eliminate the need for a local 0.1µF
supply bypass capacitor, CS, connected between the
HWD2108’s supply pins and ground. Keep the length of leads
and traces that connect capacitors between the HWD2108’s
power supply pin and ground as short as possible. Connect-
ing a 1.0µF capacitor, CB, between the IN A(+) / IN B(+) node
and ground improves the internal bias voltage’s stability and
improves the amplifier’s PSRR. The PSRR improvements
increase as the bypass pin capacitor value increases. Too
large, however, increases the amplifier’s turn-on time. The
selection of bypass capacitor values, especially CB, depends
on desired PSRR requirements, click and pop performance
(as explained in the section, Selecting Proper External
Components), system cost, and size constraints.
EXPOSED-DAP PACKAGE PCB MOUNTING
CONSIDERATION
The HWD2108’s exposed-dap (die attach paddle) package
(LD) provides a low thermal resistance between the die and
the PCB to which the part is mounted and soldered. This
allows rapid heat transfer from the die to the surrounding
PCB copper traces, ground plane, and surrounding air.
The LD package should have its DAP soldered to a copper
pad on the PCB. The DAP’s PCB copper pad may be con-
nected to a large plane of continuous unbroken copper. This
plane forms a thermal mass, heat sink, and radiation area.
However, since the HWD2108 is designed for headphone ap-
plications, connecting a copper plane to the DAP’s PCB
copper pad is not required. The HWD2108’s Power Dissipation
vs Output Power Curve in the Typical Performance Char-
acteristics shows that the maximum power dissipated is just
45mW per amplifier with a 5V power supply and a 32Ω load.
Further detailed and specific information concerning PCB
layout, fabrication, and mounting an LD (LLP) package is
available from CSMSC Semiconductor’s Package Engineer-
ing Group under application note AN1187.
SELECTING PROPER EXTERNAL COMPONENTS
Optimizing the HWD2108’s performance requires properly se-
lecting external components. Though the HWD2108 operates
well when using external components with wide tolerances,
best performance is achieved by optimizing component val-
ues.
POWER DISSIPATION
Power dissipation is a major concern when using any power
amplifier and must be thoroughly understood to ensure a
successful design. Equation 1 states the maximum power
dissipation point for a single-ended amplifier operating at a
given supply voltage and driving a specified output load.
The HWD2108 is unity-gain stable, giving a designer maximum
design flexibility. The gain should be set to no more than a
given application requires. This allows the amplifier to
achieve minimum THD+N and maximum signal-to-noise ra-
tio. These parameters are compromised as the closed-loop
gain increases. However, low gain demands input signals
with greater voltage swings to achieve maximum output
power. Fortunately, many signal sources such as audio
CODECs have outputs of 1VRMS (2.83VP-P). Please refer to
the Audio Power Amplifier Design section for more infor-
mation on selecting the proper gain.
2
PDMAX = (VDD
)
/ (2π2RL)
(1)
Since the HWD2108 has two operational amplifiers in one
package, the maximum internal power dissipation point is
twice that of the number which results from Equation 1. Even
with the large internal power dissipation, the HWD2108 does
not require heat sinking over a large range of ambient tem-
perature. From Equation 1, assuming a 5V power supply and
a 32Ω load, the maximum power dissipation point is 40mW
per amplifier. Thus the maximum package dissipation point
is 80mW. The maximum power dissipation point obtained
must not be greater than the power dissipation that results
from Equation 2:
Input and Output Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value
input and output coupling capacitors (CI and CO in Figure 1).
A high value capacitor can be expensive and may compro-
mise space efficiency in portable designs. In many cases,
however, the speakers used in portable systems, whether
internal or external, have little ability to reproduce signals
below 150Hz. Applications using speakers with this limited
frequency response reap little improvement by using high
value input and output capacitors.
PDMAX = (TJMAX − TA) / θJA
(2)
For package MUA08A, θJA = 210˚C/W. TJMAX = 150˚C for
the HWD2108. Depending on the ambient temperature,AT, of
the system surroundings, Equation 2 can be used to find the
maximum internal power dissipation supported by the IC
packaging. If the result of Equation 1 is greater than that of
Equation 2, then either the supply voltage must be de-
creased, the load impedance increased or TA reduced. For
the typical application of a 5V power supply, with a 32Ω load,
the maximum ambient temperature possible without violating
the maximum junction temperature is approximately 133.2˚C
provided that device operation is around the maximum
power dissipation point. Power dissipation is a function of
output power and thus, if typical operation is not around the
maximum power dissipation point, the ambient temperature
may be increased accordingly. Refer to the Typical Perfor-
mance Characteristics curves for power dissipation infor-
mation for lower output powers.
Besides affecting system cost and size, Ci has an effect on
the HWD2108’s click and pop performance. The magnitude of
the pop is directly proportional to the input capacitor’s size.
Thus, pops can be minimized by selecting an input capacitor
value that is no higher than necessary to meet the desired
−3dB frequency.
As shown in Figure 1, the input resistor, RI and the input
capacitor, CI, produce a −3dB high pass filter cutoff fre-
quency that is found using Equation (3). In addition, the
output load RL, and the output capacitor CO, produce a -3db
high pass filter cutoff frequency defined by Equation (4).
f
I-3db=1/2πRICI
(3)
(4)
f
O-3db=1/2πRLCO
13
package. Once the power dissipation equations have been
addressed, the required gain can be determined from Equa-
tion (7).
Application Information (Continued)
Also, careful consideration must be taken in selecting a
certain type of capacitor to be used in the system. Different
types of capacitors (tantalum, electrolytic, ceramic) have
unique performance characteristics and may affect overall
system performance.
(7)
Thus, a minimum gain of 1.497 allows the HWD2108 to reach
full output swing and maintain low noise and THD+N perfro-
mance. For this example, let AV=1.5.
Bypass Capacitor Value
Besides minimizing the input capacitor size, careful consid-
eration should be paid to the value of the bypass capacitor,
CB. Since CB determines how fast the HWD2108 settles to
quiescent operation, its value is critical when minimizing
turn-on pops. The slower the HWD2108’s outputs ramp to their
quiescent DC voltage (nominally 1/2 VDD), the smaller the
turn-on pop. Choosing CB equal to 1.0µF or larger, will
minimize turn-on pops. As discussed above, choosing Ci no
larger than necessary for the desired bandwith helps mini-
mize clicks and pops.
The amplifiers overall gain is set using the input (Ri ) and
feedback (Rf ) resistors. With the desired input impedance
set at 20kΩ, the feedback resistor is found using Equation
(8).
AV = Rf/Ri
(8)
The value of Rf is 30kΩ.
The last step in this design is setting the amplifier’s −3db
AUDIO POWER AMPLIFIER DESIGN
Design a Dual 70mW/32Ω Audio Amplifier
±
frequency bandwidth. To achieve the desired 0.25dB pass
band magnitude variation limit, the low frequency response
must extend to at lease one−fifth the lower bandwidth limit
and the high frequency response must extend to at least five
times the upper bandwidth limit. The gain variation for both
Given:
Power Output
Load Impedance
Input Level
70mW
32Ω
±
response limits is 0.17dB, well within the 0.25dB desired
1Vrms (max)
20kΩ
limit. The results are an
Input Impedance
Bandwidth
±
100Hz–20kHz 0.50dB
fL = 100Hz/5 = 20Hz
(9)
The design begins by specifying the minimum supply voltage
necessary to obtain the specified output power. One way to
find the minimum supply voltage is to use the Output Power
vs Supply Voltage curve in the Typical Performance Char-
acteristics section. Another way, using Equation (5), is to
calculate the peak output voltage necessary to achieve the
desired output power for a given load impedance. To ac-
count for the amplifier’s dropout voltage, two additional volt-
ages, based on the Dropout Voltage vs Supply Voltage in the
Typical Performance Characteristics curves, must be
and a
*
fH = 20kHz 5 = 100kHz
(10)
As stated in the External Components section, both Ri in
conjunction with Ci, and Co with RL, create first order high-
pass filters. Thus to obtain the desired low frequency re-
±
sponse of 100Hz within 0.5dB, both poles must be taken
added to the result obtained by Equation (5). For
single-ended application, the result is Equation (6).
a
into consideration. The combination of two single order filters
at the same frequency forms a second order response. This
results in a signal which is down 0.34dB at five times away
from the single order filter −3dB point. Thus, a frequency of
20Hz is used in the following equations to ensure that the
response is better than 0.5dB down at 100Hz.
(5)
(6)
Ci ≥ 1 / (2π * 20 kΩ * 20 Hz) = 0.397µF; use 0.39µF.
VDD ≥ (2VOPEAK + (VOD
+ VODBOT))
TOP
Co ≥ 1 / (2π * 32Ω * 20 Hz) = 249µF; use 330µF.
The Output Power vs Supply Voltage graph for a 32Ω load
indicates a minimum supply voltage of 4.8V. This is easily
met by the commonly used 5V supply voltage. The additional
voltage creates the benefit of headroom, allowing the
HWD2108 to produce peak output power in excess of 70mW
without clipping or other audible distortion. The choice of
supply voltage must also not create a situation that violates
maximum power dissipation as explained above in the
Power Dissipation section. Remember that the maximum
power dissipation point from Equation (1) must be multiplied
by two since there are two independent amplifiers inside the
The high frequency pole is determined by the product of the
desired high frequency pole, fH, and the closed-loop gain,
AV. With a closed-loop gain of 1.5 and fH = 100kHz, the
resulting GBWP = 150kHz which is much smaller than the
HWD2108’s GBWP of 900kHz. This figure displays that if a
designer has a need to design an amplifier with a higher
gain, the HWD2108 can still be used without running into
bandwidth limitations.
14
Demonstration
Board Layout
Recommended
LD PC Board Layout:
Recommended
SO PC Board Layout:
Top Silkscreen
Top Silkscreen
Recommended
SOP PC Board Layout:
Top Layer
Recommended
LD PC Board Layout:
Top Layer
Recommended
SOP PC Board Layout:
Bottom Layer
Recommended
LD PC Board Layout:
Bottom Layer
15
Physical Dimensions inches (millimeters)
unless otherwise noted
Order Number HWD2108LD
Order Number HWD2108M
16
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number HWD2108MM
17
Chengdu Sino Microelectronics System Co.,Ltd
(Http://www.csmsc.com)
Headquarters of CSMSC:
Beijing Office:
Address: 2nd floor, Building D,
Science & Technology
Industrial Park, 11 Gaopeng
Avenue, Chengdu High-Tech
Zone,Chengdu City, Sichuan
Province, P.R.China
Address: Room 505, No. 6 Building,
Zijin Garden, 68 Wanquanhe
Rd., Haidian District,
Beijing, P.R.China
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Tel: +86-28-8517-7737
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