HY57V653220BTC-7I [ETC]
x32 SDRAM ; X32 SDRAM\n
| 型号： | HY57V653220BTC-7I |
| 厂家： | 
ETC |
| 描述： | x32 SDRAM
|
| 文件： | 总11页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY57V653220B
4 Banks x 512K x 32Bit Synchronous DRAM
DE S CRIPT ION
T h e H y n i x H Y 5 7 V 6 5 3 2 2 0 B i s a 6 7 , 1 0 8 , 8 6 4 - b i t C M O S S y n c h r o n o u s D R A M , i d e a l l y s u i t e d f o r t h e M o b i l e a p p l i c a t i o n s
which require low power consumption and extended temperature range. HY57V653220B is organized as 4banks of
524, 288x32.
H Y 5 7 V 6 5 3 2 2 0 B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by
a
single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by
design is not restricted by a `2N` rule.)
a new burst read or write command on any cycle. (This pipelined
F EAT URES
•
JEDEC standard 3. 3V power supply
•
•
•
Auto refresh and self refresh
•
•
All device pins are compatible with LVTTL interface
4 0 9 6 r e f r e s h c y c l e s / 6 4 m s
J E D E C s t a n d a r d 4 0 0 m i l 8 6 p i n T S O P - I I w i t h 0 . 5 m m o f
pin pitch
P r o g r a m m a b l e B u r s t L e n g t h a n d B u r s t T y p e
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
All inputs and outputs referenced to positive edge of
system clock
•
•
D a t a m a s k f u n c t i o n b y D Q M 0 , 1 , 2 a n d 3
Internal four banks operation
•
•
P r o g r a m m a b l e C A S Latency ; 2, 3 Clocks
Burst Read Single Write operation
OR D E R IN G INF ORMAT ION
Par t No.
Cl ock Fr equency
Powe r
Or gani zat i on
Int er f ace
Package
H Y 5 7 V 6 5 3 2 2 0 B T C - 6 I
H Y 5 7 V 6 5 3 2 2 0 B T C -7 I
H Y 5 7 V 6 5 3 2 2 0 B T C - 1 0 I
H Y 5 7 V 6 5 3 2 2 0 B L T C - 6 I
H Y 5 7 V 6 5 3 2 2 0 B L T C - 7 I
H Y 5 7 V 6 5 3 2 2 0 B L T C - 1 0 I
1 6 6 M H z
14 3 M H z
1 0 0 M H z
1 6 6 M H z
1 4 3 M H z
1 0 0 M H z
4 B a n k s x 5 1 2 K b i t s
x 3 2
N o r m a l
L V T T L
400mil 86pin TSOP II
This document is
a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0. 6/ Aug. 01
HY57V653220 B
PIN CONF IGURAT ION
V DD
D Q 0
V DDQ
D Q 1
D Q 2
V SSQ
D Q 3
D Q 4
V DDQ
D Q 5
D Q 6
V SSQ
D Q 7
N C
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
1
V S S
2
3
D Q 1 5
V SSQ
D Q 1 4
D Q 1 3
V DDQ
D Q 1 2
D Q 1 1
V SSQ
D Q 1 0
D Q 9
V DDQ
D Q 8
N C
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
V DD
D Q M 0
/ W E
V S S
D Q M 1
N C
/ C A S
/ R A S
/ C S
N C
C L K
C K E
8 6 p i
n
l
T S OP
8 7 5 m il
p i c h
I I
N C
A 9
4 0 0 mi
x
B A 0
A 8
A 7
0 . 5 mm p i
n
t
B A 1
A 1 0 / A P
A 0
A 6
A 5
A 1
A 4
A 3
A 2
D Q M 2
V DD
D Q M 3
V S S
N C
N C
D Q 1 6
V SSQ
D Q 1 7
D Q 1 8
V DDQ
D Q 1 9
D Q 2 0
V SSQ
D Q 2 1
D Q 2 2
V DDQ
D Q 2 3
V DD
D Q 3 1
V DDQ
D Q 3 0
D Q 2 9
V SSQ
D Q 2 8
D Q 2 7
V DDQ
D Q 2 6
D Q 2 5
V SSQ
D Q 2 4
V S S
P IN DE S CRIPTION
PI N
P I N N A ME
D E S C R I PTI O N
The system clock input. All other inputs are registered to the SDRAM on the
r i s i n g e d g e o f C L K .
C L K
C l o c k
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
C K E
Clock Enable
C h i p S e l e c t
B a n k A d d r e s s
C S
E n a b l e s o r d i s a b l e s a l l i n p u t s e x c e p t C L K , C K E a n d D Q M
Selects bank to be activated during R A S activity
Selects bank to be read/written during C A S activity
B A 0 , B A 1
R o w A d d r e s s : R A 0 ~ R A 1 0 , C o l u m n A d d r e s s : C A 0 ~ C A 7
Auto-precharge flag : A10
A 0 ~ A 1 0
A d d r e s s
R o w A d d r e s s S t r o b e ,
C o l u m n A d d r e s s S t r o b e ,
Write Enable
R A S , C A S and W E define the operation
Refer function truth table for details
R A S , C A S , W E
D Q M 0 ~ 3
Data Input/Output Mask
Data Input/Output
C ontrols output buffers i n r e a d m o d e a n d m a s k s i n p u t d a t a i n w r i t e m o d e
Multiplexed data input / output pin
D Q 0
~ D Q 3 1
V D D/V S S
V D D Q/V S S Q
N C
P o w e r S u p p l y / G r o u n d
D a t a O u t p u t P o w e r / G r o u n d
N o C o n n e c t i o n
Power supply for internal circuit s and input buffers
Power supply for output buffers
N o c o n n e c t i o n
Rev. 0. 6/ Aug. 01
2
HY57V653220 B
F UNCT IONAL BL OCK DIA GR A M
5 1 2 Kbi t x 4banks x 32 I/O Sy n c h r o n o u s DRAM
S e l f R e f r e s h L o g i c
T i m e r
I n t e r n a l R o w
C o u n t e r
&
5 1 2 Kx 3 2 Ba n k 3
5 1 2 Kx 3 2 Ba n k 2
C L K
C K E
C S
R o w
P r e
R o w A c t i v e
D e c o d e r s
5 1 2 Kx 3 2 Ba n k 1
5 1 2 Kx 3 2 Ba n k 0
D Q 0
D Q 1
R A S
C A S
M e m o r y
C e l l
A r r a y
W E
C o l u m n
A c t i v e
C o l u m n
P r e
D Q M 0
D Q M 1
D Q M 2
D Q M 3
D e c o d e r s
D Q3 0
D Q3 1
Y
d e c o d e r s
C o l u m n A d d
C o u n t e r
B a n k S e l e c t
A 0
A 1
A d d r e s s
R e g i s t e r
B u r s t
C o u n t e r
A1 0
B A 0
B A 1
C A S L a t e n c y
P i p e L i n e C o n t r o l
M o d e R e g i s t e r s
D a t a O u t C o n t r o l
Rev. 0. 6/ Aug. 01
3
HY57V653220 B
ABS OL UT E MAX IMU M R A T IN G S
Par ame t er
S y mb o l
Rat i ng
Uni t
A m b i e n t T e m p e r a t u r e
T A
- 4 0 ~ 8 5
- 5 5 ~ 1 2 5
-1.0 ~ 4.6
-1.0 ~ 4.6
5 0
°C
S t o r a g e T e m p e r a t u r e
T S T G
°C
Voltage on Any Pin relative to V S S
Voltage on V D D relative to V S S
Short Circuit Output Current
Power Dissipation
V IN, V O U T
V
V D D , V D D Q
IO S
V
m A
P D
1
W
Soldering Temperature × T i m e
T S O L D E R
2 6 0 × 1 0
°C × S e c
N o t e : Operation at above absolute maximum rating can adversely affect device reliability
DC OP E RAT IN G C ON D ITION ( T A = -40 to 8 5 ° C )
Par ame t er
S y mb o l
M in
T y p .
Ma x
Uni t
N o te
P o w e r S u p p l y V o l t a g e
Input high voltage
Input low voltage
V D D , V D D Q
3 .0
2.0
3.3
3.0
0
3.6
V D D Q + 0.3
0.8
V
V
V
1 ,2
1 ,3
1 ,4
V IH
V IL
V S S Q - 0.3
N o t e :
1 .All voltages are referenced to V S S = 0V
2.V IH (max) is acceptable 5. 6V AC pulse width with £ 3ns of duration with no input clamp diodes
3 .V IL ( m in ) is acceptable -2. 0V AC pulse width with £ 3ns of duration with no input clamp diodes
AC OP E RAT IN G C ON D ITION ( T A = -40 to 8 5 ° C , 3. 0 V £V D D £ 3.6V, V S S = 0 V - Note1)
Pa r a me t e r
S y mb o l
Va l ue
Uni t
Not e
AC input high / low level voltage
V IH / V IL
Vtrip
2.4/0.4
1.4
V
V
Input timing measurement reference level voltage
Input rise / fall time
tR / tF
Voutref
C L
1
n s
V
Output timing measurement reference level
Output load capacitance for access time measurement
1.4
3 0
pF
1
N o t e :
1. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output l o a d c ircuit
Rev. 0. 6/ Aug. 01
4
HY57V653220 B
CAP ACIT ANCE ( T A = 2 5 °C , f = 1 M H z , V D D = 3 . 3 V )
Par ame t er
Pi n
S y mb o l
M in
Ma x
Uni t
Input capacitance
C L K
CI1
C I2
2.5
2.5
4
5
pF
pF
A 0 ~ A 1 0 , B A 0 , B A 1 , C K E , C S , R A S,
C A S , W E , D Q M 0 ~ 3
Data input / output capacitance
D Q 0 ~ D Q 3 1
C I/O
4
6.5
pF
OUT P UT L OAD CIRCUIT
Vtt=1. 4V
Vtt=1. 4V
R T = 5 0 0 W
R T = 5 0 W
Output
Z 0
= 5 0W
Output
30pF
30pF
DC Output Load Circuit
A C O u t p u t L o a d C i r c u i t
DC CHARACT E RIST ICS I (DC operating conditions unless otherwise noted)
Pa r a me t e r
S y mb o l
M i n.
Ma x
U n it
N o te
Input leakage current
Output leakage current
Output high voltage
Output low voltage
ILI
- 1
-1.5
2.4
-
1
1.5
-
u A
u A
V
1
2
IL O
V O H
V O L
IO H = - 2 m A
IO L = +2 m A
0.4
V
Not e :
1 .V IN = 0 to 3. 6V, All other pins are not under test = 0V
2 .D O U T is disabled, V OUT = 0 t o 3 . 6 V
Rev. 0. 6/ Aug. 01
5
HY57V653220 B
DC CHARACT E RISTICS II (DC operating conditions unless otherwise noted)
Spe e d
- 7I
Pa r a me t e r
S y mb o l
Test Condi t i on
Uni t
m A
m A
Not e
- 6I
- 10I
B u r s t L e n g t h = 1 , O n e b a n k a c t i v e
Operating Current
ID D 1
tRAS
³
t R A S ( m i n ) , t R P ³ tRP(min),
1 8 0
170
1 5 0
1
I O L = 0 m A
ID D 2 P
C K E
C K E
C K E
£
£
³
VIL(max), tCK
VIL(max), tCK
=
=
15ns
2
2
Precharge Standby Current
i n p o w e r d o w n m o d e
ID D 2 P S
¥
VIH(min), C S
³ V I H ( m i n ) , t C K = 1 5 n s
ID D 2 N
Input signals are changed one time during
2clks. All other pins V D D - 0 . 2 V o r £ 0. 2V
1 5
1 0
³
Precharge Standby Current
i n n o n p o w e r d o w n m o d e
m A
C K E
³ V I H ( m i n ) , t C K = ¥
ID D 2 N S
Input signals are stable.
ID D 3 P
3
3
C K E
C K E
C K E
£
£
³
VIL(max), tCK
VIL(max), tCK
=
=
15ns
Active Standby Current
i n p o w e r d o w n m o d e
m A
ID D 3 P S
¥
VIH(min), C S
³ V I H ( m i n ) , t C K = 1 5 n s
Input signals are changed one time during
2clks. All other pins V D D - 0 . 2 V o r £ 0. 2V
ID D 3 N
4 0
Active Standby Current
i n n o n p o w e r d o w n m o d e
³
m A
C K E
³ V I H ( m i n ) , t C K = ¥
ID D 3 N S
2 5
Input signals are stable
C L = 3
C L = 2
2 4 0
2 5 0
210
1 6 0
1 9 0
t C K
tRAS
All banks active
³
tCK(min),
Burst Mode Operating
Current
I D D 4
ID D 5
ID D 6
³
t R A S ( m i n ) , I O L = 0 m A
m A
1
A u t o R e f r e s h C u r r e n t
S e l f R e f r e s h C u r r e n t
t R R C
C K E
³
tRRC(min), All banks active
220
2
m A
m A
m A
2
3
4
£
0. 2V
1. 0
N o t e :
1.ID D 1 a n d I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh R A S c y c l e t i m e ) i s s h o w n a t A C C H A R A C T E R I S T I C S I I
3 . H Y 5 7 V 6 5 3 2 2 0 B T C - 6 I / 7 I / 1 0 I
4 . H Y 5 7 V 6 5 3 2 2 0 B L T C - 6 / 7 I / 1 0 I
Rev. 0. 6/ Aug. 01
6
HY57V653220 B
AC CHARACT E RISTICS I (AC operating conditions unless otherwise noted)
-6
- 7I
- 10I
Pa r a me t e r
S y mb o l
Uni t
Not e
M in
6
Ma x
M in
Ma x
Mi n
10
12
3. 5
3. 5
-
Ma x
C A S Lat enc y
=
=
3
2
tCK3
7
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
n s
S y s t e m c l o c k
cycle time
1000
1 0 0 0
1 0 0 0
C A S Lat enc y
tCK2
t C H W
tCLW
tAC3
tAC2
t O H
10
2.5
2.5
-
-
Clock high pulse width
Clock low pulse width
-
3
-
-
-
1
1
-
3
-
C A S Lat enc y
=
=
3
2
5. 5
-
5. 5
6
6
-
A c c e s s t i m e f r o m
clock
2
C A S Lat enc y
-
6
-
-
-
Data-out hold time
2
-
2
-
2
3
1
1
1
1
1
1
1
1
Data-Input setup time
Data-Input hold time
A d d r e s s s e t u p t i m e
A d d r e s s h o l d t i m e
t D S
1.5
1
-
1. 75
-
2. 5
1
-
t D H
-
1
-
-
t A S
1.5
1
-
1. 75
-
2. 5
1
-
t A H
-
1
-
-
C K E s e t u p t i m e
tCKS
tCKH
t C S
1.5
1
-
1. 75
-
2. 5
1
-
C K E h o l d t i m e
-
1
-
-
C o m m a n d s e t u p t i m e
C o m m a n d h o l d t i m e
CLK to data output in low Z-time
1.5
1
-
1. 75
-
2. 5
1
-
t C H
-
-
1
1
-
-
-
-
tOLZ
t O H Z 3
t O H Z 2
1
1
-
C A S Lat enc y
=
=
3
2
-
5. 5
6
5. 5
6
-
6
6
CLK to data output
in high Z-time
C A S Lat enc y
-
-
-
Not e :
1 .Assume tR / tF (input rise and fall time ) is 1ns
2 .Access times to be measured with input signals of 1v/ns edge rate, 0. 8v to 2. 0v
3. Data-out hold time to be measured under 30pF load condition, without Vt termination
Rev. 0. 6/ Aug. 01
7
HY57V653220 B
AC CHARACT E RIST ICS II (AC operating conditions unless otherwise noted)
-6
- 7I
- 10 I
Pa r a me t e r
S y mb o l
Uni t
Not e
M in
60
60
18
42
18
12
1
Ma x
M in
63
63
20
42
20
2
Ma x
Mi n
7 0
7 0
2 0
5 0
2 0
2 0
1
Ma x
Operation
t R C
-
-
-
n s
n s
R A S cycle time
A u t o R e f r e s h
t R R C
t R C D
tRAS
t R P
-
-
-
R A S to C A S d e l a y
R A S active time
-
-
-
n s
1 0 0 K
100K
1 0 0 K
n s
R A S p r e c h a r g e t i m e
-
-
-
-
-
n s
R A S to R A S bank active delay
C A S to C A S d e l a y
t R R D
t C C D
t W T L
tDPL
-
n s
-
1
-
-
C L K
C L K
C L K
nd
W r i t e c o m m a n d t o d a t a - i n d e l a y
D a t a - i n t o p r e c h a r g e c o m m a n d
Data-in to active command
D Q M t o d a t a - o u t H i - Z
0
-
0
-
0
-
2
-
2
-
2
-
tDAL
5
-
4
-
4
-
t D Q Z
t D Q M
t M R D
t P R O Z 3
t P R O Z 2
t P D E
t S R E
t R E F
2
-
2
-
2
-
C L K
C L K
C L K
C L K
C L K
C L K
C L K
m s
D Q M t o d a t a - i n m a s k
0
-
0
-
0
-
M R S t o n e w c o m m a n d
2
-
2
-
2
-
C A S Lat enc y = 3
3
-
3
-
3
-
Precharge to
data output Hi-Z
C A S Lat enc y = 2
2
-
2
-
-
2
-
P o w e r d o w n e x i t t i m e
Self refresh exit time
R e f r e s h T i m e
1
-
1
1
-
1
-
1
-
1
-
1
-
64
-
6 4
-
64
Not e :
1. A new command can be given tRRC after self refresh exit
Rev. 0. 6/ Aug. 01
8
HY57V653220 B
DEVICE OP E RAT ING OP T ION T ABL E
HY5 7 V6 5 3 2 2 0 B( L) TC- 6 I
C A S Lat ency
3 C L K s
3 C L K s
tR C D
t RAS
tR C
t RP
tA C
t OH
1 6 6 MHz ( 6 ns )
1 4 3 MHz ( 7 ns )
3 C L K s
3 C L K s
7 C L K s
6 C L K s
1 0 C L K s
9 C L K s
3 C L K s
3 C L K s
5 . 5 n s
5 . 5 n s
2 . 0 n s
2 . 0 n s
HY5 7 V6 5 3 2 2 0 B( L) TC- 7 I
C A S Lat ency
tR C D
t RAS
tR C
t RP
tA C
t OH
1 4 3 MHz ( 7 ns )
1 0 0 MHz ( 1 0 ns )
3 C L K s
2 C L K s
3 C L K s
2 C L K s
6 C L K s
5 C L K s
9 C L K s
7 C L K s
3 C L K s
2 C L K s
5 . 5 n s
6ns
2 . 0 n s
2 . 0 n s
HY5 7 V6 5 3 2 2 0 B( L) TC- 1 0 I
C A S Lat ency
tR C D
t RAS
tR C
t RP
tA C
t OH
1 0 0 MHz ( 1 0 ns )
8 3 MHz ( 1 2 ns )
3 C L K s
2 C L K s
2 C L K s
2 C L K s
5 C L K s
5 C L K s
7 C L K s
7 C L K s
2 C L K s
2 C L K s
6ns
6ns
2 . 0 n s
2 . 5 n s
Rev. 0. 6/ Aug. 01
9
HY57V653220 B
COMMAND T RUT H T ABL E
A1 0 /
A D D R
C o mma n d
CKEn- 1
C K E n
CS
R A S
C A S
W E
D Q M
BA
Not e
AP
M o d e R e g i s t e r S e t
H
H
H
H
X
L
H
L
L
X
H
L
L
X
H
H
L
X
H
H
X
O P c o d e
No Operation
X
X
X
X
X
X
X
Bank Active
L
R A
V
V
R e a d
L
H
L
L
L
H
H
L
L
L
H
L
C A
C A
X
R e a d w i t h A u t o p r e c h a r g e
Write
H
H
X
X
X
V
Write with Autoprecharge
Precharge All Banks
P r e c h a r g e s e l e c t e d B a n k
Burst Stop
H
H
L
X
V
X
X
L
L
H
H
L
L
H
H
H
H
H
X
L
X
V
X
X
X
X
X
D Q M
Auto Refresh
H
L
L
L
L
L
H
H
X
H
X
H
X
H
X
V
Entry
L
1
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
Self Refresh
Exit
L
H
L
H
L
X
X
X
H
L
Entry
P r e c h a r g e
p o w e r d o w n
H
L
Exit
H
H
L
Entry
C l o c k
H
L
L
X
X
S u s p e n d
Exit
H
X
Not e :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2 . X = D o n ¢t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s ,
O p c o d e = O p e r a n d C o d e , N O P = N o O p e r a t i o n
Rev. 0. 6/ Aug. 01
1 0
HY57V653220 B
P ACKAGE INF ORMAT ION
4 0 0 mil 86 pi n Thi n Sm al l O u tlin e Pa c k a g e
Unit : mm(inch)
11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720)
10.262(0.4040)
10.058(0.3960)
0.150(0.0059)
1.194(0.0470)
0.991(0.0390)
0.050(0.0020)
5deg
0deg
0.210(0.0083)
0.120(0.0047)
0.597(0.0235)
0.406(0.0160)
0.21(0.008)
0.18(0.007)
0.50(0.0197)
Rev. 0. 6/ Aug. 01
1 1
相关型号：
HY57V653220BTC7DR
Synchronous DRAM, 2MX32, 5.5ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86
HYNIX
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