HYS64D32000GU-7-A [ETC]
?256MB (32Mx64) PC2100 1-bank? ; ？ 256MB （ 32Mx64 ） PC2100 1 ，行吗？\n
| 型号： | HYS64D32000GU-7-A |
| 厂家： | 
ETC |
| 描述： | ?256MB (32Mx64) PC2100 1-bank?
|
| 文件： | 总24页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
2.5 V 184-pin Unbuffered DDR-I SDRAM Modules
128MByte, 256 MByte & 512 MByte Modules
PC1600, PC2100, PC2700
Preliminary Datasheet revision 0.94
•
184-pin Unbuffered 8-Byte Dual-In-Line
DDR-I SDRAM non-parity and ECC-Modules
for PC and Server main memory applications
•
•
•
•
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
•
•
One bank 16M x 64, 32M × 64, 32M x 72 and
two bank 64M x 64, 64M × 72 organization
Jedec standard MO-206 form factor:
133.35 mm × 31.75 mm × 4.00 mm max.
JEDEC standard Double Data Rate
Synchronous DRAMs (DDR-I SDRAM)
Single + 2.5 V (± 0.2 V) power supply
•
•
Jedec standard reference layout
Gold plated contacts
•
•
Built with 256 Mbit DDR-I SDRAMs in 66-
Lead TSOPII package
Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
•
Performance:
-6
-7/-7F
-8
Unit
Component Speed Grade
Module Speed Grade
DDR333B DDR266A/F DDR200
PC2700
PC2100
143
PC1600
125
fCK
fCK
Clock Frequency (max.) @ CL = 2.5 166
Clock Frequency (max.) @ CL = 2 133
MHz
MHz
133
100
The HYS64/72D32000GU and HYS64/72D64020GU are industry standard 184-pin 8-byte Dual in-
line Memory Modules (DIMMs) organized as 32M × 64 and 64M × 64 for non-parity and 32M x 72
and 64M x 72 for ECC main memory applications. The memory array is designed with 256Mbit
Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC
board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin
I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes
are available to the customer.
INFINEON Technologies
1
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Ordering Information
Type
Compliance Code
Description
SDRAM
Technology
PC2700 (CL=2):
HYS64D16301GU-6-B
HYS64D32300GU-6-B
HYS72D32300GU-6-B
HYS64D64320GU-6-B
HYS72D64320GU-6-B
PC2100 (CL=2):
PC2700-20330-C0
PC2700-20330-A0
PC2700-20330-A0
PC2700-20330-B0
PC2700-20330-B0
one bank 128 MB DIMM
256 MBit
256 MBit
256 Mbit
256 MBit
256 MBit
one bank 256 MB DIMM
one bank 256 MB ECC-DIMM
two banks 512 MB DIMM
two banks 512 MB ECC-DIMM
HYS64D16301GU-7-B
HYS64D32000GU-7-B
HYS72D32000GU-7F-B
HYS72D32000GU-7-B
HYS64D64020GU-7-B
HYS72D64020GU-7F-B
HYS72D64020GU-7-B
PC1600 (CL=2):
PC2100-20330-C0
PC2100-20330-A1
PC2100-20220-A1
PC2100-20330-A1
PC2100-20330-B1
PC2100-20220-B1
PC2100-20330-B1
one bank 128 MB DIMM
256 MBit
256 MBit
256 Mbit
256 Mbit
256 MBit
256 MBit
256 MBit
one bank 256 MB DIMM
one bank 256 MB ECC-DIMM
one bank 256 MB ECC-DIMM
two banks 512 MB DIMM
two banks 512 MB ECC-DIMM
two banks 512 MB ECC-DIMM
HYS64D16301GU-8-B
HYS64D32000GU-8-B
HYS72D32000GU-8-B
HYS64D64020GU-8-B
HYS72D64020GU-8-B
PC2100-20330-C0
PC1600-20220-A1
PC1600-20220-A1
PC1600-20220-B1
PC1600-20220-B1
one bank 128 MB DIMM
256 MBit
256 MBit
256 Mbit
256 MBit
256 MBit
one bank 256 MB DIMM
one bank 256 MB ECC-DIMM
two banks 512 MB DIMM
two banks 512 MB ECC-DIMM
Note: All part numbers end with a place code, designating the silicon-die revision. Reference information
available on request. Example: HYS 72D32000GU-8-B, indicating Rev.B dies are used for the SDRAM
components.
The Compliance Code is printed on the module labels and describes the speed sort fe. “PC2100”, the
latencies (f.e. “20330” means CAS latency = 2, trcd latency = 3 and trp latency =3 ) and the Raw Card
used for this module.
INFINEON Technologies
2
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Pin Definitions and Functions
A0 - A12
Address Inputs
S0, S1
Chip Selects
BA0, BA1
DQ0 - DQ63
CB0 - CB7
RAS
Bank Selects
VDD
Power (+ 2.5 V)
Data Input/Output
VSS
Ground
Check Bits (x72 organization only)
Row Address Strobe
Column Address Strobe
Read/Write Input
VDDQ
VDDID
VREF
I/O Driver power supply
VDD Indentification flag
I/O reference supply
Serial EEPROM power supply
Serial bus clock
CAS
WE
VDDSPD
SCL
CKE0 - CKE1
DQS0 - DQS8
CLK0 - CLK2,
CLK0 - CLK2
Clock Enable
SDRAM low data strobes
SDRAM clock (positive lines)
SDRAM clock (negative lines)
SDA
SA0 - SA2
NC
Serial bus data line
slave address select
no connect
DM0 - DM8
DQS9 - DQS17
SDRAM low data mask/
high data strobes
note: S1 and CKE1 are used on two bank modules only
Address Format
Density Organization
Memory SDRAMs
Banks
# of
# of row/bank/
Refresh Period Interval
SDRAMs columns bits
256 MB 32M x 64
256 MB 32M x 72
512 MB 64M × 64
512 MB 64M × 72
1
1
2
2
32M x 8
32M x 8
32M x 8
32M x 8
8
13/2/10
13/2/10
13/2/10
13/2/10
8k
8k
8k
8k
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
9
16
18
INFINEON Technologies
3
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Pin Configuration
Frontside
Frontside
Backside
Backside
PIN#
1
Symbol
VREF
DQ0
PIN#
48
Symbol
A0
PIN#
93
Symbol
VSS
PIN#
140
141
142
143
144
Symbol
NC / DM8/DQS17
A10
2
49
NC / CB2
VSS
94
DQ4
3
VSS
50
95
DQ5
NC / CB6
VDDQ
NC / CB7
KEY
4
DQ1
51
NC / CB3
BA1
96
VDDQ
DM0/DQS9
DQ6
5
DQS0
DQ2
52
97
6
KEY
98
7
VDD
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
99
DQ7
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
VSS
8
DQ3
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
VSS
DQ36
9
NC
NC
DQ37
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
NC
NC
VDD
VSS
NC
DM4/DQS13
DQ38
DQ8
VDDQ
DQ12
DQ13
DM1/DQS10
VDD
DQ9
BA0
DQ39
DQS1
VDDQ
CLK1
CLK1
VSS
DQ35
DQ40
VDDQ
WE
VSS
DQ44
RAS
DQ14
DQ15
CKE1
VDDQ
NC (BA2)
DQ20
NC / A12
VSS
DQ45
DQ41
CAS
VDDQ
S0
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
VSS
S1
DQS5
DQ42
DQ43
VDD
DM5/DQS14
VSS
DQ46
DQ47
NC
DQ21
A11
NC
DQ48
DQ49
VSS
VDDQ
DQ52
A9
DM2/DQS11
VDD
DQ18
A7
DQ53
CLK2
CLK2
VDDQ
DQS6
DQ50
DQ51
VSS
DQ22
A8
NC (A13)
VDD
VDDQ
DQ19
A5
DQ23
VSS
DM6/DQS15
DQ54
DQ24
VSS
A6
DQ55
DQ28
DQ29
VDDQ
DM3/DQS12
A3
VDDQ
NC
DQ25
DQS3
A4
VDDID
DQ56
DQ57
VDD
DQ60
DQ61
VDD
VSS
DQ26
DQ27
A2
DQ30
VSS
DM7/DQS16
DQ62
DQS7
DQ58
DQ59
VSS
DQ31
NC / CB4
NC / CB5
VDDQ
CK0
DQ63
VSS
VDDQ
SA0
A1
NC / CB0
NC / CB1
VDD
NC
SA1
SDA
SA2
SCL
CK0
VDDSPD
NC / DQS8
VSS
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“no-connects”) on x64 organised non-ECC
modules.
INFINEON Technologies
4
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
CS0
CS
CS
LDQS
DQS4
DM4
LDQS
LDM
DQS0
DM0
LDM
I/O 0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DM5
UDQS
UDM
DQS1
DM1
UDQS
UDM
I/O 8
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 8
DQ9
I/O 9
I/O 9
D0
D2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS2
DM2
DQS6
DM6
LDQS
LDM
I/O 0
I/O 1
CS
CS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DM3
UDQS
UDM
DQS7
DM7
UDQS
UDM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 8
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 8
I/O 9
D1
I/O 9
D3
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
Unless otherwise noted, resistor values are 22 Ohm with +/- 5% tolerance
Serial Presence Detect (SPD)
SDRAMS D0-D3
SDRAMS D0-D3
SDRAMS D0-D3
SDRAMS D0-D3
SDRAMS D0-D3
BA0-BA1
A0-AN
RAS
CAS
WE
SCL
SA0
SA1
A0
A1
A2
SDA
SA2
WP
SDRAMS D0-D3
N.C.
CKE0
CKE1
CK0
2 loads
2 loads
CK 0
CK1
SPD
V
V
SPD
DD
CK 1
SDRAMS D0-D3
REF
Note: DQ wiring may differ from that described
in this drawing; however DQ/DM/DQS
relationships are maintained as shown.
SDRAMS D0-D3
V
V
DD
SS
V
and V
Q
DD
DD
SDRAMS D0-D3, SPD
V
ID strap connections:
DD
V
ID
DD
Strap out (open): V = V
DD
DD
Q
Block Diagram: One Bank 16M x 64 DDR-I SDRAM DIMM Module
HYS64D32001GU using x16 organized SDRAMs
INFINEON Technologies
5
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
S0
DQS0
DQS4
DM4/DQS13
DM0/DQS9
CS
D4
DM
I/O 7
DQS
DQS
DM
I/O 7
CS
D0
DQ32
DQ33
DQ34
DQ35
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ36
DQ37
DQ38
DQ39
DQS5
DQS1
DM5/DQS14
DM1/DQS10
CS DQS
D5
DM
DQS
CS
D1
DM
DQ40
DQ41
DQ42
DQ43
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ8
DQ9
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ44
DQ45
DQ46
DQ47
I/O 3
I/O 2
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
CS
D6
CS DQS
D2
DM
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS3
DM3/DQS12
DQS7
DM7/DQS16
DQS
DM
I/O 7
CS
D7
DM
CS DQS
D3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
* Clock Wiring
Clock
Input
SDRAMs
Serial PD
2 SDRAMs
3 SDRAMs
3 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
SDA
SCL
A0
SA0
A1
A2
* Wire per Clock Loading
Table/Wiring Diagrams
SA1
SA2
BA0 - BA1
BA0, BA1: SDRAMs D0
- D7
Notes:
A0 - A11,A12: SDRAMs D0 - D7
A0 -A11, A12
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
RAS
RAS: SDRAMs D0 - D7
V
V
DD, DDQ
D0 - D7
D0 - D7
D0 - D7
CAS
CKE0
WE
CAS: SDRAMs D0 - D7
CKE: SDRAMs D0 - D7
VREF
V
V
SS
: SDRAMs D0 - D7
WE
DDID
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
Block Diagram: One Bank 32M x 64 DDR-I SDRAM DIMM Module
HYS64D32000GU using x8 organized SDRAMs
INFINEON Technologies
6
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
S1
S0
DQS4
DM4/DQS13
DQS0
DM0/DQS9
CS
D4
CS
DM
I/O 7
DQS
DM
I/O 0
DQS
DQS
CS
D0
DM
CS DQS
D8
DM
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ0
DQ1
DQ2
DQ3
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D12
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ4
DQ5
DQ6
DQ7
DQS5
DQS1
DM5/DQS14
DM1/DQS10
CS
DM
DM
CS
D5
DQS
DQS
DQS
CS
D1
CS DQS
D9
DM
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ40
DQ41
DQ42
DQ43
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
D13
DQ44
DQ45
DQ46
DQ47
I/O 4
I/O 5
I/O 3
I/O 2
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D6
DQS
CS DQS
D14
CS DQS
D2
DM
I/O 0
CS DQS
D10
DM
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ16
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
DQS
DQS
CS
CS
D7
DM
CS DQS
D3
DM
CS
DQS
DQ56
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ24
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D15
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D11
* Clock Wiring
Clock
Input
SDRAMs
BA0, BA1: SDRAMs D0, D15
A0 - A12: SDRAMs D0 - D15
BA0, BA1
A0 - A12
Serial PD
A1
4 SDRAMs
6 SDRAMs
6 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
SDA
V
V
DD, DDQ
D0 - D15
D0 - D15
SCL
A0
SA0
A2
VREF
* Wire per Clock Loading
Table/Wiring Diagrams
SA1
SA2
V
SS
D0 - D15
V
DDID
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
CKE1
RAS
CKE: SDRAMs D8 - D15
RAS: SDRAMs D0 - D15
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
CAS
CKE0
WE
CAS: SDRAMs D0 - D15
CKE: SDRAMs D0 - D7
WE: SDRAMs D0 - D15
Block Diagram: Two Bank 64M x 64 DDR-I SDRAM DIMM Modules
HYS64D64020GU using x8 Organized SDRAMs
INFINEON Technologies
7
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
S0
DQS0
DQS4
DM4/DQS13
DM0/DQS9
DM
I/O 7
DQS
DQS
CS
D0
CS
D4
DM
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS5
DQS1
DM5/DQS14
DM1/DQS10
CS
D5
DM
DQS
DQS
CS
D1
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
DQ14
DQ15
I/O 3
I/O 2
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
I/O 7
CS DQS
D6
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ16
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
DQS7
DM7/DQS16
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
CS
D3
CS
D7
DQS
DM
DQ56
DQ57
DQ58
DQ59
DQ24
I/O 7
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ60
DQ61
DQ62
DQ63
DQS8
DM8/DQS17
Serial PD
A1
DM
DQS
CS
D8
CB0
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CB1
CB2
CB3
CB4
CB5
CB6
CB7
SDA
SCL
A0
SA0
A2
SA2
SA1
BA0, BA1: SDRAMs D0
- D8
BA0, BA1
* Clock Wiring
A0 - A11,A12
A0 - A11, A12: SDRAMs D0 - D8
Clock
Input
SDRAMs
RAS
RAS: SDRAMs D0 - D8
V
V
DD, DDQ
D0 - D8
D0 - D8
D0 - D8
3 SDRAMs
3 SDRAMs
3 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
CAS
CAS: SDRAMs D0 - D8
CKE: SDRAMs D0 - D8
VREF
CKE0
V
SS
WE
WE: SDRAMs D0 - D8
* Wire per Clock Loading
Table/Wiring Diagrams
V
DDID
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
Block Diagram: One Bank 32M x 72 DDR-I SDRAM DIMM Module
HYS72D32000GU using x8 organized SDRAMs
INFINEON Technologies
8
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
S1
S0
DQS4
DM4/DQS13
DQS0
DM0/DQS9
DM
I/O 0
DM
I/O 7
CS DQS
D4
CS DQS
D13
DQS
CS
D0
CS
D9
DM
DQS
DM
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ0
DQ1
DQ2
DQ3
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ4
DQ5
DQ6
DQ7
DQS5
DM5/DQS14
DQS1
DM1/DQS10
CS
DM
CS
DM
DQS
DQS
CS
DQS
DQS
DM
DM
CS
D1
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ40
DQ41
DQ42
DQ43
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
DQ8
DQ9
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
D5
D14
D10
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ44
DQ45
DQ46
DQ47
I/O 4
I/O 5
I/O 3
I/O 2
DQS6
DM6/DQS15
DQS2
DM2/DQS11
CS
D6
CS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQS
DQS
DQS
DQS
DM
I/O 0
DQS
DQS
DQS
DM
I/O 7
CS
D2
CS
DQ48
DQ49
DQ50
DQ51
DQ16
D15
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D11
DQ52
DQ53
DQ54
DQ55
DQS7
DQS3
DM3/DQS12
DM7/DQS16
CS
D7
DM
I/O 0
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
DM
CS
D3
CS
DQ56
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ24
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D16
DQ25
DQ26
DQ27
D12
DQ28
DQ29
DQ30
DQ31
DQS8
DM8/DQS17
CS
DM
CS
D8
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D17
* Clock Wiring
Clock
Input
SDRAMs
BA0, BA1
A0 - A12
BA0, BA1: SDRAMs D0 - D17
A0 - A12: SDRAMs D0 - D17
Serial PD
A1
6 SDRAMs
6 SDRAMs
6 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
SDA
SCL
A0
SA0
A2
V
V
DD,
DDQ
D0 - D17
D0 - D17
* Wire per Clock Loading
Table/Wiring Diagrams
VREF
SA1
SA2
V
SS
D0 - D17
Notes:
V
DDID
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
CKE1
RAS
CKE: SDRAMs D9 - D17
RAS: SDRAMs D0 - D17
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
CAS
CKE0
WE
CAS: SDRAMs D0 - D17
CKE: SDRAMs D0 - D8
WE: SDRAMs D0 - D17
Block Diagram: Two Bank 64M x 72 DDR-I SDRAM DIMM Modules
HYS72D64020GU using x8 Organized SDRAMs
INFINEON Technologies
9
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Clock Net Wiring
4 DRAM Loads
6 DRAM Loads
DRAM 1
DR AM 1
DRAM2
DRAM3
DRAM2
Cap.
R = 120
CK
R =
120
DIMM
DIMM
Connector
Connector
DR AM4
DR AM5
Cap.
CK
DRAM5
DR AM6
DRAM6
DRAM 1
2 DRAM Loads
3 DRAM Loads
DRAM 1
Cap.
Cap.
Cap.
R =120
R =120
DIMM
Connector
DRAM3
DIMM
Connector
Cap.
Cap.
DR AM5
DR AM5
Cap.
Cap.
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
max.
3.6
3.6
+150
1
Input / Output voltage relative to VSS
Power supply voltage on VDD/VDDQ to VSS
Storage temperature range
VIN, VOUT – 0.5
VDD, VDDQ – 0.5
V
V
TSTG
PD
-55
–
oC
W
mA
Power dissipation (per SDRAM component)
Data out current (short circuit)
IOS
–
50
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
INFINEON Technologies
10
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Supply Voltage Levels
Parameter
Symbol
Limit Values
nom.
Unit
Notes
min.
max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
Termination Voltage
VDD
2.3
2.5
2.7
V
V
V
V
V
–
1)
VDDQ
VREF
VTT
2.3
2.5
2.7
2)
3)
0.49 x VDDQ
VREF – 0.04
2.3
0.5 x VDDQ
VREF
0.51 x VDDQ
VREF + 0.04
3.6
EEPROM supply voltage
VDDSPD
2.5
1)
Under all conditions, VDDQ must be less than or equal to VDD
.
2)
Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations
in VDDQ
VTT of the transmitting device must track VREF of the receiving device.
.
3)
DC Operating Conditions (SSTL_2 Inputs)
(VDDQ = 2.5 V, TA = 70 °C, Voltage Referenced to VSS
)
Parameter
Symbol
Limit Values
max.
Unit
Notes
min.
1)
DC Input Logic High
DC Input Logic Low
Input Leakage Current
Output Leakage Current
VIH (DC)
VIL (DC)
IIL
VREF + 0.15
– 0.30
– 5
VDDQ + 0.3
V
VREF – 0.15
V
–
2)
5
5
µA
µA
2)
IOL
– 5
1)
The relationship between the VDDQ of the driving device and the VREF of the receiving device is what determines
noise margins. However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving device that is
referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2
outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must tolerate input
overdrive to 3.0 V (High corner VDDQ + 300 mV).
2)
For any pin under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V. Values are shown per DDR-SDRAM component.
INFINEON Technologies
11
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC1600, -8)
128MB 256MB 256MB 512MB 512MB
x64
1bank
-8
x64
1bank
-8
x72
1bank
-8
x64
2bank
-8
x72
2bank Unit
-8
Notes
4
Symbol
Parameter/Condition
MAX
MAX
MAX
MAX
MAX
Operating Current
: one bank; active / precharge; tRC = tRC MIN;
tCK = tCK MIN; DQ, DM, and DQS inputs changing once per clock
cycle; address and control inputs changing once every two clock
cycles
IDD0
380
720
810
1080
1215
mA
1
Operating Current: one bank; active/read/precharge; Burst = 4;
IDD1
420
28
800
56
900
63
1160
112
1305
126
mA
mA
1, 3
2
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current: all banks idle; power-
IDD2P
down mode; CKE <= VIL MAX; tCK = tCK MIN
Precharge Floating Standby Current
: /CS >= VIH MIN, all banks
idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control
inputs changing once per clock cycle, VIN = VREF for DQ, DQS and
DM.
140
280
315
560
630
IDD2F
mA
2
Precharge Quiet Standby Current
: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and
DM.
88
64
176
128
198
144
352
256
396
288
IDD2Q
IDD3P
mA
mA
2
2
Active Power-Down Standby Current
: one bank active; power-
down mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ,
DQS and DM.
Active Standby Current
: one bank active; active / precharge;CS >=
VIH MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ,
DM, and DQS inputs changing twice per clock cycle; address and
control inputs changing once per clock cycle
IDD3N
IDD4R
IDD4W
200
440
480
360
760
840
405
855
945
720
1120
1200
810
1260
1350
mA
mA
mA
2
Operating Current
: one bank active; Burst = 2; reads; continuous
burst; address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge; CL = 2 for
DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT =
0mA
1, 3
Operating Current
: one bank active; Burst = 2; writes; continuous
burst; address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge; CL = 2 for
DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN
1
1
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
680
10
1360
20
1530
22,5
1720
40
1935
45
IDD5
IDD6
mA
mA
Self-Refresh Current
: CKE <= 0.2V; external clock on; tCK = tCK
MIN
Operating Current
: four bank; four bank interleaving with BL=4;
IDD7
880
1680
1890
2040
2295
mA
1, 3
Refer to the following page for detailed test conditions.
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component]
for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
2 * n * IDDx[component]
for single bank modules (n: number of components per module bank)
for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending
on load conditions
4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
12
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC2100, -7)
128MB 256MB 256MB 512MB 512MB
x64
1bank
-7
x64
1bank
-7
x72
1bank
-7
x64
2bank
-7
x72
2bank
-7
Notes
4
Symbol
Parameter/Condition
Unit
mA
MAX
MAX
MAX
MAX
MAX
Operating Current
: one bank; active / precharge; tRC = tRC MIN;
tCK = tCK MIN; DQ, DM, and DQS inputs changing once per clock
cycle; address and control inputs changing once every two clock
cycles
IDD0
420
800
900
1240
1395
1
Operating Current
: one bank; active/read/precharge; Burst = 4;
IDD1
460
32
880
64
990
72
1320
128
1485
144
mA
mA
1, 3
2
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current
: all banks idle; power-
IDD2P
down mode; CKE <= VIL MAX; tCK = tCK MIN
Precharge Floating Standby Current: /CS >= VIH MIN, all banks
idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control
inputs changing once per clock cycle, VIN = VREF for DQ, DQS and
DM.
160
320
360
640
720
IDD2F
mA
2
Precharge Quiet Standby Current
: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and
DM.
100
72
200
144
225
162
400
288
450
324
IDD2Q
IDD3P
mA
mA
2
2
Active Power-Down Standby Current: one bank active; power-
down mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ,
DQS and DM.
Active Standby Current
: one bank active; active / precharge;CS >=
VIH MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ,
DM, and DQS inputs changing twice per clock cycle; address and
control inputs changing once per clock cycle
IDD3N
IDD4R
IDD4W
240
520
560
440
920
495
1035
1125
880
1360
1440
990
1530
1620
mA
mA
mA
2
Operating Current: one bank active; Burst = 2; reads; continuous
burst; address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge; CL = 2 for
DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT =
0mA
1, 3
Operating Current: one bank active; Burst = 2; writes; continuous
burst; address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge; CL = 2 for
DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN
1000
1
1
Auto-Refresh Current
: tRC = tRFC MIN, distributed refresh
720
10
1440
20
1620
22,5
1880
40
2115
45
IDD5
IDD6
mA
mA
Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK
MIN
Operating Current: four bank; four bank interleaving with BL=4;
IDD7
940
1800
2025
2240
2520
mA
1, 3
Refer to the following page for detailed test conditions.
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component]
for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
2 * n * IDDx[component]
for single bank modules (n: number of components per module bank)
for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending
on load conditions
4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
13
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC2100, -7F)
256MB 512MB
x72
1bank
-7F
x72
2bank
-7F
Notes
Symbol
Parameter/Condition
Unit
mA
4
1
MAX
MAX
Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = tCK MIN;
IDD0 DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs
changing once every two clock cycles
990
1485
Operating Current: one bank; active/read/precharge; Burst = 4;
IDD1
1080
72
1575
144
mA
mA
1, 3
2
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE
IDD2P
<= VIL MAX; tCK = tCK MIN
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH
MIN; tCK = tCK MIN ,address and other control inputs changing once per clock
cycle, VIN = VREF for DQ, DQS and DM.
360
720
IDD2F
mA
2
: /CS >= VIH MIN, all banks idle; CKE >= VIH
Precharge Quiet Standby Current
MIN; tCK = tCK MIN ,address and other control inputs stable at >= VIH MIN or <=
VIL MAX; VIN = VREF for DQ, DQS and DM.
225
162
450
324
IDD2Q
IDD3P
mA
mA
2
2
Active Power-Down Standby Current: one bank active; power-down mode; CKE
<= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM.
Active Standby Current: one bank active; active / precharge;CS >= VIH MIN; CKE
IDD3N >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS inputs changing
twice per clock cycle; address and control inputs changing once per clock cycle
495
1035
1125
990
1530
1620
mA
mA
mA
2
: one bank active; Burst = 2; reads; continuous burst; address
Operating Current
and control inputs changing once per clock cycle; 50% of data outputs changing on
every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK
MIN; IOUT = 0mA
IDD4R
IDD4W
1, 3
: one bank active; Burst = 2; writes; continuous burst; address
Operating Current
and control inputs changing once per clock cycle; 50% of data outputs changing on
every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK
MIN
1
1
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
1620
22,5
2115
45
IDD5
IDD6
mA
mA
Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN
: four bank; four bank interleaving with BL=4;
Operating Current
IDD7
2025
2520
mA
1, 3
Refer to the following page for detailed test conditions.
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component]
for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
2 * n * IDDx[component]
for single bank modules (n: number of components per module bank)
for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending
on load conditions
4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
14
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC2700, -6)
128MB 256MB 256MB 512MB 512MB
x64
1bank
-6
x64
1bank
-6
x72
1bank
-6
x64
2bank
-6
x72
2bank
-6
Notes
4
Symbol
Parameter/Condition
Unit
mA
MAX
MAX
MAX
MAX
MAX
Operating Current
: one bank; active / precharge; tRC = tRC MIN;
tCK = tCK MIN; DQ, DM, and DQS inputs changing once per clock
cycle; address and control inputs changing once every two clock
cycles
IDD0
460
880
990
1400
1575
1
Operating Current
: one bank; active/read/precharge; BL 4;
Refer to the following page for detailed test conditions.
IDD1
500
36
960
72
1080
81
1480
144
1665
162
mA
mA
1, 3
2
Precharge Power-Down Standby Current
: all banks idle; power-
IDD2P
down mode; CKE <= VIL MAX; tCK = tCK MIN
Precharge Floating Standby Current: /CS >= VIH MIN, all banks
idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control
inputs changing once per clock cycle, VIN = VREF for DQ, DQS
and DM.
220
440
495
880
990
IDD2F
mA
2
Precharge Quiet Standby Current: /CS >= VIH MIN, all banks
idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control
inputs stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ,
DQS and DM.
112
84
224
168
252
189
448
336
504
378
IDD2Q
IDD3P
mA
mA
2
2
Active Power-Down Standby Current
: one bank active; power-
down mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for
DQ, DQS and DM.
Active Standby Current
: one bank active; active / precharge;CS
>= VIH MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN;
DQ, DM, and DQS inputs changing twice per clock cycle; address
and control inputs changing once per clock cycle
IDD3N
IDD4R
IDD4W
280
640
660
520
1120
1160
585
1260
1305
1040
1640
1680
1170
1845
1890
mA
mA
mA
2
Operating Current
: one bank active; Burst = 2; reads; continuous
burst; address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge; CL = 2 for
DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT
= 0mA
1, 3
Operating Current
: one bank active; Burst = 2; writes; continuous
burst; address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge; CL = 2 for
DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN
1
1
Auto-Refresh Current
: tRC = tRFC MIN, distributed refresh
760
10
1520
20
1710
22,5
2040
40
2295
45
IDD5
IDD6
mA
mA
Self-Refresh Current
: CKE <= 0.2V; external clock on; tCK = tCK
MIN
Operating Current
: four bank; four bank interleaving with BL=4;
IDD7
1140
2160
2430
2680
3015
mA
1, 3
Refer to the following page for detailed test conditions.
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component]
for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
2 * n * IDDx[component]
for single bank modules (n: number of components per module bank)
for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending
on load conditions
4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
15
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V)
DDR333
-6
DDR266F
-7F
DDR266A
-7
DDR200
-8
Symbol
tAC
Parameter
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
DQ output access time from CK/CK
− 0.7 + 0.7 − 0.75 + 0.75 − 0.75 + 0.75 − 0.8 + 0.8
− 0.7 + 0.7 − 0.75 + 0.75 − 0.75 + 0.75 − 0.8 + 0.8
ns
ns
tCK
tCK
ns
ns
ns
ns
ns
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
tDQSCK DQS output access time from CK/CK
tCH
tCL
tHP
tCK
tCK
tDH
tDS
CK high-level width
CK low-level width
Clock Half Period
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
min (tCL, tCH)
min (tCL, tCH)
min (tCL, tCH)
min (tCL, tCH)
CL = 2.5
CL = 2.0
6
12
12
7
12
12
7
12
12
8
12
12
Clock cycle time
7.5
7.5
0.5
0.5
7.5
0.5
0.5
10
0.6
0.6
DQ and DM input hold time
DQ and DM input setup time
0.45
0.45
–
–
Control and Addr. input pulse width (each
input)
tIPW
2.2
2.2
2.2
2.5
2
ns
ns
1, 10
1-4,
11
tDIPW DQ and DM input pulse width (each input)
1.75
1.75
1.75
tHZ
tLZ
Data-out high-impedence time from CK/CK
Data-out low-impedence time from CK/CK
− 0.7 + 0.7 − 0.75 + 0.75 − 0.75 + 0.75 − 0.8 + 0.8
− 0.7 + 0.7 − 0.75 + 0.75 − 0.75 + 0.75 − 0.8 + 0.8
ns
ns
tCK
1-4, 5
1-4, 5
1-4
tDQSS Write command to 1st DQS latching transition 0.75
1.25
0.75
1.25
+ 0.5
0.75
1.25
+ 0.5
+ 0.75
0.75
1.25
+ 0.6
+ 1.0
DQS-DQ skew
tDQSQ
+ 0.4
ns
ns
1-4
1-4
(for DQS & associated DQ signals)
tQHS
tQH
Data hold skew factor
+ 0.55
tHP
tQHS
–
+ 0.75
-
tHP
-
tHP
-
tHP-
Data Output hold time from DQS
ns
1-4
tQHS
tQHS
tQHS
tDQSL,H DQS input low (high) pulse width (write cycle) 0.35
DQS falling edge to CK setup time (write
0.35
0.35
0.35
tCK
tCK
1-4
1-4
tDSS
0.2
0.2
0.2
0.2
0.2
0.2
0.2
cycle)
DQS falling edge hold time from CK (write
cycle)
tDSH
tMRD
0.2
tCK
1-4
Mode register set command cycle time
12
0
14
0
14
0
16
0
ns
ns
tCK
tCK
ns
ns
ns
ns
tCK
tCK
1-4
1-4, 7
1-4, 6
1-4
tWPRES Write preamble setup time
tWPST Write postamble
0.40
0.25
0.75
0.60
0.40
0.25
0.9
1.0
0.9
1.0
0.9
0.40
0.60
0.40
0.25
0.9
1.0
0.9
1.0
0.9
0.40
0.60
0.40
0.25
1.1
1.1
1.1
1.1
0.9
0.40
0.60
tWPRE Write preamble
fast slew rate
slow slew rate
fast slew rate
slow slew rate
Address and control
tIS
input setup time
2-4,
10,11
0.75
Address and control
input hold time
tIH
tRPRE Read preamble
tRPST Read postamble
0.9
1.1
1.1
1.1
1-4
1-4
0.40
0.60
0.60
0.60
120,00
0
120,00
0
120,00
0
tRAS
tRC
Active to Precharge command
Active to Active/Auto-refresh command period
42
60
45
60
45
65
50
70
ns
ns
1-4
1-4
INFINEON Technologies
16
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V)
DDR333
-6
DDR266F
-7F
DDR266A
-7
DDR200
-8
Symbol
Parameter
Unit Notes
Min
72
Max
Min
75
Max
Min
75
Max
Min
Max
Auto-refresh to Active/Auto-refresh
command period
tRFC
80
ns
1-4
tRCD
tRP
tRRD
tWR
Active to Read or Write delay
Precharge command period
Active bank A to Active bank B command
Write recovery time
18
18
12
15
15
15
15
15
20
20
15
15
20
20
15
15
ns
ns
ns
ns
1-4
1-4
1-4
1-4
Auto precharge write recovery
+ precharge time
tDAL
(twr/tck) + (trp/tck)
tCK
1-4,9
tWTR
Internal write to read command delay
1
1
1
75
1
tCK
ns
tCK
µs
1-4
1-4
tXSNR Exit self-refresh to non-read command
tXSRD Exit self-refresh to read command
75
75
80
200
200
200
200
1-4
tREFI
Average Periodic Refresh Interval
7.8
7.8
7.8
7.8
1-4, 8
1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level
for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT
.
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH,
LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS
.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle
time.
10. These parameters guarantee device timing, but they are not necessarily tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ns, mea-
sured between VOH(ac) and VOL(ac)
INFINEON Technologies
17
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
SPD Codes for PC1600 Modules “-8”
128MB
x64
256MB
x64
256MB
x72
512MB
x64
512MB
x72
Byte#
Description
1bank
-8
1bank
-8
1bank
-8
2bank
-8
2bank
-8
HEX
HEX
HEX
HEX
HEX
0
1
Number of SPD Bytes
128
256
80
08
07
0D
09
01
40
00
04
80
80
00
82
10
00
80
08
07
0D
0A
01
40
00
04
80
80
00
82
08
00
80
08
07
0D
0A
01
48
00
04
80
80
02
82
08
08
80
08
07
0D
0A
02
40
00
04
80
80
00
82
08
00
80
08
07
0D
0A
02
48
00
04
80
80
02
82
08
08
Total Bytes in Serial PD
Memory Type
2
DDR-SDRAM
13
3
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
4
9 / 10
5
1 / 2
6
Module Data Width
x64 / x72
0
7
Module Data Width (cont’d)
Module Interface Levels
8
SSTL_2.5
8 ns
9
SDRAM Cycle Time at CL = 2.5
Access Time from Clock at CL = 2.5
DIMM Config
10
11
12
13
14
0.8 ns
non-ECC / ECC
Self-Refresh, 7.8 ms
x16 / x8
na / x8
Refresh Rate/Type
SDRAM Width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-to-Back
Random Column Address
Burst Length Supported
15
tccd = 1 CLK
01
01
01
01
01
16
17
2, 4 & 8
0E
04
0C
01
02
20
C0
A0
80
00
00
50
3C
50
32
20
B0
B0
60
60
00
46
50
30
3C
A0
00
00
8E
C1
0E
04
0C
01
02
20
C0
A0
80
00
00
50
3C
50
32
40
B0
B0
60
60
00
46
50
30
3C
A0
00
00
A7
C1
0E
04
0C
01
02
20
C0
A0
80
00
00
50
3C
50
32
40
B0
B0
60
60
00
46
50
30
3C
A0
00
00
B9
C1
0E
04
0C
01
02
20
C0
A0
80
00
00
50
3C
50
32
40
B0
B0
60
60
00
46
50
30
3C
A0
00
00
A8
C1
0E
04
0C
01
02
20
C0
A0
80
00
00
50
3C
50
32
40
B0
B0
60
60
00
46
50
30
3C
A0
00
00
BA
C1
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
4
18
CAS latency = 2 & 2.5
19
CS latency = 0
20
WE Latencies
Write latency = 1
21
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Min. Clock Cycle Time at CAS Latency = 2
Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1.5
Access Time from Clock at CL = 1.5
Minimum Row Precharge Time
Minimum Row Act. to Row Act. Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
Addr. and Command Setup Time
Addr. and Command Hold Time
Data Input Setup Time
unbuffered
22
–
23
10.0 ns
24
0.8 ns
25
not supported
26
not supported
27
20 ns
28
15 ns
29
20 ns
30
50 ns
31
256MByte
32
1.1 ns
33
1.1 ns
34
0.6 ns
35
Data Input Hold Time
0.6 ns
36-40
41
Superset Information
–
Minimum Core Cycle Time tRC
Min. Auto Refresh Cmd Cycle Time tRFC
Maximum Clock Cycle Time tck
Max. DQS-DQ Skew tDQSQ
X-Factor tQHS
70 ns
42
80 ns
43
12 ns
44
0.6 ns
45
1.0 ns
46-61
62
Superset Information
-
SPD Revision
Revision 0.0
63
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
Manufacturer
–
–
–
–
–
–
–
–
–
–
64
65-71
72
INFINEON INFINEON INFINEON INFINEON INFINEON
Module Assembly Location
Module Part Number
73-90
91-92
93-94
95-98
99-127
128-255
Module Revision Code
Module Manufacturing Date
Module Serial Number
–
open for Customer use
INFINEON Technologies
18
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
SPD Codes for PC2100 Modules “-7”
128MB
x64
256MB
x64
256MB
x72
512MB
x64
512MB
x72
Byte#
Description
1bank
-7
1bank
-7
1bank
-7
2bank
-7
2bank
-7
HEX
HEX
HEX
HEX
HEX
0
1
Number of SPD Bytes
128
256
80
08
07
0D
09
01
40
00
04
70
75
00
82
10
00
80
08
07
0D
0A
01
40
00
04
70
75
00
82
08
00
80
08
07
0D
0A
01
48
00
04
70
75
02
82
08
08
80
08
07
0D
0A
02
40
00
04
70
75
00
82
08
00
80
08
07
0D
0A
02
48
00
04
70
75
02
82
08
08
Total Bytes in Serial PD
Memory Type
2
DDR-SDRAM
13
3
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
4
9 / 10
5
1 / 2
6
Module Data Width
x64 / x72
0
7
Module Data Width (cont’d)
Module Interface Levels
8
SSTL_2.5
7 ns
9
SDRAM Cycle Time at CL = 2.5
Access Time from Clock at CL = 2.5
DIMM Config
10
11
12
13
14
0.75 ns
non-ECC / ECC
Self-Refresh, 7.8 ms
x16 / x8
na / x8
Refresh Rate/Type
SDRAM Width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-to-Back
Random Column Address
Burst Length Supported
15
tccd = 1 CLK
01
01
01
01
01
16
17
2, 4 & 8
0E
04
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
20
90
90
50
50
00
41
4B
30
32
75
00
00
99
C1
0E
04
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
40
90
90
50
50
00
41
4B
30
32
75
00
00
B2
C1
0E
04
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
40
90
90
50
50
00
41
4B
30
32
75
00
00
C4
C1
0E
04
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
40
90
90
50
50
00
41
4B
30
32
75
00
00
B3
C1
0E
04
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
40
90
90
50
50
00
41
4B
30
32
75
00
00
C5
C1
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
4
18
CAS latency = 2 & 2.5
19
CS latency = 0
20
WE Latencies
Write latency = 1
21
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Min. Clock Cycle Time at CAS Latency = 2
Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1.5
Access Time from Clock at CL = 1.5
Minimum Row Precharge Time
Minimum Row Act. to Row Act. Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
Addr. and Command Setup Time
Addr. and Command Hold Time
Data Input Setup Time
unbuffered
22
–
23
7.5 ns
24
0.75 ns
25
not supported
26
not supported
27
20 ns
28
15 ns
29
20 ns
30
45 ns
31
128MByte / 256MByte
32
0.9 ns
33
0.9 ns
34
0.5 ns
35
Data Input Hold Time
0.5 ns
36-40
41
Superset Information
–
Minimum Core Cycle Time tRC
Min. Auto Refresh Cmd Cycle Time tRFC
Maximum Clock Cycle Time tck
Max. DQS-DQ Skew tDQSQ
X-Factor tQHS
65 ns
42
75 ns
43
12 ns
44
0.5 ns
45
0.75 ns
46-61
62
Superset Information
–
SPD Revision
Revision 0.0
63
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
Manufacturer
–
–
–
–
–
–
–
–
–
–
64
65-71
72
INFINEON INFINEON INFINEON INFINEON INFINEON
Module Assembly Location
Module Part Number
73-90
91-92
93-94
95-98
99-127
128-255
Module Revision Code
Module Manufacturing Date
Module Serial Number
–
open for Customer use
INFINEON Technologies
19
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
SPD Codes for PC2100 Modules “-7F”
256MB
x72
512MB
x72
Byte#
Description
1bank
-7
2bank
-7
HEX
HEX
0
1
2
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
128
256
DDR-SDRAM
13
80
08
07
0D
0A
01
48
00
04
70
75
02
82
08
08
80
08
07
0D
0A
02
48
00
04
70
75
02
82
08
08
3
4
5
6
7
9 / 10
1 / 2
x64 / x72
0
8
9
SSTL_2.5
7 ns
0.75 ns
SDRAM Cycle Time at CL = 2.5
Access Time from Clock at CL = 2.5
DIMM Config
10
11
12
13
14
non-ECC / ECC
Self-Refresh, 7.8 ms
x16 / x8
na / x8
Refresh Rate/Type
SDRAM Width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-to-Back
Random Column Address
Burst Length Supported
15
tccd = 1 CLK
01
01
16
17
2, 4 & 8
4
0E
04
0C
01
02
20
C0
75
75
00
00
3C
3C
3C
2D
40
90
90
50
50
00
3C
4B
30
32
75
00
00
97
C1
0E
04
0C
01
02
20
C0
75
75
00
00
3C
3C
3C
2D
40
90
90
50
50
00
3C
4B
30
32
75
00
00
98
C1
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
18
19
20
21
CAS latency = 2 & 2.5
CS latency = 0
Write latency = 1
unbuffered
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Min. Clock Cycle Time at CAS Latency = 2
Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1.5
Access Time from Clock at CL = 1.5
Minimum Row Precharge Time
Minimum Row Act. to Row Act. Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
Addr. and Command Setup Time
Addr. and Command Hold Time
Data Input Setup Time
22
23
24
25
–
7.5 ns
0.75 ns
not supported
26
27
28
not supported
15 ns
15 ns
29
30
31
32
15 ns
45 ns
128MByte / 256MByte
0.9 ns
33
34
35
36-40
41
42
43
44
0.9 ns
0.5 ns
0.5 ns
–
Data Input Hold Time
Superset Information
Minimum Core Cycle Time tRC
Min. Auto Refresh Cmd Cycle Time tRFC
Maximum Clock Cycle Time tck
Max. DQS-DQ Skew tDQSQ
X-Factor tQHS
60 ns
75 ns
12 ns
0.5 ns
45
46-61
62
0.75 ns
–
Revision 0.0
Superset Information
SPD Revision
63
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
Manufacturer
Module Assembly Location
Module Part Number
–
–
–
–
–
–
–
–
–
–
64
65-71
72
73-90
91-92
93-94
95-98
99-127
128-255
INFINEON INFINEON
Module Revision Code
Module Manufacturing Date
Module Serial Number
–
open for Customer use
INFINEON Technologies
20
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
SPD Codes for PC2700 Modules “-6”
128MB
x64
256MB
x64
256MB
x72
512MB
x64
512MB
x72
Byte#
Description
1bank
-6
1bank
-6
1bank
-6
2bank
-6
2bank
-6
HEX
HEX
HEX
HEX
HEX
0
1
Number of SPD Bytes
128
256
80
08
07
0D
09
01
40
00
04
60
70
00
82
10
00
80
08
07
0D
0A
01
40
00
04
60
70
00
82
08
00
80
08
07
0D
0A
01
48
00
04
60
70
02
82
08
08
80
08
07
0D
0A
02
40
00
04
60
70
00
82
08
00
80
08
07
0D
0A
02
48
00
04
60
70
02
82
08
08
Total Bytes in Serial PD
Memory Type
2
DDR-SDRAM
13
3
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
4
9 / 10
5
1 / 2
6
Module Data Width
x64 / x72
0
7
Module Data Width (cont’d)
Module Interface Levels
8
SSTL_2.5
6 ns
9
SDRAM Cycle Time at CL = 2.5
Access Time from Clock at CL = 2.5
DIMM Config
10
11
12
13
14
0.70 ns
non-ECC / ECC
Self-Refresh, 7.8 ms
x16 / x8
na / x8
Refresh Rate/Type
SDRAM Width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-to-Back
Random Column Address
Burst Length Supported
15
tccd = 1 CLK
01
01
01
01
01
16
17
2, 4 & 8
0E
04
0C
01
02
20
C0
75
70
00
00
48
30
48
2A
20
75
75
45
45
00
3C
48
30
2D
55
00
00
E7
C1
0E
04
0C
01
02
20
C0
75
70
00
00
48
30
48
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
00
00
C1
0E
04
0C
01
02
20
C0
75
70
00
00
48
30
48
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
00
12
C1
0E
04
0C
01
02
20
C0
75
70
00
00
48
30
48
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
00
01
C1
0E
04
0C
01
02
20
C0
75
70
00
00
48
30
48
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
00
13
C1
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
4
18
CAS latency = 2 & 2.5
19
CS latency = 0
20
WE Latencies
Write latency = 1
21
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Min. Clock Cycle Time at CAS Latency = 2
Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1.5
Access Time from Clock at CL = 1.5
Minimum Row Precharge Time
Minimum Row Act. to Row Act. Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
Addr. and Command Setup Time
Addr. and Command Hold Time
Data Input Setup Time
unbuffered
22
–
23
7.5 ns
24
0.70 ns
25
not supported
26
not supported
27
18 ns
28
12 ns
29
18 ns
30
42 ns
31
128MByte / 256MByte
32
0.75 ns
33
0.75 ns
34
0.45 ns
35
Data Input Hold Time
0.45 ns
36-40
41
Superset Information
–
Minimum Core Cycle Time tRC
Min. Auto Refresh Cmd Cycle Time tRFC
Maximum Clock Cycle Time tck
Max. DQS-DQ Skew tDQSQ
X-Factor tQHS
60 ns
42
72 ns
43
12 ns
44
0.45 ns
45
0.55 ns
46-61
62
Superset Information
–
SPD Revision
Revision 0.0
63
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
Manufacturer
–
–
–
–
–
–
–
–
–
–
64
65-71
72
INFINEON INFINEON INFINEON INFINEON INFINEON
Module Assembly Location
Module Part Number
73-90
91-92
93-94
95-98
99-127
128-255
Module Revision Code
Module Manufacturing Date
Module Serial Number
–
open for Customer use
INFINEON Technologies
21
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Package Outlines - Raw Card C (One Bank Modules)
DDR-SDRAM DIMM Module Package
+ 0.15
-
133.35
2.7 m ax.
Front View
4.0
*)
92
53
52
pin
1
+ 0.1
-
1.27
64.77
49.53
2.3 typ.
6.62
Backside View
pin 93
144
145
184
2.5D
3
3
*) on E C C m odules only
D etail of Contacts
6.35
B
Detail of C ontacts
A
0.9R
+ 0.05
-
1
1.27
1.8
2.175
L-D IM -18 4-1 8
INFINEON Technologies
22
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Package Outlines -Raw Card A (One Bank Modules)
DDR-SDRAM DIMM Module Package
+ 0.15
-
133.35
2.7 m ax.
Front View
4.0
*)
92
53
52
pin
1
+ 0.1
-
1.27
64.77
49.53
2.3 typ.
6.62
Backside View
pin 93
144
145
184
2.5D
3
3
*) on E C C m odules only
D etail of Contacts
6.35
B
Detail of C ontacts
A
0.9R
+ 0.05
-
1
1.27
1.8
2.175
L-D IM -1 84-29
INFINEON Technologies
23
2002-10-24 (rev. 0.94)
HYS64/72D16x01/32x00/64x20GU-6/7/8-B
Unbuffered DDR-I SDRAM-Modules
Package Outlines - Raw Card B (Two Bank Modules)
DDR-SDRAM DIMM Module Package
two bank modules
+ 0.15
-
133.35
4.0 m ax.
Front View
4.0
*)
53
92
52
pin
1
+ 0.1
-
1.27
64.77
49.53
2.3 typ.
6.62
Backside View
pin 93
144 145
184
2.5D
*)
3
3
*) on EC C m odules only
D etail of C ontacts
6.35
B
D etail of C ontacts
A
0.9R
+ 0.05
-
1
1.27
1.8
2.175
L-D IM -1 84-9
INFINEON Technologies
24
2002-10-24 (rev. 0.94)
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