IRFS41N15DTRR [ETC]
TRANSISTOR | MOSFET | N-CHANNEL | 150V V(BR)DSS | 41A I(D) | TO-263AB ; 晶体管| MOSFET | N沟道| 150V V（ BR ） DSS | 41A I（ D） | TO- 263AB\n
| 型号： | IRFS41N15DTRR |
| 厂家： | 
ETC |
| 描述： | TRANSISTOR | MOSFET | N-CHANNEL | 150V V(BR)DSS | 41A I(D) | TO-263AB
|
| 文件： | 总11页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD- 93804A
IRFB41N15D
IRFS41N15D
SMPS MOSFET
IRFSL41N15D
HEXFET® Power MOSFET
Applications
l High frequency DC-DC converters
VDSS
150V
RDS(on) max
ID
41A
0.045Ω
Benefits
l Low Gate-to-Drain Charge to Reduce
Switching Losses
l Fully Characterized Capacitance Including
Effective COSS to Simplify Design, (See
App. Note AN1001)
l Fully Characterized Avalanche Voltage
and Current
D2Pak
TO-262
TO-220AB
IRFB41N15D
IRFS41N15D
IRFSL41N15D
Absolute Maximum Ratings
Parameter
Max.
41
Units
A
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
29
164
PD @TA = 25°C
PD @TC = 25°C
Power Dissipation
3.1
W
Power Dissipation
200
Linear Derating Factor
1.3
W/°C
V
VGS
dv/dt
TJ
Gate-to-Source Voltage
± 30
Peak Diode Recovery dv/dt
Operating Junction and
2.7
V/ns
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torqe, 6-32 or M3 screw
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Typical SMPS Topologies
l Telecom 48V input DC-DC Active Clamp Reset Forward Converter
Notes through ꢀ are on page 11
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IRFB/IRFS/IRFSL41N15D
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
150 ––– –––
––– 0.17 ––– V/°C Reference to 25°C, ID = 1mA
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.045
VGS(th)
Ω
VGS = 10V, ID = 25A
VDS = VGS, ID = 250µA
VDS = 150V, VGS = 0V
VDS = 120V, VGS = 0V, TJ = 150°C
VGS = 30V
Gate Threshold Voltage
3.0
––– 5.5
V
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
IDSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
IGSS
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 25A
ID = 25A
gfs
18
––– –––
72 110
S
Qg
–––
–––
–––
–––
–––
–––
–––
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
21
35
31
52
nC VDS = 120V
VGS = 10V,
VDD = 75V
16 –––
63 –––
25 –––
14 –––
ID = 25A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 2.5Ω
VGS = 10V
VGS = 0V
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
––– 2520 –––
––– 510 –––
––– 110 –––
––– 3090 –––
––– 230 –––
––– 250 –––
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
VDS = 25V
pF
ƒ = 1.0MHz
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 120V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 120V ꢀ
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Avalanche Current
Typ.
Max.
470
25
Units
mJ
EAS
IAR
–––
–––
–––
A
EAR
Repetitive Avalanche Energy
20
mJ
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
0.75
–––
62
Units
RθJC
RθCS
RθJA
RθJA
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
0.50
–––
°C/W
Junction-to-Ambient
–––
40
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
D
IS
Continuous Source Current
(Body Diode)
MOSFET symbol
41
––– –––
––– –––
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
p-n junction diode.
164
S
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 170 260
––– 1.3 1.9
V
TJ = 25°C, IS = 25A, VGS = 0V
ns
TJ = 25°C, IF = 25A
Qrr
ton
µC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFB/IRFS/IRFSL41N15D
1000
100
10
1000
VGS
15V
VGS
TOP
TOP
15V
10V
10V
9.0V
8.0V
7.5V
7.0V
6.5V
9.0V
8.0V
7.5V
7.0V
6.5V
BOTTOM 6.0V
BOTTOM6.0V
100
10
1
6.0V
20µs PULSE WIDTH
T = 175 C
J
20µs PULSE WIDTH
°
6.0V
1
°
T = 25 C
J
1
0.1
0.1
1
10
100
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
41A
=
I
D
2.5
2.0
1.5
1.0
0.5
0.0
100
10
1
°
T = 175 C
J
°
T = 25 C
J
V
= 25V
DS
20µs PULSE WIDTH
V
= 10V
GS
6
7
8
9
10
11
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
°
V
, Gate-to-Source Voltage (V)
T , Junction Temperature ( C)
J
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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IRFB/IRFS/IRFSL41N15D
20
16
12
8
100000
I
D
= 25A
V
= 0V,
f = 1 MHZ
GS
C
= C + C
,
C
ds
SHORTED
iss
gs
gd
V
V
V
= 120V
= 75V
= 30V
DS
DS
DS
C
= C
rss
gd
C
= C + C
oss
ds
gd
10000
1000
100
Ciss
Coss
Crss
4
FOR TEST CIRCUIT
SEE FIGURE 13
10
0
1
10
100
1000
0
20
40
60
80 100
120
Q
, Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
100
10
1000
100
10
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
°
T = 175 C
10us
J
100us
1ms
°
T = 25 C
J
1
10ms
°
T = 25 C
C
°
T = 175 C
Single Pulse
J
V
= 0 V
GS
1
0.1
0.2
1
10
100
1000
0.6
1.0
1.4
1.8
V
, Drain-to-Source Voltage (V)
V
,Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRFB/IRFS/IRFSL41N15D
RD
50
40
30
20
10
0
VDS
VGS
D.U.T.
RG
+VDD
-
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
175
°
, Case Temperature ( C)
T
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
10
1
D = 0.50
0.20
P
DM
0.1
0.10
0.05
t
1
t
2
0.02
0.01
Notes:
SINGLE PULSE
(THERMAL RESPONSE)
1. Duty factor D =
t / t
1 2
2. Peak T = P
x Z
+ T
C
J
DM
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFB/IRFS/IRFSL41N15D
1200
1000
800
600
400
200
0
1 5V
I
D
TOP
10A
21A
25A
BOTTOM
DRIVER
L
V
G
DS
D.U.T
R
+
V
D D
-
I
A
AS
20V
0.01
t
Ω
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
°
Starting T , Junction Temperature ( C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
VGS
Q
Q
GD
GS
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
V
GS
3mA
I
I
D
G
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
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IRFB/IRFS/IRFSL41N15D
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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IRFB/IRFS/IRFSL41N15D
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415 )
3.78 (.149)
-
B
-
10.29 (.405 )
2.87 (.1 13)
2.62 (.1 03)
4 .69 (.18 5)
4 .20 (.16 5)
3.54 (.139)
1.3 2 (.05 2)
1.2 2 (.04 8)
-
A
-
6.4 7 (.2 55)
6.1 0 (.2 40)
4
15 .24 (.60 0)
14 .84 (.58 4)
1.15 (.04 5)
M IN
LE A D A S S IG N M E N TS
1 - G A T E
1
2
3
2 - D R A IN
3 - S O U R C E
4 - D R A IN
1 4.09 (.5 55)
1 3.47 (.5 30)
4.06 (.160)
3.55 (.140)
0.93 (.0 37)
0.69 (.0 27)
0.55 (.02 2)
0.46 (.01 8)
3X
3 X
1 .40 (.05 5)
3 X
1 .15 (.04 5)
0.3 6 (.014 )
M
B
A
M
2.9 2 (.115 )
2.6 4 (.104 )
2 .54 (.10 0)
2X
N O TE S :
1
2
D IM E N S IO N IN G
&
TO LE R A N C IN G P E R A N S I Y 14 .5 M , 1 982.
3
4
O U TL IN E C O N F O R M S TO JE D E C O U T LIN E T O -2 20A B .
C O N TR O LLIN G D IM E N S IO N : IN C H
H E A T S IN K
&
LE A D M E A S U R E M E N T S D O N O T IN C L U D E B U R R S .
TO-220AB Part Marking Information
E XAM PL E : TH IS IS A N IR F 1010
W ITH AS SE M BLY
A
INTE R N AT ION AL
R E C TIFIE R
PA R T N U M BE R
LO T C O D E 9B 1M
IR F 1010
9246
LO G O
9B
1M
D ATE C O D E
(YYW W )
A S SE M B LY
LOT
C O D E
YY
=
YEA R
= W EE K
W W
8
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IRFB/IRFS/IRFSL41N15D
D2Pak Package Outline
10.54 (.415)
10.29 (.405)
10.16 (.400)
REF.
- B -
1.32 (.052)
4.69 (.185)
4.20 (.165)
1.40 (.055)
- A -
M AX.
1.22 (.048)
2
6.47 (.255)
6.18 (.243)
1.78 (.070)
1.27 (.050)
15.49 (.610)
14.73 (.580)
2.79 (.110)
2.29 (.090)
1
3
2.61 (.103)
2.32 (.091)
5.28 (.208)
4.78 (.188)
8.89 (.350)
REF.
1.40 (.055)
1.14 (.045)
1.39 (.055)
1.14 (.045)
3X
0.55 (.022)
0.46 (.018)
0.93 (.037)
0.69 (.027)
3X
5.08 (.200)
0.25 (.010)
M
B A M
M INIMUM RECOM MENDED FOOTPRINT
11.43 (.450)
8.89 (.350)
LEAD ASSIGNMENTS
1 - GATE
NO TES:
1
2
3
4
DIM ENSIONS AFTER SOLDER DIP.
17.78 (.700)
2 - DRAIN
3 - SOURCE
DIM ENSIONING & TOLERANCING PER ANSI Y14.5M , 1982.
CONTROLLING DIM ENSION : INCH.
HEATSINK & LEAD DIM ENSIONS DO NOT INCLUDE BURRS.
3.81 (.150)
2.54 (.100)
2.08 (.082)
2X
2X
D2Pak Part Marking Information
A
INTERNATIONAL
RECTIFIER
PART NUM BER
F530S
LOGO
9246
1M
DATE CODE
(YYW W )
9B
ASSEM BLY
YY
=
YEAR
= W EEK
LOT CODE
W W
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IRFB/IRFS/IRFSL41N15D
TO-262 Package Outline
TO-262 Part Marking Information
10
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IRFB/IRFS/IRFSL41N15D
D2Pak Tape & Reel Information
TR R
1 .60 (.0 63)
1 .50 (.0 59)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEE D D IREC TIO N
TR L
11.60 (.457)
11.40 (.449)
1 .85 (.0 73)
1 .65 (.0 65)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED D IRE CTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
M AX.
60.00 (2.362)
M IN.
30.40 (1.197)
M AX.
NO TES
1. CO M FORM S TO EIA-418.
2. CO NTROLLING DIM ENSIO N: M ILLIM ETER.
3. DIM ENSION M EASURED
:
26.40 (1.039)
24.40 (.961)
4
@ HUB.
3
4. INCLUDES FLANGE DISTORTION
@
O UTER EDGE.
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature.
ꢀCoss eff. is a fixed capacitance that gives the same charging time
Starting TJ = 25°C, L = 1.5mH
R
G = 25Ω, IAS = 25A.
as Coss while VDS is rising from 0 to 80% VDSS
ISD ≤ 25A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS
TJ ≤ 175°C
,
This is only applied to TO-220AB package
This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
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IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630
IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
Data and specifications subject to change without notice. 02/2000
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