L6239 [ETC]
;
ETC 
L6239
12V DISK DRIVE SPINDLE DRIVER
PRODUCT PREVIEW
General
12V OPERATION
MULTIPOWER BCD TECHNOLOGY
REGISTER BASED ARCHITECTURE
SLEEP AND IDLE MODES FOR LOW
POWER CONSUMPTION
SERIAL INTERFACE
Spindle Driver
BEMF PROCESSING FOR SENSOR-LESS
MOTOR COMMUTATION
PLCC44
INTERNAL POWER DEVICES
PROGRAMMABLE SLEW-RATE FOR RE-
DUCED E.M.I.
ORDERING NUMBER: L6239
20 FOR ANY HALF BRIDGE WORST CASE
(1Ω PER DEVICE)
B.E.M.F. DETECTION READABLE FROM
REGISTER OR PIN
NO SNUBBERS REQUIRED FOR LOOP
COMPENSATION OR E.M.I. CONTROL
B.E.M.F. processing& digital masking).
When a power On Reset (P.O.R.) is accepted,
the internal registers are reset, the spindle power
circuitry is tri-stated, and dynamic braking of the
spindle is applied.
This device is built in BCD II technology allowing
dense digital/analog circuitry to be combined with
high power DMOS output stage.
Other Functions
POWER UP SEQUENCING
POWER DOWN SEQUENCING
PWM OPERATION
PIN CONNECTION
LOW VOLTAGE SENSE
DYNAMIC BRAKE
THERMAL WARNING
6
5
4
3
2
1 44 43 42 41 40
THERMAL SHUTDOWN
NEGATIVE VOLTAGE REGULATOR SUP-
PORT
GND
Vpower
7
39
38
37
36
35
34
33
32
31
30
29
GND
8
AGND
Vpower
9
N.C.
Cpump1
Vpump
10
11
12
13
14
15
16
17
Ctr Tap
CSA Input
PWM/Slew
gm Comp
Gate Drive
PWM Timer
N.C.
Cpump2
Vanalog
DESCRIPTION
bemf_det
Vreg_Base
Vreg_Vsense
GND
The L6239 is a single chip sensorless (DC) spin-
dle motor controller including power stages suit-
able for use in disk drives.
GND
18 19 20 21 22 23 24 25 26 27 28
The device has a serial interface for a microproc-
essor running up to 10 mega bits per second.
There are registers on chip to allow the setting of
the desired operating modes No external compo-
nents are required in the sensor-lessoperation as
the control functions are integrated on chip (e.g.
D95IN222
1/13
March 1995
This is advanced information on a new product now in developmentor undergoing evaluation. Details are subject to change without notice.
L6239
- MICROPROCESSOR SPIN-UP & SPEED
CONTROL
- MICROPROCESSOR INITIATED STARTUP
- SPEED COMPENSATION BY EXTERNAL
RC NETWORK
- NO SNUBBERS REQUIRED FOR
CURRENT LOOP COMPENSATION OR
EMI CONTROL
- MICROPROCESSOR ACCELERATION
CONTROL VIA DAC (FOR SMOOTH
TRANSITION TO AT SPEED CONTROL)
- GRAY CODE COUNTER FOR
COMMUTATION CONTROL
(INCREMENTED BY SPIN_CLOCK PIN).
- BEMF DETECTION READABLE FROM
REGISTERS (A,B OR C PHASES) OR PIN
(BEMF_DET).
AUTOMATIC CLAMPING OF OUTPUT TO
PREVENT SUBSTRATE CURRENT
PROGRAMMABLE SLEW RATE CONTROL
(LINEAR MODE ONLY)
FEATURES
General
POWER UP MICROPROCESSOR RESET
SEQUENCING
- POWER UP RESET AND DELAY
- INTERNAL REGISTER INITIALIZATION
OVER TEMPERATURE PROTECTION
MASKING ON CHIP
COMMUTATION EXTERNALLY CONTROL-
LED
NEGATIVE VOLTAGE SUPPORT CIRCUITRY
Interface
SERIAL SYNCHRONOUS
- SCLK, SLOAD, SDIO, R/W
- UP TO 10 MEGABIT DATA RATE
Spindle Driver
8 BIT RESOLUTION SPINDLE DAC FOR MI-
CROPROCESSOR ACCELERATION CON-
TROL
INTERNAL POWER DEVICES
THREE PHASE BRIDGE PLUS BIPOLAR
DRIVER
DYNAMIC BRAKING BY COMMAND
BLOCK DIAGRAM
Vdgtl
21
PWM/Slew
34
PWM Timer
31
10
Cpump1
CHARGE
12
PUMP
13
PWM/Linear
spin_range
Cpump2
Vpump
VRef &
Bias
LINEAR SLEW RATE
CONTROL &
PWM MONOSTABLE
Vanalog
11
POWER
STAGE
8
9
24
25
22
27
26
POR
R/W
Vpower
SERIAL
INTERFACE
CONTROL
REGISTER
THERMAL
SHUTDOWM
SDIO
SLoad
Sclk
23
4
Brake
Out A
5
xout, yout, zout xin, yin, zin
1
Sequence
Increment
19
single/multi_
2
Out B
Out C
+
6-STATE
GRAY CODE
COUNTER
41
42
36
3
BEMF +
enable_clk
SENSE
ZERO
CROSSING
DETECTOR
+
3
-
Ctr Tap
Rsense1
Rsense2
Rsense3
bemf_A,B,C
43
44
14
20
bemf_det
8
SYSTEM
CLOCK
Spin
DAC
SYS CLOCK
+
-
Ds7 ..Ds0
6,7,17,29,39,40
GND
15
18
16
To PWM
Monostable
NEGATIVE
VOLTAGE
REGULATOR
Vreg_Base
Vreg_Isense
Vreg_Vsense
38
35
DRV
CNTL
AV=4V/V
CSA
AGND
+
-
CSA Input
PWM COMP.
33
32
Gate Drive
D95IN218A
gm Comp
2/13
L6239
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
VS
VS
Maximum Supply Voltage (Vanalog, power max)
Maximum Supply Voltage (Vdigital max)
Maximum Input Voltage
15
7
V
VImax
VI min
Ipeak/Idc
Vdigital ± 0.3
GND - 0.5
2.2
V
Minimum Input Voltage
V
Peak Sink/Source Output Current/DC Sink Source Output
Current
A
Ptot
Maximum Total Power Dissipation
3
W
Tstg, Tj
Maximum Storage and Junction Temperature Range
-40 to 150
°C
THERMAL DATA
Symbol
Parameter
Thermal Resistance Junction-ambient (standard PCB mounted)
Value
27
Unit
Rth j-amb
°C/W
Note:
This standard board construction includes: A 4 layer board, for 1cm2 hest copper area best sinks located at the chips vertices each with 4 rows
of 4 columns of plated vias (od = 0.104cm, diameter = 0.0584cm) through to the ground plane.
3/13
L6239
PIN DESCRIPTION
Pin Types: I = Input, O = Output, P = Power, A = Analog (passive)
N.
Name
Function
Pin Type
POWER
6, 7, 17,
29, 40
Ground
Power Ground
AI
38
8, 9,37
13
Analog Ground Analog Signal Return
AI
AI
AI
AI
VPower
VAnalog
Vdgtl
Driver Power Supply (12V)
Analog Supply (12V)
Logic Supply (5V)
21
SERIAL INTERFACE, DIGITAL & TEST PINS
22
25
27
26
19
SDIO
Serial Port Data I/O
DI/O
DI
R/W
Serial Port Read/Write Input
SLoad
SCLK
Serial Port Chip Select. Port is selected when low
Serial Port Clock
DI
DI
Sequence
Increment
Increments the spindle commutation on low to high transition
DI
23
Brake
Applies braking (all low side drivers energized) after the timedefined by
Brake_time. Active low
DI
24
14
20
28
30
POR
Resets the controller on receipt of POR low
DI
DO
DI
BEMF det
SYS CLK
TP out1
TP out2
Post masching BEMF zero crossing signal
Sistem clock
Test pin 1
Test pin 2
TO
TO
ANALOG PINS
4, 5
Coil A
Coil B
Coil C
Motor Coil Driver for phase A. This pin is also used for sensing the BEMF
As above for phase B
AI/O
AI/O
AI/O
AI/O
AI/O
AI/O
1, 2
41, 42
As above for phase C
36
3, 43, 44
35
Center Tap
Rsense
Center tap motor connection
Sense Resistor Pins
CSA Input
Current Sense Amplifier Input for sensing of voltage across the external
sense resistor.
33
32
GM Comp
A series RC network to ground that defines the compensation for the
Transconductance Loop
AO
Gate Drive
(NOTE 1)
For external PMOS applications
AI/O
10
12
11
34
31
15
18
16
Cpump 1
Cpump 2
Positive terminal of the pump capacitor
Negative terminal of the pump capacitor
Charge pump output
A/O
A/O
A/O
AO
AO
A/O
AI
Vpump
PWM/ Slew
PWM Timer
Vreg Base
Vreg Isense
Vreg Vsense
An RC network to GND defines the slew ate from this pin
Masking for PWM (max)
Negative voltage regulator - Base
Negative voltage regulator - Current input
Negative voltage regulator - Regulator
AI
NOTE 1: for internal mode, this pin must be grounded. For external mode, connect this pin to the external PMOS.
4/13
L6239
ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70°C; VA = Vpower = 12V; Vdigital = 5V, unless otherwise
specified. Parameters market with an * are guaranteed by design, but not 100% tested in production)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
GENERAL
Vanalog, Power Supply Voltage Range
10
12
5
13.6
5.5
V
Vdigital
Iready12
Isleep12
Iready5
Isleep5
Supply Voltage Range
Quiescent Current
Quiescent Current
Quiescent Current
Quiescent Current
4.5
V
Spindle Enabled
15
mA
µA
mA
µA
Spindle Disabled
Spindle Enabled
Spindle Disabled
1000
5
1000
THERMAL SHUTDOWN
*ThWarn
Thermal Warning
Thermal Shutdown
130
155
150
175
170
195
°C
°C
*ThSh Dwn
SPINDLE DRIVER SECTION
Io
Maximum Output Current
2.2
0.2
A
dv/dt on
Voltage Sew Rate
Turn on
Turn off
2.0
1.0*
2.0
V/µs
V/µs
Ω
0.1*
RDS(on) Total Total Output On Resistance
(Sink + Source)
Tj = 25°C, Tj = 125°C,
Iload = 2.0A
1.0
0.5
RDS(on)
Device
Sink Output On Resistance
Tj = 25°C, Tj = 125°C,
Iload = 2.0A
1.0
Ω
Io (LEAK)
VF
Output Leakage Current
Body Diode Forward Drop
1
mA
V
Im = 2.0A
1.5
0.9
0.35
Im = 100mA
Rslew = 100KΩ
V
dVo/dt
Output Slew Rate
0.30
V/µs
* Yet to be confirmed
DAC ACCELERATION CONTROL / SENSE AMPLIFIER
RES
NL
Resolution
Full scale
8
0.5
1.5
5
bits
LSB
LSB
%
Differential Non-linearity
Integral Non- linearity
Full Scale Accuracy
Conversion Time
0-1 bit excluded
INL
FS
CT
10
µs
FSCT
Gain
DACout
OFFSET
Full Scale Temp Coefficient
0 to 125°C
250
TBD
2
ppm/°C
%
Curr. Sense Gain Ratio 4:1 or 20:1 1% resistence tolerance (0.5Ω)
DAC Output
0
0
V
Input Offset of Sense Amp
7
15
mV
LOGIC SECTION (All digital inputs are CMOS compatible)
Vih
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
3.5
4.5
V
V
Vil
1.5
Voh
Vol
Iin
Iout = 1.0mA
Iout = 1.0mA
Tj = 125°C, 1
V
0.4
V
-1
1
mA
Iwsi
Minimum Sequence Increment
High Time
Note 1
Fsys
System Clock Frequency
10.0
MHz
5/13
L6239
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Cin
Logic Input Capacitance
(except Serial Port Clock)
All inputs except SCLK
5
pF
Cin
Serial Port Clock Input
SCLK
10
pF
Capacitance (Logic Level Low)
PORIN
POR Pulse Width
1
µs
4
Note1: The minimum time that the Sequence Increment pin must be held high during eternal sequence incrementing is equal to
SysCk
BEMF AMPLIFIER
IAmpin
VBEMF
Input Bias Current
10.0
25
µA
Minimum Bemf (Pk-Pk)
Voltage Offset Hysteresis
60
11
mV
mV
VOFF_HYST
18
BRAKE
Tbrake
Time from POR signal receipt
to expected receipt of Brake signal
0.01
500
10
ms
Ibrlk
Ibrin
Brake Leakage Current
Brake Low Input Current
µA
µA
100
NEGATIVE VOLTAGE REGULATOR - CURRENT SENSE COMPARATOR
Ibias
Tresp
Input Bias Current
0.3V input
2
µA
µs
V
Response Time
20mV overdrive
1
HighTh
LowTh
High hysteresis threshold
Low Hysteresis Threshold
0.336
0.033
0.464
0.046
V
NEGATIVE VOLTAGE REGULATOR - VOLTAGE SENSE COMPARATOR
Ibias
Tresp
VTh
Input Bias Current
Response Time
0.3V input
2
1
µA
µs
V
20mV overdrive
Comparator Threshold
Comparator Hysteresis
1.20
5
1.27
1.333
20
VHys
mV
NEGATIVE VOLTAGE REGULATOR - DRIVER OUTPUT
Ilow
Vhigh
Vlow
Low Output Current
Output High Voltage
Output Low Voltage
VO < 3.5V
4
mA
V
I = 0.1mA; (VDig = 5V)
I = -4mA
4.8
3.5
V
LOOP BACK COMPARATOR
Vth
Switching Threshold
0.45
0.50
0.55
V
6/13
L6239
spindle motor to allow motor control and to pre-
sent the ”at speed” voltage for the charge pump.
Often this will be used to limit the start-up current.
INTERNAL REGISTER DEFINITION
Spin Control Register (Reg 0)
The first (bits 0-8) is to program the current to the
Reg: 0
Type: Write only.
BIT
0
LABEL
DESCRIPTION
@POR_ LOW
SPIN DAC BIT 0
SPIN DAC BIT 1
SPIN DAC BIT 2
SPIN DAC BIT 3
SPIN DAC BIT 4
SPIN DAC BIT 5
SPIN DAC BIT 6
SPIN DAC BIT 7
SPIN RANGE
Spindle current limit LSB
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Spindle current limit MSB
Spindle transconductance loop gain range select, 0 = 4:1, 1= 20:1
8
System Input Register (Reg 1)
Reg: 1
Type: Write only.
BIT
0
LABEL
SLEEP
DESCRIPTION
@POR_ LOW
A0 puts the spindle into a high impedance state
A1 turns on all lower spindle drivers to brake the spindle
Selects either PWM (1) or Linear (0) modes of operation
1 selects phase. A for zero crossings, 0 selects all three phases
Enables (1) the SPIN CLK pulses to increment the spindle counter
Logic low to reset spindle counter
0
0
0
0
0
0
0
0
0
1
BRAKE
2
PWM/LINEAR
SINGLE/MULTI
ENABLE CLK
RESPHASE
TRIST di
3
4
5
6
Logic low to tristate BEMF DET output.
7
CLKDIV2
Logic low - sys clk; logic high - half system clock
Enables Negative Voltage circuitry (when set to 1).
8
ENABLE NEG
Logic low - masking time equal to 512 cycles of sys clk. Logic high -
masking time equal to 1024 cycles of sys clk.
9
TIME2X
0
10
11
TEST PIN1
TEST PIN2
Test pin
Test pin
0
0
System Input Register (Reg 2)
Reg: 2
Type: Readonly.
BIT
0
LABEL
BEMF A
DESCRIPTION
Phase A zero crossing detected
@POR
0
0
0
0
0
0
1
BEMF B
BEMF C
IN X
Phase B zero crossing detected
Phase C zero crossing detected
Grey code counter bit X
2
3
4
IN Y
Grey code counter bit Y
5
IN Z
Grey code counter bit Z
Thermal shutdown warning. This occurs approximately 25°C before
the device goes into thermal shutdown.
6
7
THERM_WARN
LOOP_BACK
0
0
If PWM bit is set to 0, this bit represent the status of the loopback
comparator
7/13
L6239
all registers to the ”@POR” state (see register de-
scription).
Register Select Table
REGISTER
SELECTED
The L6239 assumes that a separate brake com-
mand must be issues to brake the spindle.
INPUT: A3 - A0
TYPE
0000
0001
0010
0
1
2
WRITE
WRITE
READ
Serial Interface
The serial interface is designed to be compatible
with the Intel 80196 (and other similar micros) se-
rial interface but is capable of faster data rates,
up to 10MHz.
CIRCUIT OPERATION
General
All read and write operations must consists of 16
bits, with the 80196 this would be two 8 bit ac-
cesses.
The first four bits are address and the next 12 are
data. If the address is a read register, then the
L6239 will use the SCLK from the system to shift
out 12 bits of data from the addressed register.
This device includes a sensorless spin driver,
power sequencing with dynamic braking and se-
rial interface for a microprocessor. The device is
register based to eliminate single point intercon-
nects where ever possible.
It is designed to operate with a 12V power supply.
The system must provide 16 SCLK pulses to in-
sure that the read operation completes. The SDIO
line is capableof driving a 60pf load.
POR
When POR goes low, the L6239 resets itself and
Symbol
tRWS
tSLS
Description
R/W setup time to SCLK going high
SLOAD setup time to SCLK going high
R/W hold time after SCLK going high
SLOAD hold time after SCLK going high
SCLK high to Data Valid
Min.
100
100
100
100
10
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
tRWH
tSLH
tSCKD
tRWD
tAS
30
30
50
50
R/W High to Data Valid Data bit D [0] valid from HiZ
Address setup time to SCLK going high
Data setup time to SCLK going high
Address hold after SCLK going high
Data hold time after SCLK going high
SDIO tri-state after SLOAD going high
SDIO tri-state afterR/W going low
Minimum SCLK period
10
30
tDS
30
tAH
10
tDH
10
tSDZ
tRWZ
tPER
30
30
100
100
40
t
REC (*)
tDUT
Recycle - Time between successive accesses
Clock duty cycle
50
60
tSCLK
SCLK Clock timing
100
0.1
µs
(*) For 10MHz system clock operation (in other words, 1or more clock cycles of SCLK).
Serial Interface Truth Table
R/W
SLOAD
SDIO
DIRECTION
Tri-state
Tri-state
Input
1
0
0
1
1
1
0
0
Tri-state (Port un-selected)
Tri-state (Port un-selected)
Address/Data input
Data output
Output
8/13
L6239
Figure 1: Serial Write Timing Diagram
R/W
t
t
RWH
RWS
SLOAD
SCLK
t
t
SLH
SLS
t
PER
4 bit address (FIXED)
A1 A2
12 bit address (FIXED)
D4 D5 D6
SDIO
A0
A3
D0
D1
D2
D3
D7
D8
D9
D10
D11
D94IN121
t
t
t t
DS DH
AS
AH
Figure 2: Serial Read Timing Diagram
t
t
t
RWS
SLS
RWH
R/W
t
RWS
SLOAD
t
PER
SCLK
SDIO
t
t
SCKD
RWD
INPUT
A1
OUTPUT
D6
HiZ
A0
A2
A3
D0
D1
D2
D3
D4
D5
D7
D8
D9
D10
D11
D94IN122
t
t
AH
AS
The write cycle has a fixed address and data
length. Four bits of address and 12 bits of data
must be clocked in to allow the data to be loaded
into the desired register.
The write cycle is initiated by setting SLOAD and
R/W low. Setting R/W low causes the SDIO line
to be tristated for data input. SLOAD low enables
the internal counter to increment on the rising
edge of SCLK. The address and data are clocked
into the chip serially on each rising edge of SCLK
as shown above. when both the 4 bits of address
and the 12 bits of the data have been clocked in,
then the address register will be written to with
the provided data.
The read cycle is initiated by setting SLOAD low
and clocking in a valid read address.
Only four bits of address are necessary, if more
than four bits are clocked in, the four MSBs will
be ignored (i.e. only the first four bits will be
used).
If a valid address is detected, the rising edge of
R/W will liad the desired register into the internal
serial/parallel register is then serially clocked out
on every rising edge of SCLK (LSB is clocked out
first). Additional padded bits clocked out will be
zero.
NOTE:
If SLOAD isset lowwith R?Whigh, thecurrent contents ofthe internal
shift register can be clocked out. This is useful for a ”read back” of
the data last written into the required register.
Setting SLOAD high will clear theinternal logic
and tri-state the SDIO line. This also provides a
way of safely aborting a write by simply forcing
SLOADhigh.
Figure 3, illustrates the case where the serial port
is deselected while reading data.
NOTE:
During a read mode, the mP is in tri-stateand the
L6239 is writing data on to the SDIO pin. If the
SLOAD must be kept low during the entire duration of the 16 write
clocks.
9/13
L6239
Figure 4: System Level Interface
Figure 3
CLK
DATA
CS1
SCLK
SDIO
SLOAD
R/W
R/W
L6239
MICRO
R/W
SLOAD
SCLK
SDIO
CS2
R/W
CLK
DATA
CS
OTHER
DEVICE
t
t
t
t
RWZ
D95IN221
SDZ
RWD
SCKD
D94IN123
L6239 is deselected by bring SLOAD high, the
serial port stops writing and assumes a tri-state
drive is in bipolar mode (Unipolar is not sup-
ported).
conditionafter time tSTZ
.
S_A_L, S_B_L and S_C_L are the lower spindle
drive transistors. They are active in bipolar drive.
In linear mode the active transistor’s gate drive is
controlled so as to bring the current in the motor
to the level set by the speed control compensa-
tion circuit or the current limit DAC. Activating the
BRAKE mode turns on all the lower drivers.
When R/W goes low, the Serial Port stops writing
to SDIO. This is actually a transparent operation,
since SDIO is already tri-stated.
Next, SLOAD goes low, selecting the L6239, but
SDIO remains low since R/W is still low. When
R/W goes high, the L6239 starts to write to SDIO
with the data valid after time, tRWD
.
RESET places the state machine into a known
state (see @POR column of register definitions).
At the end of the read operation, R/W goes low
and SDIO goes into tristate condition after time
To increment the commutation state either
Spin_Clock signal is clocked.
tRWZ
.
Power Devices/Spindl State Machine
Thermal Warning & Shutdown
S_AU, S_B_U and S_C_U are the upper spindle
drive transistors. They are active whenever the
The Thermal (Shutdown) Warning is designed to
allow the system to take any actions required
Figure 5
+5V
Good decoupling must be used.
e.g. minimum 22µF
ENABLE_NEG
Vreg_Base
2KΩ
Vreg_Cur
-
+
75Ω
Load
1.6KΩ
100pF
2Ω
22µF
20KΩ
43KΩ
1.2V
5Ω
+5V
10KΩ
+
-
20KΩ
20KΩ
Vreg_Reg
L6239
D94IN124
10/13
L6239
prior to the L6239 shut down at the Thermal Shut-
down level.
Once the Thermal SHutdown is triggered the
spindle is tristated and the chip is reset (although
the serial interface can still be used). No braking
function taken place.
The chip remains in this state with the serial inter-
face available for access
Once the device falls below the Thermal Warning
temperature, the L6239 output stage is no longer
tristated.
Negative Voltage Regulator Support
This device includes support for a negative volt-
age supply. The regulator uses a regulation tech-
nique, that generates an external negative volt-
age, but does not require an negative power
supply. the diagram below shows the circuitry in-
cluded in the L6239 to support the Regulator.
The more lightly colored circuitry is the recom-
mended external circuitry that actually creates the
negativevoltage.
The circuit has been designed so that all external
componentsa can be inexpensive. For example,
the transistor needs only to be a 2N@()&A and
the diode a 1N4148.
If there is still sufficient motion in the motor, the
µP has the opportunutyto resynchronize the out-
put
11/13
L6239
PLCC44 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
17.4
16.51
3.65
4.2
TYP.
MAX.
17.65
16.65
3.7
MIN.
0.685
0.650
0.144
0.165
0.102
MAX.
0.695
0.656
0.146
0.180
0.108
A
B
C
D
4.57
2.74
d1
d2
E
2.59
0.68
0.027
14.99
16
0.590
0.630
0.078
0.004
e
1.27
12.7
0.050
0.500
e3
e4
F
1.98
0.101
0.46
0.71
0.018
0.028
F1
G
M
1.16
0.046
12/13
L6239
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-
tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-
press written approval of SGS-THOMSON Microelectronics.
1995 SGS-THOMSON Microelectronics - All RightsReserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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13/13
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