LC72319 [ETC]
;
| 型号： | LC72319 |
| 厂家： | 
ETC |
| 描述： | 外围集成电路 时钟 |
| 文件： | 总14页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN7022
CMOS IC
LC72317, 72318, 72319
Low-Voltage ETR-Controller
Overview
Package Dimensions
The LC72317, 72318 and 72319 are low-voltage
electronic tuning radio microcontrollers that include a PLL
that operates up to 250 MHz and a 1/4 duty 1/2 bias LCD
driver on chip. These ICs include an on-chip DC-DC
converter, making it is easy to create the supply voltages
required for tuning and allowing cost reductions in end
products.
unit: mm
3220-SQFP80
[LC72317, 72318, 72319]
14.0
12.0
0.135
1.25
1.25
0.5
60
41
61
40
These ICs are optimal for use in low-voltage portable
audio equipment that includes a radio receiver.
Function
• Program memory (ROM):
— 6144 × 16 bits (12K bytes)
— 8192 × 16 bits (16K bytes)
• Data memory (RAM):
LC72317
LC72318/319
21
80
1
20
0.2
— 256 × 4 bits
— 512 × 4 bits
• Cycle time: 40 µs (all 1-word instructions) at 75kHz
crystal oscillation
LC72317/318
LC72319
0.5
0.5
SANYO: SQFP80
• Stack: 8 levels
• LCD driver: 48 to 112 segments (1/4 duty, 1/2 bias
drive)
• Interrupts: Two external interrupts
Timer interrupts (1, 5, 10, and 50 ms)
• A/D converter: Three input channels
(5-bit successive approximation
conversion)
• Input ports: 9 ports (of which three can be switched for
use as A/D converter inputs)
• Output ports: 6 ports (of which 1 can be switched for use
as the beep tone output and 2 are open-
drain ports)
Continued on next page.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
60401TN (OT) No. 7022-1/14
LC72317, 72318, 72319
Continued from preceding page.
• Backup mode: The crystal oscillator is stopped.
• Static power-on function: Backup state is cleared with
the PF port
I/O ports: 29 pins (Of these 16 can be switched over to
function as LCD ports as a mask options, and
3 ports can be switched over for use with
serial I/O.)
• Serial I/O: One system
• Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5,
and 25 kHz
• Beep tone: 1.5 and 3.1 kHz
• Built-in tuner voltage generating circuit:
Cost reduced in tuner-use power supply circuit
• Memory retention voltage: 0.9 V at least
• V voltage
DD
• Input frequencies: FM band: 10 to 250 MHz
AM band: 0.5 to 20 MHz
— PLL: 1.8 to 3.6 V
— CPU and ADC: 1.6 to 3.6 V
• Input sensitivity:
• Optional function switches:
FM band: 35 mVrms (50 mVrms at 130 MHz or higher
frequency)
— PH0 to PH3 (open-drain output/general-purpose
input and output/S13 to S16)
AM band: 35 mVrms
• IF counting: Using the HCTR input pin for 0.4 to
12 MHz signals
• External reset input: During CPU and PLL operations,
instruction execution is started from
location 0.
— PG0 to PG3 (open-drain output/general-purpose
input and output/S17 to S20)
— PI0 to PI3 (open-drain output/general-purpose input
and output/S21 to S24)
— PJ0 to PJ3 (open-drain output/general-purpose input
and output/S25 to S28)
• Built-in power-on reset circuit:
The CPU starts execution from location 0 when power is
first applied.
— VSENSE circuit (provided/not provided)
— FM DC/DC clock (1/256, 75 kHz)
• Package: SQFP-80 (0.5-mm pitch)
• Halt mode: The controller-operating clock is stopped.
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0 V
SS
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
–0.3 to +4.0
–0.3 to VDD +0.3
–0.3 to +15
–0.3 to VDD + 0.3
0 to 3
Unit
V
VDD max
VDD
Input voltage
VIN
All input pins
AOUT, PE
V
V
OUT(1)
OUT(2)
V
Output voltage
V
All output pins except VOUT(1)
PC, PD, PG, PH, PI, PJ, PK, PL, EO
PB
V
IOUT(1)
IOUT(2)
IOUT(3)
IOUT(4)
IOUT(5)
mA
mA
mA
µA
mA
mW
°C
°C
0 to 1
Output current
AOUT, PE
0 to 2
S1 to S28
300
COM1 to COM4
3
Allowable power dissipation
Operating temperature
Storage temperature
Pdmax
Topr
Ta = –20 to +70°C
300
–20 to +70
–45 to +125
Tstg
No. 7022-2/14
LC72317, 72318, 72319
Allowable Operating Ranges at Ta = –20 to +70°C, V = 1.8 to 3.6 V
DD
Ratings
typ
Parameter
Symbol
Conditions
PLL operating voltage
Unit
V
min
1.8
max
3.6
VDD(1)
VDD(2)
VDD(3)
VDD(4)
3.0
Memory retention voltage
CPU operating voltage
1.0
1.4
1.6
Supply voltage
3.0
3.0
3.6
3.6
A/D converter operating voltage
Input ports other than VIH(2), VIH(3), AMIN,
FMIN, HCTR, and XIN
VIH(1)
VIH(2)
0.7 VDD
VDD
V
Input high-level voltage
Input low-level voltage
BRES port
Port PF
0.8 VDD
0.6 VDD
VDD
VDD
V
V
V
IH(3)
Input ports other than VIL(2), VIL(3), AMIN,
FMIN, HCTR, and XIN
VIL(1)
VIL(2)
0
0.3 VDD
V
BRES port
0
0
0.2 VDD
0.2 VDD
0.6
V
V
IL(3)
Port PF
V
VIN(1)
XIN
0.5
0.035
0.05
0.035
0
Vrms
Vrms
Vrms
Vrms
V
VIN(2)
VIN(3)
VIN(4)
VIN(5)
FIN(1)
FIN(2)
FIN(3)
FIN(4)
FIN(5)
FIN(6)
FMIN, AMIN
0.35
0.35
0.35
VDD
80
Input amplitude
FMIN
HCTR
Input voltage range
ADIO, ADI1, ADI3
XIN: CI ≤ 35 kΩ
FMIN: VIN(2), VDD(1)
FMIN: VIN(3), VDD(1)
AMIN(H): VIN(3), VDD(1)
AMIN(L): VIN(3), VDD(1)
HCTR: VIN(3), VDD(1)
70
75
kHz
MHz
MHz
MHz
MHz
MHz
10
130
250
40
130
2
Input frequency
0.5
0.4
10
12
Electrical Characteristics within the allowable operating ranges
Ratings
typ
Parameter
Symbol
Conditions
XIN: VI = VDD = 3.0 V
Unit
min
3
max
3
I
IH(1)
IH(2)
µA
µA
I
FMIN, AMIN, HCTR: VI = VDD = 3.0 V
8
20
Input high-level current
PA/PF (without pull-down resistors), the PC,
PD, PG, PH, PI, PJ, PK, and PL ports,
and BRES: VI = VDD = 3.0 V
IIH(3)
IIL(1)
3
µA
XIN: VDD(1) = VSS
–3
µA
µA
I
IL(2)
FMIN, AMIN, HCTR: VI = VDD = VSS
–3
–8
–20
Input low-level current
PA/PF (without pull-down resistors), the PC,
PD, PG, PH, PI, PJ, PK, and PL ports,
and BRES: VI = VDD = VSS
IIL(3)
VIF
–3
µA
Input floating voltage
Pull-down resistor values
Hysteresis
PA/PF (with pull-down resistors)
PA/PF (with pull-down resistors), VDD = 3.0 V
TEST1, TEST2 (with pull-down resistors)
BRES
0.05 VDD
200
V
kΩ
kΩ
V
R
PD(1)
PD(2)
VH
75
100
10
R
0.1 VDD
1.3
0.2 VDD
Referenced to VDD, C(3) = 0.47 µF,
DBR4
DBR1, 2, 3
VOH(1)
1.5
3.0
1.7
3.3
V
Voltage doubler reference voltage
1
Ta = 25°C *
C(1) = 0.47 µF
C(2) = 0.47 µF, without loading, Ta = 25°C *
Voltage doubler step-up voltage
2.7
V
V
1
VDD
0.7 VDD
VDD
0.3 VDD
VDD
0.3 VDD
VDD
–
VDD
–
PB: IO = –1 mA
0.3 VDD
–
VOH(2)
PC, PD, PG, PH, PI, PJ, PK, PL: IO = –1 mA
EO: IO = –500 µA
V
V
–
VOH(3)
Output high-level voltage
–
VOH(4)
VOH(5)
VOH(6)
XOUT: IO = –1 µA
V
V
V
0.3 VDD
1
S1 to S28: IO = –20 µA *
2.0
COM1, COM2, COM3, COM4:
1
2.0
I
O = –100 µA *
Continued on next page.
No. 7022-3/14
LC72317, 72318, 72319
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
VOL(1)
VOL(2)
VOL(3)
VOL(4)
VOL(5)
PB: IO = –1 mA
0.3 VDD
0.7 VDD
0.3 VDD
0.3 VDD
0.3 VDD
1.0
V
V
V
V
V
PC, PD, PG, PH, PI, PJ, PK, PL: IO = –1 mA
EO: IO = –500 µA
XOUT: IO = –1 µA
1
Output low-level voltage
S1 to S28: IO = –20 µA *
COM1, COM2, COM3, COM4:
1
VOL(6)
VOL(7)
1.0
V
IO = –100 µA *
PE: IO = 2 mA
1.0
0.5
V
V
V
OL(8)
AOUT, TU: IO = 1 mA, AIN = 1.3 V (AOUT), VDD = 3 V
Ports PB, PC, PD, PG, PH, PI, PJ, PK, PL, and EO
AOUT, TU and port PE
I
OFF(1)
OFF(2)
–3
–100
–1/2
1.6
+3
µA
nA
LSB
V
Output off leakage current
I
+100
+1/2
1.9
A/D converter error
ADI0, ADI1, ADI3
2
Supply voltage drop detection voltage
V
V
SENSE(1)
SENSE(2)
Ta = 25°C *
1.75
(1)min
+0.1
(1)max
+0.2
2
V
Supply voltage rise detection voltage
Ta = 25°C *
I
DD(1)
DD(2)
VDD(1): FIN(2) 130 MHz, Ta = 25°C
5
15
mA
mA
3
I
VDD(1): In HALT mode, Ta = 25°C *
0.1
VDD = 3.6 V, with the oscillator stopped,
Current drain
IDD(3)
IDD(4)
0.1
1
mA
µA
4
Ta = 25°C *
VDD = 1.8 V, with the oscillator stopped,
4
Ta = 25°C *
Note: The halt mode current is due to the CPU executing 20 instruction steps every 125 ms.
Pin Assignment
40 S20/PG3
39 S21/PI0
38 S22/PI1
37 S23/PI2
36 S24/PI3
35 S25/PJ0
34 S26/PJ1
33 S27/PJ2
32 S28/PJ3
31 VSS
I / O
I / O
I / O
I / O
COM3 61
COM2 62
COM1 63
DBR4 64
DBR3 65
DBR2 66
DBR1 67
BRES 68
TU 69
I / O
I / O
HCTR 70
VDD 71
FMIN 72
AMIN 73
VSS 74
30 ADI0/ PF0
29 ADI1/PF1
28 ADI3/PF2
27 BEEP/PE0
26 PE1
I
O (OD)
EO 75
25 PK0
AIN 76
24 SCK1/PK1
23 SO1/PK2
22 SI1/PK3
21 INT0/PD0
AOUT 77
AGND 78
TEST1 79
XIN 80
I / O
I
O
I
I / O
I / O
I / O
No. 7022-4/14
LC72317, 72318, 72319
Note: * C(1), C(2), and C(3) must be connected even if an LCD is not used.
DBR1
0.1 to 1 µF
DBR2
C(C1)
DBR3
DBR4
0.1 to 1 µF
0.1 to 1 µF
C(C2)
C(C3)
Notes: *1. The capacitors C(1), C(2), and C(3) must be connected to the DBR pins.
*2. V
SENSE
When the V
voltage drops, the V
flag is set when that voltage is 1.75 V (typical). Applications can
SENSE
DD
check the V
flag using the TST instruction. Battery or other power source depletion can be easily
SENSE
measured by monitoring this flag.
Note that the voltage for V
detection differs for the falling and rising directions. Thus, after the V
SENSE
SENSE
flag has been set due to a voltage drop, it will not be reset if the voltage rises by under 0.1 V.
V
DD
V
DD
2.1 V
1.7 V
1.9 V
1.6 V
RESET←
→
SET
SET←
→RESET
t
t
V
(1)
SENSE
V
(2)
SENSE
For a rising voltage
For a falling voltage
*3. Halt mode current measurement circuit
*4. Backup mode current measurement circuit
7 pF
7pF
7 pF
7pF
A
A
75 kHz
XOUT VDD RES
75 kHz
XOUT VDD RES
DBR1
DBR1
0.1 µF
0.1 µF
XIN
XIN
DBR2
DBR3
DBR2
DBR3
0.1 µF
0.1 µF
0.1 µF
0.1 µF
DBR4
VSS
DBR4
VSS
FMIN
AMIN
HCTR
TEST1, 2
FMIN
AMIN
HCTR
TEST1, 2
PA, PF, PL
AGND
AIN
AGND
AIN
With all ports other than those specified above left open.
With output mode selected for PC and PD.
With segments S13 to S28 selected.
With all ports other than those specified above left open.
With output mode selected for PC and PD.
With segments S13 to S28 selected.
No. 7022-5/14
LC72317, 72318, 72319
Block Diagram
XIN
PHASE
DETECTOR
DIVIDER
REFERENCE DIVIDER
PROGRAMMBLE DIVIDER
EO
TU
SYSTEM CLOCK
GENERATOR
XOUT
FMIN
75kHz
1/2
1/16,1/17
FM LOCAL 1/256
AM LOCAL 1/2
1/2
AMIN
S1
PLL CONTROL
PLL DATA LATCH
LCDA/B
VDD
VSS
V
SENSE
COUNT
TIME BASE
CONTROL
LCD
PORT
DRIVER
END
SEG
LA
4
7
122
UNIVERSAL
HCTR
RES
1/2
LCPA/B
COUNTER (20bits)
*
S12
P-ON
RESET
RAM
TEST1
TEST2
S13/PH0
S14/PH1
S15/PH2
S16/PH3
ADDRESS
DATA
LATCH
/
DECODER
256×4bits(LC72317)
×
256 4bits(LC72318)
BUS
512×4bits(LC72319)
PA0
PA1
PA2
PA3
BANK
DRIVER
BUS
DRIVER
S17/PG0
S18/PG1
S19/PG2
S20/PG3
DATA
LATCH
/
ROM
BUS
CONTROL
BUS
12k × 16bits
(LC72317)
16k × 16bits
(LC72318)
16k × 16bits
(LC72319)
DRIVER
PB0
PB1
PB2
PB3
*
DATA
LATCH
S21/PI0
S22/PI1
S23/PI2
S24/PI3
DATA
LATCH
/
/
BUS
DRIVER
INSTRUCTION
DECODER
BUS
DRIVER
PC0
PC1
PC2
PC3
DATA
LATCH
/
S25/PJ0
S26/PJ1
S27/PJ2
S28/PJ3
DATA
LATCH
/
ADDRESS DECODER
14
SKIP
BUS
JMP
CAL
RETURN
INTERRUPT
RESET
DRIVER
BUS
DRIVER
ADDRESS COUNTER
INT0/PD0
INT1/PD1
PD2
DATA
LATCH
/
DBR1
DBR2
DBR3
DBR4
DOUBLER
CIRCUIT
14
BUS
STACK
BANK CF
DRIVER
PD3
PK0
SCK1/PK1
SO1/PK2
SI1/PK3
DATA
LATCH
/
COM4
COM3
COM2
COM1
COMMON
DRIVER
JUDGE
LATCH
A
BUS
DRIVER
ALU
BEEP TONE
DATA
LATCH
B
PE0/BEEP
PE1
MPX
LATCH
/
BUS
DRIVER
TIMER 0
AIN
AOUT
AGND
MPX
MPX
(5bits)
DATA
PF0/ADI0
PF1/ADI1
PF2/ADI3
LATCH
/
BUS
DRIVER
DATA BUS
No. 7022-6/14
LC72317, 72318, 72319
Pin Functions
Pin No.
Pin
I/O
Function
I/O circuit
80
1
XIN
I
75 kHz oscillator connections
XOUT
O
79
2
TEST1
TEST2
I
I
IC testing. These pins must be connected to ground during normal operation.
—
Input with built-in
pull-down resistor
6
5
4
3
PA0
PA1
PA2
PA3
Special-purpose key return signal input ports designed with a low threshold voltage.
When used in conjunction with port PB to form a key matrix, up to 3 simultaneous key
presses can be detected. The four pull-down resistors are selected together in a
single operation using the IOS instruction; they cannot be specified individually. Input
is disabled in backup mode, and the pull-down resistors are disabled after a reset.
I
Unbalanced CMOS push-
pull/n-channel open-drain
General-purpose CMOS and n-channel open-drain output shared-function ports.
The IOS instruction (Pwn = 2) is used for function switching.
(b0: PB0, b2: PB1, b3: PB2, PB3) (0: general-purpose CMOS, 1: n-channel open-
drain)
10
9
PB0
PB1
PB2
PB3
Special-purpose key source signal output ports. Since unbalanced CMOS output
transistor circuits are used, diodes to prevent short-circuits when multiple keys are
pressed are not required. These ports go to the output high-impedance state in
backup mode. These ports go to the output high-impedance state after a reset and
remain in that state until an output instruction (OUT, SPB, or RPB) is executed.
O
8
7
*: Verify the output impedance conditions carefully if these pins are used for functions
other than key source outputs.
CMOS push-pull
14
13
12
11
PC0
PC1
PC2
PC3
General-purpose I/O ports.
PD0 and PD1 can be used as an external interrupt port. Input or output mode can be
set individually using the IOS instruction by the bit . A value of 0 specifies input, and 1
specifies output. These ports go to the input disabled high-impedance state in backup
mode. They are set to function as general-purpose input ports after a reset.
I/O
21
20
19
18
17
INT0/PD0
INT1/PD1
PD2
PD3
PL0
2
*
N-channel open-drain
General-purpose output ports with shared beep tone output function (pin 27 only).
The BEEP instruction is used to switch pin 27 between the general-purpose output
port and beep tone output functions. To use pin 27 as a general-purpose output port,
execute a BEEP instruction with b2 set to 0. Set b2 to 1 to use pin 27 as the beep
tone output port. The b0 and b1 bits are used to select the beep tone frequency.
There are two beep tone frequencies supported.
*: When pin 27 is set up as the beep tone output, executing an output instruction to
pin 27 only changes the state of the internal output latch, it does not affect the beep
tone output in any way. Only pin 27 can be switched between the general-purpose
output function and the beep tone output function; the PE1 pin only functions as a
general-purpose output. These pins go to the high-impedance state in backup
mode and remain in that state until an output instruction or a BEEP instruction is
executed. Since these ports are open-drain ports, resistors must be inserted
between these pins and VDD. These ports are set to general-purpose output port
function after a reset.
27
26
BEEP/PE0
PE1
O
Continued on next page.
No. 7022-7/14
LC72317, 72318, 72319
Continued from preceding page.
Pin No.
Pin
I/O
Function
I/O circuit
CMOS input
CMOS push-pull
General-purpose input ports, general-purpose I/O ports, and serial I/O port.
I/O
I/O
I/O
I/O
PK0
25
24
23
22
The general-purpose I/O port is switched using the IOS instruction; the direction (input
or output) is set in a 1-bit unit. Switching between the general-purpose input port and
the serial I/O port function is also performed with the IOS instruction.
SCK1/PK1
SO1/PK2
SI1/PK3
In backup mode, these ports go to the input disabled high-impedance state.
After a reset, these pins are set to function as general-purpose input ports.
CMOS input/analog input
General-purpose input and A/D converter input shared function ports. The IOS
instruction is used to switch between the general-purpose input and A/D converter
port functions. The general-purpose input and A/D converter port functions can be
switched by the bit, with 0 specifying general-purpose input, and 1 specifying the A/D
converter input function. To select the A/D converter function, set up the A/D
converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started
with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion
completes. The INR instruction is used to read in the data.
30
29
28
PF0/ADI0
PF1/ADI1
PF2/ADI3
I
*: If an input instruction is executed for one of these pins which is set up for analog
input, the read in data will be at the low level since CMOS input is disabled. In
backup mode these pins go to the input disabled high-impedance state. These
ports are set to their general-purpose input port function after a reset. The A/D
converter is a 5-bit successive approximation type converter, and features a
conversion time of 1.28 ms. Note that the full-scale A/D converter voltage (1FH) is
(63/96) 3 V.
CMOS push-pull
Shared function ports that function either as LCD driver segment outputs or general-
purpose I/O ports.
The IOS instruction is used to switch between the segment output and the general-
purpose I/O port functions. It is also used to switch the direction of pins functioning as
general-purpose I/O ports.
•
When used as segment output ports
32
33
34
35
PJ3/S28
PJ2/S27
PJ1/S26
PJ0/S25
The IOS (Pwn=8) instruction is used to set the following 4 pins to function as
segment output ports.
b0 to b3 correspond to S17 to S20/PG0 to PG3
(0: Segment output, 1: PG0 to PG3)
The IOS (Pwn=9) instruction is used to set the following 4 pins to function as
segment output ports.
36
37
38
39
PI3/S24
PI2/S23
PI1/S22
PI0/S21
b0 to b3 correspond to S13 to S16/PH0 to PH3
(0: Segment output, 1: PH0 to PH3)
The IOS (Pwn=D) instruction is used to set the following 4 pins to function as
segment output ports.
b0 to b3 correspond to S21 to S24/PI0 to PI3
(0: Segment output, 1: PG0 to PG3)
The IOS (Pwn=E) instruction is used to set the following 4 pins to function as
segment output ports.
O
40
41
42
43
PG3/S20
PG2/S19
PG1/S18
PG0/S17
b0 to b3 correspond to S25 to S28/PJ0 to PJ3
(0: Segment output, 1: PH0 to PH3)
When used as general-purpose I/O ports
•
The IOS instruction is used to switch the I/O direction. The directions of these
pins can be set individually in 1-bit units.
44
45
46
47
PH3/S16
PH2/S15
PH1/S14
PH0/S13
*2
b0 = PG0
b1 = PG1
b2 = PG2
b3 = PG3
b0 = PH0
b1 = PH1
b2 = PH2
b3 = PH3
b0 = PI0
b1 = PI1
b2 = PI2
b3 = PI3
b0 = PJ0
b1 = PJ1
b2 = PJ2
b3 = PJ3
0: Input
1: Output
In backup mode, if used as general-purpose I/O ports, they will be in the input
disabled high-impedance state. If used as segment outputs, they will be held fixed at
the low level.
After a reset, these pins function as segment output ports.
Although the general-purpose port/LCD port setting is a mask option, the setup with
the IOS instruction described above is also necessary.
Continued on next page.
No. 7022-8/14
LC72317, 72318, 72319
Continued from preceding page.
Pin No.
Pin
I/O
Function
I/O circuit
CMOS input
16
15
PL1
PL2
General-purpose input ports
I
In backup mode, these ports go to the input disabled high-impedance state.
CMOS push-pull
LCD driver segment output pins.
A 1/4-duty 1/2-bias drive technique is used.
The frame frequency is 75 Hz.
48 to
59
S12 to S1
O
In backup mode, the outputs are fixed at the low level.
After a reset, the outputs are fixed at the low level.
LCD driver common output pins.
60
61
62
63
COM4
COM3
COM2
COM1
A 1/4-duty 1/2-bias drive technique is used.
The frame frequency is 75 Hz.
O
In backup mode, the outputs are fixed at the low level.
After a reset, the outputs are fixed at the low level.
64
65
66
67
DBR4
DBR3
DBR2
DBR1
I
I
LCD power supply step-up voltage inputs.
System reset input.
In CPU operating mode or halt mode, applications must apply a low level for at least
one full machine cycle to reset the system and restart execution with the PC set to
location 0. This pin is connected in parallel with the internal power on reset circuit.
68
RES
N-channel open-drain
Tuning voltage generation circuit outputs.
69
TU
O
These pins include a transistor, and a tuning voltage (12 to 17 V) can be generated by
connecting external coil, diode, and capacitor components.
CMOS amplifier input
FM VCO (local oscillator) input.
This pin is selected with the PLL instruction CW1.
The input must be capacitor coupled.
72
FMIN
I
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
CMOS amplifier input
AM VCO (local oscillator) input.
This pin and the bandwidth are selected with the PLL instruction CW1.
CW1 b1, b0
Bandwidth
73
AMIN
I
1
1
0.5 to 10 MHz (MW, LW)
The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
Continued on next page.
No. 7022-9/14
LC72317, 72318, 72319
Continued from preceding page.
Pin No.
Pin
I/O
Function
I/O circuit
Special-purpose universal counter input port
•
To measure a frequency, set up HCTR frequency measurement mode and the
measurement time with a UCS instruction (b3=0, b2=0) and start the count with a
UCC instruction.
CMOS amplifier input
UCS b1 b0 Measurement time
Measurement
UCS b3 b2 Input pin mode
0
0
1 ms
70
HCTR
I
Frequency
measurement
0
0
HCTR
0
1
4 ms
0
1
1
0
–
–
1
1
0
1
8 ms
32 ms
The CNTEND flag is set when the count completes. Since the input circuit functions
as an AC amplifier in this mode, the input must be capacitance coupled.
This pin goes to the input disabled state in backup mode, halt mode, PLL stop mode,
and after a reset.
76
77
78
AIN
I
Connections for the built-in transistor used to form a low-pass filter.
AGND is connected to ground.
AOUT
AGND
O
–
CMOS push-pull
Main charge pump output. When the local oscillator frequency divided by N is higher
than the reference frequency a high level is output, when lower, a low level is output.
The pin is set to the high-impedance state when the frequencies match.
75
EO
O
Output goes to the high-impedance state in backup mode, in halt mode, after a reset,
and in PLL stop mode.
VSS
VSS
VDD
Power supply pin. This pin must be connected to ground.
This pin must be connected to ground.
74
31
71
—
—
This pin must be connected to VDD
.
Note 2: When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set
up output mode with an IOS instruction.
No. 7022-10/14
LC72317, 72318, 72319
LC72317, 72318 and 72319 Series Instruction Set
Terminology
ADDR
b
: Program memory address
: Borrow
C
: Carry
DH
DL
I
: Data memory address High (Row address) [2 bits]
: Data memory address Low (Column address) [4 bits]
: Immediate data [4 bits]
M
: Data memory address
N
: Bit position [4 bits]
Rn
Pn
: Resister number [4 bits]
: Port number [4 bits]
PW
r
( ), [ ]
: Port control word number [4 bits]
: General register (One of the addresses from 00H to 0FH of BANK0)
: Contents of register or memory
M (DH, DL) : Data memory specified by DH, DL
Operand
1st 2nd
Instruction format
Instruc-
tions
Mnemonic
Function
Operations function
f
e
1
1
1
d
0
0
0
c
0
0
0
b
0
0
1
a
0
1
0
9
8
7
6
5
4
3
2
1
0
AD
ADS
AC
r
M
Add M to r
r ← (r) + (M)
0
0
0
DH
DL
r
r
r
r
r
M
M
Add M to r, then skip if carry
Add M to r with carry
r ← (r) + (M), skip if carry
r ← (r) + (M) + C
DH
DH
DL
DL
Add M to r with carry,
then skip if carry
r ← (r) + (M) + C
skip if carry
ACS
r
M
0
1
0
0
1
1
DH
DL
r
AI
M
M
M
I
I
I
Add I to M
M ← (M) + I
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
0
1
0
DH
DH
DH
DL
DL
DL
I
I
I
AIS
AIC
Add I to M, then skip if carry
Add I to M with carry
M ← (M) + I, skip if carry
M ← (M) + I + C
Add I to M with carry,
then skip if carry
M ← (M) + I + C,
skip if carry
AICS
SU
M
r
I
M
M
M
M
I
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
DH
DH
DH
DH
DH
DH
DH
DH
DH
DL
DL
DL
DL
DL
DL
DL
DL
DL
I
r
r
r
r
I
Subtract M from r
r ← (r) – (M)
Subtract M from r,
then skip if borrow
r ← (r) – (M),
skip if borrow
SUS
SB
r
r
Subtract M from r with borrow
r ← (r) – (M) – b
Subtract M from r with borrow,
then skip if borrow
r ← (r) – (M) – b,
skip if borrow
SBS
SI
r
M
M
M
M
Subtract I from M
M ← (M) – I
Subtract I from M,
then skip if borrow
M ← (M) – I,
skip if borrow
SIS
SIB
SIBS
I
I
I
Subtract I from M with borrow
M ← (M) – I – b
I
Subtract I from M with borrow,
then skip if borrow
M ← (M) – I – b,
skip if borrow
I
I
Continued on next page.
No. 7022-11/14
LC72317, 72318, 72319
Continued from preceding page.
Operand
Instruction format
7
Instruc-
Mnemonic
tions
Function
Operations function
1st
r
2nd
f
e
0
0
0
d
0
0
0
c
1
1
0
b
0
1
0
a
0
0
1
9
8
6
5
4
3
2
1
0
SEQ
SEQI
SNEI
M
I
Skip if r equal to M
Skip if M equal to I
Skip if M not equal to I
(r) – (M), skip if zero
(M) – I, skip if zero
(M) – I, skip if not zero
0
0
0
DH
DL
r
I
I
M
M
DH
DH
DL
DL
I
Skip if r is greater than or
equal to M
(r) – (M),
skip if not borrow
SGE
r
M
I
0
0
0
0
0
0
1
1
1
1
0
1
DH
DH
DL
DL
r
I
Skip if M is greater than
equal to I
SGEI
M
(M) – I, skip if not borrow
SLEI
AND
ANDI
OR
M
r
I
M
I
Skip if M is less than I
AND M with r
(M) – I, skip if borrow
r ← (r) AND (M)
M ← (M) AND I
r ← (r) OR (M)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
0
0
DH
DH
DH
DH
DH
DH
DH
DL
DL
DL
DL
DL
DL
DL
I
r
I
M
r
AND I with M
M
I
OR M with r
r
I
ORI
M
r
OR I with M
M ← (M) OR I
EXL
EXLI
M
I
Exclusive OR M with r
Exclusive OR M with M
r ← (r) XOR (M)
M ← (M) XOR I
r
I
M
carry
(r)
SHR
r
Shift r right with carry
0
0
0
0
0
0
0
0
1
1
1
0
r
LD
ST
r
M
r
Load M to r
Store r to M
r ← (M)
M ← (r)
1
1
1
1
0
0
1
1
0
0
0
1
DH
DH
DL
DL
r
r
M
Move M to destination M
referring to r in the same row
MVRD
MVRS
r
M
r
[DH, Rn] ← (M)
M ← [DH, Rn]
1
1
1
1
0
0
1
1
1
1
0
1
DH
DH
DL
DL
r
r
Move source M referring to r
to M in the same row
M
MVSR
MVI
M1
M
M2 Move M to M in the same row
[DH, DL1] ← [DH, DL2]
M ← I
1
1
1
1
1
1
0
0
0
0
0
1
DH
DH
DL1
DL
DL2
I
I
Move I to M
Test M bits, then skip if all bits
specified are true
TMT
M
M
N
if M (N) = all 1s, then skip
1
1
1
1
1
0
0
0
1
DH
DH
DL
DL
N
N
Test M bits, then skip if all bits
specified are false
TMF
JMP
CAL
RT
N
if M (N) = all 0s, then skip
1
1
1
0
1
0
0
0
1
0
1
0
ADDR
ADDR
Jump to the address
PC ← ADDR
ADDR (13 bits)
ADDR (13 bits)
PC ← ADDR
Stack ← (PC) + 1
Call subroutine
Return from subroutine
PC ← Stack
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
PC ← Stack,
BANK ← Stack,
CARRY ← Stack
RTI
Return from interrupt
0
0
0
0
Continued on next page.
No. 7022-12/14
LC72317, 72318, 72319
Continued from preceding page.
Operand
Instruction format
Instruc-
tions
Mnemonic
Function
Operations function
1st
2nd
f
e
1
d
1
c
b
a
1
9
1
8
1
7
6
5
4
3
2
1
0
1
1
0
1
0
SS
RS
SWR
N
N
Set status register
(Status W-reg) N ← 1
(Status W-reg) N ← 0
SWR
SWR
N
N
1
0
1
1
1
1
1
1
1
1
SWR
Reset status register
TST
TSF
SRR
SRR
N
N
Test status register true
Test status register false
if (Status R-reg) N = all
if (Status R-reg) N = all
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
SRR
N
N
SRR
if Unlock F/F (N) = all 0s,
then skip
TUL
N
Test Unlock F/F
0
0
0
0
0
0
0
0
1
1
0
1
N
PLL
SIO
M
I1
I
Load M to PLL register
PLL reg ← PLL data
SIO reg ← I1, I2
UCCW1 ← I
1
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
DH
0
DL
I1
r
I2
I
0
1
UCS
UCC
BEEP
DZC
TMS
IOS
Set I to UCCW1
Set I to UCCW2
Beep control
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
0
I
UCCW2 ← I
0
I
I
BEEP reg ← I
DZC reg ← I
0
I
I
Dead zone control
Set timer register
Set port control word
0
I
I
Timer reg ← I
IOS reg PWn ← N
M ← (Pn)
0
I
PWn
M
N
0
PWn
DL
N
IN
Pn Input port data to M
DH
DH
DH
Pn
Pn
Pn
N
OUT
INR
M
Pn Output contents of M to port
Pn Input port data to M
P1n ← M
M ← (Pn)
(Pn)N ← 1
(Pn)N ← 0
DL
M
DL
SPB
RPB
P1n
P1n
N
N
Set port1 bits
1
0
1
Pn
Reset port1 bits
1
Pn
N
Test port1 bits, then skip if all bits
specified are true
TPT
TPF
P1n
P1n
N
N
if (Pn)N = all 1s, then skip
if (Pn)N = all 0s, then skip
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
Pn
Pn
N
N
Test port1 bits, then skip if all bits
specified are false
0
0
BANK
I
Select Bank
BANK ← I
0
0
0
0
0
0
0
0
1
1
1
I
LCDA
LCDB
LCPA
LCPB
M
M
M
M
I
I
I
I
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
DH
DL
DIGIT
DIGIT
DIGIT
DIGIT
Output segment pattern to LCD
digit direct
LCD (DIGIT) ← M
DH
DH
DH
DL
DL
DL
Output segment pattern to LCD
digit through LA
LCD (DIGIT) ← LA ← M
HALT reg ← I,
then CPU clock stop
HALT
I
Halt mode control
0
0
0
0
0
0
0
0
0
1
0
0
I
CKSTP
NOP
Clock stop
Stop x’tal OSC
No operation
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
No operation
No. 7022-13/14
LC72317, 72318, 72319
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of June, 2001. Specifications and information herein are subject to
change without notice.
PS No. 7022-14/14
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