MT7620N [ETC]
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip;
| 型号： | MT7620N |
| 厂家： | 
ETC |
| 描述： | Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip |
| 文件： | 总54页 (文件大小：1971K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT7620
DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
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MT7620 DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Overview
The MT7620 router-on-a-chip includes an 802.11n MAC and baseband, a 2.4 GHz
radio and FEM, a 580 MHz MIPS® 24K™ CPU core, a 5-port 10/100 switch and two
RGMII. The MT7620 includes everything needed to build an AP router from a
single chip. The embedded high performance CPU can process advanced
applications effortlessly, such as routing, security and VoIP. The MT7620 also
includes a selection of interfaces to support a variety of applications, such as a
USB port for accessing external storage.
Applications:
. Routers
. NAS devices
. iNICs
. Dual band
concurrent routers
Features
. Embedded MIPS24KEc (580 MHz) with 64 KB I-
Cache and 32 KB D-Cache
. An optimized PMU
. Green AP
. 2T2R 2.4 GHz with 300 Mbps PHY data rate
. Legacy 802.11b/g and HT 802.11n modes
. 20/40 MHz channel bandwidth
. Legacy 802.11b/g and HT 802.11n modes
. Reverse Data Grant (RDG)
. Maximal Ratio Combining (MRC)
. Space Time Block Coding (STBC)
. 16-bit SDRAM up to 64 Mbytes
. 16-bit DDR1/2 up to 128/256 Mbytes (MT7620A)
. SPI, NAND Flash/SD-XC
Intelligent Clock Scaling (exclusive)
DDRII: ODT off, Self-refresh mode
SDRAM: Pre-charge power down
. I2C, I2S, SPI, PCM, UART, JTAG, MDC, MDIO, GPIO
. Hardware NAT with IPv6 and 2 Gbps wired speed
. 16 Multiple BSSID
. WEP64/128, TKIP, AES, WPA, WPA2, WAPI
. QoS: WMM, WMM-PS
. WPS: PBC, PIN
. Voice Enterprise: 802.11k+r
. AP Firmware: Linux 2.6 SDK, eCOS with IPv6
. RGMII iNIC Driver: Linux 2.4/2.6
. 1x USB 2.0, 1x PCIe host/device
. 5-port 10/100 SW and two RGMII
Functional Block Diagram
16-Bit SDR/DDR1/DDR2
EJTAG
To CPU
interrupts
INTC
DRAM
Controller
MIPS 24KEc
64 KB I-Cache
32 KB D-Cache
(580 MHz)
Timer
OCP_IF
OCP Bridge
Arbiter
SPI
NFC
SPI
NAND
RBUS (SYS_CLK)
PBUS
UART
GPIO
I2C
UART
GPIO
/LED
I2C
PCIe 1.1
PHY
WLAN
11n 2x2
Switch
(4FE + 2GE)
Single Port
USB 2.0 PHY
SDHC
GDMA
RGMII
I2S
I2S
5-Port EPHY
RJ45 x5 TMII/MII x2
PCIe x1
SD
Host/Device
PCM x4
PCM
2.4 GHz
Ordering Information
Ralink Technology Corp. (USA)
Suite 200
20833 Stevens Creek Blvd.
Cupertino CA95014, U.S.A
Tel: 408-725-8070
Ralink Technology Corp. (Taiwan)
5F, 5 Taiyuan 1st St
Jhubei City, Hsinchu
Taiwan, R.O.C
Tel: 886-3-560-0868
Fax: 886-3-560
Part
Package
Number (Green/RoHS Compliant)
MT7620A TFBGA 265 ball
(11 mm x 11 mm)
MT7620N DR-QFN 148 pin
(12 mm x 12 mm)
Fax: 408-725-8069
www.ralinktech.com
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Table of Contents
1. MAIN FEATURES
2. PINS
6
7
2.1 TFBGA (11 MM X 11 MM) 265 BALL PACKAGE DIAGRAM
2.1.1 DDR2 BALL MAP
7
7
2.2 DR-QFN (12 MM X 12 MM) 148-PIN PACKAGE DIAGRAM
2.2.1 LEFT SIDE VIEW
8
8
2.2.2 RIGHT SIDE VIEW
9
2.3 PIN DESCRIPTIONS (TFBGA)
2.4 PIN DESCRIPTIONS (DRQFN)
2.5 PIN SHARING SCHEMES
11
17
22
2.5.1 GPIO PIN SHARE SCHEME
2.5.2 UARTF PIN SHARE SCHEME
22
24
25
25
25
25
26
26
27
29
30
2.5.3 RGMII PIN SHARE SCHEMES
2.5.4 WDT_RST_MODE PIN SHARE SCHEME
2.5.5 PERST_N PIN SHARE SCHEME
2.5.6 MDC/MDIO PIN SHARE SCHEME:
2.5.7 EPHY_LED PIN SHARE SCHEME
2.5.8 SPI PIN SHARE SCHEME
2.5.9 ND/SD PIN SHARE SCHEME
2.5.10 XMII PHY/MAC PIN MAPPING
2.6 BOOTSTRAPPING PINS DESCRIPTION
3. MAXIMUM RATINGS AND OPERATING CONDITIONS
3.3 ABSOLUTE MAXIMUM RATINGS
3.4 MAXIMUM TEMPERATURES
31
31
31
31
31
32
32
32
33
3.5 OPERATING CONDITIONS
3.6 THERMAL CHARACTERISTICS
3.7 STORAGE CONDITIONS
3.8 EXTERNAL XTAL SPECFICATION
3.9 DC ELECTRICAL CHARACTERISTICS
3.10 AC ELECTRICAL CHARACTERISTICS
3.10.1 SDRAM INTERFACE
3.10.2 DDR2 SDRAM INTERFACE
3.10.3 RGMII INTERFACE
33
34
36
37
38
39
40
41
42
43
3.10.4 MII INTERFACE (25 MHZ)
3.10.5 RVMII INTERFACE (PHY MODE MII TIMING) (25 MHZ)
3.10.6 SPI INTERFACE
3.10.7 I2S INTERFACE
3.10.8 PCM INTERFACE
3.10.9 POWER ON SEQUENCE
3.11 PACKAGE PHYSICAL DIMENSIONS
3.11.1 TFBGA (11 MM X 11 MM) 265 BALLS
3.11.2 DR-QFN (12 MM X 12 MM) 148LD
3.11.3 MT7620 N/A MARKING
43
45
48
49
3.11.4 REFLOW PROFILE GUIDELINE
4. ABBREVIATIONS
50
53
5. REVISION HISTORY
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Table of Figures
FIGURE 2-1 DR-QFN PIN DIAGRAM (LEFT VIEW).............................................................................................................. 9
FIGURE 2-2 DR-QFN PIN DIAGRAM (RIGHT SIDE VIEW) ................................................................................................... 10
FIGURE 2-3 MII MII PHY ..................................................................................................................................... 29
FIGURE 2-4 RVMII MII MAC ................................................................................................................................ 29
FIGURE 2-5 RGMII RGMII PHY............................................................................................................................. 29
FIGURE 2-6 RGMII RGMII MAC ........................................................................................................................... 29
FIGURE 3-1 SDRAM INTERFACE .................................................................................................................................. 33
FIGURE 3-2 DDR2 SDRAM COMMAND ....................................................................................................................... 34
FIGURE 3-3 DDR2 SDRAM WRITE DATA...................................................................................................................... 34
FIGURE 3-4 DDR2 SDRAM READ DATA ....................................................................................................................... 34
FIGURE 3-5 RGMII INTERFACE .................................................................................................................................... 36
FIGURE 3-6 MII INTERFACE......................................................................................................................................... 37
FIGURE 3-7 RVMII INTERFACE..................................................................................................................................... 38
FIGURE 3-8 SPI INTERFACE ......................................................................................................................................... 39
FIGURE 3-9 I2S INTERFACE ......................................................................................................................................... 40
FIGURE 3-10 PCM INTERFACE..................................................................................................................................... 41
FIGURE 3-11 POWER ON SEQUENCE ............................................................................................................................ 42
FIGURE 3-12 TFBGA TOP VIEW .................................................................................................................................. 43
FIGURE 3-13 TFBGA SIDE VIEW.................................................................................................................................. 43
FIGURE 3-14 TFBGA “A” EXPANDED ........................................................................................................................... 43
FIGURE 3-15 TFBGA BOTTOM VIEW............................................................................................................................ 44
FIGURE 3-16 TFBGA “B” EXPANDED ........................................................................................................................... 44
FIGURE 3-17 DR-QFN TOP VIEW................................................................................................................................ 45
FIGURE 3-18 DR-QFN SIDE VIEW ............................................................................................................................... 45
FIGURE 3-19 DR-QFN “B” EXPANDED ......................................................................................................................... 45
FIGURE 3-20 DR-QFN BOTTOM VIEW ......................................................................................................................... 46
FIGURE 3-21 DR-QFN “A” EXPANDED......................................................................................................................... 46
FIGURE 3-22 MT7620N TOP MARKING........................................................................................................................ 48
FIGURE 3-23 MT7620A TOP MARKING ........................................................................................................................ 48
FIGURE 3-24 REFLOW PROFILE FOR MT7620 ................................................................................................................ 49
List of Tables
TABLE 1-1 MAIN FEATURES........................................................................................................................................... 6
TABLE 2-1 DDR2 BALL MAP......................................................................................................................................... 8
TABLE 3-1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 31
TABLE 3-2 MAXIMUM TEMPERATURES.......................................................................................................................... 31
TABLE 3-3 OPERATING CONDITIONS ............................................................................................................................. 31
TABLE 3-4 THERMAL CHARACTERISTICS ......................................................................................................................... 31
TABLE 3-5 EXTERNAL XTAL SPECIFICATIONS.................................................................................................................... 32
TABLE 3-6 DC ELECTRICAL CHARACTERISTICS.................................................................................................................. 32
TABLE 3-7 VDD 2.5V ELECTRICAL CHARACTERISTICS ........................................................................................................ 32
TABLE 3-8 SDRAM INTERFACE DIAGRAM KEY................................................................................................................ 33
TABLE 3-9 DDR2 SDRAM INTERFACE DIAGRAM KEY...................................................................................................... 35
TABLE 3-10 RGMII INTERFACE DIAGRAM KEY................................................................................................................ 36
TABLE 3-11 MII INTERFACE DIAGRAM KEY .................................................................................................................... 37
TABLE 3-12 RVMII INTERFACE DIAGRAM KEY ................................................................................................................ 38
TABLE 3-13 SPI INTERFACE DIAGRAM KEY..................................................................................................................... 39
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
TABLE 3-14 I2S INTERFACE DIAGRAM KEY ..................................................................................................................... 40
TABLE 3-15 PCM INTERFACE DIAGRAM KEY .................................................................................................................. 41
TABLE 3-16 POWER ON SEQUENCE DIAGRAM KEY.......................................................................................................... 42
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MT7620 DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
1. Main Features
The following table covers the main features offered by the MT7620N and MT7620A. Overall, the MT7620N
supports the requirements of an entry-level AP/router, while the more advanced MT7620A supports a number
of interfaces together with a large maximum RAM capacity.
Features
MT7620N
MIPS24KEc (600/580 MHz)
580 x 1.6 DMIPs
64 KB, 32 KB
MT7620A
MIPS24KEc (580 MHz)
580 x 1.6 DMIPs
64 KB, 32 KB
CPU
Total DMIPs
I-Cache, D-Cache
L2 Cache
n/a
n/a
HNAT/HQoS
Memory
HNAT
HNAT 2 Gbps forwarding
DRAM Controller
SDRAM
16 b
16 b
512 Mb, 120 MHz
512 Mb, 193 MHz
512 Mb, 193 MHz
n/a
n/a
DDR1
n/a
DDR2
2 Gb, 193 MHz
NAND
Small page 512Byte (max 512M bit)
Large page 2Kbyte (max 8G bit)
SPI Flash
3B addr mode (max 128Mbit)
4B addr mode (max 512Mbit)
3B addr mode (max 128Mbit)
4B addr mode (max 512Mbit)
SD
n/a
SD-XC (class 10)
RF
2T2R 802.11n 2.4 GHz
2T2R 802.11n 2.4 GHz
PCIe
USB 2.0
Switch
n/a
1
1
1
5p FE SW
5p FE SW + RGMII(1)
4p FE SW + RGMII(2)
I2S
n/a
1
PCM
I2C
n/a
1
1
1
UART
JTAG
Package
1 (Lite)
2 (Lite/Full)
1
1
DRQFN148- 12 mm x 12 mm
TFBGA265- 11 mm x 11 mm
Table 1-1 Main Features
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2. Pins
2.1 TFBGA (11 mm x 11 mm) 265 Ball Package Diagram
2.1.1 DDR2 Ball Map
26
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
RF0 RF0
A _OUT _PA2
APCK
_RFCK
OP
DCDC
_V33
D
RF0_I BG_ XTAL_ XTAL BBPLL
SPI
PCIE
PCIE
UGAT VFB VFB
FB
A
N
EXTR
XI
_XO _V12A _MOSI _RXP _TXN
E
_DDR _DIG
P
_V33N
RF0
_PA1
_V33
A
RF0 RF0_V PLL
APCK
_RFCK
ON
EXT DCDC EXT
_LDO _V33 _LDO B
XTAL
_V12A
SPI_W
P
SP I
PCIE
PCIE
LGAT
E
B
C
_OUT
N
X
_VC
_HOLD _RXN _TXP
_LDO _CAP
_DDR
A
_DIG
UPH
Y0
UPHY UPHY
ADC_
UPHY
0
_VRES
RF1_I
N
PORS SPI_CS
SPI
SPI
PCIE
PCIE
0
0
GND
GND VX_LD
O
COMP
C
T _N
0
_MISO _CS1 _REXT _RFCKP _V12
_PAD _PAD
D
M
P
SOC_I
O
_V33D _N
_0
RF1
_OUT GND
P
RF1_V
X
_LDO
WDT
PCIE APCK
_RFCK _V12
GE2 GE2 GE1 GE1
_RXCL _RXD _RXD _RXCL D
BG_
V33A T_TRN
AN
PERST
D
_RST_ GPIO0 SPI_CLK
N
N
A
K
V
V
K
SOC_C
O
RF1 RF1
_OUT _PA2 _PA1
RF1
SOC_CO
_V12D_
GE2 GE2 GE1 GE1
_RXD _RXD _RXD _RXD E
ANT_ PA_PE PA_P
APCK PCIE
_V12A _V33A
UPHY0
_V33A
E
F
TRNB _G0 E _G1 _V12D
N
_V33N _V33A
0
3
1
1
0
_1
GE2 GE2 GE1 GE1
_RXD _RXD _RXD _RXD F
GE_IO
_V33D
GND
GND GND
GND
GND
GND GND GND GND
GND GND GND GND
2
0
3
2
SOC_I
GE2 GE2 GE1 GE1
_TXE _TXCL _TXE _TXCL G
WLED
_N
O
_V33D
_1
GE_IO
_V33D
G
GND GND
GND GND
N
K
N
K
EPHY
_LED
3 _N
_JTCL
K
EPHY EPHY EPHY
_LED2 _LED1 _LED0
_N _N_JT
_JTMS DI
DDR_I
O
_V18D
GE2
_TXD
2
GE1
_TXD H
0
GE2 GE1
_TXD3 _TXD1
H
J
GND
GND
GND GND GND GND
_N
_JTDO
EPHY
_LED4 DDR_I
MD14 MD9 MODT _N
GE2
_TXD
1
GE1
_TXD J
2
GE2 GE1
_TXD0 _TXD3
O
GND GND
GND GND GND GND
GND GND GND GND
_JTRST _V18D
_N
SOC_C
O
_V12D
_3
DDR_I
O
_V18D
MCS_
N
K
L
MD12 MD11
MD10 MD13
MD8 MD15
GND
MA0
GND GND
GND GND
GND
GND
GND
MDC MDIO
K
L
SOC_C
O
_V12D
_3
DDR_I
O
_VREF
EPHY EPHY
_V12 _V12
MRAS
_N
GND GND GND GND
SOC_C SOC
A
A
DDR
EPHY MDI MDI_ MDI MDI
GND GND _PLL _RN_ RP _TP_P _TN_ M
MCAS
_N
O
_IO
_V12D _V33D
_2 _2
M
MA2 _IOC GND GND
_V12D
_V12A P3
_P3
4
P4
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
26
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DDR_I
O
_V18
SOC_C SOC
_IO
_V12D _V33D
DDR
EPHY
GND _V33
A
MDI MDI MDI_ MDI
_TN_ _TP_P RP _RN_ N
MDQ MDQ
O
EPHY
_V33A
N
MA4 _IOC MA13
_V12D
S1
M1
P3
3
_P4
P4
D
_2
_2
ND_CL
E/ SD ND_W
_CARD P/ SD DSR _N RXD TXD2
_DETE _WP
CT
DDR
MDI_ MDI MDI_ MDI
TP _TN_ RP _RN_ P
MCK_ MCK_
ND_CS_
N
P
MA6 MA8 MA12 MA7 _IO
P
N
_V18D
_P2
P2
_P2
P2
ND_AL
ND
ND_RB_
N/
SD_CLK
EPHY MDI_ MDI
ND_RE E/
R
T
MD5 MD2 MA11 MA9 MA5 MA3 MBA2
_WE TXD RTS_N RXD2 _RES RP _RN_ R
_N
_N SD_CM
_VBG _P1
P1
D
ND_D4
/
BT_ST
ND_D6/
BT
_WACT
ND_D2 ND
_D0/
MDI MDI_ MDI
_RN_ TP _TN_ T
MWE
DCD
_N
I2C_S
D
MD0 MD6 MD4 MDQS0 MA1 MBA1
_N
/
RIN
SD_D2 SD _D0
P0
_P1
P1
AT
ND_D5
/
BT_ANT BT_AU
ND_D3 ND
MDI_ MDI MDI
RP _TP_P _TN_ U
MDQM
0
ND_D7/
DTR
_N
I2C
_SCLK
U
MD7 MD1 MD3
MA10 MBA0 MCKE
/
_D1/
CTS_N
SD_D3 SD _D1
_P0
0
P0
X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Table 2-1 DDR2 Ball Map
2.2 DR-QFN (12 mm x 12 mm) 148-Pin Package Diagram
2.2.1 Left side view
NC NC
74
73
72
71
70
69
68
67
66
NC
NC
75
1
76
2
148
147
146
145
144
143
PLL
142
141
140
139
S oC
RF0_OUTP
RF0_PA2_V33N
RF0_OUTN
RF0_PA1_V33A
GND
77 RF
RF1_VX_LDO
NC
RF1_OUTP
3
4
5
6
7
8
9
78
RF1_PA2_V33N
79
RF1_OUTN
RF1_PA1_V33A
SOC_IO_V33D_1
WLED_N
80
81
EPHY_LED3_N_JTCLK
EPHY_LED0_N_JTDO
EPHY_LED1_N_JTDI
EPHY_LED2_N_JTMS
EPHY_LED4_N_JTRST_N
SOC_CO_V12D_1
82
83
84
VDD18
DDR_DQ14
DDR_DQ9
VDD25 10
DDR_DQ15
DDR_DQ14 11
85
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
DDR_DQ12
DDR_DQ11
DDR_DQ10
DDR_DQ13
DDR_DQ8
DDR_DQ13
DDR_DQ12 12
DDR_DQ11
DDR_DQ10 13
DDR_DQ9
86
87
88
DDR_DQ15
DDR_DQS1
DDR_DQM1
MCK_P
MCK_N
DDR_VREF
DDR_ODT
DDR_DQ8 14
DDR_DQS1
DDR_DQM1 15
MCK_N
89
90
91
92
MCK_P 16
DDR_VREF
DDR_MA4 17
DDR_MA5
DDR_IOC_V12D 18
VDD25
DDR_RAS_N
DDR_IOC_V12D
VDD18
93
NC
DRAM
NC
94
95
96
97
98
99
100
101
102
NC NC
19
20
21
22
23
24
25
26
27
Figure 2-1 DR-QFN Pin Diagram (left view)
2.2.2 Right side view
65
64
63
62
61
134
PCIE
60
59
58
132
PMU
57
56
NC NC
NC
138
137
136
135
133
131
SoC
55 VFB_DIG
54 EXT_LDO_DIG
UPHY0_VRES
53 UPHY0_PADM
UPHY0_V33A
52 UPHY0_PADP
UPHY0_V12D
51 SOC_CO_V12D_3
MDI_TN_P4
50 MDI_TP_P4
MDI_RN_P4
49 MDI_RP_P4
MDI_RN_P3
130
129
128
127
126
125
124
123
122
121
48 MDI_RP_P3
MDI_TN_P3
47 MDI_TP_P3
EPHY_V12A
46 MDI_TN_P2
EPHY_V33A
45 MDI_TP_P2
MDI_RN_P2
44 MDI_RP_P2
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
120
119
118
EPHY_PLL_V12A
43 EPHY_RES_VBG
EPHY_V33A
42 MDI_RN_P1
MDI_RP_P1
41 MDI_TN_P1
EPHY_V33A
40 MDI_TP_P1
MDI_TN_P0
39 MDI_TP_P0
MDI_RN_P0
38 MDI_RP_P0
EPHY_V12A
37 RXD2
117
116
115
114
113
TXD2
DRAM
106
NC
NC
103
104
105
107
108
109
110
111
112
28
29
30
31
32
33
34
35
36
NC NC
Figure 2-2 DR-QFN Pin Diagram (right side view)
Note: DR-QFN support SDR/DDR1 and DDR2 pin shuffle depend on the bootstrap. For DDR2 pin assignment,
please refer to left column and bottom row using DDR_ format.
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.3 Pin Descriptions (TFBGA)
Pin
Name
Type
Driv.
Description
WLAN LED
G4
WLED_N
O, IPU
4 mA
WLAN Activity LED
UART Lite
R14
P13
RXD2
TXD2
I, IPU
O, IPU
4 mA
4 mA
UART Lite RXD
UART Lite TXD
UART Full *
P12
T13
U13
P11
T12
R12
U12
R13
SPI
RXD
RIN
I, IPD
I, IPD
I, IPD
I, IPD
I, IPD
O, IPD
O, IPD
O, IPD
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
UART RXD.
UART RIN.
CTS_N
DSR_N
DCD_N
TXD
DTR_N
RTS_N
UART CTS_N.
UART DSR_N.
UART DCD_N.
UART TXD.
UART DTR.
UART RTS.
C8
A8
B7
B8
D8
C7
C9
SPI_MISO
SPI_MOSI
SPI_WP
SPI_HOLD
SPI_CLK
I/O, IPD 4 mA
I/O, IPD 4 mA
I/O, IPD 4 mA
I/O, IPD 4 mA
Master output/Slave input
Master input/Slave output
GOP function
GOP function
SPI clock
O, IPD
O, IPU
O, IPU
4 mA
4 mA
4 mA
SPI_CS0
SPI_CS1
SPI chip select0
SPI chip select1
I2C
U14
T14
I2C_SCLK
I2C_SD
I/O, IPU 4 mA
I2C Clock
I2C Data
O, IPU
4 mA
RGMII/MII (3.3 V)*
D17
D16
E17
E16
F17
F16
G17
G16
H17
H16
J17
GE1_RXCLK
I/O
I
I
I
I
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
RGMII1 /GMII Rx Clock
RGMII1 /GMII Rx Data Valid
GE1_RXDV
GE1_RXD0
GE1_RXD1
GE1_RXD2
GE1_RXD3
GE1_TXCLK
GE1_TXEN
GE1_TXD0
GE1_TXD1
GE1_TXD2
GE1_TXD3
GE2_RXCLK
GE2_RXDV
RGMII1 Rx Data bit #0/GMII Rx Data bit #0
RGMII1 Rx Data bit #1/GMII Rx Data bit #1
RGMII1 Rx Data bit #2/GMII Rx Data bit #2
RGMII1 Rx Data bit #3/GMII Rx Data bit #3
RGMII1 /GMII Tx Clock
I
I/O
O
O
O
O
O
I/O
I
RGMII1 /GMII Tx Data Valid
RGMII1 Tx Data bit #0/GMII Tx Data bit #0
RGMII1 Tx Data bit #1/GMII Tx Data bit #1
RGMII1 Tx Data bit #2/GMII Tx Data bit #2
RGMII1 Tx Data bit #3/GMII Tx Data bit #3
RGMII2 /GMII Rx Clock
J16
D14
D15
RGMII2 /GMII Rx Data Valid
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Pin
F15
Name
Type
I
I
I
Driv.
Description
GE2_RXD0
GE2_RXD1
GE2_RXD2
GE2_RXD3
GE2_TXCLK
GE2_TXEN
GE2_TXD0
GE2_TXD1
GE2_TXD2
GE2_TXD3
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
RGMII2 Rx Data bit #0/GMII Rx Data bit #0
RGMII2 Rx Data bit #1/GMII Rx Data bit #1
RGMII2 Rx Data bit #2/GMII Rx Data bit #2
RGMII2 Rx Data bit #3/GMII Rx Data bit #3
RGMII2 /GMII Tx Clock
E15
F14
E14
G15
G14
J15
J14
H14
H15
I
I/O
O
O
O
O
O
RGMII2 /GMII Tx Data Valid
RGMII2 Tx Data bit #0/GMII Tx Data bit #0
RGMII2 Tx Data bit #1/GMII Tx Data bit #1
RGMII2 Tx Data bit #2/GMII Tx Data bit #2
RGMII2 Tx Data bit #3/GMII Tx Data bit #3
PHY Management ( 3.3 V)
K14
K15
MDC
MDIO
O
I/O
8 mA
8 mA
PHY Management Clock. Shared with GPIO23
PHY Management Data. Shared with GPIO22
GPIO
D7
5-Port PHY
H4
GPIO0
I/O, IPD 8 mA
O, IPD 4 mA
GPO0 (output only)
EPHY_LED0
_N_JTDO
EPHY_LED1
_N_JTDI
EPHY_LED2
_N_JTMS
EPHY_LED3
_N_JTCLK
10/100 PHY Port #0 activity LED, JTAG_TDO
10/100 PHY Port #1 activity LED, JTAG_TDI
10/100 PHY Port #2 activity LED, JTAG_TMS
10/100 PHY Port #3 activity LED, JTAG_CLK
10/100 PHY Port #4 activity LED, JTAG_TRST_N
H3
H2
H1
J4
I/O, IPD 4 mA
I/O, IPD 4 mA
I/O, IPD 4 mA
I/O, IPU 4 mA
A
EPHY_LED4
_N_JTRST_N
EPHY_RES _VBG
R15
Connect to an external resistor to provide accurate
bias current
T15
U15
U17
U16
R17
R16
T17
T16
P17
P16
P15
P14
M14
M15
N14
MDI_RN_P0
MDI_RP_P0
MDI_TN_P0
MDI_TP_P0
MDI_RN_P1
MDI_RP_P1
MDI_TN_P1
MDI_TP_P1
MDI_RN_P2
MDI_RP_P2
MDI_TN_P2
MDI_TP_P2
MDI_RN_P3
MDI_RP_P3
MDI_TN_P3
I
I
O
O
I
10/100 PHY Port #0 RXN
10/100 PHY Port #0 RXP
10/100 PHY Port #0 TXN
10/100 PHY Port #0 TXP
10/100 PHY Port #1 RXN
10/100 PHY Port #1 RXP
10/100 PHY Port #1 TXN
10/100 PHY Port #1 TXP
10/100 PHY Port #2 RXN
10/100 PHY Port #2 RXP
10/100 PHY Port #2 TXN
10/100 PHY Port #2 TXP
10/100 PHY Port #3 RXN
10/100 PHY Port #3 RXP
10/100 PHY Port #3 TXN
I
O
O
I
I
O
O
I
I
O
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Pin
N15
Name
Type
O
I
I
O
O
Driv.
Description
MDI_TP_P3
MDI_RN_P4
MDI_RP_P4
MDI_TN_P4
MDI_TP_P4
10/100 PHY Port #3 TXP
10/100 PHY Port #4 RXN
10/100 PHY Port #4 RXP
10/100 PHY Port #4 TXN
10/100 PHY Port #4 TXP
N17
N16
M17
M16
NAND Flash*
P8
ND_CS_N
ND_RE_N
ND_WE_N
ND_WP
ND_CLE
ND_ALE
ND_D0
ND_D1
ND_D2
ND_D3
ND_D4
O, IPD
O, IPD
O, IPD
O, IPD
O, IPD
O, IPD
I/O, IPD 4 mA
I/O, IPD 4 mA
I/O, IPD 4 mA
I/O, IPD 4 mA
I/O, IPD 4 mA
I/O, IPD 4 mA
I/O, IPD 4 mA
I/O, IPD 4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
NAND Flash Chip Select
NAND Flash Read Enable
NAND Flash Write Enable
NAND Flash Write Protect
NAND Flash Command Latch Enable
NAND Flash ALE Latch Enable
NAND Flash Data0
NAND Flash Data1
NAND Flash Data2
NAND Flash Data3
NAND Flash Data4
R9
R11
P10
P9
R10
T11
U11
T10
U10
T9
U9
T8
U8
ND_D5
ND_D6
ND_D7
NAND Flash Data5
NAND Flash Data6
NAND Flash Data7
R8
ND_RB_N
I, IPD
4 mA
NAND Flash Ready/Busy
Misc.
C6
PORST_N
I, IPU
4 mA
Power on reset
E5
PA_PE_G0
O, I PD
16
0 V to 3.3 V control for external PA0
mA
E6
PA_PE_G1
O, IPD
16
0 V to 3.3 V control for external PA1
mA
D5
E4
D6
ANT_TRN
ANT_TRNB
WDT_RST_N
O, IPD
O, IPD
O, IPU
8 mA
8 mA
4 mA
Positive signal for antenna T/R switch
Negative signal for antenna T/R switch
Watchdog Reset
USB PHY
E13
C12
UPHY0_V33A
UPHY0_V12D
UPHY0_VRES
P
P
I/O
3.3 V USB PHY analog power supply
1.2 V USB PHY digital power supply
Connect to an external 8.2 kΩ resistor for band-gap
C15
reference circuit
C16
C17
DDR2
M2
J1
L2
K1
K2
UPHY0_PADM
UPHY0_PADP
I/O
I/O
USB Port0 data pin Data-
USB Port0 data pin Data+
MD15
MD14
MD13
MD12
MD11
I/O
I/O
I/O
I/O
I/O
8 mA
8 mA
8 mA
8 mA
8 mA
DDR2 Data bit #15
DDR2 Data bit #14
DDR2 Data bit #13
DDR2 Data bit #12
DDR2 Data bit #11
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Pin
L1
J2
M1
U1
T2
Name
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MA13
MA12
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Driv.
Description
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
DDR2 Data bit #10
DDR2 Data bit #9
DDR2 Data bit #8
DDR2 Data bit #7
DDR2 Data bit #6
DDR2 Data bit #5
DDR2 Data bit #4
DDR2 Data bit #3
DDR2 Data bit #2
DDR2 Data bit #1
DDR2 Data bit #0
DDR2 Address bit #13
DDR2 Address bit #12
DDR2 Address bit #11
DDR2 Address bit #10
DDR2 Address bit #9
DDR2 Address bit #8
DDR2 Address bit #7
DDR2 Address bit #6
DDR2 Address bit #5
DDR2 Address bit #4
DDR2 Address bit #3
DDR2 Address bit #2
DDR2 Address bit #1
DDR2 Address bit #0
DDR2 MBA #2
DDR2 MBA #1
DDR2 MBA #0
DDR2 MRAS_N
DDR2 MCAS_N
DDR2 MWE_N
DDR2 MCK_P
DDR2 MCK_N
DDR2 MDM#1
DDR2 MDM#0
DDR2 MCS_N
DDR2 MDQS#1
DDR2 MDQS#0
DDR2 MCKE
DDR2 ODT
R1
T3
U3
R2
U2
T1
N5
P5
R3
U5
R4
P4
P6
P3
R5
N3
R6
M4
T5
L4
R7
T6
U6
L3
M3
T7
P1
P2
N2
U4
K3
N1
T4
MA0
MBA2
MBA1
MBA0
MRAS_N
MCAS_N
MWE_N
MCK_P
MCK_N
MDQM1
MDQM0
MCS_N
MDQS1
MDQS0
MCKE
ODT
I/O
I/O
O, IPD
O
U7
J3
PMU
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MT7620 DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Pin
A13
Name
FB
Type
A
Driv.
Description
This pin is part of the error amplifier and provides the
reference voltage which the sampled output voltage is
compared to. A difference between these two
voltages indicates an error in the output voltage.
C14
COMP
A
This pin provides the error amplifier output which
compensates for errors in the output voltage identified
using the FB pin.
A15
B14
A14
UGATE
A
A
P
Gate drive for external upper MOSFET (Ipeak<200 mA;
Iavg<20 mA)
Gate drive for external lower MOSFET (Ipeak<200 mA;
Iavg<20 mA)
3.3 V power supply only for gate driver of SW
(Ipeak<200 mA; Iavg<20 mA)
LGATE
DCDC_V33D
B16
B17
A17
B15
A16
PCIe*
D10
A10
B10
B9
DCDC_V33A
EXT_LDO_DIG
VFB_DIG
EXT_LDO_DDR
VFB_DDR
P
A
A
A
A
3.3 V analog power (Ipeak<200 mA; Iavg<10 mA)
Connect to Base terminal of external BJT (Iavg<20 mA)
1.2 V output feedback
Connect to Base terminal of external BJT (Iavg<20 mA)
DDR output feedback
PERST_N
PCIE_TXN
PCIE_TXP
PCIE_RXN
PCIE_RXP
PCIE_REXT
I/O, IPU 4 mA
PICe reset.
A
A
A
A
A
PCIe0 differential transmit TX -
PCIe0 differential transmit TX+
PCIe0 differential receive RX -
PCIe0 differential receive RX +
PCIe0 Reference resistor connection
(12K Ohm +/- 1 %)
A9
C10
PCIe Reference Clock Generator
A11
B11
E10
C11
D11
PLL
APCK_RFCKOP
APCK_RFCKON
PCIE_V33A
PCIE_RFCKP
PCIE_RFCKN
A
A
P
A
A
External reference clock output (positive)
External reference clock output (negative)
PCIe 3.3 V analog power
Device reference clock input (positive)
Device reference clock input (negative)
E9, D12
A7
B6
APCK_V12A
BBPLL_V12A
P
P
1.2 V analog power supply for CPLL/PPLL
1.2 V analog power supply to BB PLL
NC
Power
D9, G5,
M10, N10
E7, E8, L13, SOC_CO_V12D
SOC_IO_V33D
P
P
3.3 V digital I/O power supply
1.2 V digital core power supply
M9, N9,
K13
L5
DDR_IO_VREF
P
0.9 V/1.25 V/GND reference voltage power supply for
DDR2/DDR1/SDR
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Pin
H5, N6, J5,
K5, P7
Name
DDR_IO_V18D/
DDR_IO_V25D
Type
P
Driv.
Description
1.8 V/2.5 V/3.3 V level shifter power supply for
DDR2/DDR1/SDR
M5, N4
N12, N13
L14, L15
F13, G13
M13
DDR_IOC_V12D
EPHY_V33A
EPHY_V12A
GE_IO_V33D
EPHY_PLL_V12A
P
P
P
P
P
1.2 V I/O core power supply for DDR and SDR
3.3 V power supply for EPHY
1.2 V power supply for EPHY
3.3 V power supply for RGMII
1.2 V power supply for EPHY PLL
RF
A1
RF0_OUTP
RF0_OUTN
I/O
I/O
2.4 GHz TX0 PA output (positive)
2.4 GHz RX0 LNA input (positive)
2.4 GHz TX0 PA output (negative)
2.4 GHz RX0 LNA input (negative)
B2
B1
A2
A3
B3
D1
RF0_PA1 _V33A
RF0_PA2 _V33N
RF0_IN
RF0_VX_LDO
RF1_OUTP
P
P
I
P
3.3 V Supply for RF channel0
3.3 V Supply for RF channel0
2.4 GHz RX0 input (aux LNA0 input)
1.2 V to 3.3 V supply for RF0
2.4 GHz TX1 PA output (positive)
2.4 GHz RX1 LNA input (positive)
I/O
E1
RF1_OUTN
I/O
2.4 GHz TX1 PA output (negative)
2.4 GHz RX1 LNA input (negative)
E3
E2
C1
D3
D4
A4
B4
C4
C5
A5
A6
B5
RF1_PA1 _V33A
RF1_PA2 _V33N
RF1_IN
RF1_VX_LDO
BG_V33A
BG_EXTR
PLL_VC_CAP
GND
P
P
I
P
3.3 V Supply for RF channel1
3.3 V Supply for RF channel1
2.4 GHz RX1 input (aux LNA1 input)
1.2 V to 3.3 V supply for RF1
3.3 V supply for band gap reference
External reference resistor (24 kΩ)
PLL external loop filter
Ground ball
1.2 V to 3.3 V Supply for ADC
Crystal oscillator input
P
I/O
I/O
G
P
I
O
O
ADC_VX_LDO
XTAL_XI
XTAL_XO
Crystal oscillator output
Crystal LDO output
XTAL_V12A
A1, B2, D1, E1 will be output only when external PA/LNA.
Ground
C2, D2, F2, K4,
F6 to F12,
GND
G
Ground ball
G6 to G12,
H6 to H12,
J6 to J12,
K6 to K12,
L6 to L12,
M6 to M8,
M11, M12, N11
Total: 265 balls
DSMT7620_V.1.3_091212
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
NOTE:
1. Pin types marked with an * indicate that they are available only in the TFBGA package.
2. Ball mapping for these pins is shown in the DDR2 Ball Map table in section 2.3.1. For information on DDR1
ball mapping, see section 2.3.2.
3. Ball mapping for these pins is shown in the DDR2 Ball Map table in section 2.3.1. For information on DDR1
ball mapping, see section 2.3.2.
2.4 Pin Descriptions (DRQFN)
Pins
Name
Type
Driv.
Description
WLAN LED
81
WLED_N
O, IPU
4 mA
WLAN Activity LED
UART Lite
37
RXD2
TXD2
I, IPU
4 mA
4 mA
UART Lite RXD
UART Lite TXD
113
SPI
O, IPU
137
63
SPI_MISO
SPI_MOSI
SPI_WP
I/O, IPD
I/O, IPD
I/O, IPD
I/O, IPD
O, IPD
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
Master output/Slave input
Master input/Slave output
GPO function
65
138
136
64
SPI_HOLD
SPI_CLK
GPO function
SPI clock
SPI_CS0
SPI_CS1
O, IPU
SPI chip select0
62
O, IPU
SPI chip select1
I2C
111
36
I2C_SCLK
I2C_SD
I/O, IPU 4 mA
I2C Clock
I2C Data
O, IPU
4 mA
GPIO
139
GPIO0
I/O, IPD
8 mA
GPO0 (output only)
5-Port PHY
82
EPHY_LED0
_N_JTDO
O, IPD
4 mA
4 mA
4 mA
4 mA
10/100 PHY Port #0 activity LED, JTAG_TDO
10/100 PHY Port #1 activity LED, JTAG_TDI
10/100 PHY Port #2 activity LED, JTAG_TMS
10/100 PHY Port #3 activity LED, JTAG_CLK
10/100 PHY Port #4 activity LED, JTAG_TRST_N
8
EPHY_LED1
_N_JTDI
I/O, IPD
I/O, IPD
I/O, IPD
83
7
EPHY_LED2
_N_JTMS
EPHY_LED3
_N_JTCLK
9
EPHY_LED4
_N_JTRST_N
I/O, IPU 4 mA
A
43
EPHY_RES _VBG
Connect to an external resistor to provide accurate bias
current
115
38
MDI_RN_P0
MDI_RP_P0
I
I
10/100 PHY Port #0 RXN
10/100 PHY Port #0 RXP
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Pins
116
39
Name
Type
Driv.
Description
MDI_TN_P0
MDI_TP_P0
MDI_RN_P1
MDI_RP_P1
MDI_TN_P1
MDI_TP_P1
MDI_RN_P2
MDI_RP_P2
MDI_TN_P2
MDI_TP_P2
MDI_RN_P3
MDI_RP_P3
MDI_TN_P3
MDI_TP_P3
MDI_RN_P4
MDI_RP_P4
MDI_TN_P4
MDI_TP_P4
O
O
I
10/100 PHY Port #0 TXN
10/100 PHY Port #0 TXP
10/100 PHY Port #1 RXN
10/100 PHY Port #1 RXP
10/100 PHY Port #1 TXN
10/100 PHY Port #1 TXP
10/100 PHY Port #2 RXN
10/100 PHY Port #2 RXP
10/100 PHY Port #2 TXN
10/100 PHY Port #2 TXP
10/100 PHY Port #3 RXN
10/100 PHY Port #3 RXP
10/100 PHY Port #3 TXN
10/100 PHY Port #3 TXP
10/100 PHY Port #4 RXN
10/100 PHY Port #4 RXP
10/100 PHY Port #4 TXN
10/100 PHY Port #4 TXP
42
118
41
I
O
O
I
40
121
44
I
46
O
O
I
45
125
48
I
124
47
O
O
I
126
49
I
127
50
O
O
Misc.
66
PORST_N
I, IPU
4 mA
Power on reset
141
68
PA_PE_G0
PA_PE_G1
ANT_TRN
O, IPD
O, IPD
O, IPD
O, IPD
O, IPU
16 mA 0 V to 3.3 V control for external PA0
16 mA 0 V to 3.3 V control for external PA1
142
69
8 mA
8 mA
4 mA
Positive signal for antenna T/R switch
Negative signal for antenna T/R switch
Watchdog Reset
ANT_TRNB
WDT_RST_N
67
USB PHY
129
128
130
UPHY0 _V33A
UPHY0 _V12D
UPHY0 _VRES
P
3.3 V USB PHY analog power supply
1.2 V USB PHY digital power supply
P
I/O
Connect to an external 8.2 kΩ resistor for band-gap
reference circuit
53
UPHY0 _PADM
UPHY0 _PADP
I/O
I/O
USB Port0 data pin Data-
USB Port0 data pin Data+
52
DDR1/SDR
85
11
86
12
87
13
MD15
MD14
MD13
MD12
MD11
MD10
I/O
I/O
I/O
I/O
I/O
I/O
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
SDRAM/DDR Data bit #15
SDRAM/DDR Data bit #14
SDRAM/DDR Data bit #13
SDRAM/DDR Data bit #12
SDRAM/DDR Data bit #11
SDRAM/DDR Data bit #10
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Pins
88
Name
MD9
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Driv.
Description
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
SDRAM/DDR Data bit #9
SDRAM/DDR Data bit #8
SDRAM/DDR Data bit #7
SDRAM/DDR Data bit #6
SDRAM/DDR Data bit #5
SDRAM/DDR Data bit #4
SDRAM/DDR Data bit #3
SDRAM/DDR Data bit #2
SDRAM/DDR Data bit #1
SDRAM/DDR Data bit #0
SDRAM/DDR Address bit #12
SDRAM/DDR Address bit #11
SDRAM/DDR Address bit #10
SDRAM/DDR Address bit #9
SDRAM/DDR Address bit #8
SDRAM/DDR Address bit #7
SDRAM/DDR Address bit #6
SDRAM/DDR Address bit #5
SDRAM/DDR Address bit #4
SDRAM/DDR Address bit #3
SDRAM/DDR Address bit #2
SDRAM/DDR Address bit #1
SDRAM/DDR Address bit #0
SDRAM/DDR MBA #1
14
MD8
27
MD7
102
26
MD6
MD5
101
100
24
MD4
MD3
MD2
99
MD1
23
MD0
97
MA12
MA11
MA10
MA9
21
O
31
O
96
O
20
MA8
O
19
MA7
O
94
MA6
O
92
MA5
O
17
MA4
O
104
105
30
MA3
O
MA2
O
MA1
O
106
107
32
MA0
O
MBA1
MBA0
MRAS_N
MCAS_N
MWE_N
MCK_P
MCK_N
MDQM1
MDQM0
MCS_N
MDQS1
MDQS0
MCKE
ODT
O
O
SDRAM/DDR MBA #0
33
O
SDRAM/DDR MRAS_N
SDRAM/DDR MCAS_N
SDRAM/DDR MWE_N
SDRAM MCK/DDR MCK_P
DDR MCK_N
109
34
O
O
16
O
90
O
15
O
SDRAM MDQM#1/DDR MDM#1
SDRAM MDQM#0/DDR MDM#0
SDRAM/DDR MCS_N
28
O
108
89
O
I/O
I/O
O, IPD
O
DDR MDQS#1
103
22
DDR MDQS#0
DDR MCKE
98
DDR2 ODT
PMU
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Pins
58
Name
FB
Type
A
Driv.
Description
This pin is part of the error amplifier and provides the
reference voltage which the sampled output voltage is
compared to. A difference between these two voltages
indicates an error in the output voltage.
132
COMP
A
This pin provides the error amplifier output which
compensates for errors in the output voltage identified
using the FB pin.
59
UGATE
A
A
P
P
Gate drive for external upper MOSFET
(Ipeak<200 mA; Iavg<20 mA)
133
60
LGATE
Gate drive for external lower MOSFET
(Ipeak<200mA; Iavg<20mA)
DCDC _V33D
DCDC _V33A
3.3 V power supply only for gate driver of SW
(Ipeak<200 mA; Iavg<20 mA)
56
3.3 V analog power
(Ipeak<200 mA; Iavg<10 mA)
54
EXT_LDO _DIG
VFB_DIG
A
A
A
Connects to the base terminal of external BJT (Iavg<20 mA)
1.2 V output feedback
55
131
EXT_LDO _DDR
Connect to Base terminal of external BJT
(Iavg<20 mA)
57
VFB_DDR
A
DDR output feedback
PLL
61
APCK_V33A
APCK_V12A
BBPLL_V12A
P
P
P
3.3 V analog power supply for CPLL/PPLL
1.2 V analog power supply for CPLL/PPLL
1.2 V analog power supply to BB PLL
NC
135
143
70
Power
134, 6, SOC_IO _V33D
112
P
P
P
P
P
P
3.3 V digital I/O power supply
1.2 V digital core power supply
84, 35, SOC_CO _V12D
140, 51
91, 110 DDR_VREF
0.9 V/1.25 V/GND reference voltage power supply for
DDR2/DDR1/SDR
10, 93, VDD18/ VDD25
95, 29
1.8 V/2.5 V/3.3 V level shifter power supply for
DDR2/DDR1/SDR
18, 25
DDR_IOC
_V12D
1.2 V I/O core power supply for DDR and SDR
122,
119,
117
EPHY_V33A
3.3 V power supply for EPHY
123,
114
EPHY_V12A
P
1.2 V power supply for EPHY
RF
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Pins
75
Name
Type
I/O
Driv.
Description
RF0_OUTP
2.4 GHz TX0 PA output (positive)
2.4 GHz RX0 LNA input (positive)
76
RF0_OUTN
I/O
2.4 GHz TX0 PA output (negavive)
2.4 GHz RX0 LNA input (negative)
2
RF0_PA1 _V33A
RF0_PA2 _V33N
RF0_VX_LDO
RF1_OUTP
P
3.3 V Supply for RF channel0
3.3 V Supply for RF channel0
1.2 V to 3.3 V Supply for RF0
1
P
148
4
P
I/O
2.4 GHz TX1 PA output (positive)
2.4 GHz RX1 LNA input (positive)
5
RF1_OUTN
I/O
2.4 GHz TX1 PA output (negative)
2.4 GHz RX1 LNA input (negative)
80
RF1_PA1 _V33A
RF1_PA2 _V33N
RF1_VX_LDO
BG_V33A
P
3.3 V Supply for RF channel1
3.3 V Supply for RF channel1
1.2 V to 3.3 V Supply for RF1
3.3 V supply for band gap reference
External reference resistor (24 kΩ)
PLL external loop filter
79
P
3
P
147
74
P
BG_EXTR
I/O
I/O
P
73
PLL_VC_CAP
PLL_VX_LDO
ADC_VX_LDO
XTAL_XI
146
144
145
71
1.2 V to 3.3 V Supply for PLL
1.2 V to 3.3 V Supply for ADC
Crystal oscillator input
P
I
XTAL_XO
O
O
Crystal oscillator output
Crystal LDO output
72
XTAL_V12A
NC
77, 78
Ground
EPAD
NC
GND
G
Ground pin
Total: 148 pins
NOTE:
IPD : Internal pull-down
IPU : Internal pull-up
I
O
: Input
: Output
IO : Bi-directional
P
: Power
G
: Ground
NC : Not connected
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.5 Pin Sharing Schemes
Some pins are shared with GPIO to provide maximum flexibility for system designers. The MT7620 provides up
to 73 GPIO pins. Users can configure SYSCFG and GPIOMODE registers in the System Control block to specify
the pin function, or they can use the registers specified below. For more information, see the Programmer’s
Guide. Unless specified explicitly, all the GPIO pins are in input mode after reset.
2.5.1 GPIO pin share scheme
I/O Pad Group
WLED_N
Normal Mode
WLAN_LED_N
GE2_RXCLK
GE2_RXDV
GE2_RXD3
GE2_RXD2
GE2_RXD1
GE2_RXD0
GE2_TXCLK
GE2_TXEN
GE2_TXD3
GE2_TXD2
GE2_TXD1
GE2_TXD0
ND_D7
GPIO Mode
GPO#72
GPIO#71
GPIO#70
GPIO#69
GPIO#68
GPIO#67
GPIO#66
GPIO#65
GPIO#64
GPIO#63
GPIO#62
GPIO#61
GPIO#60
GPIO#59
GPIO#58
GPIO#57
GPIO#56
GPIO#55
GPIO#54
GPIO#53
GPIO#52
GPIO#51
GPIO#50
GPIO#49
GPIO#48
GPIO#47
GPIO#46
GPIO#45
GPIO#44
GPIO#43
GPIO#42
GPIO#41
RGMII2
NAND
ND_D6
ND_D5
ND_D4
ND_D3
ND_D2
ND_D1
ND_D0
ND_ALE
ND_CLE
ND_RB_N
ND_WP
ND_RE_N
ND_WE_N
ND_CS_N
SW_PHY_LED/JTAG
EPHY_LED4_N_JTRST_N
EPHY_LED3_N_JTCLK
EPHY_LED2_N_JTMS
EPHY_LED1_N_JTDI
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
I/O Pad Group
Normal Mode
EPHY_LED0_N_JTDO
SPI_WP
GPIO Mode
GPIO#40
GPO#39
GPO#38
GPIO#37
GPIO#36
GPIO#35
GPIO#34
GPIO#33
GPIO#32
GPIO#31
GPIO#30
GPIO#29
GPIO#28
GPIO#27
GPIO#26
GPIO#25
GPIO#24
GPIO#23
GPIO#22
GPIO#21
GPIO#20
GPO#19
GPO#18
GPIO#17
GPIO#16
GPO#15
GPIO#14
GPIO#13
GPIO#12
GPIO#11
GPIO#10
GPIO#9
SPI
SPI_HOLD
SPI_CS1
PERST_N
RGMII1
PERST_N
GE1_RXCLK
GE1_RXDV
GE1_RXD3
GE1_RXD2
GE1_RXD1
GE1_RXD0
GE1_TXCLK
GE1_TXEN
GE1_TXD3
GE1_TXD2
GE1_TXD1
GE1_TXD0
MDC
MDIO
PA_PE
MDIO
PA_PE_G1
PA_PE_G0
ANT_TRN
ANT_TRNB
WDT_RST_N
RXD2
WDT_RST
UARTL
TXD2
UARTF
RIN
DSR_N
DCD_N
DTR_N
RXD
CTS_N
TXD
GPIO#8
RTS_N
GPIO#7
SPI
SPI_MISO
SPI_MOSI
SPI_CLK
GPIO#6
GPO#5
GPO#4
SPI_CS0
GPIO#3
I2C/SUTIF
I2C_SCLK
GPIO#2
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
I/O Pad Group
Normal Mode
I2C_SD
GPIO Mode
GPIO#1
GPIO
GPO0
GPO#0
2.5.2 UARTF pin share scheme
Controlled by the UARTF_SHARE_MODE register.
Pin Name
3’b000
UARTF
3’b001
PCM,
UARTF
3’b010
PCM,
I2S
3’b011
I2S
UARTF
3’b100
PCM,
GPIO
3’b101
GPIO,
UARTF
3’b110
GPIO
I2S
3’b111
GPIO
RIN
RIN
PCMDTX
PCMDRX
PCMCLK
PCMFS
RXD
PCMDTX
PCMDRX
PCMCLK
PCMFS
I2SSDI
RXD
PCMDTX
PCMDRX
PCMCLK
PCMFS
GPIO#14
GPIO#13
GPIO#12
GPIO#11
RXD
GPIO#14
GPIO#13
GPIO#12
GPIO#11
I2SSDI
GPIO#14
GPIO#13
GPIO#12
GPIO#11
GPIO#10
GPIO#9
DSR_N
DCD_N
DTR_N
RXD
DSR_N
DCD_N
DTR_N
RXD
CTS_N
TXD
RTS_N
I2SSDI
I2SSDO
I2SWS
I2SCLK
GPIO#10
GPIO#9
GPIO#8
GPIO#7
CTS_N
TXD
CTS_N
TXD
CTS_N
TXD
I2SSDO
I2SWS
CTS_N
TXD
I2SSDO
I2SWS
GPIO#8
RTS_N
RTS_N
RTS_N
I2SCLK
RTS_N
I2SCLK
GPIO#7
NOTE: This scheme applies only to the TFBGA package.
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.5.3 RGMII pin share schemes
Controlled by the RGMII1_GPIO_MODE register.
Pin Name
GE1_RXCLK
GE1_RXDV
1’b0 RGMII1
GE1_RXCLK
GE1_RXDV
1’b1 GPIO
GPIO#35
GPIO#34
GE1_RXD 0 to 3 GE1_RXD 0 to 3 GPIO#33 to 30
GE1_TXCLK
GE1_TXDV
GE1_TXCLK
GE1_TXDV
GPIO#29
GPIO#28
GE1_TXD0 to 3 GE1_TXD0 to 3 GPIO#27 to 24
NOTE: This scheme applies only to the TFBGA package.
Controlled by the RGMII2_GPIO_MODE register.
Pin Name
GE2_RXCLK
GE2_RXDV
1’b0 RGMII2
GE2_RXCLK
GE2_RXDV
1’b1 GPIO
GPIO#71
GPIO#70
GE2_RXD0 to 3 GE2_RXD0 to 3 GPIO#69 to 66
GE2_TXCLK
GE2_TXDV
GE2_TXCLK
GE2_TXDV
GPIO#65
GPIO#64
GE2_TXD0 to 3 GE2_TXD0 to 3 GPIO#63 to 60
NOTE: This scheme applies only to the TFBGA package.
2.5.4 WDT_RST_MODE pin share scheme
Controlled by the WDT_RST _MODE register.
Pin Name
2’b00
2’b01
2’b1x
WDT_RST_N
WDT_RST_N
REFCLK0_OUT
GPIO#17
2.5.5 PERST_N pin share scheme
Controlled by the PERST_GPIO_MODE register.
Pin Name
2’b00
2’b01
2’b1x
PERST_N
PERST_N
REFCLK0_OUT
GPIO#36
NOTE: This scheme applies only to the TFBGA package.
2.5.6 MDC/MDIO pin share scheme:
Controlled by the the MDIO_GPIO_MODE register.
Pin Name
MDC
2’b00
MDC
2’b01
2’b1x
REFCLK0_OUT
REFCLK1_OUT
GPIO #23
GPIO #24
MDIO
MDIO
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.5.7 EPHY_LED pin share scheme
Controlled by the EPHY_BT_GPIO_MODE register.
Pin Name
EPHY_LED_GPIO_MODE =1’b0
EPHY_LED_GPIO_MODE=1’b1
EPHY_LED BS
(dbg_jtag_mode=0)
JTAG BS
(dbg_jtag_mode=1)
EPHY_LED4_N_JTRST_N
EPHY_LED3_N_JTCLK
EPHY_LED2_N_JTMS
EPHY_LED1_N_JTDI
EPHY_LED0_N_JTDO
EPHY_LED4_N
EPHY_LED3_N
EPHY_LED2_N
EPHY_LED1_N
EPHY_LED0_N
JTAG_RST_N
JTAG_CLK
JTAG_TMS
JTAG_TDI
GPIO#44
GPIO#43
GPIO#42
GPIO#41
GPIO#40
JTAG_TDO
2.5.8 SPI pin share scheme
Controlled by SPI_GPIO_MODE & SPI_REFCLK_MODE registers.
Pin Name
SPI_GPIO_MODE=0
SPI_REFCLK_MODE=0
GPO#39
SPI_GPIO_MODE=1
SPI_REFCLK_MODE=1
GPO#39
SPI_WP
GPO#39
GPO#38
GPIO#37
SPI_HOLD
SPI_CS1
GPO#38
GPO#38
SPI_CS1
REFCLK0_OUT
/GPI#37
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_MISO
SPI_MOSI
SPI_CLK
GPIO#6
GPO#5
GPO#4
GPIO#3
SPI_CS0
SPI_CS0
SPI_CS0
NOTE: I/O direction for REFCLK0_OUT at boot-up is input. Users can set GPI#37 to change to output mode.
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.5.9 ND/SD pin share scheme
Controlled by the ND_SD_GPIO_MODE register.
Pin Name
ND_D7
2’b00 NAND
ND_D7
2’b01 SD + BT + GPIO
BT_ANT
2’b1x GPIO*15
GPIO#59
GPIO#58
GPIO#57
GPIO#56
GPIO#55
GPIO#54
GPIO#53
GPIO#52
GPIO#51
GPIO#50
GPIO#49
GPIO#48
GPIO#47
GPIO#46
GPIO#45
ND_D6
ND_D6
BT_WACT
BT_AUX
ND_D5
ND_D5
ND_D4
ND_D4
BT_STAT
SD_D3
ND_D3
ND_D3
ND_D2
ND_D2
SD_D2
ND_D1
ND_D1
SD_D1
ND_D0
ND_D0
SD_D0
ND_ALE
ND_CLE
ND_RB_N
ND_WP
ND_RE_N
ND_WE_N
ND_CS_N
NOTE :
ND_ALE
ND_CLE
ND_RB_N
ND_WP
ND_RE_N
ND_WE_N
ND_CS_N
SD_CMD
SD_CARD_DETECT
SD_CLK
SD_WP
BT_ACT
GPIO#46
GPIO#45
1. All given GPIO are 4 mA drive capable.
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.5.9.1 Pin share function description
Pin Share Name
I/O Pin Share Function description
PCMDTX
O
PCM Data Transmit
DATA signal sent from the PCM host to the external codec.
PCMDRX
PCMCLK
I
PCM Data Receive
DATA signal sent from the external codec to the PCM host.
I/O PCM Clock
The clock signal can be generated by the PCM host (Output direction), or
provided by an external clock (input direction). The clock frequency should match
the slot configuration of the PCM host.
e.g.
4 slots, PCM clock out/in should be 256 kHz.
8 slots, PCM clock out/in should be 512 kHz.
16 slots, PCM clock out/in should be 1.024 MHz.
32 slots, PCM clock out/in should be 2.048 MHz.
64 slots, PCM clock out/in should be 4.096 MHz.
128 slots, PCM clock out/in should be 8.192 MHz.
PCMFS
I/O PCM SYNC signal.
In our design, the direction of this signal is independent of the direction of
PCMCLK. Its direction and mode is configurable.
I2SSDI
I2SSDO
I2SWS
I
I2S Data input
O
I2S Data output
I/O I2S Channel Selection (or Word selection)
In master mode the pin data direction is set to output, in slave mode it is set to
input.
I2SCLK
I/O I2S clock
In master mode the pin data direction is set to output, in slave mode it is set to
input.
WDT_RST_N
ND_D7
I/O Watchdog timeout reset
I/O Nand flash control data bit7
I/O Nand flash control data bit6
I/O Nand flash control data bit5
I/O Nand flash control data bit4
I/O Nand flash Address Latch Enable
I/O Nand flash Command Latch Enable
ND_D6
ND_D5
ND_D4
ND_ALE
ND_CLE
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.5.10 xMII PHY/MAC Pin Mapping
MII PHY
MII MAC
TXCLK
MII
RvMII
TXCLK
GE0_TXCLK
GE0_TXCTL
GE0_TXD[3:0]
GE0_TXCLK
GE0_TXCTL
GE0_TXD[3:0]
TXCTL/TXEN
TXD[3:0]
TXCTL/TXEN
TXD[3:0]
RvMII
MII
RXCLK
RXCLK
GE0_RXCLK
GE0_RXCLK
RXCTL/RXDV
RXD[3:0]
RXCTL/RXDV
GE0_RXCTL
GE0_RXCTL
GE0_RXD[3:0]
MDC
GE0_RXD[3:0]
RXD[3:0]
MDC
MDC
MDC
MDIO
MDIO
MDIO
MDIO
Figure 2-4 RvMII MII MAC
Figure 2-3 MII MII PHY
RGMII PHY
RGMII
RGMII MAC
RGMII
TXCLK
GE0_TXCLK
GE0_TXCTL
GE0_TXD[3:0]
RXCLK
GE0_TXCLK
GE0_TXCTL
GE0_TXD[3:0]
TXCTL/TXEN
TXD[3:0]
RXCTL/RXDV
RXD[3:0]
RGMII
RGMII
RXCLK
GE0_RXCLK
TXCLK
GE0_RXCLK
RXCTL/RXDV
RXD[3:0]
MDC
GE0_RXCTL
TXCTL/TXEN
TXD[3:0]
MDC
GE0_RXCTL
GE0_RXD[3:0]
GE0_RXD[3:0]
MDC
MDC
MDIO
MDIO
MDIO
MDIO
Figure 2-5 RGMII RGMII PHY
Figure 2-6 RGMII RGMII MAC
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.6 Bootstrapping Pins Description
Pin Name
Boot Strapping Signal
Name
Description
WLED_N
DRAM_FROM _EE
For non-scan mode:
(Validate at iNIC mode (chip mode 2 to 9) and NAND flash (chip
mode 1 and 12)
0: DRAM/PLL configuration from EEPROM
1: DRAM configuration from Auto Detect
ANT_TRN
DBG_JTAG_MODE
0: EPHY_LED
1: JTAG MODE
ANT_TRNB XTAL_FREQ_SEL
0: 20 MHz
1: 40 MHz
{SPI_WP,
SPI_HOLD}
DRAM_TYPE
1: DDR1 (CPU/3) TSOP Package
2: DDR2 (CPU/3) FBGA Package
3: SDRAM (CPU/5) (LVTTL 3.3 V) TSOP Package
{SPI_MOSI CHIP_MODE[3:0]
SPI_CLK,
TXD2
A vector to set chip function/test/debug modes.
In non-test/debug operation,
1: Normal mode (boot from ROM+NAND flash 4 cycle address/2 KB
GPIO0}
page size)
2: Normal mode (boot from SPI 3-Byte Addr)
3: Normal mode (boot from SPI 4-Byte Addr)
4: iNIC RGMII (port 5) mode(boot from ROM)
5: iNIC MII (port 5) mode(boot from ROM)
6: iNIC RVMII (port 5) mode(boot from ROM)
7: iNIC PHY (port 0) mode(boot from ROM)
8: iNIC USB mode(boot from ROM)
9: iNIC PCIe mode(boot from ROM)
10: Normal mode (boot from ROM+NAND flash 4 cycle address/512
B page size)
11: Normal mode (boot from ROM+NAND flash 5 cycle address/2
KB page size)
12: Normal mode (boot from ROM+NAND flash 3 cycle address/512
B page size)
13: Debug mode
14: Scan mode
15: Test mode(CPU will be halted in this mode)
NOTE: SDR/DDR1/DDR2 DRAM cell used is defined by register.
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3. Maximum Ratings and Operating Conditions
3.3 Absolute Maximum Ratings
I/O Supply Voltage
3.6 V
Input, Output, or I/O Voltage
GND -0.3 V to Vcc +0.3 V
Table 3-1 Absolute Maximum Ratings
3.4 Maximum Temperatures
Maximum Junction Temperature (Plastic Package)
Maximum Lead Temperature (Soldering 10 s)
125 °C
260 °C
Table 3-2 Maximum Temperatures
3.5 Operating Conditions
Core Supply Voltage
1.27 V +/- 5%
-20 to 55 °C
3.3 V +/- 10%
Ambient Temperature Range
I/O Supply Voltage
Table 3-3 Operating Conditions
3.6 Thermal Characteristics
Thermal characteristics without an external heat sink in still air conditions.
MT7620N:
Thermal Resistance θJA (°C /W) for JEDEC 2L system PCB
20.14 °C/W
17.19 °C/W
7.29 °C/W
6.14 °C/W
2.02°C/W
1.84°C/W
Thermal Resistance θJA (°C /W) for JEDEC 4L system PCB
Thermal Resistance θJC (°C /W) for JEDEC 2L system PCB
Thermal Resistance θJC (°C /W) for JEDEC 4L system PCB
Thermal Resistance ψJt (°C /W) for JEDEC 2L system PCB
Thermal Resistance ψJt (°C /W) for JEDEC 4L system PCB
MT7620A:
Thermal Resistance θJA (°C /W) for JEDEC 2L system PCB
26.67 °C/W
24.9 °C/W
9.89 °C/W
9.75 °C/W
4.31°C/W
4.19°C/W
Thermal Resistance θJA (°C /W) for JEDEC 4L system PCB
Thermal Resistance θJC (°C /W) for JEDEC 2L system PCB
Thermal Resistance θJC (°C /W) for JEDEC 4L system PCB
Thermal Resistance ψJt (°C /W) for JEDEC 2L system PCB
Thermal Resistance ψJt (°C /W) for JEDEC 4L system PCB
Table 3-4 Thermal Characteristics
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3.7 Storage Conditions
The calculated shelf life in a sealed bag is 12 months if stored between 0 °C and 40 °C at less than 90% relative
humidity (RH). After the bag is opened, devices that are subjected to solder reflow or other high temperature
processes must be handled in the following manner:
.
.
.
Mounted within 168 hours of factory conditions, i.e. < 30 °C at 60% RH.
Storage humidity needs to maintained at < 10% RH.
Baking is necessary if the customer exposes the component to air for over 168 hrs, baking conditions: 125
°C for 8 hrs.
3.8 External Xtal Specfication
Frequency
Frequency offset
VIH/VIL
20 MHz/ 40 Mhz
+/-20 ppm
Vcc-0.3 V/0.3 V
45% to 55%
Duty cycle
Table 3-5 External Xtal Specifications
3.9 DC Electrical Characteristics
Parameters
Sym
Vcc33
Vcc15
Vdd25
Vdd33
Vcc12
Vcc25
Vcc18
Icc33
Conditions
Min
3.0
Typ
3.3
1.5
2.5
3.3
1.27
2.5
1.8
218
147
380
95
Max
3.6
Unit
V
3.3 V Supply Voltage
_VX supply Voltage
RGMII IO Supply Voltage
1.3
3.3
V
2.25
3.0
2.7
V
3.6
V
1.27 V Supply Voltage
DDR1 IO Supply Voltage
DDR2 IO Supply Voltage
3.3 V Current Consumption
1.5 V Current Consumption
1.27 V Current Consumption
DDR2 Current
1.20
2.4
1.33
2.7
V
V
1.7
1.9
V
436
173
540
253
mA
mA
mA
mA
Icc15
Icc12
Icc18
Table 3-6 DC Electrical Characteristics
Vdd=2.5V
VIH
Min
Max
0.7V
0.4V
1.7V
VIL
VOH
VOL
2.25V
Table 3-7 Vdd 2.5V Electrical Characteristics
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3.10 AC Electrical Characteristics
3.10.1 SDRAM Interface
SDRAM CLK
t_IN_SU
t_IN_HD
SDRAM_INPUT
SDRAM_OUTPUT
t_OUT_VLD
Figure 3-1 SDRAM Interface
Symbol
Description
Min
Max
Unit
ns
Remark
t_IN_SU
t_IN_HD
t_OUT_VLD
Setup time for Input signals (e.g. MD*) 1.5
-
Hold time for input signals
1.7
0.8
-
ns
SDRAM_CLK to output signals (MA*,
5
ns
output load: 8 pF
MD*, SDRAM_RAS_N,…) valid
Table 3-8 SDRAM Interface Diagram Key
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3.10.2 DDR2 SDRAM Interface
The DDR2 SDRAM interface complies with 200 MHz timing requirements for standard DDR2 SDRAM. The
interface drivers are SSTL_18 drivers matching the EIA/JEDEC standard JESD8-15A.
tCH
tCL
CLK
CLK#
tIS
tIH
tIH
tIH
tIH
tIH
tIH
MCS_N
MRAS_N
tIS
tIS
tIS
tIS
tIS
MCAS_N
MWE_N
MA0 to MA13
MBA0, MBA1
Figure 3-2 DDR2 SDRAM Command
tWPRE
tWPST
tDQSH
tDQSL
MDQS
MD
tDS
D1
tDH
D2
tDS
D3
tDH
D4
MDQM
Figure 3-3 DDR2 SDRAM Write data
tRPRE
tRPST
D3
MDQS
MD
D1
D2
tQH
tDQSQ (max)
Figure 3-4 DDR2 SDRAM Read data
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Symbol
tCK(avg)
tAC
Description
Min
5
Max
Unit
ns
Remark
Clock cycle time
-
DQ output access time from SDRAM CLK
DQS output access time from SDRAM CLK
SDRAM CLK high pulse width
SDRAM CLK low pulse width
SDRAM CLK half period
-0.6
0.6
ns
tDQSCK
tCH
-0.5
0.5
ns
0.48
0.48
Min(tCH,tCL)
350
0.52
tCK(avg)
tCK(avg)
ns
tCL
0.52
tHP
-
tIS
Address and control input setup time
Address and control input hold time
Data skew of DQS and associated DQ
DQ/DQS output hold time from DQS
DQS read preamble
-
ps
tIH
475
-
ps
tDQSQ
tQH
-
0.35
ns
tHP-0.45
0.9
-
ns
tRPRE
tRPST
tDQSS
tDQSH
tDQSL
tDSS
1.1
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS read postamble
0.4
0.6
DQS rising edge to CK rising edge
DQS input-high pulse width
DQS input-low pulse width
-0.25
0.35
0.35
0.2
0.25
-
-
DQS falling edge to SDRAM CLK setup time
DQS falling edge hold time from SDRAM CLK
DQS write preamble
-
tDSH
tWPRE
tWPST
tDS
0.2
-
-
0.35
0.4
DQS write postamble
0.6
-
DQ and DQM input setup time
DQ and DQM input hold time
*0.15
*0.275
tDH
-
ns
Table 3-9 DDR2 SDRAM Interface Diagram Key
NOTE: Depends on slew rate of DQS and DQ/DQM for single ended DQS.
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3.10.3 RGMII Interface
GE0_TXCLK
t_TX_HD
GE0_TXD/TXCTL
t_TX_SU
GE0_RXCLK
t_RX_HD
GE0_RXD/RXCTL
t_RX_SU
Figure 3-5 RGMII Interface
Symbol
Description
Min
1.2
Max
-
Unit
ns
Remark
t_TX_SU
Setup time for output signals
(e.g. GE0_TXD*, GE0_TXEN)
output load: 5 pF
t_TX_HD
t_RX_SU
Hold time for output signals
1.2
1.0
-
-
ns
ns
output load: 5 pF
Setup time for input signals
(e.g. GE0_RXD*, GE0_RXDV)
t_RX_HD
Hold time for input signals
1.0
-
ns
Table 3-10 RGMII Interface Diagram Key
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3.10.4 MII Interface (25 Mhz)
t_RXCK
Receive:
MII RXCLK
t_RX_SU t_RX_HD
RXDV,RXD
t_TXCK
Transmit:
MII TXCLK
TXEN,TXD
t_TX_delay
Figure 3-6 MII Interface
(For 25 Mhz TXCLK & RXCLK)
Symbol
Description
Min
6
Max
22
Unit
ns
Remark
t_TX_delay
Delay to output signals
output load: 5 pF
(e.g. GE0_TXD*, GE0_TXEN)
t_RX_SU
t_RX_HD
Setup time for input signals
(e.g. GE0_RXD*, GE0_RXDV)
10
5
-
-
ns
ns
Hold time for input signals
Table 3-11 MII Interface Diagram Key
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3.10.5 RvMII Interface (PHY Mode MII Timing) (25 Mhz)
t_TXCK
Receive:
MII TXCLK
t_TX_SU t_TX_HD
TXEN,TXD
t_RXCK
Transmit:
MII RXCLK
RXDV,RXD
t_RX_delay
Figure 3-7 RvMII Interface
(For 25 Mhz TXCLK & RXCLK)
Symbol
Description
Min
5
Max
25
Unit
ns
Remark
t_RX_delay
Delays to output signals
output load: 5 pF
(e.g. GE0_TXD*, GE0_TXEN)
t_TX_SU
t_TX_HD
Setup time for input signals
(e.g. GE0_RXD*, GE0_RXDV)
15
6
-
-
ns
ns
Hold time for input signals
Table 3-12 RvMII Interface Diagram Key
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
3.10.6 SPI Interface
Write operation (driven by clock rising edge)
SPI_CLK
SPI_CS
SPI_MOSI
t_SPI_OVLD (max)
T_SPI_OVLD (min)
Read operation (Driven by clock rising edge (slave-device) and latched by clock rising edge)
SPI_CLK
SPI_CS
SPI_MISO
t_SPI_IS
t_SPI_IH
NOTE: 1) SPI_CLK is a gated clock.
2) SPI_CS is controlled by software
Figure 3-8 SPI Interface
Symbol
Description
Min
6.0
Max
Unit Remark
t_SPI_IS
Setup time for SPI input
Hold time for SPI input
SPI_CLK to SPI output valid
-
-
ns
ns
t_SPI_IH
-1.0
-2.0
t_SPI_OVLD
3.0
ns
output load: 5 pF
Table 3-13 SPI Interface Diagram Key
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
3.10.7 I2S Interface
Transmitter
SCK
WS & SD
t_I2S_OVLD (min)
t_I2S_OVLD (max)
Receiver
SCK
WS & SD
t_I2S_IS t_I2S_IH
Figure 3-9 I2S Interface
Symbol
t_I2S_IS
Description
Min
3.5
Max
Unit Remark
ns
Setup time for I2S input
(data & WS)
-
t_I2S_IH
Hold time for I2S input
(data & WS)
0.5
2.5
-
ns
t_I2S_OVLD
I2S_CLK to I2S output
(data & WS) valid
10.0
ns
output load: 5 pF
Table 3-14 I2S Interface Diagram Key
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
3.10.8 PCM Interface
PCMCLK
DTX
t_PCM_OVLD
PCMCLK
DRX &
FSYNC
t_PCM_IS
t_PCM_IH
Figure 3-10 PCM Interface
Symbol
Description
Min
3.0
Max
Unit Remark
ns
t_PCM_IS
Setup time for PCM input to
PCM_CLK fall
-
t_PCM_IH
Hold time for PCM input to PCM_CLK
fall
1.0
-
ns
t_PCM_OVLD
PCM_CLK rise to PCM output valid
10.0
35.0
ns
output load: 5 pF
Table 3-15 PCM Interface Diagram Key
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3.10.9 Power On Sequence
3.3 V
2.6 V
VDD33
1.5 V
SW_REG
LDO_DIG
1.27 V
1.8 V
LDO_DDR
PORST_N
T3
T4
T1
T2
3.3 V
t_PORST_N ( > 50 ms)
Figure 3-11 Power ON Sequence
Symbol
Description
Min
Max
Unit
Remark
T1
POR delay
Soft start
800
850
1.4
us
us
T2
T3
Soft start done
ms
us
T4
LDO_DIG soft start
650
t_PORST_N
Time between I/O power on to PORST_N
de-assertion
50
-
ms
Table 3-16 Power ON Sequence Diagram Key
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3.11 Package Physical Dimensions
3.11.1 TFBGA (11 mm x 11 mm) 265 balls
3.11.1.1 TFBGA Top View
Figure 3-12 TFBGA Top View
3.11.1.2 TFBGA Side View
Figure 3-14 TFBGA “A” Expanded
Figure 3-13 TFBGA Side View
3.11.1.3 TFBGA “A” Expanded
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3.11.1.6 Package Diagram Key
Dimensions
3.11.1.4 TFBGA Bottom View
Dimensions (inches)
Sym-
bol
(mm)
Min. Nom. Max. Min. Nom. Max.
---- --- 1.20 --- --- 0.047
A
A1
A2
c
0.16 0.21 0.26 0.006 0.008 0.010
0.86 0.91 0.96 0.034 0.036 0.038
0.22 0.26 0.30 0.009 0.010 0.012
10.90 11.00 11.10 0.429 0.433 0.437
10.90 11.00 11.10 0.429 0.433 0.437
D
E
D1
E1
--- 10.40 ---
--- 10.40 ---
--- 0.409 ---
--- 0.409 ---
--- 0.026 ---
e
---
0.65
---
b
0.25 0.30 0.35 0.010 0.012 0.014
aaa
bbb
ddd
eee
fff
0.15
0.10
0.08
0.15
0.08
17/17
0.006
0.004
0.003
0.006
0.003
17/17
MD/ME
Figure 3-15 TFBGA Bottom View
NOTE:
1. Controlling dimensions are in millimeters.
Primary datum C and seating plane are
defined by the spherical crowns of the solder
balls.
3.11.1.5 TFBGA “B” Expanded
Dimension b is measured at the maximum
solder ball diameter, parallel to primary
datum C.
4. Special characteristics C class: bbb, ddd.
The pattern of pin 1 fiducial is for reference
only.
Figure 3-16 TFBGA “B” Expanded
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3.11.2 DR-QFN (12 mm x 12 mm) 148LD
3.11.2.1 DR-QFN Top View
Figure 3-17 DR-QFN Top View
3.11.2.2 DR-QFN Side View
3.11.2.3 DR-QFN “B” Expanded
Figure 3-18 DR-QFN Side View
Figure 3-19 DR-QFN “B” Expanded
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3.11.2.4 DR-QFN Bottom View
Figure 3-20 DR-QFN Bottom View
3.11.2.5 DR-QFN “A” Expanded
Figure 3-21 DR-QFN “A” Expanded
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3.11.2.6 Package Diagram Key
Dimensions (mm)
Dimensions (inches)
Sym-
bol
Min.
0.80
0.00
0.65
Nom. Max. Min. Nom. Max.
A
A1
0.85
0.02
0.90 0.031 0.033 0.035
0.05 0.000 0.0008 0.002
0.75 0.026 0.028 0.030
0.006 REF
A2
0.70
A3
0.15 REF
0.22
b
0.18
0.30 0.007 0.009 0.012
D/E
D1/E1
D3/E3
eT
11.90
12.00 12.10 0.469 0.472 0.476
11.75 BSC
0.463 BSC
0.203 BSC
5.15 BSC
0.50 BSC
0.65 BSC
0.40
0.020 BSC
eR
0.026 BSC
L
0.30
5°
0.50 0.012 0.016 0.020
θ
---
15°
---
5°
---
15°
---
K
0.20
0.09
---
0.008
0.004
---
R
---
---
---
---
aaa
bbb
ccc
ddd
eee
fff
0.10
0.004
0.003
0.004
0.002
0.003
0.004
0.008
0.07
0.10
0.05
0.08
0.10
ggg
NOTE:
0.20
1. Controlling dimensions are in millimeters.
2. Reference document: JEDEC MO-267
Exposed Pad Size
D2/E2 (mm)
D2/E2 (inches)
L/F Min. Nom. Max. Min. Nom. Max.
5.65 5.80 5.95 0.222 0.228 0.234
Internal Pad Size
(mm)
(inches)
L/F Min. Nom. Max. Min. Nom. Max.
5.85 6.00 6.15 0.230 0.236 0.242
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3.11.3 MT7620 N/A marking
MEDIATEK
MT7620N
YYWW-XXXX
LLLLLLLLL
YYWW: Date code
LLLLLLLLL : Lot number
“.”
: Pin #1 dot
Figure 3-22 MT7620N top marking
MEDIATEK
MT7620A
YYWW-XXXX
LLLLLLLLL
YYWW: Date code
LLLLLLLLLL : Lot number
“.”
: Pin #1 dot
Figure 3-23 MT7620A top marking
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3.11.4 Reflow profile guideline
Figure 3-24 Reflow profile for MT7620
Notes;
1. Reflow profile guideline is designed for SnAgCulead-free solder paste.
2. Reflow temperature is defined at the solder ball of package/or the lead of package.
3. MTK would recommend customer following the solder paste vendor’s guideline to design a profile
appropriate your line and products.
4. Appropriate N2 atmosphere is recommended since it would widen the process window and mitigate the risk
for having solder open issues.
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4. Abbreviations
Abbrev.
AC
Description
Abbrev.
CLK
Description
Access Category
Clock
ACK
Acknowledge/ Acknowledgement
Adjacent Channel Power Ratio
CPU
Central Processing Unit
Cyclic Redundancy Check
Control Status Register
Clear to Send
ACPR
AD/DA
CRC
Analog to Digital/Digital to Analog
converter
CSR
CTS
ADC
AES
Analog-to-Digital Converter
Advanced Encryption Standard
Auto Gain Control
CW
Contention Window
Maximum Contention Window
Minimum Contention Window
Digital-To-Analog Converter
Distributed Coordination Function
DMA Done
CWmax
CWmin
DAC
AGC
AIFS
AIFSN
Arbitration Inter-Frame Space
Arbitration Inter-Frame Spacing
Number
DCF
DDONE
DDR
ALC
Asynchronous Layered Coding
Double Data Rate
A-MPDU
A-MSDU
Aggregate MAC Protocol Data Unit
DFT
Discrete Fourier Transform
DCF Inter-Frame Space
Direct Memory Access
Digital Signal Processor
DWORD
Aggregation of MAC Service Data
Units
DIFS
DMA
DSP
AP
Access Point
ASIC
ASME
Application-Specific Integrated Circuit
DW
American Society of Mechanical
Engineers
EAP
Expert Antenna Processor
Enhanced Distributed Channel Access
EEPROM chip select
EEPROM data input
EDCA
EECS
EEDI
EEDO
EEPROM
ASYNC
BA
Asynchronous
Block Acknowledgement
Block Acknowledgement Control
Base Address Register
Baseband Processor
BAC
BAR
BBP
EEPROM data output
Electrically Erasable Programmable
Read-Only Memory
BGSEL
BIST
BSC
Band Gap Select
eFUSE
EESK
EIFS
EIV
electrical Fuse
Built-In Self-Test
EEPROM source clock
Extended Inter-Frame Space
Extend Initialization Vector
Error Vector Magnitude
Frequency Domain Spreading
Front-End Module
Frequency Equalization
First In First Out
Basic Spacing between Centers
BJT
BSSID
BW
Basic Service Set Identifier
Bandwidth
EVM
FDS
CCA
Clear Channel Assessment
Complementary Code Keying
FEM
FEQ
FIFO
FSM
GF
CCK
CCMP
Counter Mode with Cipher Block
Chaining Message Authentication
Code Protocol
Finite-State Machine
Green Field
CCX
Cisco Compatible Extensions
Control Frame End
CF-END
CF-ACK
GND
GP
Ground
Control Frame Acknowledgement
General Purpose
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Abbrev.
GPO
GPIO
HCCA
HCF
HT
Description
Abbrev.
MOSFET
Description
General Purpose Output
General Purpose Input/Output
HCF Controlled Channel Access
Hybrid Coordination Function
High Throughput
Metal Oxide Semiconductor Field
Effect Transistor
MPDU
MSB
NAV
NAS
MAC Protocol Data Units
Most Significant Bit
Network Allocation Vector
Network-Attached Server
Network Address Translation
Null Data Packet
HTC
ICV
High Throughput Control
Integrity Check Value
NAT
NDP
NVM
ODT
IFS
Inter-Frame Space
Non-Volatile Memory
On-die Termination
iNIC
IV
I2C
I2S
Intelligent Network Interface Card
Initialization Vector
Oen
Output Enable
Inter-Integrated Circuit
Integrated Inter-Chip Sound
Input/Output
OFDM
Orthogonal Frequency-Division
Multiplexing
I/O
OSC
PA
Open Sound Control
Power Amplifier
IPI
Idle Power Indicator
IQ
In phase/Quadrature phase
PAPE
Provider Authentication Policy
Extension
JEDEC
Joint Electron Devices Engineering
Council
PBC
PBF
Push Button Configuration
Packet Buffer
JTAG
kbps
KB
Joint Test Action Group
kilo (1000) bits per second
Kilo (1024) Bytes
PCB
PCF
Printed Circuit Board
Point Coordination Function
Pulse-Code Modulation
Physical Layer
LDO
Low-Dropout Regulator
LDO for DIGital part output voltage
Light-Emitting Diode
Low Noise Amplifier
PCM
PHY
PIFS
PLCP
PLL
LDODIG
LED
PCF Interframe Space
Physical Layer Convergence Protocol
Phase-Locked Loop
LNA
LO
Local Oscillator
L-SIG
MAC
MCU
MCS
MDC
MDIO
MEM
MFB
MFS
MIC
Legacy Signal Field
PME
PMU
PN
Physical Medium Entities
Power Management Unit
Packet Number
Medium Access Control
Microcontroller Unit
Modulation and Coding Scheme
Management Data Clock
Management Data Input/Output
Memory
PROM
PSDU
PSI
Programmable Read-Only Memory
Physical layer Service Data Unit
Power supply Strength Indication
Power Save Mode
PSM
PTN
QoS
RDG
RAM
RF
MCS Feedback
Packet Transport Network
Quality of Service
MFB Sequence
Message Integrity Code
Multiple-Input Multiple-Output
Monolithic Low Noise Amplifier
Mixed Mode
Reverse Direction Grant
Random Access Memory
Radio Frequency
MIMO
MLNA
MM
RGMII
Reduced Gigabit Media Independent
Interface
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Abbrev.
RH
Description
Abbrev.
TKIP
Description
Relative Humidity
Temporal Key Integrity Protocol
Tx/Rx Switch
RoHS
ROM
RSSI
Restriction on Hazardous Substances
Read-Only Memory
TRSW
TSF
Timing Synchronization Function
Transmit Signal Strength Indication
Transmit
Received Signal Strength Indication
(Indicator)
TSSI
Tx
RTS
Request to Send
TxBF
TXD
Transmit Beamforming
Transmitted Data
RvMII
Rx
Reverse Media Independent Interface
Receive
TXDAC
TXINFO
TXOP
TXWI
UART
USB
Transmit Digital-Analog Converter
Transmit Information
Opportunity to Transmit
Tx Wireless Information
Universal Asynchronous Rx/ Tx
Universal Serial Bus
RXD
Received Data
RXINFO
RXWI
S
Receive Information
Receive Wireless Information
Stream
SDXC
SDIO
SDRAM
Secure Digital eXtended Capacity
Secure Digital Input Output
UTIF
VGA
Universal Test Interface
Variable Gain Amplifier
Voltage Controlled Amplifier
High Level Input Voltage
Low Level Input Voltage
Voice over IP
Synchronous Dynamic Random Access
Memory
VCO
SEC
Security
VIH
SGI
Short Guard Interval
VIL
SIFS
SoC
Short Inter-Frame Space
System-on-a-Chip
VoIP
WCID
WEP
WI
Wireless Client Identification
Wired Equivalent
SPI
Serial Peripheral Interface
Static Random Access Memory
Spread Spectrum Clock Generator
Space–Time Block Code
Switch Regulator
SRAM
SSCG
STBC
SW
Wireless Information
Wireless Information Valid
Wi-Fi Multimedia
WIV
WMM
WPA
WPDMA
Wi-Fi Protected Access
TA
Transmitter Address
Wireless Polarization Division Multiple
Access
TBTT
TDLS
Target Beacon Transmission Time
Tunnel Direct Link Setup
WS
Word Select
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
5. Revision History
Rev
1.0
1.1
1.2
1.3
Date
Description
2012/07/09
2012/07/18
2012/08/20
2012/09/12
Initial Release
Update SPI_WP/SPI_HOLD GPO table
Fix DRQFN internal pad size typo
Add IR reflow guideline
This product is not designed for use in medical and/or life support applications. Do not use this product in these
types of equipment or applications. This document is subject to change without notice and Ralink assumes no
responsibility for any inaccuracies that may be contained in this document. Ralink reserves the right to make
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Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
changes in its products to improve function, performance, reliability, and to attempt to supply the best product
possible.
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