MTD502EF_技术文档

MYSON

MTD502E

TECHNOLOGY

2 Port 10M/100M Switch With Build_in Memory

FEATURES

GENERAL DESCRIPTION

•

IEEE802.3 and IEEE802.3u compliant.

Single chip, low cost, two port switch controller. 100M two port switch controller with build_in

Build_in embedded memory on chip for packet

buffering.

Provide 2 MII/RMII (Reduced Media Indepen-

dent Interface) ports.

The MTD502E is a highly integrated, 10M/

embedded memory. It supports 2 MII/RMII ports

for 10M/100M operation, and both can operate

under half or full duplex mode.

•

The MTD502E is an ideal solution for two

A flexible MII interface design can directly con- port bridge or dual speed hub application, and no

nect with standard MII or pseudo MII.

Support half/full duplex operation per port.

Optional back_pressure control for half_duplex

mode.

need any external memory buffers in application

design. The flexible MII interface design can

directly connect with pseudo MII interface

(Am79c901, HomePNA PHY).

•

Provide “store and forward” switching, and for-

warding rate at full_wire speed.

Support up to 2048 MAC addresses filtering

database, and automatical address aging_out

function (300 secs).

Low power CMOS design, with single 3.3V

supply voltage, 50 MHZ operation.

Provide 128 pin PQFP package (MTD502EF),

and 80 pin LQFP package (MTD502EG).

The MTD502E provides packet forward-

ing, address filtering, learning, and aging func-

tion, and have an optional back_presure control

implemented in half duplex mode.

The MTD502E supports an effective

address filtering database, which can recognize

up to 2048 MAC addresses. It also support an

automatical aging function for address table

updating (aging time is 300 secs default).

•

BLOCK DIAGRAM

MAC0

MAC1

MII0

MII1

Port0 DMA

Embedded Memory

Port1 DMA

Two

Port

Switch

Engine

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification

without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of

the product.

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MYSON

MTD502E

TECHNOLOGY

SYSTEM DIAGRAM

1). Two Port Switch Application (HomePNA to LAN)

MTD502E

MII1

MII0

HomePNA

PHYsceiver

10M/100M

PHYsceiver

Transformer

RJ45

RJ11

2). Dual Speed Hub Application

MTD502E

10M/100M

Repeater

10M/100M

Repeater

(Without 2P_sw)

.......

Expansion Bus

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification

without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of

the product.E

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MYSON

MTD502E

TECHNOLOGY

1.0 PIN CONNECTION (under MII mode)

1) 128 Pin PQFP (MTD502EF)

VCC

NC

GND

NC

103

104

105

106

107

108

109

110

111

112

113

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

SPEED1

COL1

CRS1

RXDV1

GND

VCC

RXD1_3

RXD1_2

NC

CLK25OUT 114

FULL1

RXD1_1

RXD1_0

NC

115

116

117

118

119

120

121

122

123

124

125

126

127

128

NC

GND

NC

MTD502EF

NC

RXC1

GND

VCC

SYSCLK

GND

NC

VCC

NC

TXC1

TXEN1

TXD1_0

TXD1_1

NC

RSTB

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MTD502E

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2) 80 Pin LQFP (MTD502EG)

NC

61

62

63

64

65

66

67

68

69

70

71

40 COL1

39 CRS1

38 RXDV1

37 GND

VCC

NC

GND

NC

36 VCC

NC

35 RXD1_3

34 RXD1_2

33 NC

NC

32 FULL1

31 RXD1_1

30 RXD1_0

29 RXC1

28 TXC1

27 TXEN1

26 TXD1_0

25 TXD1_1

24 NC

NC

MTD502EG

NC

CLK25OUT 72

VCC

73

74

75

76

77

78

79

80

SYSCLK

NC

RSTB

LINK0

TXD0_3

VCC

23 TXD1_2

22 TXD1_3

21 LINK1

TXD0_2

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MTD502E

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2.0 PIN DESCRIPTIONS

MTD502EF (128PQFP) Pin Definition Mapping Under Different Configurations

MII

mode

Phy_MII Rmii Phy_Rm

Pin No. I/O

Descriptions

mode

mode ii mode

1

I

LINK0

(NC)

LINK0

(NC) Pin 1~32 for Port0, suitable for connecting with 10/

100PHY , RISC_CPU, Switch,....

2

O

TXD0_3 RXD0_3

(NC)

3

VCC

4

O

TXD0_2 RXD0_2

(NC)

5

O

(NC)

CRS0

(NC)

6~8

9

I

O

TXD0_1 RXD0_1

TXD0_0 RXD0_0

TXEN0 RXDV0

10

11

12

13

14

15

16

17

18

19

20

21

22~24

25

26

27

28

29

30

31

32

33

O

I

TXC0

(NC)

I

GND

I

RXC0

(NC)

CRSDV0 TXEN0

O

RXC0 TXD0_1 RXD0_1

COL0 TXD0_0 RXD0_0

O

TXC0

TXEN0 CRSDV0

I

RXD0_0 TXD0_0 RXD0_0 TXD0_0

RXD0_1 TXD0_1 RXD0_1 TXD0_1

I

FULL0 FULL0 FULL0

(NC)

O

(NC)

I

RXD0_2 TXD0_2

RXD0_3 TXD0_3

RXDV0 TXEN0

I

CRS0 SPEED0 SPEED0

I

COL0

(NC)

SPEED0

VCC

GND

I

LINK1

(NC)

LINK1

(NC) Pin 33~64 for Port1, suitable for connecting with

HomePNA PHY.

34

O

TXD1_3

TXD1_2

(NC)

35

O

36

O

(NC)

37,38

39

I

(NC)

I

O

(NC)

CRSDV1

TXD1_1

TXD1_0

TXEN1

RXD1_0

RXD1_1

40

TXD1_1

TXD1_0

TXEN1

TXC1

41

O

42

O

43

I

44

I

(NC)

45

VCC

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MTD502E

TECHNOLOGY

MTD502EF (128PQFP) Pin Definition Mapping Under Different Configurations

MII

mode

Phy_MII Rmii Phy_Rm

Pin No. I/O

Descriptions

mode

mode ii mode

46

GND

47

I

RXC1

(NC)

FULL1

(NC)

48~50

51

O

I

RXD1_0

RXD1_1

FULL1

(NC)

52

I

(NC)

53

I

SPEED1

(NC)

54~56

57

O

I

RXD1_2

RXD1_3

(NC)

58

I

VCC

GND

I

(NC)

59

60

61

RXDV1

CRS1

(NC)

62

I

63

I

COL1

64

I

SPEED1

(NC)

65~66

67

I

VCC

IO

VCC

IO

GND

IO

I

*

68~71

72

(NC)

73

74

75,76

77~79

80

(NC)

O

81

IO

GND

IO

I

82

83~85

86~88

89

(NC)

O

(NC)

90

IO

Co1_D

Co1_D Port1: COL LED display, low_active. *

when in half duplex mode: this LED pin present

port1’s collision event.

91

IO

Co0_D

Co0_D Port0: COL LED display, low_active. *

when in half duplex mode: this LED pin present

port0’s collision event.

92

93

GND

IO FdCo1_D FdCo1_D FdCo1_D FdCo1_D Port1: FULL/COL LED display, low_active. *

when in full duplex mode: this LED pin is always in

low_active.

when in half duplex mode: this LED pin present

port1’s collision event, using flash style for display.

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MTD502E

TECHNOLOGY

MTD502EF (128PQFP) Pin Definition Mapping Under Different Configurations

MII

mode

Phy_MII Rmii Phy_Rm

mode mode ii mode

Pin No. I/O

Descriptions

94

IO FdCo0_D FdCo0_D FdCo0_D FdCo0_D Port0: FULL/COL LED display, low_active. *

when in full duplex mode: this LED pin is always in

low_active.

when in half duplex mode: this LED pin present

port0’s collision event, using flash style for display.

95

IO LnAc1_D LnAc1_D LnAc1_D LnAc1_D Port1: Link_Activity LED display, low_active. *

when in Link_On state : this LED pin is always in

low_active.

when have Tx or Rx activity in this port : this LED

pin present port1’s Tx/Rx activity, using flash style

for display.

96

97

98

IO LnAc0_D LnAc0_D LnAc0_D LnAc0_D Port0: Link_Activity LED display, low_active. *

when in Link_On state : this LED pin is always in

low_active.

when have Tx or Rx activity in this port : this LED

pin present port0’s Tx/Rx activity, using flash style

for display.

IO LnRx1_D LnRx1_D LnRx1_D LnRx1_D Port1: Link_Rx LED display, low_active. *

when in Link_On state : this LED pin is always in

low_active.

when have Rx activity in this port : this LED pin

present port1’s Rx activity, using flash style for dis-

play.

IO LnRx0_D LnRx0_D LnRx0_D LnRx0_D Port0: Link_Rx LED display, low_active. *

when in Link_On state : this LED pin is always in

low_active.

when have Rx activity in this port : this LED pin

present port0’s Rx activity, using flash style for dis-

play.

99~102

103

IO

VCC

IO

(NC)

104

105

GND

106~110 IO

(NC)

P0MDIO

P0MDC

(NC)

P0MDIO

P0MDC

(NC)

111

112

113

114

IO

IO CLK25O CLK25O CLK25O CLK25O clock 25Mhz output.

115~116 IO

(NC)

117

GND

118~120 IO

121

122

123

VCC

I

SYSCLK SYSCLK SYSCLK SYSCLK system clock input, 50Mhz operation.

GND

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MYSON

MTD502E

TECHNOLOGY

MTD502EF (128PQFP) Pin Definition Mapping Under Different Configurations

MII

mode

Phy_MII Rmii Phy_Rm

Pin No. I/O

Descriptions

mode

mode ii mode

124~127 IO

(NC)

RSTB system resetb input, low_active.

128

I

RSTB

note: input signal LINK,SPEED,FULL from PHY device are low_active definnition.

MTD502EF(128PQFP) Jumper Setting Table After Power On Reset

Pin No. IO

IO

Setting Function

Descriptions

5

2P_Sw Enable

Jumper setting function after power on reset.

-external pull_high = 1, means enter 2 port switch mode.

-external pull_low = 0, means an internal test mode.

-external floating : default is 0.

For MTD502E application, this pin must always use “external

pull_hgih” for well operation.

18

IO Back Pressure Disable Jumper setting function after power on reset.

-external pull_high = 1, means back_pressure function ( under

half_duplex) is disabled for two ports both.

-external pull_low = 0, means back_pressure function enable.

-external floating : default is 0.

95

IO

P1_Rmii Enable

P0_Rmii Enable

Jumper setting function after power on reset.

-external pull_high = 1, means Port 1 RMII interface enable..

-external pull_low = 0, means Port 1 is MII interface.

-external floating : default is 0.

97

Jumper setting function after power on reset.

-external pull_high = 1, means Port 0 RMII interface enable..

-external pull_low = 0, means Port 0 is MII interface.

-external floating : default is 0.

98

IO P0_Phy_Mode Enable Jumper setting function after power on reset.

-external pull_high = 1, means Port 0 interrface enter PHY mode.

-external pull_low = 0, means Port 0 interface is using MAC mode.

-external floating : default is 0.

100

IO

P1_Bkoff_4 Enable Jumper setting function after power on reset.

-external pull_high = 1, means Port 1 MAC backoff engine is using

limit_4 modified method.

-external pull_low = 0, means Port 1 MAC backoff engine is using

specification defined method.

-external floating : default is 0.

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MTD502E

TECHNOLOGY

MTD502EF(128PQFP) Jumper Setting Table After Power On Reset

Setting Function Descriptions

P0_Bkoff_4 Enable Jumper setting function after power on reset.

-external pull_high = 1, means Port 0 MAC backoff engine is using

Pin No. IO

101

IO

limit_4 modified method.

-external pull_low = 0, means Port 0 MAC backoff engine is using

specification defined method.

-external floating : default is 0.

102

104

106

107

108

109

IO

DeviceID[4]

DeviceID[3]

DeviceID[2]

DeviceID[1]

DeviceID[0]

Jumper setting function after power on reset.

-external pull_high = 1.

-external pull_low = 0.

-external floating : default is 0.

Jumper setting function after power on reset.

-external pull_high = 1.

-external pull_low = 0.

-external floating : default is 0.

Jumper setting function after power on reset.

-external pull_high = 1.

-external pull_low = 0.

-external floating : default is 0.

Jumper setting function after power on reset.

-external pull_high = 1.

-external pull_low = 0.

-external floating : default is 0.

Jumper setting function after power on reset.

-external pull_high = 1.

-external pull_low = 0.

-external floating : default is 0.

P1_CRCchk Disable Jumper setting function after power on reset.

-external pull_high = 1, means Port1 CRC check and drop function

is disabled.

-external pull_low = 0, means Port1 CRC check and drop function

is enabled.

-external floating : default is 0.

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MTD502E

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MTD502EF(128PQFP) Jumper Setting Table After Power On Reset

Setting Function Descriptions

P0_CRCchk Disable Jumper setting function after power on reset.

-external pull_high = 1, means Port0 CRC check and drop function

Pin No. IO

110

IO

is disabled.

-external pull_low = 0, means Port0 CRC check and drop function

is enabled.

-external floating : default is 0.

126

IO

VLAN tag Enable

Jumper setting function after power on reset.

-external pull_high = 1, means MAC receiving accept 1522 Bytes

packet (VLAN tag enable).

-external pull_low = 0, means MAC receiving reject 1522 Bytes

packet (VLAN tag disable).

-external floating : default is 0.

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3.0 MTD502EG (80LQFP) PIN DESCRIPTIONS

MTD502EG(80LQFP) Pin Definition Mapping Under Different Configurations

MII

mode

Phy_MII Rmii Phy_Rm

Pin No. I/O

Descriptions

mode

mode ii mode

1

O

(NC)

CRS0

(NC)

(NC) Pin 77~80, 1~20 for Port0, suitable for

connecting with 10/100PHY ,

RISC_CPU, Switch,....

2

O

TXD0_1 RXD0_1

TXD0_0 RXD0_0

TXEN0 RXDV0

(NC)

3

O

4

O

5

I

TXC0

(NC)

6

GND

7

I

O

I

RXC0

(NC)

CRSDV0 TXEN0

8

RXC0 TXD0_1 RXD0_1

COL0 TXD0_0 RXD0_0

9

10

11

12

13

14

15

16

17

18

19

20

21

TXC0

TXEN0 CRSDV0

RXD0_0 TXD0_0 RXD0_0 TXD0_0

RXD0_1 TXD0_1 RXD0_1 TXD0_1

I

FULL0 FULL0 FULL0

(NC)

O

I

(NC)

RXD0_2 TXD0_2

RXD0_3 TXD0_3

RXDV0 TXEN0

I

CRS0

COL0

SPEED0 SPEED0

I

(NC)

I

SPEED0

LINK1

I

(NC) Pin 21~41 for Port1, suitable for con-

necting with HomePNA PHY.

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

O

TXD1_3

TXD1_2

(NC)

O

TXD1_1

TXD1_0

TXEN1

TXC1

O

I

RXC1

I

RXD1_0

RXD1_1

FULL1

(NC)

I

O

I

RXD1_2

RXD1_3

I

VCC

GND

I

RXDV1

CRS1

(NC)

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MTD502E

TECHNOLOGY

MTD502EG(80LQFP) Pin Definition Mapping Under Different Configurations

MII

mode

Phy_MII Rmii Phy_Rm

Pin No. I/O

Descriptions

mode

mode ii mode

40

41

42

43

44

45

46

47

48

49

I

COL1

(NC)

VCC

I

*

SPEED1

(NC)

VCC

GND

IO

Co1_D

Co0_D

Co1_D

Co0_D

Co1_D

Co0_D

Co1_D Port1: COL LED display, low_active. *

when in half duplex mode: this LED pin

present port1’s collision event.

50

IO

Co0_D Port0: COL LED display, low_active. *

when in half duplex mode: this LED pin

present port0’s collision event.

51

52

53

GND

IO FdCo1_D FdCo1_D FdCo1_D FdCo1_D Port1: FULL/COL LED display,

low_active. *

when in full duplex mode: this LED pin

is always in low_active.

when in half duplex mode: this LED pin

present port1’s collision event, using

flash style for display.

54

55

IO FdCo0_D FdCo0_D FdCo0_D FdCo0_D Port0: FULL/COL LED display,

low_active. *

when in full duplex mode: this LED pin

is always in low_active.

when in half duplex mode: this LED pin

present port0’s collision event, using

flash style for display.

IO LnAc1_D LnAc1_D LnAc1_D LnAc1_D Port1: Link_Activity LED display,

low_active. *

when in Link_On state : this LED pin is

always in low_active.

when have Tx or Rx activity in this port

: this LED pin present port1’s Tx/Rx

activity, using flash style for display.

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TECHNOLOGY

MTD502EG(80LQFP) Pin Definition Mapping Under Different Configurations

MII

mode

Phy_MII Rmii Phy_Rm

mode mode ii mode

Pin No. I/O

Descriptions

56

57

58

IO LnAc0_D LnAc0_D LnAc0_D LnAc0_D Port0: Link_Activity LED display,

low_active. *

when in Link_On state : this LED pin is

always in low_active.

when have Tx or Rx activity in this port

: this LED pin present port0’s Tx/Rx

activity, using flash style for display.

IO LnRx1_D LnRx1_D LnRx1_D LnRx1_D Port1: Link_Rx LED display,

low_active. *

when in Link_On state : this LED pin is

always in low_active.

when have Rx activity in this port : this

LED pin present port1’s Rx activity,

using flash style for display.

IO LnRx0_D LnRx0_D LnRx0_D LnRx0_D Port0: Link_Rx LED display,

low_active. *

when in Link_On state : this LED pin is

always in low_active.

when have Rx activity in this port : this

LED pin present port0’s Rx activity,

using flash style for display.

59-61

62

IO

VCC

IO

GND

IO

O

(NC)

63

64

65-69

70

(NC)

P0MDIO

P0MDC

P0MDIO

P0MDC

71

72

CLK25O CLK25O CLK25O CLK25O clock 25Mhz output.

73

VCC

I

74

SYSCLK SYSCLK SYSCLK SYSCLK system clock input, 50Mhz operation.

75

IO

I

(NC)

RSTB

LINK0

(NC)

RSTB

(NC)

RSTB

LINK0

(NC)

76

RSTB system resetb input, low_active.

77

I

(NC)

78

O

TXD0_3 RXD0_3

79

VCC

O

80

TXD0_2 RXD0_2

(NC)

note: input signal LINK,SPEED,FULL from PHY device are low_active definnition.

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MTD502EG(80LQFP) Jumper Setting Table After Power On Reset

Pin No. IO

IO

Setting Function

Descriptions

1

2P_Sw Enable

Jumper setting function after power on reset.

-external pull_high = 1, means enter 2 port switch mode.

-external pull_low = 0, means an internal test mode.

-external floating : default is 0.

For MTD502E application, this pin must always use “external

pull_hgih” for well operation.

10

IO Back Pressure Disable Jumper setting function after power on reset.

-external pull_high = 1, means back_pressure function ( under

half_duplex) is disabled for two ports both.

-external pull_low = 0, means back_pressure function enable.

-external floating : default is 0.

57

58

59

IO

P0_Rmii Enable

Jumper setting function after power on reset.

-external pull_high = 1, means Port 0 RMII interface enable..

-external pull_low = 0, means Port 0 is MII interface.

-external floating : default is 0.

IO P0_Phy_Mode Enable Jumper setting function after power on reset.

-external pull_high = 1, means Port 0 interrface enter PHY mode.

-external pull_low = 0, means Port 0 interface is using MAC mode.

-external floating : default is 0.

IO

P1_Bkoff_4 Enable Jumper setting function after power on reset.

-external pull_high = 1, means Port 1 MAC backoff engine is using

limit_4 modified method.

-external pull_low = 0, means Port 1 MAC backoff engine is using

specification defined method.

-external floating : default is 0.

60

61

P0_Bkoff_4 Enable Jumper setting function after power on reset.

-external pull_high = 1, means Port 0 MAC backoff engine is using

limit_4 modified method.

-external pull_low = 0, means Port 0 MAC backoff engine is using

specification defined method.

-external floating : default is 0.

DeviceID[4]

Jumper setting function after power on reset.

-external pull_high = 1.

-external pull_low = 0.

-external floating : default is 0.

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MTD502EG(80LQFP) Jumper Setting Table After Power On Reset

Pin No. IO

Setting Function

Descriptions

63

65

66

67

68

IO

DeviceID[3]

Jumper setting function after power on reset.

-external pull_high = 1.

-external pull_low = 0.

-external floating : default is 0.

DeviceID[2]

DeviceID[1]

DeviceID[0]

Jumper setting function after power on reset.

-external pull_high = 1.

-external pull_low = 0.

-external floating : default is 0.

Jumper setting function after power on reset.

-external pull_high = 1.

-external pull_low = 0.

-external floating : default is 0.

Jumper setting function after power on reset.

-external pull_high = 1.

-external pull_low = 0.

-external floating : default is 0.

P1_CRCchk Disable Jumper setting function after power on reset.

-external pull_high = 1, means Port1 CRC check and drop function

is disabled.

-external pull_low = 0, means Port1 CRC check and drop function

is enabled.

-external floating : default is 0.

69

71

IO

P0_CRCchk Disable Jumper setting function after power on reset.

-external pull_high = 1, means Port0 CRC check and drop function

is disabled.

-external pull_low = 0, means Port0 CRC check and drop function

is enabled.

-external floating : default is 0.

VLAN tag Enable

Jumper setting function after power on reset.

-external pull_high = 1, means MAC receiving accept 1522 Bytes

packet (VLAN tag enable).

-external pull_low = 0, means MAC receiving reject 1522 Bytes

packet (VLAN tag disable).

-external floating : default is 0.

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MTD502E

TECHNOLOGY

4.0 FUNCTIONAL DESCRIPTIONS

The MTD502E implements a 10/100M two port switch for 10M/100M packet switching. Total 2K

address entrys are provided for packets’ SA learning and DA routing; and also provide automatic aging

function ( aging time = 300secs). When using in two port bridge application, the input packets from

port0 will be stored in an embedded memory buffers of MTD502E first, while packets is good for for-

warding ( CRC chech ok, 64Bytes < length > 1518Bytes, and not local packets ) , than forward this

packet to port1.

4.1 Learning and Routing

The MTD502E supports 2K MAC entries for filtering. Dynamic address learning is performed by each

good unicast packet is completely received. The routing process is performed whenever the packet’s

DA is captured. If the DA get a hit result in self port’s address table, this packet will be treated as a “

local packet”, and then drop the packet forwarding to the other port. On the other hand, if this packet is

not a “local packet”, then will be forwarded to the other port.

4.2 Aging

The address entries are scheduled in the aging machine. If one station does not transmit any packet for

a period of time, the belonging MAC address will be kicked out from the address table. The aging out

time value is 300 seconds.

4.3 Buffer Queue Management

The buffer queue manager is implemented to manage the embedded memory packet buffering. The

main function of the buffer queue manager is to maintain the linked list consists of buffer IDs, which is

used to show the corresponding memory address for each incoming packet. In addition, the buffer

queue manager monitors the rested free spaces status of the memory buffers, If the packet storage

achieve the predefined threshold value, the buffer queue manager will raise the alarm signal which is

used to enable the flow control mechanism for avoiding transmission ID queue overflow happening.

MTD502E provide back pressure control scheme in half duplex mode.

4.4 Half Duplex Back Pressure Control

In half duplex mode, MTD502E provide a back pressure control mechanism to avoid dropping packets

during network conjection situation. When the “back pressure control enable” bit is set during power on

reset (pin_18 is external pull_low), it enables MTD502E supporting back pressure function in

half_duplex mode; When output port buffer queue’s on_using value reach the initialization setting

threshold value, MTD502E will send a JAM pattern in the input port when it senses an incoming packet

, thus force a collision to inform the remote node transmission back off and will effectively avoid drop-

ping packets. If the “back pressure control disable” bit is set, and there is no free buffer queue available

for the incoming packets, the incoming packets will be dropped.

4.5 MAC and DMA engine

The MTD502E’s MAC performs all the functions in IEEE802.3 protocol, such as frame formatting,

frame stripping, CRC checking, bad packet dropping, defering to line traffic, and collision handling. The

MAC Rx_engine checks incoming packets and drops the bad packet which include CRC error, align-

ment error, short packet (less than 64 bytes), and long packet(more than 1518 bytes or 1522 bytes

when the “VLAN tag 1522 bytes receive enable” bit is set during power on reset). Before transmission,

The MAC Tx_engine will constantly monitor the line traffic using derfering precedure. Only if it has been

idle for a 96 bits time (a minimum interpacket gap time, IPG time), actual transmmission can be started.

For the half duplex mode, MAc engine will detect collision; if a collision is detected, the MAC Tx_engine

will transmit a JAM pattern and then delay the re_transmission for a random time period determined by

the back_off algorithm (MTD502E implements the truncated exponential back_off algorithm defined in

IEEE 802.3 standard). For the full duplex mode, collision signal is ignored.

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MTD502E

TECHNOLOGY

5.0 Electrical Characteristics

5.1 Absolute Maximum Ratings

Symbol

Parameter

Power Supply Voltage

Input Voltage

RATING

-0.3 to 3.6

Unit

V

V_CC

V_IN

-0.3 to Vcc+0.3

-55 to 150

V

V_OUT

T_STG

Output Voltage

V

^oC

Storage Temperature

5.2 Recommended Operating Conditions

Symbol

Parameter

Min.

3.0

0

Typ.

3.3

-

Max.

3.6

Unit

V

V_CC

Power Supply

Input Voltage

V_IN

Vcc

115

V

^oC

Commercial Junction Operating Temperature

Industrial Junction Operating Temperature

0

25

T_j

-40

25

125

5.3 DC Electrical Characteristics

Symbol

Parameter

Input Leakage Current

Tri-state Leakage Current

Input Capacitance

Conditions

Min.

Typ.

Max.

Unit

uA

pF

V

I_IL

no pull-up or down

-1

1

I_OZ

C_IN

2.8

C_OUT

C_BID3

V_IL

Output Capacitance

2.7

4.9

Bi-direction buffer Capacitance

Input Low Voltage

CMOS

0.3*Vcc

V_IH

Input High Voltage

CMOS

0.7*Vcc

2.4

V

V_OH

V_OL

R_I

I_OL=2,4,8,12,16,24mA

I_OH=2,4,8,12,16,24mA

V_IL=0V or V_IH=V_CC

Output High Voltage

Output Low Voltage

0.4

V

Input Pull-up/down resistance

75

KOhm

(Under recommended operating conditions and Vcc = 3.0 ~ 3.6V, Tj = 0 to +115 ^oC)

17/20

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MTD502E

TECHNOLOGY

5.4 Electrical Characteristics

FIGURE 1. MII timing

T5

RXCLK0

T6

Valid

CRS0/RXDV0

RXD0[3:0]

TXCLK0

T7

T8

Valid

TXEN0

TXD0[3:0]

Symbol

Parameter

MII input setup time

Min.

10

3

Typ.

Max.

Unit

Note

T5

T6

T7

T8

nS

MII input hold time

MII output setup time

MII output hold time

5

FIGURE 2. RMII timing

T1

T3

REFCLK

T2

Valid

T4

Valid

CRSDV

RXD[1:0]

TXEN

TXD[1:0]

Symbol

T1

Parameter

RMII input setup time

RMII input hold time

RMII output setup time

RMII output hold time

Min.

Typ.

Max.

Unit

nS

Note

1

3

5

T2

nS

T3

nS

T4

nS

18/20

MTD502E Revision 1.3 12/07/2000

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MTD502E

TECHNOLOGY

6.0 128 pin PQFP Package Data

Dimension in inch

Min Norm Max

Dimension in mm

Symbol

D

1

Min Norm Max

A

A1

A2

B

-

0.134

-

3.40

-

D

0.010

0.25

102

65

0.107 0.112 0.117 2.73 2.85 2.97

0.007 0.009 0.011 0.17 0.22 0.27

103

64

C

0.004

-

0.008 0.09

-

0.20

D

0.906 0.913 0.921 23.00 23.20 23.40

0.783 0.787 0.791 19.90 20.00 20.10

0.669 0.677 0.685 17.00 17.20 17.40

0.547 0.551 0.555 13.90 14.00 14.10

D

1

E

1

e

L

0.020 BSC

0.50 BSC

0.029 0.035 0.041 0.73 0.88 1.03

L1

y

0.063 BSC

1.60 BSC

128

39

-

0.004

-

0.10

o

z

0

7

0

7

1

38

e

B

Note:

1.Dimension D1 & E1 do not include mold protrusion.

But mold mismatch is included. Allowable protrusion is .25mm/.010” per side.

2.Dimension B does not include dambar protrusion. Allowable dambar protru-

sion .08mm/.003”. Total in excess of the B dimemsion at maximum material

condition. Dambar cannot be located on the lower radius or the foot.

3.Controlling dimension : Millimeter.

y

See Detail B

See Detail A

Seating Plane

B

With Plating

Gage Plane

L

z

Base Metal

L1

Detail A

Detail B

19/20

MTD502E Revision 1.3 12/07/2000

MYSON

MTD502E

TECHNOLOGY

7.0 80 pin LQFP Package Data

Dimension in inch

Min Norm Max

Dimension in mm

Symbol

D

Min Norm Max

1

A

A1

A2

b

-

0.063

-

1.60

0.15

1.45

0.002

0.006 0.05

60

41

0.053 0.055 0.057 1.35

1.4

61

40

0.007 0.009 0.011 0.17 0.22 0.27

0.007 0.008 0.009 0.17 0.20 0.23

b

1

C

0.004

-

0.008 0.09

0.006 0.09

-

0.20

0.16

C

1

-

D

0.551 BSC

0.472 BSC

0.551 BSC

0.472 BSC

0.020 BSC

14.00 BSC

12.00 BSC

14.00 BSC

12.00 BSC

0.50 BSC

D

1

E

80

21

E

1

20

e

L

e

b

0.018 0.024 0.030 0.45 0.60 0.75

L

1

0.039 REF

1.00 REF

R

1

0.003

-

0.08

-

R

2

0.008 0.08

0.2

See Detail B

See Detail A

Seating Plane

b

R

1

R

2

b

1

With Plating

Gage Plane

L

Base Metal

L1

Detail A

Detail B

20/20

MTD502E Revision 1.3 12/07/2000


型号：	MTD502EF
厂家：	ETC
描述：	2 Port 10M/100M Switch With Build_in Memory 2端口10M / 100M交换机采用Build_in记忆
文件：	总20页 (文件大小：195K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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