NCP1205/D_技术文档

NCP1205

Single Ended PWM

Controller Featuring QR

Operation and Soft

Frequency Foldback

The NCP1205 combines a true Current Mode Control modulator

and a demagnetization detector to ensure full Discontinuous

Conduction Mode in any load/line conditions and minimum drain

voltage switching (Quasi−Resonant operation, also called critical

conduction operation). With its inherent Variable Frequency Mode

(VFM), the controller decreases its operating frequency at constant

peak current whenever the output power demand diminishes.

Associated with automatic multiple valley switching, this unique

architecture guarantees minimum switching losses and the lowest

power drawn from the mains when operating at no−load conditions.

Thus, the NCP1205 is optimal for applications targeting the newest

International Energy Agency (IEA) recommendations for standby

power.

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MARKING

DIAGRAMS

8

NCP1205P

AWL

PDIP−8

N SUFFIX

CASE 626

YYWW

8

1

The internal High−Voltage current source provides a reliable

14

charging path for the V capacitor and ensures a clean and short

CC

PDIP−14

P SUFFIX

CASE 646

NCP1205P2

AWLYYWW

start−up sequence without deteriorating the efficiency once off.

The continuous feedback signal monitoring implemented with an

Over−Current fault Protection circuitry (OCP) makes the final design

rugged and reliable. The DIP14 offers an adjustable version of the OVP

threshold via an external resistive network.

14

16

1

16

Features

SO−16

D SUFFIX

CASE 751B

• Natural Drain Valley Switching for Lower EMI and Quasi−Resonant

Operation (QR)

• Smooth Frequency Foldback for Low Standby and Minimum Ripple

at Light−Load

1205

AWLYYWW

1

• Adjustable Maximum Switching Frequency

• Internal 200 ns Leading Edge Blanking on Current Sense

• 250 mA Sink and Source Driver

• Wide Operating Voltages: 8.0 to 30 V

• Wide UVLO Levels: 7.2 to 15 V Typical

• Auto−Recovery Internal Short−Circuit Protection (OCP)

• Integrated 3.0 mA Typ. Start−Up Source

• Current Mode Control

A

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

ORDERING INFORMATION

Device

Package

PDIP−8

PDIP−14

SO−16

Shipping

50 Units/Rail

NCP1205P

• Adjustable Over−Voltage Level

• Available in DIP8, DIP14 and SO16 Packages

NCP1205P2

NCP1205DR2

25 Units/Rail

2400/Tape & Reel

Applications

• High Power AC/DC Adapters for Notebooks, etc.

• Offline Battery Chargers

• Power Supplies for DVD, CD Players, TVs, Set−Top Boxes, etc.

• Auxiliary Power Supplies (USB, Appliances, etc.)

Semiconductor Components Industries, LLC, 2003

1

Publication Order Number:

September, 2003 − Rev. 4

NCP1205/D

NCP1205

PIN CONNECTIONS

HV

NC

16

1

2

3

4

5

6

7

15 NC

HV

NC

1

2

3

4

5

6

7

14

V

NC

Demag

FB

13 V

CC

Drive

Isense

GND

NC

13

12

11

10

9

Demag

FB

Drive

Isense

GND

NC

12

11

10

9

HV

Demag

FB

V

CC

1

2

3

4

8

7

6

5

Drive

Isense

GND

Ct

OVP

NC

OVP

NC

Ct

NC

8

NC

8

PDIP−14

PDIP−8

SO−16

PIN FUNCTION DESCRIPTION

Pin No.

DIP8

DIP14

SO16

Pin Name

Function

Start−up rail

Description

Connected to the rectified HV rail, this pin provides a

1

HV

charging path to V bulk capacitor.

CC

2

3

4

3

4

5

4

5

6

Demag

FB

Zero primary−current

detection

This pin ensures the re−start of the main switcher when

operating in free−run.

Feedback signal to

control the PWM

This level modulates the peak current level in free−running

operation and modulates the frequency in VFM operation.

Ct

Timing capacitor

By adding a capacitor from Ct to the ground, the user selects

the minimum/maximum operating frequency.

5

10

6

11

7

Gnd

The IC’s ground

−

NA

OVP

Overvoltage input

By applying a 2.8 V typical level on this pin, the IC is

permanently latched−off until V falls below UVLO .

CC

L

6

7

8

11

12

13

12

13

14

Isense

Drv

The primary−current

sensing pin

This pin senses the primary current via an external shunt

resistor.

This pin drives the

external switcher

The IC is able to deliver or absorb 250 mA peak currents

while delivering a clamped driving signal.

V

CC

Powers the IC

A positive voltage up to 30 V maximum can be applied upon

this pin before the IC stops.

1. DIP14 has different pinouts. Please see Pin Connections.

2. Pin 2, 7, 8, 9 and 14 are nonconnected on DIP14.

3. Pin 2, 3, 8, 9, 10, 15 and 16 are nonconnected on SO−16.

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2

NCP1205

R2 D2

150 1N4148

D6

1N5819

L2

10 µH

+

C1

C14

5 V

22 µF

10 µF

C10

+

C11

470 µF

4x1N4007

10 V

100 µF

10 V

R5

15

* R10

15 k

D7

5.1 V

R8

22 k

M2

MTD1N60E

R4

10

1

2

8

7

6

5

Universal Input

IC4

NCP1205P

3

4

SFH6156−2

R1

560

C12

1 nF

R6

4.7 k

R3

3.3

C13

1.5 nF Y1

* Please refer to the application information section regarding this element.

Figure 1. Typical Application Example for DIP8 Version

+

R2 D2

C1

15

1N4148

10 µF

D6

1N5819

L2

10 µH

+

C14

5 V

4x1N4007

33 µF/35 V

* R10

15 k

C10

+

C11

470 µF

10 V

47 µF

10 V

R5

15

NCP1205P2

R8

22 k

D7

4.3 V

M2

1

2

3

4

5

6

7

14

13

12

11

10

9

MTD1N60E

IC4

R4

6.8

Universal Input

SFH6156−2

R1

560

8

R6

R3

3.3

2.7 k

C12

1 nF

* Please refer to the application information section regarding this element.

Figure 2. Typical Application Example for DIP14 Version

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3

NCP1205

Startup

UVLO = 15 V

H

HV

1

2

3

4

8

7

6

5

V

CC

UVLO = 7.2 V

L

Last Pulse of Demag

Internal V

after 4 µs

CC

Internal Regulator

DRV

DEMAG ?

Rf

Demag

Internal Clamp

V

err

Max = 3 V

V

err

Min = 10 mV

Clock

−

+

Ri

Flip−Flop

R

I

Q

FB

sense

1/3

D

Driver

+

−

2.5 V

Current Comparator

Ct

Gnd

200 ns L.E.B

Over Current

Protection (OCP)

V(−) < 1.5 V

1 V

+

−

V

T

Feedback

= f (V )

err

CO

V

err

off

Max T = f (Ct)

off

Lasts more than 128 ms?

−−> Protection Circuitry

+

−

OVP

18 k

+

−

2.8 V

Figure 3. Internal Circuit Architecture for DIP8 Version

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4

NCP1205

V

CC

Pin 13

Startup

UVLO = 15 V

H

UVLO = 7.2 V

L

HV

NC

1

2

14

Internal V

CC

Last Pulse of Demag

Internal Regulator

after 4 µs

13 V

CC

3

12 DRV

DEMAG ?

Rf

Demag

Internal Clamp

V

err

Max = 3 V

V

err

Min = 10 mV

Clock

OVP

−

+

Ri

Flip−Flop

R

4

11 I

Q

FB

sense

1/3

D

Driver

+

−

2.5 V

Current Comparator

5

6

10

9

Ct

Gnd

NC

200 ns L.E.B

OVP

Over Current

Protection (OCP)

V(−) < 1.5 V

1 V

V

T

Feedback

= f (V )

err

CO

NC

V

err

7

8

+

−

off

Max T = f (Ct)

off

+

−

Lasts more than 128 ms?

−−> Protection Circuitry

OVP

18 k

+

2.8 V

−

2.0 k

Figure 4. Internal Circuit Architecture for DIP14 Version

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5

NCP1205

MAXIMUM RATINGS

Pin No.

DIP14

13

Value

DIP8

SO16

Min

Max

Rating

Symbol

Unit

V

Power Supply Voltage

8

14

V

in

−

30

Thermal Resistance Junction−to−Air

DIP8

DIP14

SO16

−

R

−

100

145

°C/W

q

JA

Operating Junction Temperature Range

Maximum Junction Temperature

−

T

−

−25 to +125

150

°C

J

T

Jmax

Storage Temperature Range

ESD Capability, HBM Model

ESD Capability, Machine Model

Demagnetization Pin Current

−

T

−

−60 to +150

2.0

°C

kV

V

stg

All Pins

2

All Pins

3

All Pins

4

−

200

−5.0/+10

mA

ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −25°C to +125°C, Max T = 150°C,

A

J

V

CC

= 12 V unless otherwise noted.)

Pin No.

DIP8

DIP14 SO16

Characteristics

Demagnetization Block

Input Threshold Voltage (V

Symbol

Min

Typ

Max

Unit

increasing)

2

3

4

Vth

50

−

65

30

85

−

mV

V

pin2

Hysteresis (V

decreasing)

V

H

pin2

Input Clamp Voltage

High State (I

Low State (I

= 3.0 mA)

= −3.0 mA)

VC

8.0

−0.9

10

−0.7

12

−0.5

pin2

H

L

Demag Propagation Delay

No Demag Signal Activation

−

2

−

3

−

4

−

100

−

300

4.0

10

350

8.0

−

ns

µs

pF

ns

−

Internal Input Capacitance at 1.0 V

C

−

pin2

Demag Propagation Delay with 22 kΩ External Resistor

−

100

370

480

Feedback Path

Input Impedance at V = 3.0 V

3

−

4

−

5

−

Zin

AV

−

50

−3.0

2.5

−

kΩ

−

FB

Internal Error Amplifier Closed Loop Gain

Internal Built−In Offset Voltage for Error Detection

Error Amplifier Level of VCO Take Over

CL

V

ref

2.2

−

2.8

−

V

−

1.0

V

Internal Divider from Internal Error Amp, Pin to Current Setpoint

−

3.0

−

Fault Detection Circuitry

Internal Over Current Level

−

6

−

7

WL

−

1.5

128

1.0

100

2.8

−

V

ms

s

L

Fault Time Duration to Latch Activation @ Ct = 1.0 ηF

Over Current Latch−Off Phase @ Ct = 1.0 ηF

−

Hysteresis when V goes back into Regulation

−

mV

V

FB

Overvoltage Protection Threshold for DIP14 and

SO−16 versions

OVP1

2.5

3.1

Current Sense Comparator

Input Bias Current @ 1.0 V

6

11

12

I

−

0.02

1.0

−

µA

V

IB

Maximum Current Setpoint

Minimum Current Setpoint

V

0.9

225

1.1

285

cl

V

min

250

mV

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6

NCP1205

ELECTRICAL CHARACTERISTICS (continued) (For typical values T = 25°C, for min/max values T = 25°C to +125°C,

A

J

Max T = 150°C, V = 12 V unless otherwise noted.)

J

CC

Pin No.

DIP8

DIP14 SO16

Characteristics

Symbol

Min

Typ

Max

Unit

Current Sense Comparator (continued)

Propagation Delay from Current Detection to Gate OFF State

6

11

12

T

−

200

250

−

ns

del

Leading Edge Blanking (LEB)

leb

Frequency Modulator

Minimum Frequency Operation @ Ct = 1.0 ηF and

4

5

6

F

−

0

−

kHz

min

V

CC

= 30 V

Maximum Frequency Operation @ Ct = 1.0 ηF and

= 30 V

F

max

90

110

125

V

CC

Minimum Ct Charging Current (Note 4)

Maximum Ct Charging Current (Note 4)

Discharge Time @ Ct = 1.0 ηF

4

5

6

I

min

−

280

−

0

−

420

−

µA

ns

Ct

I

Ct

max

−

350

500

Drive Output

Output Voltage Rise Time @ C = 1.0 ηF (DV = 10 V)

7

12

13

12

t

−

30

13

−

50

16

0.5

ns

V

L

r

Output Voltage Fall Time @ C = 1.0 ηF (DV = 10 V)

t

f

L

Clamped Output Voltage @ V = 30 V (Note 5)

7

V

11

−

CC

DRV

Voltage Drop on the Stage @ V = 10 V (Note 5)

12

V

CC

Undervoltage Lockout

Startup Threshold (V Increasing)

8

13

14

UVLO

13.5

6.5

15

16.5

8.0

V

CC

H

Minimum Operating Voltage (V Decreasing)

UVLO

7.2

CC

L

Startup Current Source

Maximum Voltage, Pin 1 Grounded

1

−

450

500

3.0

32

−

V

Maximum Voltage, Pin 1 Decoupled (470 µF)

Startup Current Source Flowing through Pin 1

Leakage Current in Offstate @ Vpin 1 = 500 V

2.3

−

4.8

70

mA

µA

Device Current Consumption

V

less than UVLO

8

13

14

−

1.5

1.2

3.0

−

1.8

3.0

4.0

−

mA

CC

H

= 30 V and Fsw = 2.0 kHz, C = 1.0 ηF

L

= 30 V and Fsw = 125 kHz, C = 1.0 ηF

−

L

Startup Current to V Capacitor

1.4

CC

4. Typical capacitor swing is between 0.5 V and 3.5 V.

5. Guaranteed by design, T = 25°C.

J

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7

NCP1205

420

400

380

360

340

320

125

120

115

110

105

100

300

280

95

90

−50

0

50

100

150

−50

0

50

100

150

TEMPERATURE (°C)

Figure 5. Ct Charging Current versus

Temperature

Figure 6. Switching Frequency @ Ct = 1 nF

versus Temperature

16.5

16

1100

1050

1000

15.5

15

14.5

950

900

14

13.5

−50

0

50

100

150

−50

0

50

100

150

TEMPERATURE (°C)

Figure 7. Start−up Threshold versus

Temperature

Figure 8. Maximum Current Set Point versus

Temperature

8

7.75

7.5

7.25

7

6.75

6.5

−50

0

50

TEMPERATURE (°C)

100

150

Figure 9. Minimum Operating Voltage versus

Temperature

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8

NCP1205

APPLICATION INFORMATION

Introduction

nominal output power, the circuit implements a traditional

current−mode SMPS whose peak current setpoint is given

by the feedback signal. However, rather than keeping the

switching frequency constant, each cycle is initiated by the

end of the primary demagnetization. The system therefore

operates at the boundary between Discontinuous

Conduction Mode (DCM) and Continuous Conduction

Mode (CCM). Figure 10 details this terminology:

By implementing a unique smooth frequency reduction

technique, the NCP1205 represents a major leap toward

low−power Switch−Mode Power Supply (SMPS) integrated

management. The circuit combines free−running operation

with minimum drain−source switching (so−called valley

switching), which naturally reduces the peak current stress

as well as the ElectroMagnetic Interferences (EMI). At

L > Lc

I

L

Not 0 at

Turn ON

I

P

0

L = Lc

L < Lc

OFF

ON

I

L(avg)

0 Before

Turn ON

Borderline

D/Fs

0

Dead−Time

Time

Figure 10. Defining the Conduction Mode, Discontinuous, Continuous and Borderline

When the output power demands decreases, the natural

switching frequency raises. As a natural result, switching

losses also increase and degrade the SMPS efficiency. To

overcome this problem, the maximum switching frequency

of the NCP1205 is clamped to typically 125 kHz. When the

free running mode (also called Borderline Control Mode,

BCM) reaches this clamp value, an internal

Voltage−Controlled Oscillator (VCO) takes over and starts

to decrease the switching frequency: we are in Variable

Frequency Mode (VFM). Please note that during this

transition phase, the peak current is not fixed but is still

decreasing because the output power demand does. At a

given state, the peak current reaches a minimum peak

(typically 250 mV/Rsense), and cannot go further down: the

switching frequency continues its decrease down to a

possible minimum of 0 Hz (the IC simply stops switching).

During normal free−running operation and VFM, the

controller always ensures single or multiple drain−source

valley switching. We will see later on how this is internally

implemented.

The FLYBACK operation is mainly defined through a

simple formula:

1

2

Pout + · Lp · Ip · Fsw

(eq. 1)

With:

Lp the primary transformer inductance (also called the

magnetizing inductance)

Ip the peak current at which the MOSFET is turned off

Fsw the nominal switching frequency

To adjust the transmitted power, the PWM controller can

play on the switching frequency or the peak current setpoint.

To refine the control, the NCP1205 offers the ability to play

on both parameters either altogether on an individual basis.

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9

NCP1205

In order to clarify the device behavior, we can distinguish the

Detailed Description

following simplified operating phases:

The following sections describe the internal behavior of

the NCP1205.

1. The load is at its nominal value. The SMPS operates in

borderline conduction mode and the switching

frequency is imposed by the external elements (Vin,

Lp, Ip, Vout). The MOSFET is turned on at the

minimum drain−source level.

Free−Running Operation

As previously said, the operating frequency at nominal load

is dictated by the external elements. We can split the different

switching sections in two separated instants. In the following

text we use the internal error voltage, Verr. This level is

elaborated in Figure 13. Verr is linked to VFB (pin 4) by the

following formula:

2. The load starts to decrease and the free−running

frequency hits the internal clamp.

3. The frequency can no longer naturally increase

because of the clamp. The frequency is now controlled

by the internal VCO but remains constant. The peak

current finds no other option that diminishing to satisfy

equation (1).

4. The peak current has reached the internal minimum

ceiling level and is now frozen for the remaining

cycles.

Verr + 10 * 3 · V

(eq. 2)

FB

ON time: The ON time is given by the time it takes to

reach the peak current setpoint imposed by the level on FB

pin (pin 4). Since this level is internally divided by three, the

peak setpoint is simply:

1

Ipk +

· Verr

(eq. 3)

5. To further reduce the transmitted power (V goes up),

FB

3 · Rsense

the VCO decreases the switching frequency. In case of

output overshoot, the VCO could decrease the

frequency down to zero. When the overshoot has gone,

The rising slope of the peak current is also dependent on

the inductance value and the rectified DC input voltage by:

dIL

dt

Vin

DC

Lp

V

FB

diminishes again and the IC smoothly resumes its

+

(eq. 4)

operation.

By combining both equations, we obtain the ON time

definition:

Lp

Vin

Lp · V

ERR

· 3 · Rsense

ton +

· Ip +

(eq. 5)

Advantages of the Method

By implementing the aforementioned control scheme, the

NCP1205 brings the following advantages:

• Discontinuous only operation: in DCM, the Flyback is

a first order system (at low frequencies) and thus

naturally eases the feedback loop compensation.

Vin

DC

OFF time: The time taken by the demagnetization of the

transformer depends on the reset voltage applied at the

switch opening. During the conduction time of the

secondary diode, the primary side of the transformer

undergoes a reflected voltage of: [Np/Ns . (Vf + Vout)]. This

voltage applied on the primary inductance dictates the time

needed to decrease from Ip down to zero:

• A low−cost secondary rectifier can be used due to

smooth turn−off conditions.

• Valley switching ensures minimum switching losses

brought by Coss and all the parasitic capacitances.

Lp

toff +

Np

ƪ

_{· (Vout ) Vf)}ƫ

Ns

• By folding back the switching frequency, you turn the

system into Pulse Duration Modulation. This method

prevents from generating uncontrolled output ripple as

with hysteretic controllers.

(eq. 6)

Lp · Verr

· Ip +

Np

Ns

ƪ

_{· (Vout ) Vf)}ƫ _{· 3 · Rsense}

By adding ton + toff, we obtain the natural switching

frequency of the SMPS operating in Borderline Conduction

Mode (BCM):

• By letting you control the peak current value at which

the frequency goes down, you ensure that this level is

low enough to avoid transformer acoustic noise

generation even at audible frequencies.

ȱ

ȳ

Verr · Lp

3 · Rsense

1

DC

1

)

ton ) toff +

·

ȧ_Vin

ȧ

_{· (Vout ) Vf)}ƫ

Np

Ns

ƪ

Ȳ

ȴ

(eq. 7)

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10

NCP1205

If we now enter this formula into a spreadsheet, we can easily plot the switching frequency versus the output power demand:

250000

Transition

BCM to VFM

200000

150000

100000

Fmax

50000

0

V

CO

Action

5

0

10

15

20

OUTPUT POWER (W)

Figure 11. A Typical Behavior of Free Running Systems

with a Smooth Frequency Foldback with the NCP1205

The typical above diagram shows how the frequency

the VCO frequency decreases with a typical small−signal

slope of −175 kHz/mV @ Verr = 500 mV down to

zero (typically at FB ≈ 3.3 V). The demagnetization

synchronization is however kept when the Toff expands.

The maximum switching frequency can be altered by

adjusting the Ct capacitor on pin 5. The 125 kHz maximum

operation ensures that the fundamental component stays

external from the international EMI CISPR−22

specification beginning.

moves with the output power demand. The components used

for the simulation were: Vin = 300 V, Lp = 6.5 mH,

Vout = 10 V, Np/Ns = 12.

The red line indicates where the maximum frequency is

clamped. At this time, the VCO takes over and decreases the

switching frequency to the minimum value.

VCO Operation

The VCO is controlled from the Verr voltage. For Verr

levels above 1.0 V, the VCO frequency remains unchanged

at 125 kHz. As soon as Verr starts to decrease below 1.0 V,

The following drawing explains the philosophy behind

the idea:

Internal V

err

3 V

V

Frequency

CO

BCM Mode

Peak current

can change

is Fixed at 130 kHz

1 V

0.75 V

V

CO

Frequency

can Decrease

Peak Current is Fixed

Figure 12. When the Power Demand goes Low, the Peak Current is Frozen and the Frequency Decreases

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11

NCP1205

Zero Crossing Detector

given point, the demag activity on the auxiliary

winding becomes too low to be detected. To avoid

any re−start problem, the NCP1205 features an

internal 4.0 µs timeout delay. This timeout runs

after each demag pulse. If within 4.0 µs further to

a demag pulse no activity is detected, an internal

signal is combined with the VCO to actually

re−start the MOSFET (synchronized with Ct).

To detect the zero primary current, we make use of an

auxiliary winding. By coupling this winding to the primary,

we have a voltage image of the flux activity in the core.

Figure 10 details the shape of the signal in BCM (L = Lc).

The auxiliary winding for demagnetization needs to

be wired in Forward mode. However, the application

note describes an alternative solution showing how to wire

the winding in Flyback as well. As Figure 13 depicts, when

the MOSFET closes, the auxiliary winding delivers

(Naux/Np . Vin). At the switch opening, we couple the

auxiliary winding to the main output power winding and

thus deliver: (−Naux/Ns . Vout). When DCM occurs, the

ringing also takes place on the auxiliary winding. As soon

as the level crosses−up the internal reference level

(65 mV), asignal is internally sent to re−start the MOSFET.

Three different conditions can occur:

Error Amplifier and Fault Detection

The NCP1205 features an internal error amplifier solely

used to detect an overcurrent problem. The application

assumes that all the error gain associated with the precise

reference level is located on the secondary side of the SMPS.

Various solutions can be purposely implemented such as the

TL431 or a dedicated circuit like the MC33341. In the

NCP1205, the internal OPAMP is used to create a virtual

ground permanently biased at 2.5 V (Figure 14), an internal

reference level. By monitoring this virtual ground further

called V(−), we have the possibility to confirm the good

behavior of the loop. If by any mean the loop is broken

(shorted optocoupler, open LED etc.) or the regulation

cannot be reached (true output short−circuit), the OPAMP

network is adjusted in order to no longer be able to ensure

the 2.5 V virtual point V(−). If V(−) passes down the 1.5 V

level (e.g. output shorted) for a time longer than 128 ms, then

the pulses are stopped for 8 x 128 ms. The IC enters a kind

of burst mode with bunch of pulses lasting 128 ms and

repeating every 8 x 128 ms. If the loop is restored within the

8 x 128 ms period, then the pulses are back again on the

1. In BCM, every time the 65 mV line is crossed, the

switch is immediately turned−on. By accounting

for the internal Demag pin capacitance (10−15 pF

typical), you can introduce a fixed delay, which,

combined to the propagation delay, allows to

precisely re−start in the drain−source valley

(minimum voltage to reduce capacitive losses).

2. When the IC enters VFM, the VCO delivers a

pulse which is internally latched. As soon as the

demagnetization pulse appears, the logic re−starts

the MOSFET.

3. As can be seen from Figure 13, the parasitic

oscillations on the drain are subject to a natural

damping, mainly imputed to ohmic losses. At a

output drive (synchronized with UVLO ).

H

Drain Level

Valley

Switching

Possible Demag

65 mV

0 V

2

Auxiliary Level

4 µs

I

P

= 0

Restart when Demag is too low

750.0 U 754.0 U 758.0 U

762.0 U

766.0 U

Figure 13. Core Reset Detection is done through an Auxiliary Winding Operated in Forward

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12

NCP1205

Monitor

Rf

150 k

V

fb

V

HIGH

V

LOW

= 3 V

= 5 mV

Ri

50 k

V(−)

2R

−

+

Current

Setpoint

3

1

6

2

+

V

fb

+

V1

R

2.5 V

+

−

OCP

Circuitry

7

5

+

V

low

1.5 V

Figure 14. This Typical Arrangement Allows for an Easy Fault Detection Management

To illustrate how the system reacts to a variable FB level,

we have entered the above circuit into a SPICE simulator

and observed the output waveforms. When FB is within

regulation, the error flag is low. However, as soon as FB

leaves its normal operating area, the OPAMP can no longer

keep the V(−) point and either goes to the positive top or

down to zero: the error flag goes high.

connected from ground to pin 5. In normal VFM operation,

this timing capacitor serves as the VCO capacitor and the

error management circuit is transparent. As soon as an error

is detected (error flag goes high), an internal switch routes

Ct to the 128 ms generator. As a first effect, the switching

frequency is no longer controlled by the VCO (if the error

appears during VFM) and the system is relaxed to natural

BCM. The capacitor now ramps up and down to be further

divided and finally create the 128 ms delay.

Because of the large amount of delay necessary for this

128 ms operation, the capacitor used for the timing is Ct,

6.500

FB

Regulation Area

4.500

2.500

Virtual Point

1.5 V

OCP Condition

500.0 M

Error Flag

1.000 M

3.000 M

5.000 M

7.000 M

9.000 M

Figure 15. By Monitoring the Internal Virtual Ground, the System can Detect the Presence of a Fault

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13

NCP1205

As soon as the system recovers from the error, e.g. FB is

Overvoltage Detection (OVP)

back within its regulation area, the IC operation comes back

to normal.

On the DIP14 and the SO16 versions, an OVP pin allows

to shutdown the controller as soon as the level on this pin

exceeds 2.8V, as detailed in Figure 16. In lack of switching

pulses, the Vcc capacitor is no longer refreshed by the

auxiliary supply and slowly discharges toward ground.

When the Vcc level crosses UVLOL, a new startup sequence

occurs. If the OVP has gone, the converter resumes its

operation.

To avoid any system thermal runaway, another internal

8 x 128 ms delay is combined with the previous 128 ms. It

works as follows: the 128 ms delay is provided to account for

any normal transients that engender a temporary loss of

feedback (FB goes toward ground). However, when the

128 ms period is actually over (the feedback is definitively

lost) the IC stops the output driving pulses for a typical

period of 8 x 128 ms. During this mode, the rest of the

functions are still activated. For instance, in lack of pulses,

the self−supplied being no longer provided, the start−up

source turns on and off (when reaching the corresponding

+

−

OVP

Latched

OVP

7

1

8

2 k

2

18 k

+

2.8 V

UVLO and UVLO levels), creating an hiccup waveform

L

H

on the Vcc line. As soon as the feedback condition is

restored, the 8 x 128 ms is interrupted and, in synchronism

with the Vcc line, the IC is back to normal. The following

diagrams show how this mechanism takes place when FB is

down to zero (optocoupler opened) or up to Vcc

(optocoupler shorted). If we assume that the error is

permanently present, then a burst mode takes place with a

128/8 x 128 = 12.5% duty−cycle. The real transmitted

Figure 16. In the DIP8 Version, the OVP Pad is not

Pinned Out and is Available with DIP14 Devices Only

Protecting Pin 1 Against Negative Spikes

As any CMOS controller, NCP1205 is sensitive to

negative voltages that could appear on it’s pins. To avoid any

adverse latch−up of the IC, we strongly recommend

inserting a 15 k resistor in series with pin 1 and the

high−voltage rail, as shown in Figures 17 and 18. This 15 k

resistor prevents from adversely latching the controller in

case of negative spikes appearing on the bulk capacitor

during the power−off sequence. Please note that this resistor

does not dissipate any continuous power and can therefore

be of low power type. Two 8.2 k can also be wired in series

to sustain the large DC voltage present on the bulk.

power is thus:

1

2

· Lp · Ip · Fsw · Duty

BURST

Pout

BURST

+

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14

NCP1205

OVP detected on Pin 6

V

CC

UVLO

H

L

Drive

Unit V Reaches UVLO

CC

L

Figure 17. When the V_CCVoltage Goes Above the

Maximum Value, the Device Enters Safe Burst Mode

V

CC

Arbitrary V Representation

CC

UVLO

H

L

Drive

8 x 128 ms maximum if loop does not

recover

V(−)

3.5 V

1.5 V

Loop Recovers

Here

128 ms

Figure 18. When the Internal V(−) Passes Below 1.5 V, the IC

Senses a Short−Circuit Event

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15

NCP1205

PACKAGE DIMENSIONS

PDIP−8

N SUFFIX

CASE 626−05

ISSUE L

NOTES:

1. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

2. PACKAGE CONTOUR OPTIONAL (ROUND OR

SQUARE CORNERS).

8

5

3. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

−B−

MILLIMETERS

INCHES

MIN

1

4

DIM MIN

MAX

10.16

6.60

4.45

0.51

1.78

MAX

0.400

0.260

0.175

0.020

0.070

A

B

C

D

F

9.40

6.10

3.94

0.38

1.02

0.370

0.240

0.155

0.015

0.040

F

−A−

NOTE 2

L

G

H

J

2.54 BSC

0.100 BSC

0.76

0.20

2.92

1.27

0.30

3.43

0.030

0.008

0.115

0.050

0.012

0.135

K

L

C

7.62 BSC

0.300 BSC

M

N

−−−

0.76

10

_

1.01

−−−

0.030

10

0.040

_

J

−T−

SEATING

PLANE

N

M

D

K

G

H

M

B

0.13 (0.005)

T

A

PDIP−14

P SUFFIX

CASE 646−06

ISSUE M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

14

1

8

7

B

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

INCHES

DIM MIN MAX

MILLIMETERS

A

F

MIN

18.16

6.10

3.69

0.38

1.02

MAX

18.80

6.60

4.69

0.53

1.78

A

B

C

D

F

0.715

0.240

0.145

0.015

0.040

0.770

0.260

0.185

0.021

0.070

L

N

C

G

H

J

0.100 BSC

2.54 BSC

0.052

0.008

0.115

0.290

−−−

0.095

0.015

0.135

0.310

10 −−−

_

1.32

0.20

2.92

7.37

2.41

0.38

3.43

7.87

−T−

SEATING

PLANE

K

L

J

K

M

N

10

_

0.015

0.039

0.38

1.01

D 14 PL

H

G

M

0.13 (0.005)

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16

NCP1205

PACKAGE DIMENSIONS

SO−16

D SUFFIX

CASE 751B−05

ISSUE J

−A−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

16

9

8

−B−

P 8 PL

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

M

S

B

0.25 (0.010)

1

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

G

MILLIMETERS

INCHES

MIN

0.386

DIM MIN

MAX

0.393

0.157

0.068

0.019

0.049

F

A

B

C

D

F

9.80

3.80

1.35

0.35

0.40

10.00

R X 45

K

_

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

C

G

J

1.27 BSC

0.050 BSC

−T−

SEATING

PLANE

0.19

0.10

0

0.25 0.008

0.25 0.004

0.009

7

J

M

K

M

P

R

D

16 PL

7

0

_

5.80

0.25

6.20 0.229

0.50 0.010

0.244

0.019

M

S

A

0.25 (0.010)

T

B

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17

NCP1205

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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NCP1205/D

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18


型号：	NCP1205/D
厂家：	ETC
描述：	Single Ended PWM Controller Featuring QR Operation and Soft Frequency Foldback 单端PWM控制器配备的QR操作和软频率折返\n 控制器
文件：	总18页 (文件大小：176K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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