P3055LLG [ETC]
N-Channel Logic Level Enhancement Mode Field Effect Transistor; N沟道逻辑电平增强模式场效应晶体管
| 型号： | P3055LLG |
| 厂家： | 
ETC |
| 描述： | N-Channel Logic Level Enhancement Mode Field Effect Transistor |
| 文件： | 总4页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P3055LLG
SOT-223
NIKO-SEM
Lead-Free
D
PRODUCT SUMMARY
1. GATE
2. DRAIN
3. SOURCE
V(BR)DSS
25
RDS(ON)
ID
G
6A
90mΩ
S
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
Gate-Source Voltage
SYMBOL
LIMITS
±20
6
UNITS
VGS
V
TC = 25 °C
Continuous Drain Current
ID
TC = 100 °C
3.6
22
A
Pulsed Drain Current1
Avalanche Energy
Repetitive Avalanche Energy2
IDM
EAS
EAR
L = 0.1mH
L = 0.05mH
TC = 25 °C
TC = 100 °C
60
mJ
W
3
3
Power Dissipation
PD
1.5
Operating Junction & Storage Temperature Range
Lead Temperature (1/16” from case for 10 sec.)
Tj, Tstg
TL
-55 to 150
275
°C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
Junction-to-Case
Junction-to-Ambient
SYMBOL
TYPICAL
MAXIMUM
UNITS
°C / W
12
42
RθJC
RθJA
1Pulse width limited by maximum junction temperature.
2Duty cycle ≤ 1%
ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)
LIMITS
MIN TYP MAX
PARAMETER
SYMBOL
TEST CONDITIONS
UNIT
STATIC
GS = 0V, ID = 250µA
DS = VGS, ID = 250µA
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
VGS(th)
IGSS
25
V
V
0.8 1.2
2.5
V
VDS = 0V, VGS = ±20V
VDS = 20V, VGS = 0V
±250 nA
25
µA
Zero Gate Voltage Drain Current
On-State Drain Current1
IDSS
VDS = 20V, VGS = 0V, TJ = 125 °C
250
ID(ON)
VDS = 10V, VGS = 10V
6
A
NOV-05-2004
1
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P3055LLG
SOT-223
NIKO-SEM
Lead-Free
VGS = 5V, ID = 3A
GS = 10V, ID = 6A
VDS = 15V, ID = 6A
DYNAMIC
70
50
16
120
90
Drain-Source On-State
Resistance1
RDS(ON)
mΩ
V
Forward Transconductance1
gfs
S
Input Capacitance
Ciss
Coss
Crss
Qg
450
200
60
VGS = 0V, VDS = 15V, f = 1MHz
pF
nC
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge2
Gate-Source Charge2
Gate-Drain Charge2
Turn-On Delay Time2
Rise Time2
15
VDS = 0.5V(BR)DSS, VGS = 10V,
ID = 3A
Qgs
Qgd
td(on)
tr
2.0
7.0
6.0
6.0
20
VDS = 15V, RL = 1Ω
nS
Turn-Off Delay Time2
td(off)
ID ≅ 10A, VGS = 10V, RGS = 2.5Ω
Fall Time2
tf
5.0
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current IS
ISM
6
A
Pulsed Current3
35
1.5
Forward Voltage1
VSD
trr
IF = IS, VGS = 0V
V
nS
A
Reverse Recovery Time
Peak Reverse Recovery Current
Reverse Recovery Charge
30
15
IRM(REC)
IF = IS, dlF/dt = 100A / µS
Qrr
0.043
µC
1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％.
2Independent of operating temperature.
3Pulse width limited by maximum junction temperature.
REMARK: THE PRODUCT MARKED WITH “P3055LLG”, DATE CODE or LOT #
Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name.
NOV-05-2004
2
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P3055LLG
SOT-223
NIKO-SEM
Lead-Free
NOV-05-2004
3
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P3055LLG
SOT-223
NIKO-SEM
Lead-Free
SOT-223 MECHANICAL DATA
mm
mm
Typ.
3.5
Dimension
Dimension
Min.
0.67
6.7
Typ.
0.7
7
Max.
0.73
7.3
Min.
3.3
Max.
3.7
A
B
C
D
E
F
H
I
0.63
0.65
0.32
0.67
0.4
2.9
3
3.1
J
2.27
4.57
1.5
2.3
4.6
1.6
6.5
2.33
4.63
1.7
K
L
0°
10°
0.1
0.03
M
N
G
6.3
6.7
NOV-05-2004
4
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