P3055LS [ETC]
N-Channel Logic Level Enhancement Mode Field Effect Transistor; N沟道逻辑电平增强模式场效应晶体管
| 型号： | P3055LS |
| 厂家： | 
ETC |
| 描述： | N-Channel Logic Level Enhancement Mode Field Effect Transistor |
| 文件： | 总4页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P3055LS
NIKO-SEM
TO-263
D
PRODUCT SUMMARY
1. GATE
V(BR)DSS
RDS(ON)
ID
2. DRAIN
3. SOURCE
G
25
12A
50mΩ
S
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
LIMITS
UNITS
Gate-Source Voltage
VGS
±20
V
TC = 25 °C
12
Continuous Drain Current
ID
TC = 100 °C
8
A
Pulsed Drain Current1
Avalanche Energy
IDM
EAS
EAR
45
L = 0.1mH
L = 0.05mH
TC = 25 °C
TC = 100 °C
60
mJ
W
Repetitive Avalanche Energy2
3
43
Power Dissipation
PD
15
Operating Junction & Storage Temperature Range
Lead Temperature (1/16” from case for 10 sec.)
Tj, Tstg
TL
-55 to 150
275
°C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
TYPICAL
MAXIMUM
UNITS
Junction-to-Case
2.6
60
RθJC
RθJA
RθCS
Junction-to-Ambient
Case-to-Heatsink
°C / W
0.6
1Pulse width limited by maximum junction temperature.
2Duty cycle ≤ 1%
ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)
LIMITS
PARAMETER
SYMBOL
TEST CONDITIONS
STATIC
GS = 0V, ID = 250µA
DS = VGS, ID = 250µA
UNIT
MIN TYP MAX
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
VGS(th)
IGSS
25
V
V
0.8 1.2
2.5
V
VDS = 0V, VGS = ±20V
VDS = 20V, VGS = 0V
±250 nA
25
µA
Zero Gate Voltage Drain Current
IDSS
VDS = 20V, VGS = 0V, TJ = 125 °C
250
DEC-03-2001
1
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P3055LS
NIKO-SEM
TO-263
On-State Drain Current1
ID(ON)
RDS(ON)
gfs
VDS = 10V, VGS = 10V
VGS = 5V, ID = 12A
12
A
70
120
90
Drain-Source On-State
mΩ
Resistance1
V
GS = 10V, ID = 12A
VDS = 15V, ID = 12A
DYNAMIC
50
16
Forward Transconductance1
S
Input Capacitance
Ciss
Coss
Crss
Qg
450
200
60
V
GS = 0V, VDS = 15V, f = 1MHz
pF
nC
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge2
Gate-Source Charge2
Gate-Drain Charge2
Turn-On Delay Time2
Rise Time2
15
VDS = 0.5V(BR)DSS, VGS = 10V,
ID = 6A
Qgs
Qgd
td(on)
tr
2.0
7.0
6.0
6.0
20
VDS = 15V, RL = 1Ω
nS
Turn-Off Delay Time2
td(off)
ID ≅ 12A, VGS = 10V, RGS = 2.5Ω
Fall Time2
tf
5.0
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current
IS
ISM
12
20
A
Pulsed Current3
Forward Voltage1
VSD
trr
IF = IS, VGS = 0V
1.5
V
nS
A
Reverse Recovery Time
Peak Reverse Recovery Current
Reverse Recovery Charge
30
15
IRM(REC)
Qrr
IF = IS, dlF/dt = 100A / µS
0.043
µC
1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%.
2Independent of operating temperature.
3Pulse width limited by maximum junction temperature.
REMARK: THE PRODUCT MARKED WITH “P3055LS”, DATE CODE or LOT #
DEC-03-2001
2
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P3055LS
NIKO-SEM
TO-263
DEC-03-2001
3
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P3055LS
NIKO-SEM
TO-263
TO-263 (D2PAK) MECHANICAL DATA
mm
mm
Typ.
1.5
Dimension
Dimension
Min.
14.5
4.2
Typ.
15
Max.
15.8
4.7
Min.
1.0
Max.
1.8
A
B
C
D
E
H
I
9.8
10.3
1.20
1.35
J
6.5
1.5
2.8
0.4
K
L
0.3
0.5
0.203
9.5
0.7
1.4
F
-0.102
8.5
M
N
4.83
5.08
5.33
G
9
DEC-03-2001
4
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