PEF24911H [ETC]
?Quad ISDN Echocancellation Circuit Digital Front End - 2B1Q Code? ; ？四ISDN Echocancellation电路数字前端 - 2B1Q码？\n
| 型号： | PEF24911H |
| 厂家： | 
ETC |
| 描述： | ?Quad ISDN Echocancellation Circuit Digital Front End - 2B1Q Code?
|
| 文件： | 总155页 (文件大小：2605K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, DS 3, July 2001
DFE-Q V2.1
Quad ISDN 2B1Q
Echocanceller Digital
Front End
PEF 24911 Version 2.1
Wired
Communications
N e v e r s t o p t h i n k i n g .
Edition 2001-07-16
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 7/16/01.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, DS 3, July 2001
DFE-Q V2.1
Quad ISDN 2B1Q
Echocanceller Digital
Front End
PEF 24911 Version 2.1
Wired
Communications
N e v e r s t o p t h i n k i n g .
PEF 24911
Revision History:
2001-07-16
DS 3
DS 2
Previous Version:
Data Sheet 11.00
Page
Subjects (major changes since last revision)
Page 13
Page 13
New function: Disable Super Frame Marker introduced on pin 16: DSFM
Refined description of pin 49: CRCON
Page 13, Especially, CRCON = ’1’ selects MFILT= 0011 0xxx (erroneously, MFILT=
Page 39
Page 28
Page 43
Page 54
Page 63
000010xx was documented in DS2)
Added note: MON-12 read access is impossible in state ’Deactivated’
Restriction: PACA/PACE must not be used during local loopback active
C/I-command LTD added (function as in V1.x)
AR0 and ARX set UOA = ’1’ (before: AR0 and ARX set UOA to the same
value as the received SAI bit)
Page 95
Refined description ’Framer / Deframer Loopback’:
Page 130 - always transparent
- prerequisite is transparent state
Bit Error Rate Counter: refined operational description
Page 97
Page 103 Data Through is only test mode, C/I-command = ARL must not be applied
when pin DT = ’1’
Page 113 Refined description of ’Control via MON-2’
Page 119 Removed ’Propagation Delay Measurement’: function not supported
Page 120 Refined description of mode register evaluation timing
Page 121 Removed description OPMODE.MODE1,0: no settings possible
SAI-evaluation / UOA-control:
Page 125 - M4RMASK.bit6: only SAI-reporting via MON-2 is selected
Page 127 - M4WMASK.bit6: in addition to UOA-bit control, also SAI-evaluation by the
state machine is selected; refined description
(see also Figure 21 and Figure 22)
Page 129 Changed TEST.bit6 = ’1’ (not ’0’)
Page 130 Statemachine is put into transparent state by TRANS=’0’ (not ’1’)
Page 135 Refined reset timing description; added 900µs internal delay to figure
Page 136 Refined description of FSC / Superframe-FSC-timing
Page 137 Table 21: Max. connection resistance specified
Page 139 Removed input capacitance of pin XIN (pin XIN is not supported)
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PEF 24911
Page
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
1.2
1.3
1.4
2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pinning Changes from DFE-Q V1.3 to DFE-Q V2.1 . . . . . . . . . . . . . . . . . 19
2.1
2.2
2.3
3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.3
3.4
3.5
3.6
3.7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
IOM®-2 Interface Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Superframe Marker Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
IOM®-2 Command/ Indicate Channel . . . . . . . . . . . . . . . . . . . . . . . . . . 24
IOM®-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MON-12 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Interface to the Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
General Purpose I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
U-Transceiver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2B1Q Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Maintenance Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
M4 Bit Reporting to State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
M4, M5, M6 Bit Control Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Start of Maintenance Bit Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Embedded Operations Channel (EOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
EOC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Scrambling/ Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Encoding/ Decoding (2B1Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
C/I Codes (2B1Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
State Machine Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
LT Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Inputs to the U-Transceiver in LT-Mode . . . . . . . . . . . . . . . . . . . . . . . . 58
Outputs of the U-Transceiver in LT-Mode . . . . . . . . . . . . . . . . . . . . . . . 62
LT-States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.8
3.8.1
3.8.2
3.8.3
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.16.1
3.16.2
3.16.3
4
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Layer 1 Activation/ Deactivation Procedures . . . . . . . . . . . . . . . . . . . . . . . 71
4.1
4.2
4.3
Data Sheet
2001-07-16
PEF 24911
Page
Table of Contents
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
Complete Activation Initiated by LT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Activation with ACT-Bit Status Ignored by the Exchange Side . . . . . . . 74
Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Complete Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Partial Activation (U Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Activation Initiated by LT with U Active . . . . . . . . . . . . . . . . . . . . . . . . . 82
Activation Initiated by TE with U Active . . . . . . . . . . . . . . . . . . . . . . . . . 84
Deactivating S/T-Interface Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Maintenance and Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Analog Loopback (No.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Loopback No.2 - Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Loopback No.2 - Complete Loopback . . . . . . . . . . . . . . . . . . . . . . . . 91
Loopback No.2 - Single Channel Loopbacks . . . . . . . . . . . . . . . . . . . 93
Local Loopbacks Featured By Register LOOP . . . . . . . . . . . . . . . . . 95
Bit Error Rate Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Block Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Near-End and Far-End Block Error Counter . . . . . . . . . . . . . . . . . . . 97
Testing Block Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
System Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Single-Pulses Test Mode (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Data Through Test Mode (DT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Pulse Mask Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Power Spectral-Density Measurement . . . . . . . . . . . . . . . . . . . . . . 104
Total Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Return-Loss Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Quiet Mode Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Insertion Loss Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.1.3
4.4.1.4
4.4.1.5
4.4.2
4.4.3
4.4.3.1
4.4.3.2
4.4.4
4.4.4.1
4.4.4.2
4.4.4.3
4.4.4.4
4.4.4.5
4.4.4.6
4.4.4.7
4.4.4.8
4.4.4.9
4.4.5
5
Monitor Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
MON-0 - Exchanging EOC Information . . . . . . . . . . . . . . . . . . . . . . . . . . 110
MON-2 - Exchanging Overhead Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
MON-8 - Local Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.1
5.2
5.3
6
6.1
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Register Summary
118
6.2
6.3
6.4
6.4.1
Reset of U-Transceiver Functions in State ’Deactivated’ . . . . . . . . . . . . 120
Mode Register Evaluation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LP_SEL - Line Port Selection Register . . . . . . . . . . . . . . . . . . . . . . . . 121
Data Sheet
2001-07-16
PEF 24911
Page
Table of Contents
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.4.9
6.4.10
OPMODE - Operation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . 121
MFILT - M-Bit Filter Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
M4RMASK - M4 Read Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 125
M4WMASK - M4 Write Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 127
TEST - Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
LOOP - Loop Back Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
FEBE - Far End Block Error Counter Register . . . . . . . . . . . . . . . . . . 132
NEBE - Near End Block Error Counter Register . . . . . . . . . . . . . . . . . 132
BERC - Bit Error Rate Counter Register . . . . . . . . . . . . . . . . . . . . . . . 132
7
7.1
7.2
7.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
IOM®-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Interface to the Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
7.6
7.6.1
7.6.2
8
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Appendix A: Standards and Specifications . . . . . . . . . . . . . . . . . . . . 141
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9
10
Data Sheet
2001-07-16
PEF 24911
Page
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
DFE-Q/ AFE 2nd Generation Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . 1
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
16-Line Card Application with DELIC Solution. . . . . . . . . . . . . . . . . . . . 5
16-Line Card Application with ELIC®/ IDEC® Solution . . . . . . . . . . . . . 6
Connecting Two AFE/DFE-Q Chip Sets . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Clocking Scheme for More Than Two DFE-Q/AFE Chip
Sets 8
Figure 7
Figure 8
Figure 9
Pin Configuration (63 of 64 used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Diagram and Data Flow (DFE-Q V2.1 + AFE V2.1). . . . . . . . . . 20
Clock Supply and Data Exchange between Master and Slave . . . . . . 21
Multiplexed Frame Structure of the IOM®-2 Interface . . . . . . . . . . . . . 23
Superframe Marker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Handshake Protocol with a 2-Byte Monitor Message/Response. . . . . 26
Abortion of Monitor Channel Transmission . . . . . . . . . . . . . . . . . . . . . 28
Interface to the Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Frame Structure on SDX/SDR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
U-Superframe Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
U-Basic Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
MON-0/2 - M-Bit Correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Maintenance Channel Filtering Options. . . . . . . . . . . . . . . . . . . . . . . . 40
M4 Bit Report Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
M4, M5, M6 Bit Control in Transmit Direction . . . . . . . . . . . . . . . . . . . 44
M4, M5, M6 Bit Control in Receive Direction . . . . . . . . . . . . . . . . . . . . 44
EOC-Procedure in Auto- and Transparent Mode. . . . . . . . . . . . . . . . . 49
CRC-Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Scrambler/ Descrambler Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Explanation of the State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
State Transition Diagram in LT-Mode . . . . . . . . . . . . . . . . . . . . . . . . . 57
Complete Activation Initiated by LT . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Activation with ACT-Bit Status Ignored by the Exchange . . . . . . . . . . 75
Complete Activation Initiated by TE. . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Complete Deactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
U Only Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
LT Initiated Activation with U-Interface Active . . . . . . . . . . . . . . . . . . . 82
TE-Activation with U Active and Exchange Control (case 1) . . . . . . . . 84
TE-Activation with U Active and no Exchange Control (case 2) . . . . . 86
Deactivation of S/T Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Complete Loopback Options in the NT . . . . . . . . . . . . . . . . . . . . . . . . 91
Loopbacks Featured by Register LOOP . . . . . . . . . . . . . . . . . . . . . . . 96
Block Error Counter Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Total Power Measurement Set-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Data Sheet
2001-07-16
PEF 24911
Page
List of Figures
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
DFE-Q V2.1 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . 135
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
IOM®-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Boundary Scan Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Data Sheet
2001-07-16
PEF 24911
Page
List of Tables
Table 1
Table 2
Table 3
Table 4
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pinning Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
IOM®-2 Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Assignments of IOM® Channels to Time-Slots No. on SDX/SDR and Line
Ports No. 30
Table 5
Table 6
Table 7
Table 8
2B1Q Coding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2B1Q U-Frame Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Overhead Bits Filter Setting by CRCON Pin . . . . . . . . . . . . . . . . . . . . 40
Supported EOC-Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2B1Q Coding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Command / Indicate Codes (2B1Q). . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Timers Used in LT-Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
U-Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Boundary Scan Cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
TAP Controller Instructions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
MON-0 Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
MON-2 and Overhead Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
MON-8-Local Function Commands . . . . . . . . . . . . . . . . . . . . . . . . . 115
Register Map Reference Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
IOM®-2 Dynamic Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . 136
IOM®-2 Dynamic Output Characteristics. . . . . . . . . . . . . . . . . . . . . . 137
Interface Signals of AFE and DFE-Q. . . . . . . . . . . . . . . . . . . . . . . . . 137
Boundary Scan Dynamic Timing Requirements . . . . . . . . . . . . . . . . 138
Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Data Sheet
2001-07-16
PEF 24911
Introduction
1
Introduction
The Quad ISDN 2B1Q Echocanceller Digital Front End (DFE-Q) is the digital part of an
optimized two-chip solution featuring 4x ISDN basic rate access and IDSL access at 144
kbit/s. The PEF 24911 is designed to provide in conjunction with the Quad ISDN
Echocanceller Analog Front End (PEF 24902 V2.1) full duplex data transmission at the
U-reference point according to ANSI T1.601 (1998), ETSI TS 102 080 (1998) and ITU-
T G.961 standards.
The DFE-Q 2nd generation has been completely reengineered to guarantee the
availability of the well proved DFE-Q/AFE solution over the year 2000. The PEF 24911
V2.1 is downwards pin compatible and functionally equivalent to the DFE-Q V1.x. Thus,
line card manufacturers can make use of the most advanced process technology without
the need to change their current design (besides the changeover to 3.3 V power supply).
No software changes are required if the DFE-Q V2.1 is deployed in existing DFE-Q V1.x
solutions. Some new features are provided such as free programmable filtering options
for the maintenance bits (M1-6) and enhanced monitoring and test functions. The data
rate is programmable from 1 Mbit/s to 4 Mbit/s.
15.36MHz
Hybrid
IOM®-2
Hybrid
AFE V2.1
DFE-Q V2.1
4x U
PEF 24902
PEF 24911
Hybrid
Hybrid
Relay Driver/
Power Controller
chipset.vsd
Figure 1
DFE-Q/ AFE 2nd Generation Chip Set
The output and input pins are throughout 5 V TTL compatible although the PEF 24911
is processed in advanced 3.3 V CMOS technology. A power down state with very low
power consumption is featured.
The PEF 24911 comes in a P-MQFP-64 package.
Data Sheet
1
2001-07-16
Quad ISDN 2B1Q Echocanceller Digital Front End
DFE-Q V2.1
PEF 24911
Version 2.1
1.1
Features
U-Interface
• Digital part of a two-chip solution featuring full duplex
data transmission and reception over two-wire metallic
subscriber loops providing 4x ISDN basic rate access
or IDSL access at 144 kbit/s
P-MQFP-64
• Conforms to:
– ANSI T1.601–1998
– ETSI TS 102 080 (1998)
– Recommendation ITU-T G.961
• 2B1Q-block code (2 binary, 1 quaternary) at 80-kHz symbol rate
• LT mode
• Data rate of the system interface programmable
• Activation/ deactivation controller
• 15 s start-up guard timer (T1) can be disabled for use in repeater applications
• Adaptive echo cancellation and equalization
• Automatic gain control and polarity adaptation
• Clock recovery (frame and bit synchronization) in all applications
• Built-in wake-up unit for activation from power-down state.
System Interface
®
• IOM -2 interface with programmable data rates (1 Mbit/s to 4 Mbit/s)
• SW controlled I/O ports for relay driver and power feeder control
– 4 relay driver pins per port
– 2 status pins per port
Type
Package
PEF 24911
P-MQFP-64
Data Sheet
2
2001-07-16
PEF 24911
Introduction
Others
• Software compatible to PEF 24911 V1.3 (Quad IEC DFE-Q)
• Inputs and outputs 5 V TTL compatible
• DOUT (open drain) accepts pull-up to 3.3 V or 5 V
• +3.3 V ±0.3 V Power Supply
• Advanced low power CMOS technology
• Extended temperature range (– 40...to 85 °C)
• Boundary-Scan, JTAG IEEE 1149.1
Add-On Features and Differences with Respect to DFE-Q V1.3/V1.2/V1.1
®
• Max. IOM -2 data rate 4 Mbit/s (DCL= 8 MHz)
• +3.3 V instead of +5 V power supply
• Dedicated pins for SSP and DT test modes
• DOUT configurable either as open drain or push-pull (tristate) output
• New MON-12 class features internal register access
• Coefficients retrievable by MON-12 commands instead of MON-8 commands
• Advanced filter options for MON-0 and MON-2 messages
• Bit Error Rate measurement per port
• Additional digital local loops
• C/I codes ’LTD’ and ’HI’ are no more supported
• Optimized LT-state machine
• JTAG Boundary-Scan with dedicated reset line TRST
(replaces power-on reset functionality)
Addressed Applications
• ISDN Line Cards for Central Office
• ISDN Line Cards for Access Networks
• ISDN Line Cards in PBX Systems
• IDSL Line Cards
Data Sheet
3
2001-07-16
PEF 24911
Introduction
1.2
Logic Symbol
•
Boundary Scan
0V
+3.3V
4
4
TMS TCK TDI TDO TRST
VDD VSS
FSC
DCL
DIN
SDX
SDR
4
PDM0 .. 3
DOUT
SLOT0
SLOT1
PUP
DFE-Q V2.1
4
4
D0A, D0B, D0C, D0D
CL15
CLS0
CLS1
CLS2
CLS3
D3A, D3B, D3C, D3D
2
2
ST00, ST01
ST30, ST31
CRCON
AUTO
DT SSP
RES
logsym.emf
Mode Settings
Figure 2
Logic Symbol
Data Sheet
4
2001-07-16
PEF 24911
Introduction
1.3
System Integration
This paragraph shows how the DFE-Q V2.1 may be integrated in systems using other
Infineon ISDN devices. The PEF 24911 DFE-Q is optimized for use in the following
applications:
– Digital Line Cards for Central Office
– Digital Line Cards for Access Networks (LT mode only)
– PBX applications (LT mode only)
Figure 3 and Figure 4 illustrate line card solutions with various Infineon line card
®
controllers. The DELIC-PB (PEB 20571) supersedes the ELIC (PEB 20550) and will
feature up to 32 HDLC controllers on-chip.The DELIC controls up to 4 devices of DFE-
®
Q V2.1 on a single IOM -2 interface. In this application an additional clock doubler is
necessary to generate the 8.192 MHz DCL clock for the DFE-Q derived from the 4.096
MHz BCL clock of the DELIC.
•
Test Unit
1
PCM HW
IOM-2
DFE-Q
2
3
AFE V2.1
V2.1
DELIC-PB
PEB 20571
PEF 24902
PEF 24911
Signalling
4
Q-IHPC
RAM
µC
PEB 2426
appl_delic.vsd
Figure 3
16-Line Card Application with DELIC Solution
Data Sheet
5
2001-07-16
PEF 24911
Introduction
•
Test Unit
PCM
Highway
1
2
3
ELIC
PEB 20550
IOM®-2
Signalling
AFE
DFE-Q
V2.1
V2.1
PEF 24902
PEF 24911
µC-Bus
IDEC
PEB 2075
4
Q-IHPC
PEB 2426
µC
C165/6
appl_elic.vsd
®
®
Figure 4
16-Line Card Application with ELIC / IDEC Solution
Figure 5 shows how an 8 channel line card application is realized by use of two AFE/
DFE-Q chip sets:
One AFE-PLL generates the synchronized 15.36 MHz clock and provides the master
clock at pin CL15 for the other 3 devices. The internal PLL of the first AFE synchronizes
the 15.36 MHz master clock onto a PTT reference clock of either 8 kHz or 2048 kHz.
Infineon recommends to feed the FSC clock input of the DFE-Q V2.1 and the PLL
reference clock input (pin CLOCK) of the AFE from the same clock source.
The PLL of the second AFE is deactivated. The 15.36 MHz master clock is applied at pin
CL15. CL15 is configured as input if XIN is clamped either to VDD or to VSS. Pin XOUT
has to be left open and CLOCK shall be tied to GND.
Data Sheet
6
2001-07-16
PEF 24911
Introduction
•
8/ 2048kHz PTT
Reference Cock
15.36MHz
IOM®-2
FSC
DCL
DIN
XIN XOUT
CLOCK
Hybrid
Hybrid
Hybrid
Hybrid
PDM0..3
SDR
AFE V2.1
DFE-Q V2.1
4x U
4x U
SDX
DOUT
PEF 24902
PEF 24911
15.36MHz
CL15
CL15
1-4MBit/s
15.36MHz
Hybrid
Hybrid
Hybrid
Hybrid
CL15
CL15
SDX
AFE V2.1
DFE-Q V2.1
SDR
PEF 24902
PEF 24911
PDM0..3
XIN XOUT
CLOCK
VSS
VDD/ N.C.
VSS
clkchain1.vsd
Figure 5
Connecting Two AFE/DFE-Q Chip Sets
The DFE-Q devices are supplied by the first AFE at pin CL15 with the synchronized
®
15.36 MHz clock. The IOM -2 channels the DFE-Q devices are assigned to can be
programmed by the two slot pins. Starting from channel no. 0/4/8/12 always four
subsequent channels are occupied.
Alternatively the clocking scheme as shown in Figure 6 may be applied if more than 3
devices are to be clocked (e.g. in a 16-channel line card application). Instead to supply
the 2nd AFE with the master clock at pin CL15, here the 15.36 MHz master clock is input
at pin XIN. Thereby pin CL15 is configured as output and passes the 15.36 MHz clock
on to the attached DFE-Q. If the clock chain is extended in the same way by another two
AFE/DFE-Q chip sets a 16-channel line card application can be realized with just one
single crystal. Note that the 15.36 MHz clock is inverted once by the AFE if it is input at
XIN and output at CL15. This way the duty cycle is recovered again.
Data Sheet
7
2001-07-16
PEF 24911
Introduction
•
8/ 2048kHz PTT
Reference Cock
15.36MHz
IOM®-2
XIN XOUT
CLOCK
Hybrid
Hybrid
Hybrid
Hybrid
PDM0..3
FSC
DCL
DIN
SDR
AFE V2.1
DFE-Q V2.1
4x U
4x U
4x U
SDX
DOUT
PEF 24902
PEF 24911
15.36MHz
CL15
CL15
15.36MHz
N.C.
VSS
1-4MBit/s
XIN XOUT
CLOCK
Hybrid
Hybrid
Hybrid
Hybrid
PDM0..3
SDR
AFE V2.1
DFE-Q V2.1
SDX
PEF 24902
PEF 24911
15.36MHz
CL15
CL15
15.36MHz
N.C.
VSS
XIN XOUT
CLOCK
Hybrid
Hybrid
Hybrid
Hybrid
AFE V2.1
PEF 24902
CL15
clkchain2.vsd
Figure 6
Recommended Clocking Scheme for More Than Two DFE-Q/AFE
Chip Sets
Data Sheet
8
2001-07-16
PEF 24911
Introduction
1.4
Operational Overview
The DFE-Q V2.1 operates always in LT mode. Other operating modes known from
former versions of the DFE-Q are not further supported.
System Interface Configurations
The following parameters of the system interface are configurable:
• Open Drain/ Push-Pull Mode
Configured as open drain the output pin DOUT is floating and a pull-up resistor is
required. In push-pull mode the output pin is high impedance outside the active time
slots.
®
• IOM -2 Channel Assignment
®
• IOM -2 channels are always assigned in blocks of four.
•
®
SLOT1
SLOT0
Assigned IOM -2 Channels
0
0
1
1
0
1
0
1
0 .. 3
4 .. 7
8 .. 11
12 .. 15
®
• IOM -2 Data Rates
•
®
DCL Frequency
[kHz]
Data Rate
[kBit/s]
IOM -2 Channels
2048
3072
4096
6144
8192
1024
1536
2048
3072
4096
4
6
8
12
16
Send Single Pulses Test Mode
In test mode ’Send Single Pulses’ +/-3 pulses spaced by 1.5 ms are transmitted on all U
lines. The test mode is activated by pin SSP= set to ’1’. The SSP test function can be as
well stimulated by C/I= SSP besides the fact that the HW selection impacts all line ports
while the SW selection impacts only the chosen line.
Data Sheet
9
2001-07-16
PEF 24911
Introduction
Data Through Mode
In test mode ’Data Through’ the U-transceiver is forced to enter the ’Transparent’ state
and to issue SL3T (see Table 12) independently of the wake-up protocol. The DT test
mode is activated by pin DT= set to ’1’. The DT test function can be as well stimulated
by C/I= DT besides the fact that the HW selection impacts all line ports while the SW
selection impacts only the chosen line.
Data Sheet
10
2001-07-16
PEF 24911
Pin Descriptions
2
Pin Descriptions
2.1
Pin Diagram
(top view)
43 42 41 40 39 3837 36 3534 33
48 47 46 45 44
49
50
51
CRCON
PUP
D1A
32
D2D
D3D
CLS2
LT
VDD
SLOT0
SSP
31
30
29
28
27
26
D0A
52
53
54
55
56
57
58
59
60
61
CLS0
ST00
ST01
ST10
VSS
ST11
ST20
VDD
ST21
25
24
23
22
P-MQFP-64
VSS
PBX
AUTO
RES
CLS3
DT
21
20
19
18
17
CLS1
ST30
ST31
62
63
64
TRST
TCK
SDX
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
pinning.vsd
Figure 7
Pin Configuration (63 of 64 used)
Data Sheet
11
2001-07-16
PEF 24911
Pin Descriptions
2.2
Pin Definitions and Functions
Pin Definitions and Functions
•
Table 1
Pin No.
Symbol Input (I)
Function
Output (O)
®
IOM -2 Interface
13
FSC
I
Frame Synchronization Clock (8kHz)
the start of the first B1-channel in time-slot 0 is
marked,
FSC is expected to be ’1’ for at least two DCL
periods.
12
14
15
DCL
DIN
I
I
Data Clock
clock rate ranges from 2048 to 8192 kHz
(1024 to 4096 kBit/s)
Data In
®
input of IOM -2 data synchronous to DCL
clock
DOUT
O
(OD/
PuP)
Data Out
®
output of IOM -2 data synchronous to DCL
clock
Mode Selection Pins
60
RES
I
I
Reset
triggers asynchronous HW reset, Schmitt
trigger input
’1’= inactive
’0’= active
®
55
SLOT0
IOM -2 Channel Slot Selection 0
®
assigns IOM -2 channels in blocks of 4
SLOT1, 0:
®
’00’= IOM -2 channels 0 to 3
®
’01’= IOM -2 channels 4 to 7
®
’10’= IOM -2 channels 8 to 11
®
’11’= IOM -2 channels 12 to 15
®
45
SLOT1
I
IOM -2 Channel Slot Selection 1
®
(PD)
assigns IOM -2 channels in blocks of 4
Data Sheet
12
2001-07-16
PEF 24911
Pin Descriptions
Table 1
Pin No.
Pin Definitions and Functions (cont’d)
Symbol Input (I)
Output (O)
Function
16
DSFM
I
Disable Super Frame Marker
(PD)
’1’ = Inhibits the evaluation of the super frame
marker on FSC. I.e the transmitted super-
frame is not affected by an FSC pulse shorter
than 2 DCL clock periods.
’0’ = The position of the transmitted
superframe is synchronized to short FSC
pulses.
32
49
PUP
I
Push Pull Mode
(PD)
in push pull mode ’0’ and ’1’ is actively driven
during an occupied time slot, outside the
active time slots DOUT is high impedance
(tristate)
’1’= configures DOUT as push/pull output
’0’= configures DOUT as open drain output
CRCON
I
CRC Check On/Off
(PD)
defines the condition on which MON-2
messages and M4 bit will be passed on,
the setting has effect on all ports (see
Table 7).
Pin CRCON is evaluated only after hardware
reset.
’1’= CRC Check On
MON-2 messages are not issued and M4-bit
are not forwarded to the statemachine if the
CRC-check of the U-superframe containing
M4-bit changes is not ok.
(MFILT= 0011 0xxx)
’0’= CRC Check Off
MON-2 messages are issued every time a
change in at least one of the overhead bits
(M4,5,6) of the U-interface is detected,
regardless of the CRC checksum status.
M4-bit are forwarded to the statemachine with
triple-last-look filtering (TLL).
(MFILT= 0000 0xxx)
53
LT
I
reserved, clamp to high
Data Sheet
13
2001-07-16
PEF 24911
Pin Descriptions
Table 1
Pin No.
Pin Definitions and Functions (cont’d)
Symbol Input (I)
Output (O)
Function
58
59
PBX
I
reserved, clamp to low
EOC Auto Mode
selects auto or transparent mode for EOC
channel processing,
the setting has effect on all ports
’1’= EOC auto mode
(MFILT= xxxx x100)
AUTO
I
I
I
’0’= EOC transparent mode
(MFILT= xxxx x001)
56
SSP
Send Single Pulses (SSP) Test Mode
’1’= alternating +/-3 pulses are issued at all
line ports in 1.5 ms intervals
’0’= deactivated, clamp to GND if not used
This pin function corresponds to the SW
selection by C/I= SSP besides the fact that the
HW selection impacts all line ports while the
SW selection impacts only the chosen line
62
DT
Data Through (DT) Test Mode
enables/disables DT test mode
’1’= DT test mode enabled,
the U-transceiver is forced on all line ports to
enter the ’Transparent’ state
’0’= DT test mode disabled
This pin function corresponds to the SW
selection by C/I= DT besides the fact that the
HW selection impacts all line ports while the
SW selection impacts only the chosen line
Interface to the Analog Front End
4
CL15
I
I
15.36 MHz Master Clock Input
11
PDM0
Pulse Density Modulated Receive Data of Line
Port 0
pulse density modulated bit stream from the
PEF 24902 Quad AFE that is output from the
second-order sigma-delta ADC
Data Sheet
14
2001-07-16
PEF 24911
Pin Descriptions
Table 1
Pin No.
Pin Definitions and Functions (cont’d)
Symbol Input (I) Function
Output (O)
10
PDM1
PDM2
PDM3
SDR
I
Pulse Density Modulated Receive Data of Line
Port 1
pulse density modulated bit stream from the
PEF 24902 Quad AFE that is output from the
second-order sigma-delta ADC
8
I
Pulse Density Modulated Receive Data of Line
Port 2
pulse density modulated bit stream from the
PEF 24902 Quad AFE that is output from the
second-order sigma-delta ADC
7
I
Pulse Density Modulated Receive Data of Line
Port 3
pulse density modulated bit stream from the
PEF 24902 Quad AFE that is output from the
second-order sigma-delta ADC
5
I
Serial Data Receive Line
interface signal from the PEF 24902 Quad
AFE that transports level detect information for
the wake-up recognition of all 4 lines by use of
TDM
17
SDX
O
Serial Data Transmit Line
interface to the PEF 24902 Quad AFE for the
transmit and control data. Transmission is
based on clock CL15 (15.36 Mbit/s). For each
line port the following bits are exchanged:
TD0, TD1: Transmit data
RANGE: Range select
LOOP: Analog loopback switch
PDOW: Power down/power up
Synchronization information
Data Sheet
15
2001-07-16
PEF 24911
Pin Descriptions
Table 1
Pin No.
Pin Definitions and Functions (cont’d)
Symbol Input (I) Function
Output (O)
Relay Driver/ Status Pins
30,
35,
42,
47
D0A
D0B
D0C
D0D
O
Relay Driver Pins of Line Port 0
®
addressable via MON-8 command in IOM -2
channel 0/4/8/12. The logic values of the bit
positions A,B,C, D of the MON-8 command
’SETD’ determine the output setting.
Default value after pin-reset is low. C/I-code
reset does not affect the current status.
31,
37,
43,
48
D1A
D1B
D1C
D1D
O
O
Relay Driver Pins of Line Port 1
addressable via MON-8 command in IOM -2
®
channel 1/5/9/13. The logic values of the bit
positions A,B,C, D of the MON-8 command
’SETD’ determine the output setting.
Default value after pin-reset is low. C/I-code
reset does not affect the current status.
33,
39,
44,
50
D2A
D2B
D2C
D2D
Relay Driver Pins of Line Port 2
addressable via MON-8 command in IOM -2
channel 2/6/10/14.
The logic values of the bit positions A,B,C, D
of the MON-8 command ’SETD’ determine the
output setting.
®
Default value after pin-reset is low. C/I-code
reset does not affect the current status.
34,
40,
46,
51
D3A
D3B
D3C
D3D
O
Relay Driver Pins of Line Port 3
addressable via MON-8 command in IOM -2
channel 3/7/11/15.
The logic values of the bit positions A,B,C, D
of the MON-8 command ’SETD’ determine the
output setting.
®
Default value after pin-reset is low. C/I-code
reset does not affect the current status.
28,
27
ST00
ST01
I
Status Pin of Line Port 0
change of status is passed to IOM -2 channel
®
0/4/8/12 via MON-8 message ’AST’ at bit
positions S S .
0,
1
Connect to either VDD or VSS if not used.
Data Sheet
16
2001-07-16
PEF 24911
Pin Descriptions
Table 1
Pin No.
Pin Definitions and Functions (cont’d)
Symbol Input (I)
Output (O)
Function
26,
24
ST10
ST11
I
Status Pin of Line Port 1
change of status is passed to IOM -2 channel
®
1/5/9/13 via MON-8 message ’AST’ at bit
positions S S .
0,
1
Connect to either VDD or VSS if not used.
23,
21
ST20
ST21
I
I
Status Pin of Line Port 2
change of status is passed to IOM -2 channel
2/6/10/14 via MON-8 message ’AST’ at bit
®
positions S S .
0,
1
Connect to either VDD or VSS if not used.
19,
18
ST30
ST31
Status Pin of Line Port3
change of status is passed to IOM -2 channel
®
3/7/11/15 via MON-8 message ’AST’ at bit
positions S S .
0,
1
Connect to either VDD or VSS if not used.
Test Pins
29
CLS0
CLS1
CLS2
O
O
O
12 msec clock synchronized to the received
Superframe of Port 0
can be used for monitoring and test purposes
Note: The delay between both signals may
vary from activation to activation.
20
52
12 msec clock synchronized to the received
Superframe of Port 1
can be used for monitoring and test purposes
Note: The delay between both signals may
vary from activation to activation.
12 msec clock synchronized to the received
Superframe of Port 2
can be used for monitoring and test purposes
Note: The delay between both signals may
vary from activation to activation.
Data Sheet
17
2001-07-16
PEF 24911
Pin Descriptions
Table 1
Pin No.
Pin Definitions and Functions (cont’d)
Symbol Input (I) Function
Output (O)
61
CLS3
O
12 msec clock synchronized to the received
Superframe of Port 3
can be used for monitoring and test purposes
Note: The delay between both signals may
vary from activation to activation.
JTAG Boundary Scan
64
1
TCK
TMS
I
Test Clock
I
Test Mode Select
(PU)
internal pullup resistor (160 kΩ)
2
TDI
I
Test Data Input
(PU)
internal pullup resistor (160 kΩ)
3
TDO
O
Test Data Output
63
TRST
I
JTAG Boundary Scan Disable
resets the TAP controller state machine
(asynchronous reset), active low, internal
pullup (160 kΩ). Clamp TRST to GND if the
Boundary Scan logic is not used
’1’= reset inactive
(PU)
’0’= reset active
Power Supply Pins
6, 22, 38, 54 VDD
9, 25, 41, 57 VSS
3.3V ±0.3V supply voltage
0V ground
OD:
PuP:
PD:
PU:
Open Drain
Push Pull
Internal Pull Down (e.g.. 10 to 20 kOhms)
Internal Pull Up (e.g.. 10 to 20 kOhms)
Data Sheet
18
2001-07-16
PEF 24911
Pin Descriptions
2.3 Pinning Changes from DFE-Q V1.3 to DFE-Q V2.1
•
Table 2
Pin No.
16
Pinning Changes
V2.1
V1.3
Comment
DSFM
TPD
new function for suppression of
short FSC evaluation
32
PUP
N.C.
additional push-pull mode for pin
DOUT eases interface adaptation
36
45
N.C.
DSYNC
N.C.
obsolete
SLOT1
increased max data rate requires
additional SLOT pin
49
53
55
56
CRCON
LT
CRCON
LT
see Page 39
dedicated LT mode pin is obsolete
renamed
SLOT0
SSP
SLOT
TSP
dedicated pin for ’Send Single
Pulses’ test mode
58
62
PBX
DT
PBX
TP
function removed
dedicated pin for ’Data Through’
test mode
63
TRST
TP1
BScan power-on-reset is replaced
by a dedicated reset line
Data Sheet
19
2001-07-16
PEF 24911
Functional Description
3
Functional Description
3.1
Functional Overview
A functional overview of the DFE-Q V2.1 is given in Figure 8. Besides the signal
processing and frame formatting blocks the PEF 24911 features an on-chip activation/
deactivation controller and programmable general purpose I/O pins for the control of test
relays and power feeding circuits. An application specific DSP core services the four U-
lines and cuts chip size to a minimum.
AFE V2.1
DFE-Q V2.1
DSP
LIU
U Protocol Processing Unit
SIU
2B1Q
DAC
Scram bler
U Fram ing
Encoder
4x U
Echo
IOM-2®
Canceller
System
Interface
Unit
A
G
C
PDM
+
2B1Q
De-
U De-
Equalizer
ADC
Filter
Decoder
Scram bler
Fram ing
Timing
Level
Recovery
Activation/Deactivation
Controller
Detection for
Wake Up
Bandgap,
Clock Generation
Clocks
Mode Setting
I/O Control
Bias, Refer.
Mode Pins
General
Purpose I/Os
dataflow.vsd
Figure 8
Block Diagram and Data Flow (DFE-Q V2.1 + AFE V2.1)
Data Sheet
20
2001-07-16
PEF 24911
Functional Description
3.2
IOM®-2 Interface
®
The IOM -2 interface is a four-wire serial interface providing a symmetrical full-duplex
communication link to layer-1 and layer-2 backplane devices. It transports user data,
control/programming and status information via dedicated time multiplexed channels.
The structure used follows the 2B + 1 D-channel structure of ISDN. The ISDN-user data
rate of 144 kbit/s (B1 + B2 + D) on the U-interface is transmitted transparently in both
®
directions (U <=> IOM ) over the interface.
FSC
DCL
IOM®-2
Slave
IOM®-2
Master
DU
DD
DCL
FSC
DU
DD
Last Bit of Frame
1. Bit of Frame
2. Bit of Frame
3. Bit of Frame
iomif.emf
Figure 9
Clock Supply and Data Exchange between Master and Slave
The Frame Sync Signal FSC is a 8 kHz signal delimiting the frames. This signal is used
to determine the start of a frame.
The data is clocked by a Data Clock (DCL) which operates at twice the data rate. The
data clock is a square wave signal with a duty cycle ratio of typically 1:1. Incoming data
is sampled on the falling edge of the DCL-clock.
Data is carried over Data Upstream (DU) and Data Downstream (DD) signals. The
upstream and downstream directions are always defined with respect to the exchange:
Downstream refers to information flowing from the exchange to the subscriber, upstream
is defined vice versa.
The output line is operating either as open drain or push-pull output. Both modes are
selected by signal “PUP”. In open drain mode an external pull-up resistor is required. The
absence of a pull-up resistor is not automatically recognized (i.e. no push-pull detection).
Data Sheet
21
2001-07-16
PEF 24911
Functional Description
Within one FSC-period, 128 to 512 bit are transmitted, corresponding to DCL-
frequencies ranging from 2048 kHz up to 8192 kHz. The following table shows possible
®
operating frequencies of the IOM -2-interface.
®
Table 3
IOM -2 Data Rates
®
DCL Frequency
[kHz]
Data Rate
[kBit/s]
IOM -2 Channels
2048
3072
4096
6144
8192
1024
1536
2048
3072
4096
4
6
8
12
16
3.2.1
IOM®-2 Interface Frame Structure
®
The typical IOM -2 line card application comprises a DCL-frequency of 4096 kHz with a
nominal bit rate of 2048 kbit/s. Therefore eight channels are available, each consisting
of the basic frame with a nominal data rate of 256 kbit/s. The downstream data (DD) is
®
transferred on signal DIN, the upstream data (DU) on signal DOUT. The IOM -2 channel
assignment is programmable by pin strapping (SLOT1,0).
®
The basic IOM -2 frame and clocking structure consists of:
•
channel
bits
B1
8
B2
8
Monitor
8
D
2
Command / Indicate
4
MR
1
MX
1
• Two 64-kbit/s channels B1 and B2
• The monitor channel for transferring maintenance information between layer-1 and
layer-2 devices
• Two bits for the 16-kbit/s D-channel
• Four command / indication (C/I) bits for controlling of layer-1 functions (activation/
deactivation and additional control functions) by the layer-2 controller
• Two bits MR and MX for handling the monitor channel
Data Sheet
22
2001-07-16
PEF 24911
Functional Description
®
Figure 10
3.2.2
Multiplexed Frame Structure of the IOM -2 Interface
Superframe Marker Function
The start of a new superframe is programmed by a FSC high-phase lasting for one single
DCL-period. A FSC high-phase of two (or more) DCL-periods is transmitted for all other
®
IOM -2-frame starts.
It is optional to include superframe markers in every 96th “frame synchronization” signal.
The remaining 95 FSC-clocks must be of at least two DCL-periods duration. If no
superframe marker is to be used all FSC high-phases need to be of at least two DCL-
periods duration.
With the SF function enabled the next outgoing basic frame on U defines the start of the
U superframe by an inverted sync word (see Figure 11). This way the positions of the
®
IOM -2 and the U superframe are no more arbitrary but definite within a tolerance of
1.5 ms.
Data Sheet
23
2001-07-16
PEF 24911
Functional Description
Fixed Chip Internal Delay
FSC
DU/
DD
IOM-2 Frame (1)
IOM-2 Frame (12)
M
M
U
2B+D
ISW
2B+D
SW
Bits
Bits
U Superframe Start
sf_pos.emf
Figure 11
Superframe Marker
If no superframe marker is to be used, all FSC high-phases need to be of at least two
DCL-periods duration.
®
The relationship between the IOM -2-superframe on the LT-side, the U-frame and the
®
IOM -2-superframe on the NT-side is fixed after activation of the U-interface. I.e. data
®
inserted on LT-side in the first B1-channel after the IOM -2-slave superframe marker will
always appear on NT-side with a fixed offset, e.g. in the 5th B1-channel after the master
superframe marker. After a new activation this relationship (offset) may be different.
Note: The evaluation of short FSC by the DFE-Q V2.1 can be suppressed by pin DSFM
(see Page 13).
3.2.3
IOM®-2 Command/ Indicate Channel
The Command/Indication (C/I) channel carries real-time control and status information
between the DFE-Q V2.1 and a layer-1 control device. A new C/I code must be applied
®
in six consecutive IOM -2 frames to be considered valid, unconditional commands (i.e.
RES, SSP, DT and commands in the states “Test” and “Reset”) must be applied up to 2
ms before they are recognized. An indication is issued permanently by the DFE-Q V2.1
on DOUT until a new indication needs to be forwarded.
The C/I code is 4 bit wide and located at bit positions 27–30 in each time-slot. A listing
and explanation of the U-transceiver C/I codes can be found on page 3-54.
3.2.4
IOM®-2 Monitor Channel
The Monitor channel represents a second method of initiating and reading U-transceiver
specific information. Features of the monitor channel are supplementary to the
command/indicate channel. Unlike the command/indicate channel with an emphasis on
status control, the monitor channel provides access to internal bits (maintenance,
overhead) and test functions (local loop-backs, block error counter etc.).
Data Sheet
24
2001-07-16
PEF 24911
Functional Description
Besides the known MON-0/2/8 commands a new MON class, MON-12 is introduced in
the DFE-Q V2.1:
New MON-12 Class
By use of MON-12 commands the DFE-Q V2.1 provides the ability to address parts of
the device internal register map and thus to address functions that have been added with
version 2.1. MON-12 commands are always prioritized and processed first if other
Monitor commands are outstanding. See Chapter 3.2.5 for the details.
This means that Monitor commands are split into four categories. Each category derives
its name from the first nibble (4 bits) of the two byte long message. These are:
• MON-12(Internal Register Map)
• MON-0(Transparent Channel)
• MON-2(Overhead Bits)
• MON-8(Local Functions)
The order of the list above corresponds to the priority attributed to each category. MON-
12 commands are always processed first. MON-0 messages will be transmitted before
MON-2 messages in case several messages are initiated simultaneously. The various
MON-0, MON-2 and MON-8-commands are discussed in detail in Chapter 5, “Monitor
Commands” on Page 110.
Structure
The structure of the Monitor channel is 8 bit wide, located at bit position 17 – 24 in every
time-slot. Monitor commands/messages sent to/from the U-transceiver are always 2
bytes long.
®
Transmission of multiple monitor bytes is specified by IOM -2 (see next section
“Handshake Procedure” for details). For handshake control in multiple byte transfers, bit
31, monitor read “MR”, and bit 32, monitor transmit “MX”, of every time-slot are used.
Verification
A double last-look criterion is implemented for the monitor channel. If the monitor
message that was received consecutively after a change has been detected is not
identical to the message that was received before the message will be aborted.
Handshake Procedure
®
IOM -2 provides a sophisticated handshake procedure for the transfer of monitor
®
messages. For handshake control two bits, MX and MR, are assigned to each IOM -2
frame (on DIN and DOUT). The monitor transmit bit (MX) indicates when a new byte has
been issued in the monitor channel (active low). The transmitter postpones transmitting
the next information until the correct reception has been confirmed. A correct reception
will be confirmed by setting the monitor read bit (MR) to low.
Data Sheet
25
2001-07-16
PEF 24911
Functional Description
The monitor channel is full duplex and operates on a pseudo-asynchronous base, i.e.
while data transfer on the bus takes place synchronized to frame synchronization, the
flow of monitor data is controlled by the MR- and MX-bits. Monitor data will be transmitted
repeatedly until its reception is acknowledged.
Figure 12 illustrates a monitor transfer at maximum speed. The transmission of a 2-byte
®
monitor command followed by a 2-byte response requires a minimum of 15 IOM -2
frames (reception 7 frames + transmission 8 frames = 1.875 ms). In case the controller
is able to confirm the receipt of first response byte in the frame immediately following the
MX-transition on DOUT from high to low (i.e. in frame No. 9), 1 byte may be saved (7
frames + 7 frames).
Transmission and reception of monitor messages can be performed simultaneously by
the U-transceiver. In the procedure depicted in Figure 12 it would be possible for the U-
transceiver to transmit monitor data in frames 1–5 (excluding EOM-indication) and
receive monitor data from frame 8 onwards.
M 1/2:Monitor message 1. and 2. byte
R 1/2:Monitor response 1. and 2. byte
Figure 12
Idle State
Handshake Protocol with a 2-Byte Monitor Message/Response
After the bits MR and MX have been held inactive (i.e. high) for two or more successive
®
IOM -frames, the channel is considered idle in this direction.
Data Sheet
26
2001-07-16
PEF 24911
Functional Description
Standard Transmission Procedure
1. The first byte of monitor data is placed by the external controller on the DIN line of the
DFE-Q V2.1 and MX is activated (low; frame No. 1).
2. The DFE-Q V2.1 reads the data of the monitor channel and acknowledges by setting
the MR-bit of DOUT active if the transmitted bytes are identical in two received frames
(frame No. 2 because data are already read and compared while the MX-bit is not
activated).
3. The second byte of monitor data is placed by the controller on DIN and the MX-bit is
®
set inactive for one single IOM -frame. This is performed at a time convenient to the
controller.
4. The DFE-Q V2.1 reads the new data byte in the monitor channel after the rising edge
of MX has been detected. In the frame immediately following the MX-transition active-
to-inactive, the MR-bit of DOUT is set inactive. The MR-transition inactive-to-active
®
exactly one IOM -frame later is regarded as acknowledgment by the external
controller (frame No. 4–5).
The acknowledgement by the DFE-Q V2.1 will always be sent two IOM -frames after
®
the activation of a new data byte.
5. After both monitor data bytes have been transferred to the DFE-Q V2.1, the controller
transmits “End Of Message” (EOM) by setting the MX-bit inactive for two or more
®
IOM -frames (frame No. 5–6).
6. In the frame following the transition of the MX-bit from active to inactive, the DFE-Q
V2.1 sets the MR-bit inactive (as was the case in step 4). As it detects EOM, it keeps
the MR-bit inactive (frame No. 6). The transmission of the monitor command by the
controller is complete.
7. If the DFE-Q V2.1 is requested to return an answer it will commence with the response
as soon as possible. Figure 12 illustrates the case where the response can be sent
immediately.
The procedure for the response is similar to that described in points 1 – 6 except for
the transmission direction. It is assumed that the controller does not latch monitor
data. For this reason one additional frame will be required for acknowledgement.
Transmission of the 2nd monitor byte will be started by the DFE-Q V2.1 in the frame
immediately following the acknowledgment of the first byte. The U-transceiver does
not delay the monitor transfer.
Transmission Abortion
If no EOM is detected after the first two monitor bytes, or received bytes are not identical
in the first two received frames, transmission will be aborted through receiver by setting
®
the MR-bit inactive for two or more IOM -2-frames. The controller reacts with EOM. This
situation is illustrated in Figure 13.
Data Sheet
27
2001-07-16
PEF 24911
Functional Description
Figure 13
3.2.5
Abortion of Monitor Channel Transmission
MON-12 Protocol
MON-12 commands feature direct access to the device internal register map via the
Monitor channel. This means, although the DFE-Q V2.1 features no microcontroller
interface, internal register functions can be directly addressed by use of MON-12
commands.
A MON-12 read request command must be first acknowledged by the DFE-Q V2.1
before a subsequent read request can be triggered. In case of a failure condition the
DFE-Q V2.1 repeats the last outstanding MON-12 answer. MON-12 commands are
prioritized over the other MON classes.
Note: Register read access via MON-12 commands is not possible in state
'Deactivated'.
However, register read access via MON-12 commands is still possible in state
'Reset' and all active states except 'Deactivated'.
If U-interface functions are addressed, the value of register LP_SEL determines the
register bank of the channel that is referred to. As a result the desired line port number
must be programmed first in register LP_SEL before any U-interface register can be
accessed. For this reason MON-12 commands may not be issued simultaneously on
®
different IOM -2 channels, but must be issued consecutively if they address U-interface
functions.
For registers that are addressable by MON-12 commands please refer to the “Detailed
Register Description” on Page 121.
MON-12 commands are of the following format:
• A MON-12 write command comprises 3 bytes, the first byte contains the MON-12
header, the second byte the register address, the third byte the register value.
Data Sheet
28
2001-07-16
PEF 24911
Functional Description
3. Byte
1. Byte
w=1 0 0 0
2. Byte
A A A A
Register Address
1100
A A A A
D D D D
D D D D
MON-12
Register Value
• A MON-12 read request command comprises 2 bytes, the first byte contains the
MON-12 header, the second byte the register address of the data that is requested.
1. Byte
r=0 0 0 0
2. Byte
A A A A
Register Address
1100
A A A A
MON-12
• After a read request the DFE-Q V2.1 reacts with a 3-byte message. A MON-12 read
answer comprises 3 bytes, the first byte contains the MON-12 header, the second
byte the register address, the third byte the register value.
1. Byte
r=0 0 0 0
2. Byte
A A A A
Register Address
3. Byte
D D D D
Register Value
1100
A A A A
D D D D
MON-12
Data Sheet
29
2001-07-16
PEF 24911
Functional Description
3.3
Interface to the Analog Front End
The interface to the PEF 24902 AFE V2.1 is a 6-wire interface (see Figure 14). On SDX
and SDR transmit and receive data is exchanged as well as control information for the
start-up procedure by means of time division multiplexing.
On SDX transmit data, power-up/down information, range function and analog loopback
requests are transferred.
On SDR level status information is received for all line ports.
On PDM0..PDM3 the ADC output data from the AFE is transferred to the DFE-Q V2.1.
The timing of all signals is based on the 15.36 MHz master clock which is provided by
the AFE.
SDX
SDR
PDM0
AFE V2.1
DFE-Q V2.1
PDM1
PDM2
PDM3
PEF 24902
PEF 24911
dfe_afe_if.vsd
Figure 14
Interface to the Analog Front End
The 192 available bits (related to the 15.36 MHz clock) on SDR/SDX during a 80 kHz
period are divided into 9 time-slots. 8 time-slots are 21 bits long and are reserved for data
transmission, 1 time-slot is 24 bits long and used for synchronization purposes. The
DFE-Q V2.1 uses four of them, time-slots no. 1, 3, 5 and 7. Table 4 shows the
®
assignment of the IOM -2 channels to the time-slots on SDX/SDR and the assignment
of the time-slots to the line ports.
®
Table 4
Assignments of IOM Channels to Time-Slots No. on SDX/SDR and
Line Ports No.
®
IOM -2 Channel No.
0/4/8/12
Time-Slot No.
Line Port No.
1
3
5
7
0
1
2
3
1/5/9/13
2/6/10/14
3/7/11/15
Data Sheet
30
2001-07-16
PEF 24911
Functional Description
The status on SDR is synchronized to SDX. Each time-slot on SDR carries the
corresponding LD bit during the last 20 bits of the slot.
Figure 15
Frame Structure on SDX/SDR
The data on SDX is interpreted as follows:
NOP:
The no-operation-bit is set to ’0’ if none of the control bits (PDOW,
RANGE and LOOP) shall be changed. The values of the control bits of the
assigned line port is latched. The states of the control bits on SDX are
ignored, they should be set to ’0’ to reduce any digital cross-talk to the
analog signals.
The NOPQ bit is set to ’1’ if at least one of the control bits shall be
changed. In this case all control bits are transmitted with their current
values.
PDOW:
If the PDOW bit is set to ’1’, the assigned line port is switched to power-
down. Otherwise it is switched to power-up.
RANGE:
RANGE activates the range function which attenuates the received U-
signal
’1’= RANGE function is activated (short line)
’0’= RANGE function is deactivated (long line)
LOOP:
SY:
LOOP = ’1’ activates the loop function, i.e. the loop is closed. Otherwise
the line port is in normal operation.
First bit of the time-slots with transmission data. For synchronization and
bit allocation on SDX, SY is set to ’1’ on SDX and ’0’ on SDR.
"0":
Reserved bit. Reserved bits are currently not defined and shall be set to
’0’. Some of these bits may be used for test purposes or can be assigned
to a function in later versions.
The 2B1Q data is coded with the bits TD2, TD1, TD0:
Data Sheet
31
2001-07-16
PEF 24911
Functional Description
Table 5
2B1Q Coding Table
2B1Q Data
TD2
1
TD1
TD0
0
don´t care
don´t care
– 3
– 1
+ 3
+ 1
0
0
0
1
1
0
1
0
1
0
0
0
The data on SDR is interpreted as follows:
LD:
The level detect information is communicated to the DFE-Q V2.1 on SDR.
If the signal amplitude reaches the wake-up level, the LD bit toggles with
the signal frequency. If the input signal at the U-interface is below the
wake-up level, the LD bit is tied to either low or high.
SY:
First bit of the time-slots with transmission data. For synchronization and
bit allocation on SDX, SY is set to ’1’ on SDX and ’0’ on SDR.
Data Sheet
32
2001-07-16
PEF 24911
Functional Description
3.4
General Purpose I/Os
The DFE-Q V2.1 features 6 general purpose I/O pins per line port. This way transparent
®
control of test relays and power feeding circuits is possible via the IOM -2 Monitor
channel. Four of the six pins are outputs, two are inputs.
Setting Relay Driver Pins
Four relay driver output pins Dij (where i = 0, 1, 2, 3 denotes the line port no. and j = A,
B, C, D specifies the pin) are available per line port. The logic state of the four relay driver
outputs which are assigned to the same line port can be set by a single MON-8
command, called ’SETD’. The value is latched as long as no other SETD command with
different relay driver settings is received.
The state of the relay driver pins is not affected by any software reset (C/I= RES). The
state of all relay driver pins after hardware reset is „low“.
Reading Status Pins
Each line port owns two status pins ST (where i = 0,1, 2, 3 denotes the line port no. and
ij
j = 0, 1 specifies the pin) whose logical value is reported in the associated Monitor
channel. Any signal change at one of the status pins ST1..4 causes automatically the
issue of a two-byte MON-8 message ’AST’ whose two least significant bits reflect the
status of pin STij.
However, this automatic mechanism is only enabled again, if the previous status pin
message has been transferred and acknowledged correctly according to the Monitor
®
channel handshake protocol. It takes the DFE-Q V2.1 at least 8x IOM -2 frames (1 ms)
to transmit the 2-byte MON-8 message. Thus, repeated changes within periods shorter
®
than 8x IOM -2 frames will overwrite the status pin register information. For this reason
only the value of the last recent status change will be reported. Note that the MON-8
transfer time depends also on the reaction time (acknowledge by MR-bit) of the DFE-Q
counterpart.
Besides this automatic report the DFE-Q V2.1 will issue the status pin Monitor message
’AST’ upon the MON-8 request ’RST’ .
The ST pins have to be tied to either VDD or GND, if they are not used.
ij
Data Sheet
33
2001-07-16
PEF 24911
Functional Description
3.5
Clock Generation
The U-transceiver has to synchronize onto an externally provided PTT-master clock. A
phase locked loop (PLL) is integrated in the AFE (PEF 24902) to generate the 15.36 MHz
system clock. A synchronized system clock guarantees that U-interface transmission will
be synchronous to the PTT-master clock.
The AFE is able to synchronize onto a 8 kHz or a 2048 kHz system clock. Infineon
recommends however to feed the FSC clock input of the DFE-Q V2.1 and the PLL
reference clock input (pin CLOCK) of the AFE from the same clock source. Please
refer to the PEF 24902 Data Sheet for further details on the PLL.
For the connection of the AFE clock output line with the DFE-Q V2.1 clock input line
(CL15) please refer to Figure 5 and Figure 6.
3.6
U-Transceiver Functions
The U-interface establishes the direct link between the exchange and the terminal side.
It consists of two copper wires. The Quad IEC AFE uses four differential outputs (AOUT,
BOUT) and four differential inputs (AIN, BIN) for transmission and reception. These
differential signals are coupled via four hybrids and four transformers to the four two-wire
U-interfaces. The nominal peak values of ±3 correspond to a 3.2 Vpp chip output and 2.5
Vpp on the U-interface.
Direct access to the U-interface is not possible. 2B + D user data can be inserted and
®
extracted via the IOM -2 interface. Control of maintenance bits is partly provided via
®
IOM -2 monitor commands. The remaining maintenance bits are fully controlled by the
DFE-Q V2.1 itself and allow no external influence (e.g. CRC-checksum).
3.7
2B1Q Frame Structure
Transmission over the U
-interface is performed at a symbol rate of 80 kBaud. The
2B1Q
code used reduces two binary informations to one quaternary symbol (2B1Q) resulting
in a total bit rate of 160 kbit/s. 144 kbit/s are user data (B1 + B2 + D), 16 kbit/s are used
for maintenance and synchronization information.
Data is grouped together into U-superframes of 12 ms each. The beginning of a new
superframe is marked by an inverted synchronization word (ISW). Each superframe
consists of eight basic frames (1.5 ms) which begin with a standard synchronization word
(SW) and contain 222 bits of information. The structure of one U-superframe is illustrated
in Figure 16 and Figure 17.
ISW
1. Basic Frame
SW
2. Basic Frame
. . .
SW
8. Basic Frame
<---
12 ms
--->
Figure 16
U-Superframe Structure
Data Sheet
34
2001-07-16
PEF 24911
Functional Description
(I) SW
12 × 2B + D
M1 – M6
(Inverted) Synch Word
18 Bit (9 Quat)
User Data
216 Bits (108 Quat)
Maintenance Data
6 Bits (3 Quat)
<---
1,5 ms
--->
Figure 17
U-Basic Frame Structure
®
Out of the 222 information bits 216 contain 2B + D data from 12 IOM -frames, the
remaining 6 bits are used to transmit maintenance information. Thus 48 maintenance
bits are available per U-superframe. They are used to transmit two EOC-messages (24
bit), 12 Maintenance (overhead) bits and one checksum (12 bit).
Table 6
2B1Q U-Frame Structure
Framing 2B + D
Overhead Bits (M1 – M6)
Quat
Positions
1 – 9
10 –
117
118 s
118 m
119 s
119 m
120 s
120 m
240
Bit
1 – 18
19 –
235
236
237
238
239
Positions
234
Super
Frame # Frame #
Basic
Sync
Word
2B + D
M1
M2
M3
M4
M5
1
M6
1
1
1
2
ISW
2B + D EOCa1 EOCa2 EOCa3
ACT/
ACT
SW
2B + D EOCd EOCi1 EOCi2
m
DEA /
PS1
1
FEBE
3
4
5
6
SW
SW
SW
SW
2B + D EOCi3 EOCi4 EOCi5
1/ PS2
CRC1 CRC2
CRC3 CRC4
CRC5 CRC6
CRC7 CRC8
2B + D EOCi6 EOCi7 EOCi8 1/ NTM
2B + D EOCa1 EOCa2 EOCa3 1/ CSO
2B + D EOCd EOCi1 EOCi2
m
1
7
8
SW
SW
2B + D EOCi3 EOCi4 EOCi5
UOA /
SAI
CRC9
CRC
10
2B + D EOCi6 EOCi7 EOCi8 AIB / NIB CRC11 CRC12
2,3…
LT- to NT dir. >
/
< NT- to LT dir.
Data Sheet
35
2001-07-16
PEF 24911
Functional Description
– ISW Inverted Synchronization Word (quad):
– SW Synchronization Word (quad):
– 3 – 3 + 3 + 3 + 3 – 3 + 3 – 3 – 3
+ 3 + 3 – 3 – 3 – 3 + 3 – 3 + 3 + 3
– CRC Cyclic Redundancy Check
– EOC Embedded Operation Channel
a
= address bit
d/m
i
= data / message bit
= information (data / message)
– ACT Activation bit
ACT = (1) –> Layer 2 ready for communication
DEA = (0) –> LT informs NT that it will turn off
CSO = (1) –> NT-activation with cold start only
UOA = (0) –> U-only activated
– DEA Deactivation bit
– CSO Colt Start Only
– UOA U-Only Activation
– SAI
S-Activity Indicator
SAI
= (0) –> S-interface is deactivated
– FEBE Far-end Block Error
FEBE = (0) –> Far-end block error occurred
PS1 = (1) –> Primary power supply ok ?
PS2 = (1) –> Secondary power supply ok ?
NTM = (0) –> NT busy in test mode
– PS1 Power Status Primary Source
– PS2 Power Status Secondary Source
– NTM NT-Test Mode
– AIB
Alarm Indication Bit
AIB
NIB
= (0) –> Interruption (according to ANSI)
= (1) –> no function (reserved)
– NIB Network Indication Bit
3.8
Maintenance Channel
The last three symbols (6 bits) form the 4 kbit/s M(Maintenance)-channel used for
exchange of operations and maintenance data between the network and the NT.
Approved M-bit data is first processed and then reported to the system by Monitor
channel messages (MON-0, MON-2).
MON-0/ MON-2 - M Bit mapping
The M1-3 bits over four basic frames constitute one complete EOC word. EOC words
®
are exchanged across the IOM -2 interface via MON-0 messages. The overhead bits
(M4,M5,M6) of one U-superframe are collected and transported in a MON-2 message.
Figure 18 shows in detail how the maintenance bits of one received U-superframe are
mapped to MON-0 and MON-2 messages.
M1-6 Filtering Options
To reduce processor load the DFE-Q V2.1 provides several programmable filters for the
issue of MON-0 and MON-2 messages. In the following paragraphs the various
verification algorithms and the provided control mechanism for the overhead bits
(M4,M5,M6) are presented.
The verification method of received M-channel data can be programmed in the MFILT
register using the MON-12 protocol. The following options are provided:
Data Sheet
36
2001-07-16
PEF 24911
Functional Description
U-Frame Structure
Super
Basic
M1
M2
M3
M4
M5
M6
Frame
Frame
1
1
2
3
4
5
6
7
8
ACT
DEA/PS1
SCO/PS2
1/NTM
1/CSO
1
1
1
1
FEBE
CRC2
CRC4
CRC6
CRC8
CRC10
CRC12
EOC 1
CRC1
CRC3
CRC5
CRC7
CRC9
CRC11
EOC 2
UOA/SAI
AIB/NIB
2,3 ...
/
LT to NT >
M3
< NT to LT
MON-0/2 Correspondence
Super
Basic
M1
M2
M4
M5
M6
Frame
Frame
1
1
2
3
4
5
6
7
8
A1
D/M
I3
A2
I1
A3
I2
D11
D8
D5
D4
D3
D2
D1
D0
D10
D7
D9
D6
I4
I5
CRC1
CRC3
CRC5
CRC7
CRC9
CRC11
CRC2
CRC4
CRC6
CRC8
CRC10
CRC12
I6
I7
A2
I1
I8
A3
I2
A1
D/M
I3
I4
I5
I6
I7
I8
2,3 ...
MON-0
MON-2
MON-0 Format
1. Byte
2. Byte
D/M
MON-0
Address
A1 A2 A3 D/M I1
EOC Code
0
0
0
0
I2
I3
I4
I5
I6
I7
I8
MON-2 Format
1. Byte
2. Byte
Single Bits (M4, M5, M6 except CRC)
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
mon02corrsp.emf
MON-2
0
0
1
0
Figure 18
MON-0/2 - M-Bit Correspondence
Data Sheet
37
2001-07-16
PEF 24911
Functional Description
EOC (M1-M3) Filtering
The first three M-bits (M1-M3) in each basic U-frame constitute an EOC command/
message. For the different EOC commands and their meaning see the next paragraph.
Via register MFILT the following operating modes can be set:
• Automode (MFILT.EOC= ’100’)
In automode received EOC messages are checked by ’triple-last-look’ (TLL) before
they are signalled to the system by a MON-0 message. The Return Message
Reception Function is activated (see “EOC Auto Mode” on Page 47).
• Transparent mode (MFILT.EOC= ’001’)
In transparent mode received EOC messages are forwarded via MON-0 to the system
interface. This means that every 6 ms a MON-0 message is issued.
• Transparent mode with On Change function active (MFILT.EOC= ’010’)
Only if a change in the EOC message has been detected the received EOC message
is reported via a MON-0 message.
• Transparent mode with TLL active (MFILT.EOC= ’011’)
A change is only reported via MON-0 if the new EOC command has been detected in
at least three consecutive EOC messages.
For more details on EOC commands and messages and its processing please refer to
chapter 3.9 on page 46.
Overhead Bit (M4, M5, M6) Filtering
M4 bits are used to communicate status and maintenance functions between the
transceivers. The meaning of a bit position depends on the direction of transmission
(upstream/downstream) and the operation mode (NT/LT). See Table 6 for the different
meaning of the M4 bits.
To reflect a change of the system status a new value for M4 bits shall be repeated in at
least three consecutively transmitted superframes. All overhead bits are set to binary ’1’
when leaving a power-down state.
Four different validation modes can be selected and take effect on a per bit base. Only
if the received M4 bit change has been approved by the programmed filter algorithm the
corresponding MON-2 message is issued. The following filter algorithms are provided:
• On Change (MFILT.M4= ’X00’)
• Triple-Last-Look (TLL) coverage (MFILT.M4= ’X01’)
• CRC coverage (MFILT.M4= ’X10’)
• CRC and TLL coverage (MFILT.M4= ’X11’)
Some M4 bits, ACT, DEA and UOA, have two destinations, the state machine and the
system interface. Via bit no. 5 of the MFILT register the user can decide whether the M4
bits which are input to the state machine shall be approved
• by TLL (MFILT.M4= ’0XX’) or
Data Sheet
38
2001-07-16
PEF 24911
Functional Description
• by the same verification mode (MFILT.M4= ’1XX’) as selected for the issue of a MON-
2 message.
The user has the choice to program one of the following two options for filtering the M5
and M6 bits changes except FEBE or CRC bits:
• Same validation algorithm as programmed for M4 bits (MFILT.M56= ’X0’ = default
setting)
Note that unlike the M4 bits the M56 bits are not included in the CRC!
• On Change (MFILT.M56= ’X1’)
Note: The issue of the corresponding Monitor messages is delayed for 12 ms (= U-
superframe) if received M-bits are CRC covered. This way the M-bit data is
checked with the actual CRC sum which is received one U-superframe later.
Filter Setting via Pin AUTO and Pin CRCON
Once after a pin reset, the settings of both AUTO and CRCON pins are evaluated and
the MFILT register is preset as follows. The setting of pin AUTO determines the
operational mode of the Embedded Operations Channel:
• Pin AUTO set to ’1’ selects automode for all line ports and corresponds to the following
register setting of MFILT = xxxx x100.
• Pin AUTO set to ’0’ selects transparent mode for all line ports and corresponds to the
following register setting of MFILT = xxxx x001.
Via pin CRCON the CRC filter mode for the overhead bits can be activated or
deactivated (See Table 7):
• Pin CRCON set to ’1’ enables the CRC mode for all line ports and corresponds to the
following register setting of MFILT = 0011 0xxx.
• Pin CRCON set to ’0’ disables the CRC mode for all line ports and corresponds to the
following register setting of MFILT = 0000 0xxx.
Note that the pin setting is only evaluated once after pin reset. This fact allows to
reprogram the verification modes later on by a MON-12 command. The MFILT register
setting is evaluated each time the U-transceiver enters the DEACTIVATED state.
Figure 19 summarizes the various filtering options that are provided for the several bits
of the Maintenance channel .
Data Sheet
39
2001-07-16
PEF 24911
Functional Description
TLL
M
U
X
M1-3
MON-0
(EOC)
On
Change
MFILT.EOC(Bit3,2,1)
M
U
X
State
Machine
TLL
MFILT.M4(Bit5)
M
U
X
&
&
M4
MON-2
CRC
On
Change
MFILT.M4(Bit4,3)
TLL
M
U
X
M5, M6
CRC
On
M
U
X
Change
MON-2
MFILT.M56(Bit6)
m456_fi l ter.emf
Figure 19
Maintenance Channel Filtering Options
Overhead Bits Filter Setting by CRCON Pin
Table 7
Pin
Towards FSM (“single” M4 bits) Towards System (M4, M5, M6 bits)
CRCON = 1
CRCON = 0
CRC
TLL
CRC & on change
on change
Data Sheet
40
2001-07-16
PEF 24911
Functional Description
3.8.1
M4 Bit Reporting to State Machine
Figure 20 illustrates the point of time when a detected M4 bit change is reported to the
system interface and when it is reported to the state machine:
• towards the system interface MON-2 messages might be sent after one complete
U-superframe was received,
• whereas towards the state machine M4-bit changes (ACT, SAI) are instantly passed
on as soon as they were approved by TLL (default setting in register MFILT, see
“MFILT - M-Bit Filter Options” on Page 122).
In context to Figure 20 this means that a verified ACT bit change is already reported
at the end of basic frame #1 instead at the end of basic frame #8.
1) CRCON = 1: CRC
→
SM / CRC & on-change
→
MON2
SF2
SF1
BF1
SF3
change
CRCNearend (SF1)
CRCFarend (SF1)
SM & MON2
2) CRCON = 0: TLL
→
SM / on-change
→
MON2
SF1
BF1
SF2
BF1
SF3
change
no change
no change
MON2
SM
3) MON12: MFILT = 14H: TLL
→
SM / CRCR on-change
→
MON2
SF1
BF1
SF2
BF1
SF3
BF1
change
no change
no change
SM
MON2
m4tim2sm_a.emf
Figure 20
M4 Bit Report Timing
Data Sheet
41
2001-07-16
PEF 24911
Functional Description
However, if the same filter is selected towards the state machine as programmed
towards the system interface (by Bit5= ’1’ in register MFILT) the user has to be aware
that if CRC mode is active the state machine is informed at the end of the next U-
superframe.
Data Sheet
42
2001-07-16
PEF 24911
Functional Description
3.8.2
M4, M5, M6 Bit Control Mechanisms
Figure 21 to Figure 22 show the control mechanisms that are provided for M4, M5 and
M6 bit data:
Via the M4WMASK register the user can selectively program which M4 bits are
externally controlled and which are set by the internal state machine. If one M4WMASK
bit is set to ’0’ then the M4 bit value in the U-transmit frame is determined by the bit value
at the corresponding bit position of the MON-2 command.
Note that the MON-8 command PACE/PACA corresponds to bit 6 in the M4WMASK
register. By bit 6 it can be selected whether SAI is set by the state machine or by MON-
2 commands.
Note: During Local Loop test mode (C/I-input = ’ARL’), the user must neither send MON-
8 PACE/PACA, nor program register M4WMASK. Otherwise, switching back and
forth between PACE/PACA will easily cause a failure where the SAI/UOA bits
toggle permanently.
Via the M4RMASK register the user can selectively program which M4 bit changes shall
cause a MON-2 message. With respect to the SAI bit the corresponding bit (no. 6) in the
M4RMASK bit decides in addition whether the value of the received SAI bit is reported
to the state machine or SAI= ’1’ is signalled.
Access to M4WMASK and M4RMASK is provided by the MON-12 protocol. By MON-2
commands the M4 bits can be set that are sent with the next available U-superframe. By
MON-2 messages the status of the last validated M4 bit data is reported.
Also the default values of the spare bits, M51, M52 and M61 can be overwritten at any
time by a MON-2 command. A MON-2 messages reports the last received and verified
M5, M6 bit data.
Data Sheet
43
2001-07-16
PEF 24911
Functional Description
MON-2
C/I codes
State
M4W Register
Machine
AIB
UOA M46
M45
M44 SCO DEA ACT
'1'
'1'
'1'
'1'
'1'
M4WMASK.Bit6=
MUX
MUX MUX MUX MUX
MUX
MUX
MUX
M4WMASK
MON-8(PACE, PACA)
'1'= M4W Reg.
'0'= SM/ Pin
U Transmit Superframe
MUX
OPMODE.FEBE
M56W Register
1
1
1
1
M61
M52
M51
FEBE
NEBE
Counter
MON-2
m456_dfeq_tx.emf
Figure 21
M4, M5, M6 Bit Control in Transmit Direction
U Receive Superframe
M4 Filtering (per bit)
M56 Filtering (per bit)
MFILT.M4
MFILT.M56
M4R Register
M56R Register
SAI
ACT
NIB
SAI
M46 CSO NTM
PS2
PS1
ACT
0
MS2 MS1 NEBE M61
M52
M51 FEBE
EN/
DIS
EN/
DIS
EN/
DIS
EN/
DIS
EN/
DIS
EN/
DIS
EN/
DIS
EN/
DIS
M4RMASK
'0'= enabled
'1'= disabled
'1'
Monitor
Channel
Controller
MUX
M4WMASK.Bit6
= MON-8(PACE/ PACA)
State
Machine
MON-2
m456_dfeq_rx.emf
Figure 22
M4, M5, M6 Bit Control in Receive Direction
Data Sheet
44
2001-07-16
PEF 24911
Functional Description
3.8.3
Start of Maintenance Bit Evaluation
MON-0/2 messages will be issued only if the receiver is synchronized. This is done to
avoid meaningless MON-0/2 messages if data transmission is not synchronized.
In other words, MON-0/2 messages will be issued only in the following states:
States
Line Active
Pending Transparent
S/T Deactivated
Pending Deactivation
Transparent
Data Sheet
45
2001-07-16
PEF 24911
Functional Description
3.9
Embedded Operations Channel (EOC)
The Embedded Operations Channel (EOC) is used to transfer data from the exchange
to the terminal side and vice versa without occupying B- or D-channels. It is used to
transmit diagnostic functions and signaling information.
EOC-data is inserted into the U-frame at the positions M1, M2 and M3 thereby permitting
the transmission of two complete EOC-messages (2 x 12 bits) within one U-superframe.
With a MON-0-command a complete EOC-message (address field, data/message
indicator and information field) can be passed to the U-transceiver.
The EOC contains an address field, a data/message indicator and an eight-bit
information field. With the address field the destination of the transmitted message/data
is defined. Addresses are defined for the NT, 6 repeater stations and broadcasting.
The data/message indicator needs to be set to (1) to indicate that the information field
contains a message. If set to (0), numerical data is transferred to the NT. Currently no
numerical data transfer to or from the NT is required.
From the 256 codes possible in the information field 64 are reserved for non-standard
applications, 64 are reserved for internal network use and eight are defined by ANSI for
diagnostic and loopback functions. All remaining 120 free codes are available for future
standardization.
Table 8
Supported EOC-Commands
EOC
Address
Field
Data/
Message
Indicator
Information
Message
O (rigin)
D (estination)
a1 a2 a3
d/m
i1 i2 i3 i4 i5 i6 i7 i8
LT
NT
0
1
0
1
0
1
x
x
x
NT
Broadcast
0
1
0
1
1
0
Repeater stations
No. 1 – No. 6
0
1
Data
Message
1
1
1
1
1
0 1 0 1 0 0 0 0
0 1 0 1 0 0 0 1
0 1 0 1 0 0 1 0
0 1 0 1 0 0 1 1
0 1 0 1 0 1 0 0
O
D
LBBD
LB1
O
O
O
O
D
D
D
D
LB2
RCC
NCC
Data Sheet
46
2001-07-16
PEF 24911
Functional Description
Table 8
Supported EOC-Commands
EOC
1
1
1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0
O
D/O
D
D
O/D
O
RTN
H
UTC
The EOC protocol operates in a repetitive command/response mode. Three identical
properly-addressed consecutive messages shall be received by the NT before an action
is initiated. In order to cause the desired action the Line Card controller continues to send
the message until it receives three identical consecutive EOC frames from the NT that
agree with the transmitted EOC frame.
The response of the NT is the echo of the received EOC frame. Any reply or echoed EOC
frame is sent upstream in the next available returning EOC frame. All actions to be
initiated at the NT shall be latching, permitting multiple EOC-initiated actions to be in
effect simultaneously. Latched functions are resolved by the RTN (return-to-normal)
command.
Access to the EOC is only possible when a superframe is transmitted. This is the case
in the following states:
– Line Active
– Pend. Transparent
– S/T Deactivated
– Pend. Deactivation
– Transparent
In other states than the listed above all EOC-bits on the U-interface are clamped to high.
3.10
EOC Processor
The on-chip EOC-processor is responsible for the correct insertion and extraction of
EOC-data on the U-interface. MON-0-messages provide the access to the device
internal EOC-registers. The EOC processor performs code repetition. This means that a
MON-0 message transporting the EOC command needs to be transferred only once
The EOC-processor can be programmed to automode or transparent mode:
EOC Auto Mode
– Acknowledgment: There is no acknowledgment in LT mode, i.e received EOC
messages are not echoed.
– Latching: No latching is performed.
®
– Transfer to IOM : ’Return Message Reception Function’ is enabled as soon as the
LT has transmitted an EOC command. It causes the U-transceiver in LT mode to
compare the received and verified (by TLL) EOC messages with the last downstream
Data Sheet
47
2001-07-16
PEF 24911
Functional Description
transmitted EOC command. A MON-0 message is issued if they prove to be equal.
For this particular received EOC message the ’different from previous’ rule is NOT
applied. This means that a MON-0 message is even issued if the received EOC
message is not different to the one previously accepted.
All other incoming EOC messages besides the echo of the one transmitted
downstream will be evaluated by TLL and the ’different from previous’ verification.
New received EOC messages will be passed independently of the address used, i.e.
not only messages addressed with (000) or (111) but all received EOC-messages will
be transmitted with MON-0-messages.
– Execution: No execution in LT mode, i.e. verified EOC messages cause no action or
execution other than being forwarded to the system.
EOC Transparent Mode
®
Every 6 ms a MON-0-message is issued on IOM . It contains the last received EOC-
message. This occurs even if no change occurred in the EOC-channel. No “triple-last-
look” is performed before a MON-0-message is sent.
Figure 23 summarizes the different processing of EOC/MON-0 commands/messages in
LT and NT mode.
Data Sheet
48
2001-07-16
PEF 24911
Functional Description
MON-0
EOC
NT
M1,M2,M3,
EOC
MON-0
EOC
LT
U
Transmission Possible
ARM (C/I) Indication
T
T
IOM -2
IOM -2
IOM -2
IOM -2
3x
A
A
Transmit
Request
will enable
Return
Execute
Message
Echo
A
3x
T
T
Reception Possible
UAI (C/I) Indication
MON-0
EOC
M1,M2,M3,
EOC
MON-0
EOC
ITD04233.vsd
A: Auto-Mode
T: Transparent-Mode
Figure 23
EOC-Procedure in Auto- and Transparent Mode
Data Sheet
49
2001-07-16
PEF 24911
Functional Description
3.11
Cyclic Redundancy Check
An error monitoring function is implemented covering the 2B + D and M4 data
transmission of a U-superframe by a Cyclic Redundancy Check (CRC).
The computed polynomial is:
12
11
3
2
G (u) = u + u + u + u + u + 1
(+ modulo 2 addition)
The check digits (CRC bits CRC1, CRC2, …, CRC12) generated are transmitted in the
U-superframe. The receiver will compute the CRC of the received 2B + D and M4 data
and compare it with the received CRC-bits generated by the transmitter.
A CRC-error will be indicated to both sides of the U-interface, as a NEBE (Near-end
Block Error) on the side where the error is detected, as a FEBE (Far-end Block Error) on
the remote side. The FEBE-bit will be placed in the next available U-superframe
transmitted to the originator.
Far-end or near-end error indications increment the corresponding block error counters
of exchange and terminal side. Figure 24 illustrates the CRC-process.
Data Sheet
50
2001-07-16
PEF 24911
Functional Description
IOM®-2
IOM®-2
NT
LT
U
(2B + D), M4
SFR(n)
DD
DD
G(u)
G(u)
CRC1... CRC12
CRC1... CRC12
SFR(n + 1)
No
=?
SFR(n + 1.0625)
FEBE = "1"
FEBE
Error
Counter
Yes
(MON-8)
(MON-1)
SFR(n + 1.0625)
NEBE
FEBE = "0"
NEBE
Error
Counter
(MON-8)
(2B + D), M4
G(u)
SFR(n + 0.0625)
DU
DU
G(u)
CRC 1... CRC 12
CRC1... CRC 12
SFR(n + 1.0625)
SFR(n + 2)
FEBE = "1"
SFR(n + 2)
No
=?
FEBE
Error
Counter
Yes
(MON-8)
(MON-1)
FEBE
FEBE = "0"
NEBE
Error
Counter
(MON-8)
crc.emf
Figure 24
CRC-Process
Data Sheet
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PEF 24911
Functional Description
3.12
Scrambling/ Descrambling
The scrambling algorithm ensures that no sequences of permanent binary 0s or 1s are
transmitted. It is defined in ETSI TS 102 080 and ANSI T1.601. The algorithms used for
scrambling and descrambling in LT- and NT-mode are given in Figure 25.
Note that one wrong bit decision in the receiver automatically leads to at least three bit
errors. Whether all of these are recorded by a bit error counter depends on the fact
whether all faulty bits are part of the monitored channels or not.
Figure 25
Scrambler/ Descrambler Algorithms
Data Sheet
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PEF 24911
Functional Description
3.13
Encoding/ Decoding (2B1Q)
The 2B1Q line code is a 4-level pulse amplitude modulation (PAM) code without
redundancy. 2B1Q stands for 2 Binary, 1 Quaternary. In transmit direction two-bit binary
pairs are converted into quaternary symbols that are called quats. In each pair of bits the
first bit is called the sign bit and the second is called the magnitude bit. Table 9 shows
the relationship of the bits to quats.
Table 9
2B1Q Coding Table
First bit
Second bit
(magnitude)
Quaternary Symbol
(quat)
(sign)
1
1
0
0
0
1
1
0
+3
+1
-1
-3
The four values listed under ’Quaternary symbol’ in the table above should be
understood as symbol names, not numerical values.
At the receiver, each quaternary symbol is converted to a pair of bits by reversing the
table, descrambled and finally formed into the original bit stream.
Data Sheet
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PEF 24911
Functional Description
3.14
C/I Codes (2B1Q)
The operational status of the DFE-Q V2.1 is controlled by the Control/Indicate channel
(C/I-channel). The four C/I channels operate completely independently.
Table 10 presents the existing C/I codes. A new command or indication will be
®
recognized as valid after it has been detected in two to five successive IOM -frames
(Unconditional commands must be applied up to 2 ms before they are recognized).
Indications are strictly state oriented. Refer to the state diagrams in the following
sections for commands and indications applicable in various states.
Commands have to be applied continuously on DIN until the command is validated by
the DFE-Q V2.1 and the desired action has been initiated. Afterwards the command may
be changed.
An indication is issued permanently by the DFE-Q V2.1 on DOUT until a new indication
needs to be forwarded. Because a number of states issue identical indications it is not
possible to identify every state individually.
Table 10
Code
Command / Indicate Codes (2B1Q)
LT-Mode
DIN
DR
RES
–
DOUT
–
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DEAC
FJ
LTD
RES1
SSP
DT
–
RSY
EI2
–
UAR
AR
UAI
AR
ARM
–
ARX
ARL
–
EI3
AI
–
AR0
–
LSL
–
DC
DI
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PEF 24911
Functional Description
AI
Activation Indication
EI2
Error Indication 2 (error on S/T)
AR
Activation Request
LSL
DC
RES
Loss of Signal Level on U
Deactivation Confirmation
Reset
AR0
ARL
ARM
ARX
DR
Activation Request with act bit = 0
Activation Request Local Loop
Activation Request Maintenance bits
Activation Request without 15 sec limit
Deactivation Request
RES1 Reset receiver
RSY
SSP
UAI
UAR
FJ
Loss of Synchronization
Send-Single-Pulses test mode
U-Activation Indication
U-Activation Request
Frame Jump
DEAC Deactivation Accepted
DI
DT
EI3
Deactivation Indication
Data-Through test mode
Error Indication 3 (time-out T1 [15 s],
error on U)
LTD
LT Disable
3.15
State Machine Notation
The state machines control the sequence of signals at the U-interface that are generated
during the start-up procedure. The informations contained in the following state diagrams
are:
– State name
– U-signal transmitted
– Overhead bits transmitted
– C/I-code transmitted
– Transition criteria
– Timers
Figure 26 shows how to interpret the state diagrams.
Figure 26
Explanation of the State Diagram
Data Sheet
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PEF 24911
Functional Description
The following example explains the use of a state diagram by an extract of the LT-state
diagram. The state explained is the “Deactivated” state in LT-mode.
The state may be entered by either of three methods:
– From state “Receive Reset” after time T7 has expired (T7 Expired)
– From state “Tear Down” after the internal transition criterion “LSU” is fulfilled
– From state “Reset” or “Test” after the C/I-command “DR” has been sent on DIN
The following information is transmitted:
– SL0 is sent on the U-interface
– No overhead bits are sent
– C/I-message “DI” is issued on DOUT
The state may be left by either of the following methods:
– Leave for state “Awake” after NT wake up tone (TN) was detected and the C/I-code
DC is present on DIN
– Leave for state “Alerting” after C/I-commands “AR”, “ARX”, “AR0” or “UAR” were
received
– Leave for state “Reset for Loop” after C/I-command “ARL” was received
Combinations of transition criteria are possible. Logical “AND” is indicated by “&” (TN &
DC), logical “OR” is written “or” and for a negation “/” is used. The start of a timer is
indicated with “TxS” (“x” being equivalent to the timer number). Timers are always
started when entering the new state. The action resulting after a timer has expired is
indicated by the path labelled “TxE”.
The sections following the state diagram contain detailed information on all states and
signals used. These details are mode dependent and may differ for identically named
signals/states. They are therefore listed for each mode.
Data Sheet
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PEF 24911
Functional Description
3.16
LT Mode State Diagram
TN & ( AR or AR0 or
ARX or UAR or DC)
Pin-RES or
DR
.
.
C/I= 'RES'
SL0
SL0
Deactivated
DI
Reset
DEAC
ARL
T2S
T1S, T2S
T1S, T2S
( AR or AR0 or
.
.
SL0
TL
ARX or UAR )
& /TN
T2E
Reset for Loop
DI
Alerting
DI
Pin-SSP or
C/I= 'SSP' or
C/I='LTD'
RES1
DR
T2E
T3S
SL0
T2S
.
SP/SL0
T3E
Test
DEAC
.
RES1
T1E
Wait for TN
DI
TN
T4S, T1S
T1S
.
.
SL0
SL0
T4S,
T9S, T4S
Awake Error
AR
Awake
AR
LSEC or
T4E
SL1
(T9E & LSEC)
or T4E
T5S
.
.
T1S, T5S
SL0
EC-Training
AR
Alerting_Error
EI3
RES1
LSEC or T5E
T6S
SL2
a=0,d=1
EC-Converged
ARM
FW_OK or T6E
or ARL
T2S
a=0,d=1
RES1
SL2
EQ-Training
EI 3
(/T1E or ARX) & SFD &
(BBD0 or BBD1 or
CRCOK)
ARM
T1E
SL3T**) a=0,d=1
SL3T a=1,d=1
DR or LOF
or LSUE
T8S
Pend.Transparent
Line Active
UAI/FJ
DR or LOF
or LSUE
act =1 & /AR0
sai=0 & act=0
UAI, FJ
T8E
UAR
Any State
Pin-DT or DT
AR0
AR0
a=0,d=1
SL3T
a=1,d=1
SL3T
DR or LOF
or LSUE
DR or LOF
or LSUE
Transparent
S/T Deactivated
sai=1
act=0
act=1
AI/FJ
EI2/FJ
AR/FJ
UAI/FJ
sai=0
DR T10S
LOF
LSUE
a=0,d=1
SL3T a=0,d=1
Loss of Synchr.
SL3T a=0,d=0
SL3T
Pend. Deactivation
Loss of Signal
RSY
DEAC
LSL
RES1
RES1
T10E
T7S
.
.
.
SL0
SL0
Tear Down
DEAC
SL0
LSU
LSU
TN
Tear Down Error
RSY
Receive Reset
T7S
LSL
T7E
**) When state Line Active is entered the first time
at startup the 2B+D data must be clamped to '0',
until act= '1' has been received from the NT
LT_SM_2B1Q_cust.emf
Figure 27
State Transition Diagram in LT-Mode
Data Sheet
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PEF 24911
Functional Description
3.16.1
Inputs to the U-Transceiver in LT-Mode
The transition criteria are described in the following sections. They are grouped into:
– C/I-commands
– Pin settings
– Events related to the U-interface
– Timers
C/I-Commands
AR
Activation Request
The U-transceiver is requested to enter the power-up state and to start an activation
procedure by sending the wake-up signal TL. In case the U-transceiver is in state
"Deactivated" it is recommended always to apply DC before AR to resolve the situation if
a TN tone has been detected before.
AR0
Activation Request with “ACT” bit = (0)
The U-transceiver is requested to enter the power-up state and to start an activation
procedure by sending the wake-up signal TL. After “EQ Training” the state “Line Active” will
be entered independent of the “ACT” bit. Evaluation of the “ACT” bit is disabled when AR0
is received and enabled when AR is received.
In case the U-transceiver is in state "Deactivated" it is recommended always to apply DC
before AR0 to resolve the situation if a TN tone has been detected before.
ARL
ARX
DC
Activation Request Local Loop-back
The U-transceiver is requested to operate an analog loop-back (close to the U-interface)
and to start the start-up sequence by sending the wake-up tone TL. This command may be
issued only after the U-transceiver has been set to the “Deactivated” state (C/I-channel
code DI issued on DOUT) and has to be issued continuously as long as loop-back is
requested.
Activation Request Extended
The DFE-Q is requested to enter the power-up state and to start an activation procedure by
sending the wake-up signal TL. The difference to the command AR is that the activation
duration may exceed 15 sec.
In case the U-transceiver is in state "Deactivated" it is recommended always to apply DC
before ARX to resolve the situation if a TN tone has been detected before.
Deactivation Confirmation
If ’DC’ is applied in state “Deactivated” the DFE-Q transitions to state "AWAKE" as soon
as it receives a wake-up tone from the NT. If ’DR’ is applied in state “Deactivated” the wake
up request of the NT is not acknowledged. This way the linecard is able to reject an
activation attempt by the NT e.g. during a service procedure.
By means of the ’DC’ command the LT is also during an U-only activation capable to
control the point of time when the complete transmission line is set transparent in case a
terminal initiated activation request has occurred. In state ’S/T Deactivated’ with applied C/
I code ’UAR’ the DFE-Q issues ’UOA= 0’ and receives ’SAI= 0’ from the deactivated S
interface. If the terminal requests an activation with ’AR’ issued in the NT the SAI bit is set
Data Sheet
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PEF 24911
Functional Description
to ’1’ and the LT indication ’UAI’ switches to ’AR’. As soon as ’DC’ is applied instead of
’UAR’ on the LT side the line is set transparent, since the UOA bit reflects the polarity of
SAI and is thus set to ’1’.
DR
DT
Deactivation Request
This command requests the U-transceiver to start a deactivation procedure by setting the
DEA bit to “0” and to cease transmission afterwards. The DR-code is a conditional
command causing the U-transceiver only to react in the states “Reset”, “Test”, “S/T
Deactivated”, “Line Active”, “Pending Transparent” and “Transparent”, i.e. when the C/I-
channel codes DEAC, UAI, AR, AI, FJ or EI2 are issued on DOUT.
Data Through
This unconditional command is used for test purposes only and forces the U-transceiver
into the transparent state independent of the wake-up protocol. A far-end transceiver
needs not to be connected; in case a far-end transceiver is present it is assumed to be in
the same condition.
LTD
RES
LT Disable
This unconditional command forces the U-transceiver to state Test, where it transmits
signal SL0. No further action is initiated.
Reset
Unconditional command which resets the whole chip; note that on contrary to the pin reset
a clock signal must be provided for the C/I code processing.
RES1 Reset 1
The reset 1 command resets all receiver functions; especially the EC- and EQ-coefficients
and the AGC are set to zero. The RES1-code does not reset any other than receiver
®
functions (e.g. IOM -functions or relay driver settings). The RES1-code should be used
when the U-transceiver has entered a failure condition (expiry of timer T1, loss of framing
or loss of signal level) indicated by the C/I-channel EI3, RSY or LSL on DOUT. Besides
resetting the receiver, this command stops transmission on the U-interface. The DEA bit is
not set to “0” by RES1.
SSP
UAR
Send Single Pulses
Unconditional command which requests the transmission of single pulses on the
U-interface. The pulses are issued at 1.5 ms intervals and have a duration of 12.5 µs.
The chip is transferred to the “Test” state; the receiver will not be reset.
Partial Activation Request (U only)
The U-transceiver is requested to enter power-up state and to start an activation procedure
of the U-interface only.
Pins
Pin-RES
Pin-Reset
A HW-Reset was applied and released. C/I-message DEAC will be issued in all
channels.
Pin-SSP
Send Single Pulses
The function of this pin is the same as for the C/I-code SSP in all channels. The C/I-
Data Sheet
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PEF 24911
Functional Description
message DEAC will be issued. The high level needs to be applied continuously for
the transmission of single pulses.
Pin-DT
Data Through
The function is identical with the C/I-code DT in all channels.
U-Interface Events
ACT = 0/1
“ACT” bit received from the NT-side.
– ACT = 1 signals that the NT has detected INFO3 on the S/T-interface and indicates
that the complete basic access system is synchronized in both directions of
transmission. The LT-side is requested to provide transparency of transmission in
both directions and to respond with setting the ACT-bit to “1”. In the case of loop-
backs (loop-back 2 or single-channel loop-back in the NT), however, transparency
is required even when the NT is not sending ACT = 1. Transparency is achieved in
the following manner:
– The U-transceiver performs transparency in both directions of transmission after
the receiver has achieved synchronization (state EQ-training is left) independent of
the status of the received ACT-bit.
– The status “ready for sending” is reached when the state transparent is entered i.e.
when the C/I-channel indication AI is issued. This is valid in the case of a normal
activation procedure for call control. In the case of loop-backs (loop-back 2 or
single-channel loop-back in the NT and analog loop-back in the LT) however, the
status “ready for sending” is reached when the state line active is entered i.e. when
the C/I-channel indication UAI is issued. Until the status “ready for sending” is
reached, binary “0s” have to be passed in the B- and D-channels on DIN.
– ACT = 0 indicates the loss of transparency on the NT-side (loss of framing or loss
of signal level on the S/T-interface). The U-transceiver informs the LT-side by
issuing the C/I-channel indication EI2, but performs no state change or other
actions.
CRCOK
LOF
Cyclic Redundancy Check OK
This input is used as a criterion that the receiver has acquired frame synchronization
and both its EC and EQ coefficients have converged.
Loss of Framing on the U-interface
This condition is fulfilled if framing is lost for 576 ms. 576 ms are the upper limit. If the
correlation between synchronization word and input signal is not optimal, LOF can be
issued earlier.
LSEC
LSU
Loss of Signal Level behind the Echo Canceler
In the “Awake” state, this input is used as indication that the NT has ceased the
transmission of signal SN1. In the EC-training state, this input is used as an internal
signal indicating that the EC in the LT has converged.
Loss of Signal Level on the U-interface
This signal indicates that a loss of signal level for the duration of 3 ms has been
detected on the U-interface. This short response time is relevant in all cases where
Data Sheet
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PEF 24911
Functional Description
the LT waits for a response (no signal level) from the NT-side, i.e. after a deactivation
procedure has been started or after loss of framing in the LT occurred.
LSUE
Loss of Signal Level on the U-interface (error condition)
After a loss of signal level has been noticed, a 492 ms timer is started. After this timer
has elapsed, the LSUE-criterion is fulfilled. This long response time (see also LSU) is
valid in all cases where the LT is not prepared to lose signal level. Note that 492 ms
represent a minimum value; the actual loss of signal might have occurred earlier, e.g.
when a long loop is cut at the LT-side, the echo coefficients need to be readjusted to
new parameters. Only after the adjusted coefficient cancel the echo completely, the
loss of signal is detected and the timer can be started (if the long loop is cut at the
remote end, the coefficients are still correct and a loss of signal will be detected
immediately).
SEC
Signal Level behind the echo canceler
This signal indicates that a signal level corresponding to SN2 from the NT has been
detected on the U-interface.
SFD
TN
Superframe Detected
Tone (wake-up signal) received from the NT.
When in the “Deactivated” state, the U-transceiver is requested to start an activation
procedure and to inform the LT-side making use of the C/I-channel code AR. When
in the “Wait for TN” state, the signal TN sent by the NT acknowledges the receipt of
a wake-up signal TL from the LT.
When an analog loop-back is operated, the wake-up signal TL sent by the
LT-transmitter is detected by the LT-receiver.
The TN-criteria is fulfilled when 12 consecutive periods of the 10 kHz wake-up tone
were detected.
BBD0/1
Binary “0” or “1s” detected in the B- and D-channels
This internal signal indicates that for a period of time of 6–12 ms a continuous stream
of binary “0s” or “1s” has been detected. It is used as a criterion that the receiver has
acquired frame synchronization and both its EC- and EQ-coefficients have
converged. BBD1 corresponds to the signals SN2 or SN3 in the case of a normal
activation and BBD0 corresponds to the internally received signal SL2 in the case of
an analog loop-back or possibly a loop-back 2 in the NT.
Timers
The start of timers is indicated by TxS, the expiry by TxE. The following Table 11 shows
which timers are used in LT-modes:
Table 11
Timers Used in LT-Modes
Duration (ms) Function
Timer
T1
State
15000
3
Supervisor for start-up
T2
TL-transmission
Receiver reset
Alerting
Reset for loop
Data Sheet
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Functional Description
Timer
T3
Duration (ms) Function
State
40
Re-transmission of TL
Wait for TN
Awake
T4
6000
1000
6000
40
Supervisor SN0 detect
Supervisor EC converge
Supervisor SN2 detect
Hold time
T5
EC training
T6
EC converge
Receiver reset
Pend. transparent
Awake error
Pend. Deactivation
T7
T8
24
Delay time for AI detection
Hold time
T9
40
T10
40
“DEA” = (0) transmission
3.16.2
Outputs of the U-Transceiver in LT-Mode
®
Signals and indications are issued on the IOM -2-interface (C/I-codes) and U-interface
(predefined U-signals).
C/I-Indications
AI
Activation Indication
This indication signals that “ACT” = 1 has been received and that timer T8 has
elapsed. This indication is not issued in case AR0 is applied to DOUT or an analog
loop-back is operated.
AR
Activation Request
The AR-code signals that a wake-up signal has been received and that a start-up
procedure has commenced. Receiver synchronization has not yet been achieved.
When already partially active (U only activation), AR indicates that the “SAI” bit was
set to (1), i.e. the S/T-interface has become active.
DEAC
DI
Deactivation
This indication is issued in response to a DR-code (Pend. Deactivation, Tear Down)
and in the “Reset” and “Test” states.
Deactivation Indication
Idle code on the IOM -interface. Normally the U-transceiver stays in the
®
“Deactivated” state unless an activation procedure is started by the NT-side.
EI2
Error Indication 2
EI2 is issued if the received ACT-bit is (0). The NT receiver indicates a loss of signal
or framing on the S/T-interface by setting the upstream ACT-bit to (0). The U-
transceiver remains in the “Transparent” state. After a signal level or framing is
detected again, the C/I-indication AI will be issued anew.
EI3
Error Indication 3
This indication is issued when the U-transceiver has not been able to activate
successfully (expiry of timer T1).
LSL
Loss of Signal Level
The U-transceiver has entered a failure condition after loss of signal level (LSUE).
Data Sheet
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Functional Description
RSY
FJ
Re-Synchronization indication after a loss of framing (LOF)
For EI3, LSL and RSY indication the LT-side should react by applying the C/I-channel
code RES1 to allow the U-transceiver to enter the “Receive reset” state and to reset
the receiver functions.
Frame Jump
This indication signals that either a data buffer overflow/underflow has been detected
®
or a phase jump of one of the IOM -timing signals DCL or FSC has occurred. The
FJ-code is issued for a period of 1.5 ms.
UAI
U-Activation Indication
The UAI-code signals that the line system is synchronized in both directions of
transmission (see also the input ACT = 1). Maintenance bits are transmitted normally.
ARM
Activation Request Maintenance
Transmission of maintenance bits is possible.
Signals on U-Interface
The signals SLx, TL and SP transmitted on the U-interface are defined in Table 12 "U-
Interface Signals" on Page 71. The polarity of the overhead bits ACT and DEA is
indicated as follows:
a = 0/1 corresponds to ACT bit set to binary “0/1”.
d = 0/1 corresponds to DEA bit set to binary “0/1”.
The polarity of the transmitted UOA-bit depends on the received C/I-channel code:
– UAR sets UOA-bit to binary 0.
– AR, AR0, and ARX sets UOA-bit to binary 1.
– Any other C/I-codes sets the UOA to the same value as the received SAI bit. After deactivation
the UOA-bit is set to binary 0 until a valid SAI-bit is received.
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Functional Description
3.16.3
LT-States
This section describes the functions of all states defined in LT-mode.
Alerting
The wake-up signal TL is transmitted for 3 ms (T2) in response to an activation request
from the LT side (AR or ARL). In the case of an analog loop-back, the signal TL is
forwarded internally to the wake-up signal detector and stored.
Alerting Error
When timer T1 (15 s) is expired in state "Alerting" before TN has been detected then the
DFE-Q transits from state "Alerting" to state "Alerting Error". Once "Alerting Error" has
been entered the receiver must be reset by C/I RES1.
Awake
The “Awake” state is entered upon the receipt of a wake-up or an acknowledge signal
TN from the NT. In the case of an activation started by the LT-side, timer T1 is restarted
when the “Awake” state is entered.
Awake Error
The “Awake Error” state is equivalent to the “Awake” state, but is entered only when a
wake-up signal is received while being in the “Receive reset” state. As the “Receive
reset” state was entered upon the application of the C/I-channel code RES1, the “Awake
error” state assures that a minimum amount of time elapses between the application of
the RES1-code and the U-transceiver entering a state (EQ training) in which it again
reacts on the RES1-code. The LT-side is requested to stop issuing the command RES1
within T9 after the receipt of the C/I-channel code AR on DOUT and to replace it by
another command such as the idle code DC for instance.
Deactivated (Full Reset)
In the “Deactivated” state the device may enter the low power consumption condition.
The power-down mode is entered if no monitor messages are to be expected. In power-
down the receiver and parts of the interface are deactivated while functions related to the
®
IOM -2-interface and the wake-up detector are still active.
No signal is sent on the U-interface, the differential outputs AOUT and BOUT are set to
0 V. The U-transceiver waits for a wake-up signal TN from the NT-side or an activation
request (AR, AR0, UAR or ARL) from the LT-side to start an activation procedure. Note
that in state "Deactivated" no activation can be initiated by AR, ARX, AR0 or UAR if a TN
tone has been recognized before. This situation can be only resolved by applying DC.
Therefore it is recommended to apply always DC before AR, ARX, AR0 or UAR.
For the recognition of the wake-up signal TN the following procedure applies:
Data Sheet
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Functional Description
– TN detected for 8 periods –> transfer within the “Deactivated” state into power-up
– In power-up both differential outputs, AOUTx and BOUTx, are set to the common mode DC level
of VDDmin/2
– TN detected for a total of 12 consecutive periods –> transition criterion TN fulfilled, change to
next state, if in addition the C/I-command DC is given on DIN.
– TN detected for more than 8 but less than 12 periods –> return to power-down
The input sensitivity is stated in the AFE V1.1 Data Sheet. There the minimum level
required is specified to meet the TN transition criterion. The power-up condition may thus
already be entered at a lower level.
EC Converged
Upon the EC-coefficients having converged, the U-transceiver starts the transmission of
signal SL2 and waits for the receipt of signal SN2 from the NT (SEC). If no signal is
detected within T6, nevertheless the start-up procedure will be continued. In the case of
an analog loop-back, this state is left immediately because the EC compensates for the
looped back transmit signal.
EC-Training
The signal SL1 is transmitted on the U-interface to allow the LT-receiver to update its
EC-coefficients. The “EC-training” state is left when the EC has converged (LSEC) or
when timer T5 has elapsed. Timer T5 allows the start-up procedure to proceed even if
LSEC due to a high noise level on the U-interface for instance, could not be detected.
EQ-Training
In state “EQ-Training” the equalizer coefficients are trained for a minimum period of
3 ms. Upon expiry of timer T2 state “EQ-Training 1” is entered.
Line Active
In the “Line Active” state, the U-transceiver transmits transparently in both directions.
The U-Interface is synchronized and the maintenance channel is operational. The U-
transceiver stays in the line-active state
– during a normal activation procedure while the “ACT” bit = (0) is received
– when an analog loop-back is established
– while C/I-command AR0 is applied to DIN
In the case of normal activation with call control, binary “0s” have to be applied to the B
®
and D channels on the IOM -interface. After the C/I-channel indication UAI has been
issued, the layer-2 receiver should be fully operational to prevent the first layer-2
message issued by the NT-side upon the receipt of the AI-code in the TE, to be lost.
Data Sheet
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2001-07-16
PEF 24911
Functional Description
Loss of Signal
The “Loss of Signal” state is entered upon the detection of a failure condition i.e. loss of
receive signal (LSUE). The ACT bit is set to “0” and the C/I-channel indication LSL is
issued. The U-transceiver waits for the C/I-channel command RES1 to enter the
“Receive Reset” state.
Loss of Synchronization
The “Loss of Synchronization” state is entered upon the detection of a failure condition
i.e. loss of framing by the LT-receiver (LOF). The ACT-bit is set to “0” and the C/I-channel
indication RSY is issued. The U-transceiver waits for the C/I-channel command RES1 to
enter the “Tear Down Error” state and subsequently the “Receive Reset” state.
Pending Deactivation
“Pending Deactivation” is a transient state entered after the receipt of a DR-code. The
DEA-bit is set to “0”. Timer T10 assures that the DEA-bit is set to “0” in at least three
consecutive superframes before the transmit level is turned off.
Pending Transparent
“Pending Transparent” is a transient state entered upon the detection of ACT = 1 and left
by T8. The ACT-bit is set to “1”. The purpose of this state is to issue the C/I-channel
indication AI (corresponding to “ready for sending”) 24 ms after the ACT-bit has been set
to “1” by the LT-transceiver. This assures that under normal operating conditions the AI-
indication is issued first on the TE-side and only afterwards on the LT-side. Thus the
layer-2 receiver in the TE is already operational when the first layer-2 message is issued
by the LT-side.
Reset
The “Reset” state is entered with the unconditional command RES, respectively Pin-
RES. It is left when pin RESQ is inactive and the C/I-channel code DR is received. SL0
and DEAC are output in “Reset” state. The U-transceiver does not react to the receipt of
a wake-up signal TN.
Reset for Loop
“Reset for Loop” resets the receiver in order to guarantee a correct adaption of the echo-
and equalizer coefficients.
Receive Reset
The “Receive Reset” state assures that for a period of T7 no signal, especially no wake-
up signal TL, is sent on the U-interface, i.e. no activation procedure is started from the
LT-side. A wake-up signal TN, however, from the NT-side is acknowledged.
Data Sheet
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2001-07-16
PEF 24911
Functional Description
S/T Deactivated
The state “S/T Deactivated” will be entered if the received ACT- and SAI-bits are set to
(0). In this state the signal SL3T, ACT = (0), DEA = (1) and UOA = (0) are transmitted
®
downstream. On the IOM -2-bus the C/I-code UAI is issued while the received SAI = (0).
In order to initiate a complete activation from the S/T deactivation state, the LT needs to
set the UOA-bit to (1). This will occur if either of the following three conditions are met:
– C/I = AR(LT-activation)
– SAI = (1) & AR(TE-activation with exchange control [DIN = C/I UAR])
– SAI = (1)(TE-activation without exchange control [DIN = C/I DC])
“S/T deactivated” will be left if the received ACT bit is (1), or the C/I code AR0 is applied.
Tear Down
In “Tear Down” state, transmission ceases in order to deactivate the basic access, and
the U-transceiver waits for a response (no signal level, LSU) from the NT-side.
Tear Down Error
“Tear Down Error” state is entered after loss of framing has been detected. Transmission
ceases in order to deactivate the basic access and the U-transceiver waits for a
response (no signal level, LSU) from the NT-side. EI3-indication is transmitted after a
transition forced by RES1 from the wait-for-TN or EQ-training states. In the case of
transition from the “Loss of synchronization” state RSY is sent.
Test
This “Test” mode is entered when the unconditional commands LTD, SSP or Pin-SSP is
applied. It is left when pin SSP is set inactive again and the C/I-channel code DR or
RES1 is received. Single pulses (SP) and DEAC are output in “Test” state. The U-
transceiver does not react to the receipt of a wake-up signal TN.
Transparent
This “Transparent” state corresponds to the fully active state in the case of a normal
activation for call control. It may also be entered in the case of a loop-back #2 if the NT
issues ACT = 1 or in case of a single-channel loop-back in the NT. The LT-side is
informed that the status “ready for sending” is reached (indication AI). If the NT-side
loses transparency (receipt of ACT = 0), the LT-side is informed by making use of the C/
I-channel indication EI2, but no state change is performed. Upon reception of ACT= (1)
the C/I indication AI is issued again. If the S/T-interface is deactivated (SAI = (0) & ACT
= (0)), the device is transferred to the S/T deactivated state.
Data Sheet
67
2001-07-16
PEF 24911
Functional Description
Wait for TN
In “Wait for TN” the U-transceiver waits for a response (tone TN from the NT or tone TL
in case of an analog loop-back) to the transmission of the wake-up signal TL. If no
response is received within T3, the state is left for re-transmission of a wake-up tone TL.
This procedure is repeated until the detection of tone TN or until expiry of timer T1. In
this case the C/I-channel indication EI3 is issued, but no state change is performed.
Data Sheet
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PEF 24911
Operational Description
4
Operational Description
The scope of this section is to describe how the DFE-Q V2.1 works and behaves in the
system environment. Activation/ deactivation control procedures are exemplary given for
SW programmers reference.
4.1
Reset
There are two different ways to apply a reset,
• either as a hardware reset by setting pin RES to low
• or as a software reset by applying ’C/I= RES’
Hardware Reset
A hardware reset affects all design components and takes effect immediately
(asynchronous reset style). No clock signal other than the 15.36 MHz master clock is
required for reset execution.
Software Reset
C/I ’RES’ resets the receiver and the activation/deactivation state machine.
Transmission on U is stopped. It is an unconditional command and is therefore
applicable in any state.
Unlike a hardware reset, a software reset triggered by ’C/I= RES’ or ’C/I= RES1’ has only
effect on the addressed line port.
– C/I= RES resets the receiver and the activation/deactivation state machines. It is an
unconditional command.
– C/I= RES1 resets all receiver functions. Transmission on U is stopped. EC-, and EQ-
coefficients and AGC are set to zero. It is a conditional command.
The remaining line ports, the system interface, the relay driver/ status pins and other
global functions are not affected. Note that FSC and DCL clock signals must be provided
for the C/I code processing.
4.2
Power Down
Each building block of the DFE-Q V2.1 is optimized with respect to power consumption
and support a power down mode. See Chapter 7.6.2 on Page 139 for the specified max.
power consumption.
The DFE-Q V2.1 goes in power down mode if the U-transceiver is in state
DEACTIVATED. The DFE-Q V2.1 leaves power down mode when a wake up tone (TN)
has been detected on the U-interface for at least 800 µs.
• as the internal control logic of the activation/deactivation procedures are event driven
power is saved as soon as one of the four lines transits in the ’Deactivated’ state
Data Sheet
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2001-07-16
PEF 24911
Operational Description
Regarding the DFE-Q V2.1 power down mode means that
• the DSP clock is turned off
• all digital circuits (excluding the IOM -2 interface) go in power down mode
• no timing signals are delivered (CLS0, ... , CLS3)
®
• as the internal control logic of the activation/deactivation procedures are event driven
power is saved as soon as one of the four lines transits in the DEACTIVATED state
Regarding a connected AFE power down mode means that
• no signal is sent on the U-interface
• only functions that are necessary to detect the wake up conditions are kept active
• transmit path, receive path and auxiliary functions of the analog line port are switched
to a low power consuming mode when the power down function is activated. This
implies the following:
• the ADC, the relevant output is tied to GND.
• the DAC and the output buffer; the outputs AOUTx/ BOUTx are tied to GND.
• the internal DC voltage reference is switched off.
• the range and the loop functions are deactivated.
Data Sheet
70
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PEF 24911
Operational Description
4.3
Layer 1 Activation/ Deactivation Procedures
This chapter illustrates the interactions during activation and deactivation between the
LT and NT station. An activation can be initiated by either of the two stations involved. A
deactivation procedure can be initiated only by the exchange.
This chapter shows the user how to activate and deactivate the device under various
circumstances. Two types of start-up procedures are supported by the U-transceiver:
• cold starts and
• warm starts.
Cold starts are performed after a reset and require all echo and equalizer coefficients to
be recalculated. This procedure typically is completed after 1-7 seconds depending on
the line characteristic and the connected NT. Cold starts are recommended for
activations where the line characteristic has changed considerably since the last
deactivation.
A warm start procedure uses the coefficient set saved during the last deactivation. It is
therefore completed much faster (maximum 300 ms). Warm starts are however
restricted to activations where the line characteristic has not changed significantly since
the last deactivation.
Both start-up procedures differ only in the fact that the device has been transferred into
the RESET state (= cold start) prior to activation. Activation initialization and procedure
is in both cases identical. The following sections thus apply to both warm and cold start-
ups.
The table below summarizes the existing U-interface signals as specified by ETSI/ ANSI.
Table 12
U-Interface Signals
Signal
Synch. Word
(SW)
Superframe
(ISW)
2B + D
M-Bits
NT-Modes (NT –> LT)
1)
TN
±⊄3
± 3
no signal
absent
± 3
± 3
no signal
1
SN0
SN1
SN2
SN3
SN3T
no signal
present
present
present
present
no signal
1
absent
1
1
1
present
normal
normal
present
normal
LT-Modes (LT –> NT)
± 3
1)
TL
± 3
± 3
no signal
1
± 3
no signal
1
SL0
SL1
no signal
present
no signal
absent
Data Sheet
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PEF 24911
Operational Description
Signal
Synch. Word
(SW)
Superframe
(ISW)
2B + D
M-Bits
SL2
present
present
present
present
present
0
0
normal
normal
normal
2)
SL3
3)
SL3T
present
normal
Test Mode
no signal
4)
SP
no signal
± 3
no signal
1)
Note: Alternating ± 3 symbols at 10 kHz
2)
Note: Must be generated by the exchange
3)
Note: If state ’Line Active’ is entered from state ’EQ-Training 1’ the 2B+D data must
be clamped to ’0’ by the exchange until act= ’1’ has been received from the NT-
side
4)
Note: Alternating ± 3 single pulses of 12.5 µs duration spaced by 1.5 ms
Data Sheet
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PEF 24911
Operational Description
4.3.1
Complete Activation Initiated by LT
Figure 28 depicts the procedure if the activation has been initiated by the exchange
side.
•
IOMR- 2
IOM R- 2
S/T
U - Reference Point
INFO 0
INFO 0
DC
DI
SL0
SN0
DC
DI
AR
TL
PU
DC
TN
AR
SN1
SN0
SL1
SL2 act = 0 dea = 1 uoa = 1
SN2
ARM
UAI
AR
AR
SN3 act = 0 (sai = 0)
INFO 2
SN3 act = 0 sai = 1
SL3T act = 0 dea = 1 uoa = 1
INFO 3
INFO 4
AI
AI
SN3 act = 1 sai = 1
SL3T act = 1 dea = 1 uoa = 1
AI
SN3T
SL3T
Layer-1
S-Transceiver
U-Transceiver
DFE-Q V2.1
Controller
NT
LT
actbyLT_2b1q.emf
Figure 28
Complete Activation Initiated by LT
Data Sheet
73
2001-07-16
PEF 24911
Operational Description
The activation protocol and the user interactions are summarized below:
•
®
®
NT IOM -2
LT IOM -2
<––––– C/I DC
–––––> C/I DI
(1111 )
CI/DC
C/IDI
(1111 ) <––––– ; Initial state is “Deactivated”
B
B
(1111 )
(1111 ) –––––>
;
B
B
<––––– C/I PU
<––––– C/I DC
(0111 )
C/I AR
C/I AR
(1000 ) <––––– ; Start activation
B
B
(1111 )
(1000 ) –––––> ; Activation proceeds
B
B
C/I ARM
C/I UAI
(1001 ) –––––>
;
;
:
:
B
<––––– C/I AR
–––––> C/I AI
(1000 )
(0111 ) –––––>
B
B
(1100 )
; Confirm that terminal is
; active
B
<––––– C/I AI
(1100 )
C/I AI
(1100 ) –––––> ; Activation complete
B
B
4.3.2
Activation with ACT-Bit Status Ignored by the Exchange Side
The LT ignores the ACT-bit transmitted upstream from the NT if the LT-activation has
been initiated with „AR0“ instead of „AR“. Activation with C/I-command “AR0” forces the
state machine into the state “Line Active” independently of the ACT-bit status transmitted
upstream from the network.
Because the activation with AR0 is performed with the UOA-bit set to “0”, initially only a
partial activation is started. By setting UOA = 1 via a MON-2 message the S-interface is
activated as well. Activation may be completed after the ACT-bit evaluation has been
enabled with C/I-command “AR”.
Data Sheet
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PEF 24911
Operational Description
•
IOMR- 2
IOM R- 2
S/T
U - Reference Point
INFO 0
INFO 0
DC
DI
SL0
SN0
DC
DI
AR0
TL
PU
DC
TN
AR
SN1
SN0
SL1
SL2 act = 0 dea = 1 uoa = 0
SN2
ARM
SN3 act = 0 (sai = 0)
SL3T act = 0 dea = 1 uoa = 0
SL3T act = 0 dea = 1 uoa = 1
UAI
MON 2: uoa = 1
AR
AR
AI
INFO 2
INFO 3
SN3 act = 0 sai = 1
SN3 act = 1 sai = 1
AR
AI
SL3T act = 1 dea = 1 uoa = 1
AI
INFO 4
SN3T
SL3T
Layer-1
S-Transceiver
U-Transceiver
DFE-Q V2.1
Controller
NT
LT
actbyLT_ignact_2b1q.emf
Figure 29
Activation with ACT-Bit Status Ignored by the Exchange
Data Sheet
75
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PEF 24911
Operational Description
The activation protocol and the user interaction is summarized below:
®
®
NT IOM -2
LT IOM -2
<––––– C/I DC (1111 ) C/I DC
(1111 )
<––––– ; Initial state is “Deactivated”
–––––> ;
B
B
–––––> C/I DI
<––––– C/I PU
(1111 ) C/I DI
(1111 )
B
B
C/I AR0
(0111 ) C/I AR
(1101 )
<––––– ; Start activation
–––––> ;
B
(1000 )
B
B
<––––– C/I DC (1111 ) C/I ARM
(1001 )
–––––> ;
B
B
C/I UAI
(0111 )
–––––> ;
B
MON8 PACE (80 BE ) <––––– ; Enable control of UOA-bit
H
MON2 UOA
(2F FF ) <––––– ; and set UOA = 1
H
<––––– C/I AR
–––––> C/I AI
<––––– C/I AR
(1000 )
B
(1100 )
: Confirm that terminal is
; active
B
(1000 ) C/I UAI
(1100 )
–––––> ; ACT-bit status ignored
<––––– ; Enable ACT-bit evaluation
–––––> ; Activation complete
B
B
C/I AR
(1000 )
B
<––––– C/I AI
<––––– C/I AR
(1100 ) C/I AI
(1100 )
B
B
C/I AR0
(1000 ) C/I UAI
(1101 )
<––––– : Disable ACT-bit evaluation
–––––> : ACT-bit status ignored
B
(0111 )
B
B
Data Sheet
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PEF 24911
Operational Description
4.3.3
Complete Activation Initiated by TE
Figure 30 depicts the procedure if the activation has been initiated by the terminal side.
•
S/T
IOMR- 2
IOMR- 2
U - Reference Point
INFO 0
INFO 0
INFO 1
DC
DI
SL0
SN0
DC
DI
TIM
PU
AR
TN
AR
DC
SN1
SN0
SL1
SL2 act = 0 dea = 1 uoa = 0
SN2
ARM
UAI
SN3 sai = 1
SL3T uoa = 1
AR
actbyNT_2b1q.emf
Figure 30
Complete Activation Initiated by TE
When initiating an activation from the terminal side, the LT must be in the
DEACTIVATED state. For a TE initiated activation to be successful the downstream LT
C/I-code must be DC. This is not the case if the DEACTIVATED state has been entered
from the RESET or TEST state (the last code is DR in this case).
•
Data Sheet
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PEF 24911
Operational Description
®
®
NT IOM -2
LT IOM -2
<––––– C/I DC
(1111 )
C/I DC
C/I DI
(1111 ) <––––– ; Initial state is “Deactivated”
B
B
–––––> C/I DI
(1111 )
(1111 ) –––––>
B
B
®
–––––> C/I TIM
<––––– C/I PU
(0000 )
; Start IOM -clocks
B
(0111 )
; U-transceiver is in power-
up
B
–––––> C/I AR
(1000 )
B
2)
–––––> TIM release
; Start activation
<––––– C/I DC
(1111 )
C/I AR
(1000 ) –––––> ; Activation proceeds
B
B
C/I ARM
C/I UAI
(1001 ) –––––>
;
;
:
:
B
<––––– C/I AR
–––––> C/I AI
(1000 )
(0111 ) –––––>
B
B
(1100 )
; Confirm that terminal is
; active
B
<––––– C/I AI
(1100 )
C/I AI
(1100 ) –––––> ; Activation complete
B
B
Data Sheet
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PEF 24911
Operational Description
4.3.4
Complete Deactivation
•
IOMR- 2
IOMR- 2
AR
S/T
U - Reference Point
INFO 4
INFO 3
AI
AI
SL3T act = 1 dea = 1 uoa = 1
SN3T act = 1 sai = 1
AI
DR
SL3T act = 0 dea = 1
SL0
DEAC
40 ms
DC
DR
SN0
3 ms
INFO 0
INFO 0
3 ms
DI
TIM
DI
40 ms
DC
Layer-1
S-Transceiver
U-Transceiver
DFE-Q V2.1
Controller
NT
LT
deac_2b1q.emf
Figure 31
Complete Deactivation
Deactivating the U-interface can be initiated only by the exchange. A deactivation can
be started when the device is in the states LINE ACTIVE, PEND. TRANSPARENT or
TRANSPARENT.
•.
®
®
NT IOM -2
LT IOM -2
C/I DR
(0000 ) <––––– ; Start deactivation
B
<––––– C/I DR
(0000 )
C/I DEAC (0001 ) –––––> ; Deactivation proceeds
B
B
C/I DI
(1111 ) –––––> ; Deactivation complete on
B
; LT
Data Sheet
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PEF 24911
Operational Description
®
®
NT IOM -2
LT IOM -2
–––––> C/I DI
<––––– C/I DC
(1111 )
; Power down NT
; Deactivation complete on
; NT
B
(1111 )
B
4.3.5
Partial Activation (U Only)
If the U-transceiver is only partially activated the S-interface remains deactivated. When
the partial activation is initiated by the LT-side, the exchange has two options:
• First, in case the C/I-command DC is not issued after the partial activation is complete,
the exchange has to issue AR before a terminal initiated complete activation request
is accepted. This allows the exchange to retain full control, even in case of terminal
initiated activation requests.
• Secondly the exchange can issue DC after UAI has been received. This allows the
terminal to activate the S-interface independently of the exchange. In this case the
exchange has no control of the S-interface activation procedure.
The NT U-transceiver is in the “Synchronized 1” state after a successful partial
activation. On DOUT the C/I-message “DC” as well as the LT-user data is sent.
While the C/I-messages “DI” (1111 ) or “TIM” (0000 ) are received on DIN, the U-
B
B
transceiver will transmit “SAI” = (0) upstream. Any other code results in “SAI” = (1) to be
sent. On the U-interface the signal SN3 (i.e. 2B + D = (1)) will be transmitted continuously
regardless of the data on DIN.
The LT will transmit all user data transparently downstream (signal SL3T). In case the
last C/I-command applied to DIN was “UAR”, the LT retains activation control when an
activation request comes from the terminal (confirmation with C/I = “AR” required. With
C/I “DC” applied on DIN, TE initiated activations will be completed without the necessity
of an exchange confirmation.
•
•
®
®
NT IOM -2
LT IOM -2
<––––– C/I DC
(1111 )
C/I DC
C/I DI
(1111 ) <––––– ; Initial state is “Deactivated”
B
B
–––––> C/I DI
(1111 )
(1111 ) –––––>
B
B
C/I UAR
C/I AR
(0111 ) <––––– ; Start partial activation
B
<––––– C/I PU
<––––– C/I DC
(0111 )
(1000 ) –––––> ; Activation proceeds
B
B
(1111 )
C/I ARM
C/I UAI
[C/I DC
(1001 ) –––––>
;
:
B
B
(0111 ) –––––> ; Partial activation complete
B
(1111 )] <––––– ; Exchange retains no
B
; control of S-interface
activation
Data Sheet
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PEF 24911
Operational Description
•
IOMR- 2
IOM R- 2
S/T
U - Reference Point
INFO 0
INFO 0
DC
DI
SL0
SN0
DC
DI
UAR
TL
PU
DC
TN
AR
SN1
SN0
SL1
SL2 act = 0 dea = 1 uoa = 0
SN2
ARM
SN3 act = 0 sai = 0
SL3T act = 0 dea = 1 uoa = 0
UAI
(DC)
Layer-1
S-Transceiver
U-Transceiver
DFE-Q V2.1
Controller
NT
LT
actbyLT_uar_2b1q.emf
Figure 32
U Only Activation
Data Sheet
81
2001-07-16
PEF 24911
Operational Description
4.3.6
Activation Initiated by LT with U Active
When U is already active, the S-interface can be activated either by the exchange or by
the terminal. The first case is described here, the second in the next section.
•
IOMR- 2
IOMR- 2
S/T
U - Reference Point
INFO 0
INFO 0
DC
DI
SL3T act = 0 dea = 1 uoa = 0
SN3 act = 0 sai = 0
DC / UAR
UAI
AR
SL3T act = 0 dea = 1 uoa = 1
SN3 act = 0 sai = 1
AR
AR
INFO 2
INFO 3
AR
AI
AI
SN3 act = 1 sai = 1
SL3T act = 1 dea = 1 uoa = 1
UAI
AI
INFO 4
SN3T
SL3T
Layer-1
S-Transceiver
U-Transceiver
DFE-Q V2.1
Controller
NT
LT
actbyLT_uactiv_2b1q.emf
Figure 33
LT Initiated Activation with U-Interface Active
The S-interface is activated from the exchange with the command “AR”. Bit “UOA”
changes to (1) requesting S-interface activation.
Data Sheet
82
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PEF 24911
Operational Description
•
®
®
NT IOM -2
LT IOM -2
<––––– C/I DC
–––––> C/I DI
(1111 )
C/I UAR [DC]
<––––– ; U only is activated
B
(1111 )
C/I UAI
(0111 ) –––––> ; [exchange retains no
B
B
; control]
C/I AR
(1000 ) <––––– ; Start complete activation
B
<––––– C/I AR
–––––> C/I AR
(1000 )
B
(1100 )
B
C/I AR
(1000 ) –––––> ; Activation proceeds
B
–––––> C/I AI
<––––– C/I AI
(1100 )
; Confirm that terminal is
; active
B
C/I UAI
C/I AI
(0111 ) –––––>
B
(1100 )
(1100 ) –––––> ; Activation complete
B
B
Data Sheet
83
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PEF 24911
Operational Description
4.3.7
Activation Initiated by TE with U Active
When the terminal requests to activate the S-interface (U-interface already active) two
cases can occur:
In the first case the exchange has retained control over the S-interface activation. Then
S-activation can proceed only after the explicit permission by the exchange with AR. This
situation is discussed in this section under “case 1”.
In the second case the exchange is not requested to send AR in order to continue
activation. This situation is described in “case 2” of this section.
The TE initiates complete activation with INFO 1 leading to “SAI” = (1). Case 1 requires
the exchange side to acknowledge the TE-activation by sending C/I = “AR”, Case 2
activates completely without any LT-confirmation. The TE recognizes no difference
between the two types, the procedure on NT-side consequently is identical in both
cases.
•
IOM R- 2
IOMR- 2
S/T
U - Reference Point
INFO 0
INFO 0
INFO 1
DC
DI
SL3T act = 0 dea = 1 uoa = 0
SN3 act = 0 sai = 0
UAR
UAI
AR
SN3 act = 0 sai = 1
AR
AR
SL3T act = 0 dea = 1 uoa = 1
AR
AI
INFO 2
INFO 3
SN3 act = 1 sai = 1
SL3T act = 1 dea = 1 uoa = 1
AI
UAI
AI
INFO 4
SN3T
SL3T
Layer-1
S-Transceiver
U-Transceiver
DFE-Q V2.1
Controller
NT
LT
actbyNT_uactiv1_2b1q.emf
Figure 34
TE-Activation with U Active and Exchange Control (case 1)
Data Sheet
84
2001-07-16
PEF 24911
Operational Description
Case 1 (controlled by exchange)
®
®
NT IOM -2
LT IOM -2
<––––– C/I DC
(1111 )
C/I UAR
C/I UAI
(0111 ) <––––– ; U only is activated
B
B
–––––> C/I DI
–––––> C/I AR
(1111 )
(0111 ) –––––>
B
B
(1000 )
; Terminal requests
; activation
B
C/I AR
(1000 ) –––––> ; Exchange is notified of
B
; request
C/I AR
(1000 ) <––––– ; Exchange permits
B
; S-activation
<––––– C/I AR
–––––> C/I AI
(1000 )
B
(1100 )
; Confirm that terminal is
; active
B
C/I UAI
C/I AI
(0111 ) –––––>
B
<––––– C/I AI
(1100 )
(1100 ) –––––> ; Activation complete
B
B
Data Sheet
85
2001-07-16
PEF 24911
Operational Description
•
IOMR- 2
IOMR- 2
S/T
U - Reference Point
INFO 0
INFO 0
INFO 1
DC
DI
SL3T act = 0 dea = 1 uoa = 0
SN3 act = 0 sai = 0
DC
UAI
AR
SN3 act = 0 sai = 1
AR
SL3T act = 0 dea = 1 uoa = 1
AR
AI
INFO 2
INFO 3
SN3 act = 1 sai = 1
SL3T act = 1 dea = 1 uoa = 1
AI
UAI
AI
INFO 4
SN3T
SL3T
Layer-1
S-Transceiver
U-Transceiver
DFE-Q V2.1
Controller
NT
LT
actbyNT_uactiv2_2b1q.emf
Figure 35
TE-Activation with U Active and no Exchange Control (case 2)
Case 2 (no control by exchange)
•
®
®
NT IOM -2
LT IOM -2
<––––– C/I DC
(1111 )
C/I DC
C/I UAI
<––––– ; U only is activated
(0111 ) –––––>
B
–––––> C/I DI
(0011 )
B
B
–––––> C/I AR
(1000 )
; Terminal requests
; activation
B
C/I AR
(1000 ) –––––> ; Exchange is notified of
B
<––––– C/I AR
–––––> C/I AI
(1000 )
; proceeding S-activation
; Confirm that terminal is
; active
B
(1100 )
B
C/I UAI
C/I AI
(0111 ) –––––>
B
<––––– C/I AI
(1100 )
(1100 ) –––––> ; Activation complete
B
B
Data Sheet
86
2001-07-16
PEF 24911
Operational Description
4.3.8
Deactivating S/T-Interface Only
The following shows the procedure for deactivating the S-interface only while leaving the
U-interface active. Deactivation of the S-interface only is initiated from the exchange by
setting the “UOA” bit = (0).
•
IOM R- 2
IOMR- 2
S/T
U - Reference Point
INFO 4
INFO 3
AI
AI
SL3T act = 1 dea = 1 uoa = 1
SN3T act = 1 sai = 1
AR
AI
UAR
SL3T act = 1 dea = 1 uoa = 0
DR
DI
INFO 0
INFO 0
SN3 act = 0 sai = 0
UAI
SL3T act = 0 dea = 1 uoa = 0
DC
(DC)
Layer-1
S-Transceiver
U-Transceiver
DFE-Q V2.1
Controller
NT
LT
deacST_2b1q.emf
Figure 36
Deactivation of S/T Only
•
®
®
NT IOM -2
LT IOM -2
<––––– C/I AI
–––––> C/I AI
(1100 )
C/I AI
(1100 ) –––––> ; Initial state: layer 1 activated
B
B
(1100 )
C/I AR
(1000 ) <–––––
B
B
<––––– C/I DR
(0000 )
C/I UAR
(0111 ) <––––– ; Deactivate S-interface only
B
B
Data Sheet
87
2001-07-16
PEF 24911
Operational Description
®
®
NT IOM -2
LT IOM -2
–––––> C/I DI
<––––– C/I DC
(1111 )
C/I UAI
[C/I DC
(0111 ) –––––> ; S-interface is deactivated
B
B
(1111 )
(1111 )] <–––––
;
Exchange retains no
control
B
B
4.4
Maintenance and Test Functions
This chapter summarizes all features provided by the DFE-Q V2.1 to support
maintenance functions and system measurements. Three main groups may be
distinguished:
– maintenance functions to close and open test loopbacks
– features facilitating the recognition of transmission errors
– test modes required for system measurements
The next sections describe how these test and maintenance functions are implemented
and used in applications.
4.4.1
Test Loopbacks
Test loopbacks are specified by the national PTTs in order to facilitate the location of
defect systems. Four different loopbacks are defined. The position of each loopback is
illustrated in Figure 37.
•
U
U
IOM®-2
S-BUS
Loop 2
Loop 2
S-Transceiver
U-Transceiver
IOM®-2
Loop 1 A
IOM®-2
NT
U-Transceiver
U-Transceiver
Loop 1
IOM®-2
U-Transceiver
Repeater (optional)
Loop 2
Layer-1 Controller
Layer-1 Controller
U-Transceiver
Exchange
IOM-2
Loop 3
U-Transceiver
PBX or TE
loop_2b1q.emf
Figure 37
Test Loopbacks
Data Sheet
88
2001-07-16
PEF 24911
Operational Description
Loopbacks #1, #1A and #2 are controlled by the exchange. Loopbacks #1 is closed by
the DFE-Q V2.1 itself whereas loopbacks #1A and #2 are remote controlled and closed
in the repeater and NT. Loopback #3 is closed and controlled by the terminal.
All four loopback types are transparent. This means all bits that are looped back will also
be passed onwards in the normal manner. The propagation delay of B- and D-channel
data is identical in all loopbacks.
Beside the remote loopback stimulation via the EOC- and MON-channel the DFE-Q V2.1
features also direct loopback control via its register set. The next sections describe how
these loopbacks are closed and opened using C/I- and MON-commands.
4.4.1.1 Analog Loopback (No.1)
Loopback #1 is closed by the DFE-Q V2.1 as near to the U-interface as possible. For this
reason it is called analog loopback. The 6 dB range attenuation in the receive path is
active.
Transparent
All analog signals will still be passed on to the U-interface. As a result the NT-station will
be activated as well. Only the internal loopback signal is processed. Signals on the
receive pins are ignored. For this reason the device stays in the “Line Active” state
(upstream ACT-bit cannot be received).
Loopback Activation
Before an analog loopback is closed the device should have been reset and put into
state “Deactivated” first before Loop-back #1 is closed. Then the C/I-command ARL
(activation request loopback) must be applied continuously as long as the loopback is
requested.
Loopback Deactivation
In order to open an analog loopback again the device should be reset by applying the C/
I-command RES (or by pin reset). This ensures that the echo coefficients and equalizer
coefficients will converge correctly when activating the next time.
The example below demonstrates the control of loopbacks #1.
•
®
®
NT IOM -2
<––––– C/I DC (1111B) C/I DI
C/I ARL (1010B) <––––– ; Close loopback #1
LT IOM -2
(1111B) –––––>
Data Sheet
89
2001-07-16
PEF 24911
Operational Description
®
®
NT IOM -2
LT IOM -2
<––––– C/I AR (1000B) C/I AR
(1000B) –––––> ; Activation proceeds in
NT
C/I ARM (1001B) –––––> ; and LT
C/I UAI (0111B) –––––> ; Activation complete,
; #1 closed
C/I RES (0001B) <––––– ; Open loopback #1,
; reset the U-transceiver
4.4.1.2 Loopback No.2 - Overview
For loopback #2 several alternatives exist. Both the type of loopback and the location
may vary. Three loopback types belong to the loopback #2 category:
• Complete loopback, in the NT U-transceiver or in a downstream device
• B1-channel loopback, always performed in the NT U-transceiver
• B2-channel loopback, always performed in the NT U-transceiver
®
All loop variations are closed as near to the IOM -interface as possible.
Complete Loopback
The complete loopback comprises both B-channels and the D-channel. It may be closed
either in the U-transceiver itself or in a downstream device. The propagation delay of B
and D-channel data is identical.
Single Channel Loopback
Single channel loopbacks are always performed within the U-transceiver. In this case the
digital data of DOUT will be directly fed back into DIN. This also applies if the complete
loopback is closed in the U-transceiver.
Normally loopback #2 is controlled from the exchange by the MON-0 commands LBBD,
LB1 and LB2. The loop requests are recognized and executed automatically by the NT
U-transceiver if automode is selected.
All loopback functions are latched in the NT. This allows channel B1 and channel B2 to
be looped back simultaneously. All loopbacks are opened again upon reception of the
EOC command RTN.
Transparency
Data sent downstream will be passed on transparent independently of closed loopbacks.
Data Sheet
90
2001-07-16
PEF 24911
Operational Description
4.4.1.3 Loopback No.2 - Complete Loopback
Upon receiving the EOC-command LBBD in EOC automode, the NT U-transceiver does
not close the loopback immediately. Because the intention of this loopback is to test the
complete NT, the U-transceiver passes the complete loopback request on to the next
downstream device (e.g. S-Transceiver). This is achieved by issuing the C/I-code AIL in
the “Transparent” state or C/I = ARL in states different than “Transparent”.
If the downstream device is not able to close the complete loopback, a MON-8-message
LBBD may be returned to the NT U-transceiver. This in turn will close the complete
loopback within the NT U-transceiver itself (B1 + B2 + D-channels).
®
All remaining IOM -information (monitor, C/I-channel as well as the bits MR and MX) are
®
still read from the IOM -2-interface. For this reason it is still possible for a layer-2 device
to deactivate the NT despite the fact that the loopbacks are controlled by the exchange.
Figure 38 illustrates these two options.
•
S-Transceiver
2B+D
NT U-Transceiver
C/I = AIL/ARL
U
28 B+D
EOC= "LBBD"
Auto-Mode
MON-8 "LBBD"
Layer-1
Controller
lp2bymon8.emf
Figure 38
Complete Loopback Options in the NT
The complete loopback is opened again by the NT U-transceiver (e.g. IEC-Q, PEB 2091)
when the EOC command RTN or the MON-8-command NORM is received. No reset is
required for loopback #2. The line stays active and is ready for data transmission. The
typical procedure for closing and opening a complete loopback is demonstrated in the
examples below. There the LT is always operated in EOC automode.
Complete Loopback in EOC Automode (NT-side):
•
®
®
NT IOM -2
LT IOM -2
C/I AR
(1000 ) <––––
; U-interface is activated
; without terminal
; confirmation
B
<–––– C/I AR
(–––> C/I AI
(1000 ) C/I UAI
(0111 ) ––––>
B
B
(1100 )
; or with
B
Data Sheet
91
2001-07-16
PEF 24911
Operational Description
®
®
NT IOM -2
LT IOM -2
<–––– C/I AI
(1100 ) C/I AI
(1100 ) ––––>
; terminal confirmation)
B
B
MON-0
LBBD
(50 )
<––––
; Close complete loop (EOC)
H
<–––– C/I AIL
<–––– MON-0
LBBD
(1110 )
; Request for downstream
; device to close complete
; loopback
B
(50 )
H
MON-0
LBBD
(50 )
––––>
; Receive acknowledgment
H
––––> MON-8
(F1 )
; If downstream device can’t
; close, loop is closed in the
NT U-transceiver
H
LBBD
MON-0
RTN
(FF )
<––––
––––>
; Open all loopbacks
H
<–––– MON-0 RTN (FF )
; All loopbacks opened
H
MON-0
RTN
(FF )
; Receive acknowledgment
H
Data Sheet
92
2001-07-16
PEF 24911
Operational Description
Complete Loopback in EOC Transparent Mode (NT side):
®
®
NT IOM -2
LT IOM -2
–––>
<–––
C/I AI
C/I AI
(1100 ) C/I AR
(1000 ) <–––– ; U-interface is activated
B
B
(1100 ) C/I AI
(1100 ) ––––>
B
B
MON-0
LBBD
(50 )
<–––– ; Close complete loop (EOC)
H
<–––– MON-0
(50 )
; Request passes
; transparently the NT
H
LBBD
U-transceiver
–––>
–––>
MON-0
LBBD
MON-8
LBBD
(50 )
MON-0 LBBD (50 )
––––> ; Transmit acknowledgment
H
H
(F1 )
; Close complete loop in IEC
H
<–––– MON-0 RTN (FFH)
MON-0 RTN (FF )
<–––– ; Request to open all loops
––––> ; Receive acknowledgment
; Open all loopbacks
H
–––>
–––>
MON-0 RTN (FF )
MON-0 RTN (FF )
H
H
MON-8
NORM
(FF )
H
4.4.1.4
Loopback No.2 - Single Channel Loopbacks
Single channel loopbacks are always performed directly in the NT U-transceiver. No
difference between the B1-channel and the B2-channel loopback control procedure
exists. They are therefore discussed together.
• In EOC automode the B1-channel is closed by the EOC-command LB1. LB2 causes
the channel B2 to loopback. Because these functions are latched, both channels may
be looped back simultaneously by sending first the command to close one channel
followed by the command for the remaining channel.
• In EOC transparent mode single channels are closed by the corresponding MON-8-
commands.
Single channel loopbacks are resolved in the same manner as described for the
complete loopback, either by the EOC command RTN or by the MON-8 command
NORM. The NT may be deactivated while single loopbacks are closed.
Typical procedures for closing and opening single channel loopbacks are given in the
examples below. There the LT is always operated in EOC automode.
Data Sheet
93
2001-07-16
PEF 24911
Operational Description
Single-Channel Loopback in EOC Automode (NT-side):
®
®
NT IOM -2
LT IOM -2
–––>
<–––
C/I AI
C/I AI
(1100 ) C/I AR
(1000 ) <–––– ; U-interface is activated
B
B
(1100 ) C/I AI
(1100 ) ––––>
B
B
MON-0 LB1 (51 )
<–––– ; Close B1 loop (EOC)
H
<–––
<–––
MON-0 LB1 (51 )
; Loop B1 closed
H
MON-0 LB1 (51H)
––––> ; Receive acknowledgment
<–––– ; Close B2 loopback (EOC)
MON-0 LB2 (52 )
H
MON-0 LB2 (52 )
; Loop-back B1 and B2
; closed
H
MON-0 LB2 (52 )
––––> ; Receive acknowledgment
<–––– ; Open all loopbacks
; All loopbacks opened
H
MON-0 RTN (FF )
H
<–––
MON-0
RTN
(FF )
H
MON-0 RTN (FF )
––––> ; Receive acknowledgment
H
Single-Channel Loopback in EOC Transparent Mode (NT-side):
®
®
NT IOM -2
LT IOM -2
–––>
<–––
C/I AI
C/I AI
(1100 ) C/I AR
(1000 ) <–––– ; U-interface is activated
B
B
(1100 ) C/I AI
(1100 ) ––––>
B
B
MON-0 LB1
(51 )
<–––– ; Close B1 loop (EOC)
; Request passes IEC
H
<–––
MON-0 LB1 (51 )
H
; transparent
–––>
–––>
MON-0 LB1 (51 )
MON-0 LB1
(51 )
––––> ; Transmit acknowledgment
; Close B1 loop in IEC
H
H
MON-8 LB1 (F4 )
H
MON-0 LB2
(52 )
<–––– ; Close B2 loop (EOC)
; Request passes IEC
H
<–––
MON-0 LB2 (52 )
H
; transparent
–––>
–––>
MON-0 LB2 (52 )
MON-0 LB2
(52 )
––––> ; Transmit acknowledgment
; Close B2 loop in IEC
H
H
MON-8 LB2 (F2 )
H
; B1 and B2 closed
MON-0 RTN (FF )
<––––– ; Request to open all loops
H
–––>
–––>
MON-0 RTN (FF )
MON-0 RTN (FF )
–––––> ; Receive acknowledgment
H
H
MON-8
NORM
(FF )
; Open all loopbacks
H
Data Sheet
94
2001-07-16
PEF 24911
Operational Description
4.4.1.5 Local Loopbacks Featured By Register LOOP
Besides the standardized remote loopbacks the DFE-Q V2.1 features additional local
loopbacks for enhanced test and debugging facilities. The local loopbacks that are
featured by the internal register LOOP are shown in Figure 39. They are closed in the
DFE-Q V2.1 itself.
By register LOOP it can be configured whether the digital local looback is closed only for
the B1 and/or B2 or for all ISDN-BA channels and whether the loopback is closed
®
towards the IOM -2 interface or towards the U-Interface.
The bit TRANS in the LOOP register allows for selection of transparent or non-
transparent loopback mode. In transparent mode the data is both passed on and looped
back. In non-transparent mode the data is not forwarded but substituted by 1s (idle
code).
Note: The digital framer/deframer loopback (DLB) is always transparent.
Besides the loopbacks in the system interface a further digital loopback, the Framer/
Deframer loopback, is provided. It allows to test all digital functions of the 2B1Q U-
transceiver besides the signal processing blocks. However, an activation procedure is
not possible by closing the Framer/Deframer Loopback. Therefore, before loop DLB may
be closed, the DFE-Q V2.1 must be in a transparent state, e.g. by applying C/I-command
’Data Through DT’. If DLB is set to ’1’ in state ’Deactivated’, then a subsequent activation
fails.
Data Sheet
95
2001-07-16
PEF 24911
Operational Description
•
LOOP.LB1=1 or
LOOP.LB1=1 or
LOOP.LB2=1 or
LOOP.LBBD= 1
&
LOOP.LB2=1 or
LOOP.LBBD= 1
&
LOOP.U/IOM=
0
LOOP.U/IOM=
1
DFE-Q V2.1
DSP
U Protocol Processing Unit
SIU
2B1Q
Scram bler
U Fram ing
Encoder
Echo
Canceller
IOM®-2
A
G
C
2B1Q
PDM
De -
U De -
+
Equalizer
Filter
Decoder
Scram bler
Fram ing
System
Interface
Unit
Timing
Recovery
Activation/Deactivation
Controller
LOOP.DLB= 1
DFE-Q V2.1
DSP
U Protocol Processing Unit
SIU
2B1Q
Scrambler
U Fram ing
Encoder
IOM®-2
Echo
Canceller
System
Interface
Unit
A
G
C
PDM
Filter
2B1Q
De -
U De-
Equ aliz e r
+
Decoder
Scrambler
Fram ing
Timing
Recovery
Activation/Deactivation
Controller
loopreg.emf
Figure 39
Loopbacks Featured by Register LOOP
Data Sheet
96
2001-07-16
PEF 24911
Operational Description
4.4.2
Bit Error Rate Counter
For bit error rate monitoring the DFE-Q V2.1 features a 16-bit Bit Error Rate counter
(BERC) per line. The function is channel selective. The user can direct that the
measurement is performed only for the B1 or for the B2 or for the B1-, B2- and the D-
channel. Prerequisite is that the corresponding loop #2 of the addressed channel(s) has
been closed on the NT side before by an EOC command.
Operation:
• The respective loopback command has to be transmitted to the NT (EOC message
LBBD, LB1, or LB2).
• The system sets the respective channel to ’all zeros’.
• The respective lineport is adressed by setting the LP_SEL register.
• The BERC counter is reset to ’0000’ by reading register BERC.
• The BERC counter can be started after some time (full round trip delay) by selecting
the channel (s) to be checked in bits TEST.BER.
• The BERC is stopped by setting TEST.BER to ’00’.
• The number of bit errors (received ’1’s) can be read in register BERC.
• The system can enable the tested channel again.
4.4.3
Block Error Counters
The DFE-Q V2.1 provides internal counters for far-end and near-end block errors. This
allows a comfortable surveillance of the transmission quality on the U-interface. In
addition MON-messages indicate the occurrence of near-end errors, far-end errors and
the simultaneous occurrence of both error types.
A block error is detected each time when the calculated checksum of the received data
does not correspond to the control checksum transmitted in the successive superframe.
One block error thus indicates that one U-superframe has not been transmitted correctly.
No conclusion with respect to the number of bit errors is therefore possible.
The following two sections describe the operation of near and far-end block error
counters as well as the commands available to test them.
4.4.3.1 Near-End and Far-End Block Error Counter
A near-end block error (NEBE) indicates that the error has been detected in the receive
direction (i.e. NEBE = NT => LT error). Each detected NEBE-error increments the 8-bit
NEBE-counter. The NEBE counter stops at its maximum value FF and does not
H
overflow.
The current value of the NEBE counter can be read by the MON-8-command RBEN. The
response comprises two bytes: the first byte always indicates that a MON-8-message is
replied (80 ), the second represents the counter value (00 ) … (FF ). Each read
H
H
H
operation resets the counter to (00 ).
H
Data Sheet
97
2001-07-16
PEF 24911
Operational Description
A far-end block error identifies errors in transmission direction (i.e. FEBE = LT => NT
error). FEBE errors are processed in the same manner as NEBE-errors. The FEBE
counter is read and reset by the MON-8-command RBEF.
Data Sheet
98
2001-07-16
PEF 24911
Operational Description
Near-End Errors - Summary:
- Definition
A near-end block error (NEBE) indicates errors that occurred in the receive direction, i.e.
an detected error during transmission from NT to LT. A near-end block error is
considered detected when the calculated check-sum of the received U-superframe does
not correspond to the check-sum sent in the following U-superframe.
- Indications
Each detected NEBE causes the NEBE counter to be incremented (maximum count is
FF , no overflow). The U-maintenance bit “FEBE” is set to zero in the next U-superframe
H
(for a duration of one superframe).
- Read Out and Reset
The counter value may be read out by the MON-8-command RBEN
MON-8
RBEN
Read Block Errors Near-end
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
MON-8
ABEN
Answer Block Errors Near-end
C7 C6 C5 C4 C3 C2 C1 C0
1
0
0
0
C0 … C7: 8-bit counter value
Each read operation resets the NEBE-counter to 00 . The counter is also reset in all
H
states except the following ones:
- Line Active
- Pend. Transparent
- Transparent
- S/T Deactivated
Data Sheet
99
2001-07-16
PEF 24911
Operational Description
Far End Errors - Summary:
- Definition
A far-end block error (FEBE) indicates errors that occurred in the transmit direction, i.e.
an detected error during transmission from LT to NT. A far-end block error is detected
when the U-maintenance bit “FEBE” is set to zero.
- Indications
Each detected FEBE will cause the FEBE-counter to be incremented (maximum count
is FF , no overflow)
H
- Read Out and Reset
The counter value may be read out by the MON-8-command RBEF
MON-8
RBEF
Read Block Errors Far-end
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
MON-8
ABEN
Answer Block Errors Far-end
C7 C6 C5 C4 C3 C2 C1 C0
1
0
0
0
C0 … C7:8-bit counter value
Each read operation resets the FEBE-counter to 00 . The counter is also reset in all
H
states except the following ones:
- Line Active
- Pend. Transparent
- Transparent
- S/T Deactivated
The following section illustrates how block error counters are tested.
4.4.3.2 Testing Block Error Counters
Figure 40 illustrates how near- and far-end block error counters can be tested.
Transmission errors are simulated with artificially corrupted CRCs. With two commands
the cyclic redundancy checksum can be inverted. A third command offers the possibility
to invert single FEBE-bits.
• MON-8 CCRC causes the DFE-Q V2.1 to permanently transmit inverted CRCs.
With CCRC issued on LT-side, near-end block errors will be observed at the NT and
far-end errors are noticed at the LT.
Data Sheet
100
2001-07-16
PEF 24911
Operational Description
• MON-0 RCC requests the NT to send corrupt CRCs. Again the CRC will be
permanently inverted. After issuing RCC (NT in EOC automode) near-end block errors
will be registered on the LT-side.
• MON-0 NCC requests the NT to disable the NEBE-detection. However, the NCC
command shows only effect if the NT U-transceiver operates in EOC automode. The
different behavior of the NT U-transceiver is summarized below
Auto-modeNEBE-detection stopped, no MON-1 NEBE
messages and NEBE-counter disabled
Transparent modeNEBE-detection enabled, MON-1-message NEBE
issued and NEBE-counter enabled
• MON-8 SFB causes the DFE-Q V2.1 to invert single FEBE-bits. Because this
command does not provoke permanent FEBE-bit inversion but sets only one FEBE-
bit to (0) per SFB command it is possible to predict exactly the FEBE-counter value.
• MON-0 RTN and MON-8 NORM disable again activated test functions
Data Sheet
101
2001-07-16
PEF 24911
Operational Description
Figure 40
Block Error Counter Test
Data Sheet
102
2001-07-16
PEF 24911
Operational Description
4.4.4
System Measurements
The DFE-Q V2.1 features dedicated test modes to enable and ease system
measurements on U-interface. How these test modes can be used to conduct the most
frequently needed system measurements is described in the following sections.
4.4.4.1 Single-Pulses Test Mode (SSP)
In the send single pulses test mode the U-transceiver transmits on the U-interface
alternating ± 3 pulses spaced by 1.5 ms. Two options exist for selecting the “Send-
Single-Pulses” (SSP) mode:
– hardware selection:
– software selection:
Pin-SSP= ’1’
C/I code= SSP (0101 )
B
Both methods are fully equivalent besides the fact that the HW selection impacts all line
ports while the SW selection impacts only the chosen line. In SSP-mode the C/I-code
transmitted by the DFE-Q V2.1 is DEAC.
The SSP-test mode is required for pulse mask measurements.
4.4.4.2 Data Through Test Mode (DT)
When selecting the data-through test mode the DFE-Q V2.1 is forced directly into the
“Transparent” state. This is possible from any state in the state diagram.
Note: Data Through is a pure test mode. It is not suited to replace the activation/
deactivation procedures for normal operation, which are described in
Chapter 4.3.
The Data-Through option (DT) provides the possibility to transmit a standard scrambled
U-signal even if no U-interface wake-up protocol is possible. This feature is of interest
when no counter station can be connected to supply the wake-up protocol signals.
As with the SSP-mode, two options are available.
– hardware selection:
– software selection:
Pin-DT= ’1’
C/I code= DT (0110 )
B
Both methods are fully equivalent besides the fact that the HW selection impacts all line
ports while the SW selection is channel selective.
Note: In contrast to former versions, C/I-command ’ARL’ is not executed while Data
Through test mode is activated with pin DT = ’1’.
The DT test mode is required for power spectral density and total power measurements.
4.4.4.3 Reset Mode
In the reset mode the DFE-Q V2.1 does not transmit any signals. The chip is in RESET
state. All echo canceller and equalizer coefficients are reset.
Data Sheet
103
2001-07-16
PEF 24911
Operational Description
There are two methods in order to transfer the U-transceiver into the reset mode (See
Chapter 7.4.1 for reset timing):
– hardware selection:
– software selection:
Pin RES= ’0’ -> ’1’
C/I-code= RES (0001 )
B
Both alternatives are fully compatible besides the fact that the SW selection is channel
selective. The C/I-code DEAC is output by the DFE-Q V2.1 in the RESET state.
The master reset test mode is used for return-loss measurements.
4.4.4.4 Pulse Mask Measurement
– Pulse mask is defined in ANSI T1.601 and ETSI TS 102 080
– U-interface has to be terminated with 135 Ω
– DFE-Q V2.1 is in Send Single Pulses test mode (C/I = ’SSP’ or Pin SSP= ’1’)
– Measurements are done using an oscilloscope
4.4.4.5 Power Spectral-Density Measurement
– PSD is defined in ANSI T1.601 and ETSI TS 102 080
– U-interface has to be terminated with 135 Ω
– DFE-Q V2.1 is in Data Through test mode (C/I = ’DT’ or Pin DT= ’1’)
– For measurements a spectrum analyzer is employed
4.4.4.6 Total Power Measurement
– Total power is defined in ANSI T1.601 and ETSI TS 102 080
– Total power must be between 13 dBm and 14 dBm
– U-interface has to be terminated with 135 Ω
– DFE-Q V2.1 is in Data Through test mode (C/I= ’DT’ or Pin DT= ’1’)
– Measurements are done using an 80 kHz high-impedance low-pass filter and true
RMS-voltmeter
•
DFE-Q
V2.1
True RMS
Voltmeter
80 kHz
totpow .emf
Figure 41
Total Power Measurement Set-Up
Data Sheet
104
2001-07-16
PEF 24911
Operational Description
4.4.4.7 Return-Loss Measurement
– Return loss is defined in ANSI T1.601 and ETSI TS 102 080
– DFE-Q V2.1 is in RESET state (C/I = ’RES’ or Pin RES= ’0’)
– Measure complex impedance “Z” from 1 kHz – 200 kHz
– Calculate return loss with formula:
RL(dB) = 20log (abs((Z + 135) / (Z –135)))
4.4.4.8 Quiet Mode Measurement
– Quite mode is defined in ANSI T1.601 and ETSI TS 102 080
– DFE-Q V2.1 is in the “Reset” state (C/I = ’RES’ or Pin RES= ’0’)
– Trigger and exit criteria have to be realized externally
4.4.4.9 Insertion Loss Measurement
– Insertion loss is defined in ANSI T1.601 and ETSI TS 102 080
– DFE-Q V2.1 is in Data Through test mode (C/I = ’DT’ or Pin DT= ’1’)
– Trigger and exit criteria have to be realized externally
4.4.5
Boundary Scan
The DFE-Q V2.1 provides a boundary scan support for a cost effective board testing. It
consists of:
• Boundary scan according to IEEE 1149.1 specification
• Test Access Port controller (TAP)
• Five dedicated pins (TCK, TMS, TDI, TDO, TRST)
• Pins TRST, TDI and TMS are provided with an internal pullup resistor
• One 32-bit IDCODE register
• Pin TRST tied to low resets the Boundary Scan TAP Controller
(recommended setting for normal operation if the Boundary Scan logic is not used)
• Instructions CLAMP and HIGHZ were added, instructions SSP and DT were removed
in V2.1
Data Sheet
105
2001-07-16
PEF 24911
Operational Description
Boundary Scan
All pins except the power supply pins, the "Not Connected" pins and the pins TDI, TDO,
TCK, TMS, and TRST are included in the boundary scan chain. Depending on the pin
functionality one, two or three boundary scan cells are provided.
Table 13
Pin Type
Boundary Scan Cells.
Number of
Usage
Boundary Scan Cells
Input
Output
I/O
1
2
3
input
output, enable
input, output, enable
When the TAP controller is in the appropriate mode data is shifted into or out of the
boundary scan via the pins TDI/TDO using the 6.25 MHz clock on pin TCK.
The pins are included in the following sequence in the boundary scan chain:
•
BoundaryScan Pin Number
Number
Pin Name
Type
Number of
Scan Cells
TDI ––>
1.
62
61
60
59
58
56
55
53
52
51
50
49
48
47
46
DT
CLS3
RES
I
I/O
I
1
3
1
1
1
1
1
1
3
3
3
1
3
3
3
2.
3.
4.
AUTO
PBX
I
5.
I
6.
SSP
I
7.
SLOT0
LT
I
8.
I
9.
CLS2
D3D
I/O
I/O
I/O
I
10.
11.
12.
13.
14.
15.
D2D
CRCON
D1D
I/O
I/O
I/O
D0D
D3C
Data Sheet
106
2001-07-16
PEF 24911
Operational Description
BoundaryScan Pin Number
Number
Pin Name
Type
Number of
Scan Cells
TDI ––>
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
45
44
43
42
40
39
37
35
34
33
32
31
30
29
28
27
26
24
23
21
20
19
18
17
16
15
14
13
12
11
SLOT1
D2C
I
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
3
3
3
3
3
3
3
3
3
1
3
3
3
1
1
1
1
3
3
3
3
3
3
1
3
1
1
1
1
D1C
D0C
D3B
D2B
D1B
D0B
D3A
D2A
PUP
D1A
I/O
I/O
I/O
I
D0A
CLS0
ST00
ST01
ST10
ST11
ST20
ST21
CLS1
ST30
ST31
SDX
TPD
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I
DOUT
DIN
I/O
I
FSC
I
DCL
I
PDM0
I
Data Sheet
107
2001-07-16
PEF 24911
Operational Description
BoundaryScan Pin Number
Number
Pin Name
Type
Number of
Scan Cells
TDI ––>
46.
47.
48.
49.
50.
10
8
PDM1
PDM2
PDM3
SDR
I
I
I
I
I
1
1
1
1
1
7
5
4
CL15
TAP Controller
The Test Access Port (TAP) controller implements the state machine defined in the
JTAG standard IEEE 1149.1. Transitions on pin TMS cause the TAP controller to
perform a state change. Before operation the TAP controller has to be reset by TRST.
According to the IEEE 1149 standard 7 instructions are executable. The instructions
’CLAMP’ and ’HIGHZ’ were added. Instructions ’SSP’ and ’DT’ are no more supported
since its function is identical to that of the SSP and DT pins.
•
Table 14
TAP Controller Instructions:
Code
0000
0001
0010
0011
0100
0101
1111
Instruction
EXTEST
Function
External testing
INTEST
Internal testing
SAMPLE/PRELOAD
IDCODE
Snap-shot testing
Reading ID code
CLAMP
Reading outputs
HIGHZ
Z-State of all boundary scan output pins
Bypass operation
BYPASS
EXTEST is used to examine the board interconnections.
When the TAP controller is in the state "update DR", all output pins are updated with the
falling edge of TCK. When it has entered state "capture DR" the levels of all input pins
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
INTEST supports internal chip testing.
When the TAP controller is in the state "update DR", all inputs are updated internally with
the falling edge of TCK. When it has entered state "capture DR" the levels of all outputs
Data Sheet
108
2001-07-16
PEF 24911
Operational Description
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
0001 (INTEST) is the default value of the instruction register.
SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is
used to preload (TDI) / shift out (TDO) the boundary scan with a test vector. Both
activities are transparent to the system functionality.
IDCODE Register
The 32-bit identification register is serially read out via TDO. It contains the version
number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB
is fixed to "1".
Version
0001
Device Code
Manufacturer Code
0000 1000 001
Output
0000 0000 0111 0010
1
-->
TDO
Note: In the state "test logic reset" the code "0011" is loaded into the instruction code
register.
CLAMP allows the state of the signals included in the boundary scan driven from the
PEF 24911 to be determined from the boundary scan register while the bypass register
is selected as the serial path between TDI and TDO. These output signals driven from
the DFE-Q V2.1 will not change while CLAMP is selected.
HIGHZ sets all output pins included to the boundary scan path into a high impedance
state. In this state, an in-circuit test system may drive signals onto the connections
normally driven by the DFE-Q V2.1 outputs without incurring the risk of damage to the
DFE-Q V2.1.
BYPASS, a bit entering TDI is shifted to TDO after one TCK clock cycle, e.g. to skip
testing of selected ICs on a printed circuit board.
Data Sheet
109
2001-07-16
PEF 24911
Monitor Commands
5
Monitor Commands
®
The registers of the DFE-Q V2.1 are accessed via the Monitor channel of the IOM -2
interface. This chapter summarizes the available Monitor commands and messages.
Please refer to Chapter 3.2.4 for a detailed description of the Monitor handshake
procedure.
Monitor commands supported by the DFE-Q V2.1 are divided into three categories. Each
category derives its name from the first nibble (4 bits) of the two byte long message.
These are MON-0, MON-2 and MON-8. All monitor messages representing similar
functions are grouped together.
A special Monitor class are MON-12 commands which exist beside the known classes
listed above. By MON-12 commands it is possible to address internal registers directly.
MON-12 commands are always prioritized and are acknowledged first. See
Chapter 3.2.5 for the details on MON-12 commands and messages.
5.1
MON-0 - Exchanging EOC Information
MON-0 messages are used to write and read the registers containing the information of
the EOC-channel on the U-interface. It is important to note that MON-0 messages
provide only access to the device internal EOC-registers. The insertion and extraction of
a message on the U-frame is handled automatically by the EOC-processor of the device.
®
The EOC is controlled and monitored via MON-0 commands and messages in the IOM -
2 Monitor channel. MON-0 commands may be passed at any instant and need to be
transferred only once (applicable for auto and transparent mode). Code repetition is
performed within the chip by the EOC-processor. For more information about the EOC
processor and a detailed description of EOC auto/ transparent mode please see
Chapter 3.9.
The structure of a MON-0 message is shown below. The structure is identical in EOC
auto and transparent mode.
MON-0 Structure
1. Byte
2. Byte
0 0 0 0
MON-0
A A A | 1
i1 i2 i3 i4
i5 i6 i7 i8
Addr. | d/m
EOC Code
Addr: Address
– 0 = NT
– 1 … 6 = Repeater
– 7 = Broadcast
– 0 = Data
– 1 = Message
– 00 … FFH = coded EOC command/indication
d/m:
E:
Data/Message
EOC Code
Data Sheet
110
2001-07-16
PEF 24911
Monitor Commands
Nine MON-0 commands are defined and can be interpreted. MON-0 commands are
applied at DIN, MON-0 messages are issued at DOUT for confirmation. MON-0
messages have the highest priority among MON-0,2,8 and are issued first if i.e. a MON-
2 or a MON-8 message is simultaneously outstanding.
•
Table 15
MON-0 Functions
Function
Hex-
code
LT
i1-i8
D
U
00
H
H
Hold
Provokes no change. It may be used as a preliminary message in
configurations where the acknowledgment is delayed. E.g. in a repeater
configuration the NT-RP could answer with H while the EOC-
acknowledgment is passed upstream. Thereby it can be avoided that
the LT-control unit misinterprets the delayed ACK as a malfunction. The
device issues Hold if no NT or broadcast address is used or if the d/m
indicator is set to (0).
50
LBBD
Close complete loop-back (B1, B2, D)
The NT does not close the complete loop-back immediately after receipt
of this code. Instead it issues the C/I-command AIL (in “Transparent”
state and auto mode) or ARL in the states “Error S/T” and
“Synchronized”. This allows the downstream device to close the loop-
back if desired (e.g. S-transceiver). If the downstream device does not
close the loop a MON-8 command (LBBD) must be returned and the
loop-back is closed within the U-transceiver.
51
52
53
LB1
LB2
RCC
Closes B1 loop-back in NT
All B1-channel data will be looped back within the NT U-transceiver.
Closes B2 loop-back in NT
All B2-channel data will be looped back within the NT U-transceiver.
Request corrupt CRC
Upon receipt the NT transmits corrupted (= inverted) CRCs upstream.
This allows to test the near end block error counter on the LT-side. The
far end block error counter at the NT-side is stopped and NT-error
indications (MON-1) are retained.
54
NCC
Notify of corrupt CRC
Upon receipt of NCC the NT-block error counters (near-end only) are
disabled and error indications are retained. This prevents wrong error
counts while corrupted CRCs are sent (MON-8 CCRC).
AA
UTC Unable to comply
Message sent instead of an acknowledgment if an undefined EOC-
command was received by the NT.
Data Sheet
111
2001-07-16
PEF 24911
Monitor Commands
Table 15
MON-0 Functions (cont’d)
Hex-
code
LT
Function
i1-i8
D
U
FF
RTN
Return to normal
With this command all previously sent EOC-commands will be released.
The EOC-processor is reset to its initial state (FF ).
H
XX
ACK Acknowledge
If a defined and correctly addressed EOC-command was received by
the NT, the NT replies by echoing back the received command.
5.2
MON-2 - Exchanging Overhead Bits
MON-2 indications are used to transfer all overhead bits except those representing EOC-
and CRC-bits. Starting with the ACT-bit, the order is identical to the position of the bits
on the U-interface.
The first MON-2 message is issued immediately after reaching the ’Line Active’ state in
LT-mode. Thereby the control system is informed about the initial U-interface status after
a successful activation.
Later on MON-2 messages will only be sent if the system status has been changed. No
MON-2 messages are issued while CRC-violations are detected (default setting). This
prevents the system of being overloaded by faulty monitor indications. Alternative
validation modes besides CRC are provided by the MFILT register which can be
accessed via the MON-12 protocol (see Chapter 3.2.5 for the details).
MON-2 monitor messages have the second highest priority after MON-0 commands. Via
the MON-8 command “PACE” bit D1, SAI/UOA, can be controlled by a MON-2
command. By use of register M4WMASK the user can also gain control on all other
overhead bits via MON-2 commands (see again Chapter 3.8.2 for the details).
Latching
®
MON-2 data that is received from IOM is latched and transmitted on U. MON-2 data
®
received from U is just forwarded on IOM and is not latched.
MON-2 Structure
1. Byte
2. Byte
0 0 1 0
MON-2
D11 D10 D9 D8
Overhead Bits
D7 D6 D5 D4 D3 D2 D1 D0
Overhead Bits
D0 … 11: Overhead bits
Data Sheet
112
2001-07-16
PEF 24911
Monitor Commands
The bit positions in the MON-2 message correspond to the following overhead bits:
Table 16
MON-2 and Overhead Bits
Position
LT –> NT
MON-2/ U-Frame
D11/M41
D10/M51
D9/M61
Bit
ACT
1
Control
U-Trans/MON-2
MON-2
1
MON-2
D8/M42
DEA
1
U-Trans/MON-2
MON-2
D7/M52
D6/M62
FEBE
SCO
1
U-Trans/MON-2
MON-2
D5/M43
D4/M44
MON-2
D3/M45
1
MON-2
D2/M46
1
MON-2
D1/M47
UOA
AIB
U-Trans/MON-2
MON-2
D0/M48
Control via U-Transceiver
– ACT (Activation bit).ACT
– DEA (Deactivation bit).DEA
– UOA (U-Only Activation).UOA
= (1) –> Layer 2 ready for communication
= (0) –> LT informs NT that it will turn off
= (0) –> U-activation only
– FEBE (Far-end Block Error).FEBE = (0) –> Far-end block error occurred
Control via MON-2 is enabled:
– for SCO, AIB and the undefined bits marked with binary ’1’: by default
– for all other M4 bits: by programming register M4WMASK via MON-12 command
especially for UOA (U-Only Activation): also after MON-8 ’PACE’
– for bit FEBE: by programming register OPMODE.FEBE via MON-12 command
Control via other MON-Commands
– FEBE (Far-end Block Error)
MON-8 message ’SFB’ sets a single FEBE bit to ’0’
For more details about the meaning of the overhead bits please refer to ETSI TS 102
080 and ANSI T1.601.
Data Sheet
113
2001-07-16
PEF 24911
Monitor Commands
Transmission on U-Interface
– In transmit direction register M4WMASK decides which M4, M5 and M6 bits are controlled
automatically by the internal logic or by a MON-2 message.
– The DFE-Q V2.1 transmits a given bit polarity as long as it is not changed by a new MON-2
message.
– The spare bits (M51, M52, M61) are set to binary ’1’ when leaving a power-down state. No further
processing is performed by the U-transceiver.
Reception on U-Interface
– In the receive direction (on DOUT), the incoming M4, M5 and M6 bits are checked by the
selected validation mode. A MON-2 message defining all 12 bits is issued if a change of at least
one single bit other than the FEBE bit has been approved valid. Therefore a MON-2 message is
sent not more often than once per superframe (12 ms interval).
– In order to notify the controller of the initial system status, one MON-2 message is issued
immediately after reaching the “Line Active” state in LT-mode.
– The DFE-Q V2.1 will not issue MON-2 messages while the programmed validation criterion
(CRC, TLL, ... ) is not fulfilled.
5.3
MON-8 - Local Functions
Local functions are controlled via MON-8-commands. Local functions comprise e.g.
reading block error counters, stimulating test functions, etc. MON-8-commands have the
lowest priority and may be passed at any time and need to be transferred only once.
Latching
Latched commands in the NT must be disabled explicitly with the “NORM” command.
Internal transfer commands (RBEN/F, RID) are not latched. Test and activation control
commands (PACE, PACA, CCRC, LB1/2, LBBD) will be latched.
The following tables give an overview of structure and features of commands belonging
to this category.
MON-8 Structure
1. Byte
2. Byte
1 0 0 0
MON-8
0 0 0 0 / 1
D7 D6 D5 D4 D3 D2 D1 D0
Local Command (Message/Data)
The following local commands are defined. If a response is expected, it will comprise 2
bytes. In the two-byte response the first byte will indicate that a MON-8 answer is
transmitted, the second byte contains the requested information.
Data Sheet
114
2001-07-16
PEF 24911
Monitor Commands
Table 17
1.Byte
MON-8-Local Function Commands
MON-8-Functions
2.Byte
LT
Function
2nd
nibble
Code
(Bin)
D
U
0000 1011 1110 PACE
Partial Activation Control External
the PACE-command causes the DFE-Q V2.1 to ignore the
actual status of the SAI-bit and to behave as if SAI = (1) is
received. The SAI-bit is then controlled by MON-2
commands.
0000 1011 1111 PACA
Partial Activation Control Automatic
PACA enables the device to interpret and control the SAI-
bit automatically.
0000 1111 0000 CCRC
Corrupt CRC
this command causes the device to send inverted (i.e.
corrupted) CRCs. Corrupted CRCs are used to test block
error counters.
0000 1111 1111 NORM
0000 1111 1011 RBEN
Return to Normal
the NORM-command requests the device to stop the
transmission of corrupted CRCs.
Read Near-End Block Error Counter
the value of the near-end block error counter is returned
and the counter is reset to zero. The maximum value is
FF .
H
0000 1111 1010 RBEF
0000 r r r r r r r r
Read Far-End Block Error Counter
The value of the far-end block error counter is returned
and the counter is reset to zero. The maximum value is
FF .
H
ABEC Answer Block Error Counter
The value of the requested block error counter (FEBE/
NEBE) is returned (8 bit).
0000 0000 0000 RID
0000 0000 0110
Read Identification
AID
Answer Identification.
The DFE-Q V2.1 will reply with its ID upon a RID request
0000 1111 1001 SFB
0001 0111 DCBA SETD
Set FEBE-Bit to ’0’
FEBE is set to ’0’ for one single U-superframe
Set status of relay driver pins
four driver pins (DxA, DxB, DxC, DxD, x= line port no.) can
be set to either low or high.
Data Sheet
115
2001-07-16
PEF 24911
Monitor Commands
MON-8-Functions
Read status pin
0001 0000 0000 RST
the logic state of the status pins STx0, STx1 is requested.
0001 xxxxxxS S
1
AST
Answer ’RST’ request
also issued without explicit request - issued upon signal
change at the pins STx0, STx1
0
Notes:
r … r result from block error counter
x … x don’t care
Data Sheet
116
2001-07-16
PEF 24911
Register Description
6
Register Description
In this section the complete register map is described that is provided with the new MON-
12 protocol. For the protocol details please refer to Chapter 6.4.
The register address arrangement is given in Figure 42. The U-interface registers are
provided per line port. By register LP_SEL it can be determined which U register bank
and by that which line port number is addressed. LP_SEL adds an offset value to the
current address. The offset value is latched as long as register LP_SEL is overwritten
again.
Some registers, however, are identical to all line ports, writing into one of these registers
affects the settings of all ports independent from the value in LP_SEL.
6..0
U Register
Banks
ADR
+
Line Port 3
Line Port 2
Line Port 1
Line Port 0
Offset
1CH
LP_SEL
TEST
0FH
00H
6..0
M4WMASK
...
ADR
...
OPMODE
regmap_cust.emf
Figure 42
DFE-Q V2.1 Register Map
Data Sheet
117
2001-07-16
PEF 24911
Register Description
6.1
Register Summary
7
0
6
0
5
0
4
0
3
0
2
0
1
0
WR/RD
1/4
Ch.
ADR
LP_SEL
1C
LN2
LN1
WR/RD*
1
H
U-Interface Registers
OPMODE
MFILT
00
01
07
08
0F
0
0
FEBE
0
0
0
1
0
WR/RD*
WR/RD*
WR/RD*
WR/RD*
1
1
1
1
4
H
H
H
H
H
M56 FILTER
M4 FILTER
EOC FILTER
M4RMASK
M4WMASK
TEST
M4 Read Mask Bits
M4 Write Mask Bits
0
0
1
BER
CCRC
+-1
Tones
0
40KHz WR/RD*
TRANS
U/
IOM
LOOP
10
DLB
1
LBBD
LB2
LB1
WR/RD*
4
H
®
FEBE
NEBE
BERC
11
12
13
14
FEBE Counter Value
NEBE Counter Value
RD
RD
RD
4
4
4
H
H
H
H
BERC Counter Value (Bit 15-8)
BERC Counter Value (Bit 7-0)
*) read-back function for test use
l
Table 18
Register Map Reference Table
Reg Name Access
Address
Reset
Value
Comment
Page
No.
LP_SEL
WR
1C
00
Line Port Selection Reg.
line port 0 is selected by
default
121
H
H
U-Interface Registers
OPMODE WR
00
01
02
14
Opmode Register
121
122
H
H
H
MFILT
WR
M-Bit Filter Register
H
– EOC in automode
®
– M4 CRC checked vs. IOM
– M4 TLL checked vs. SM
– M56 CRC checked
M4RMASK
Data Sheet
WR
07
00
M4 Read Mask Register
any M4-bit change causes a
MON-2 message
125
H
H
118
2001-07-16
PEF 24911
Register Description
Table 18
Register Map Reference Table
Reg Name Access
Address
Reset
Value
Comment
Page
No.
M4WMASK
WR
08
BC
M4 Write Mask Register
automatic control of ACT,
DEA, UOA bit
127
H
H
TEST
LOOP
WR
WR
0F
40
08
TEST Register
129
130
H
H
10
LOOP Register
H
H
all local loops deactivated
FEBE
NEBE
BERC
RD
RD
RD
11
12
00
00
FEBE Counter Register
NEBE Counter Register
132
132
H
H
H
H
13 =−=14
0000
H
Bit Error Rate Counter Reg. 132
H
H
Data Sheet
119
2001-07-16
PEF 24911
Register Description
6.2
Reset of U-Transceiver Functions in State ’Deactivated’
The following U-transceiver registers are reset upon the transition to state ’Deactivated’:
Register
Reset to
Affected Bits/ Comment
U-Interface Registers
TEST
only the bits BER and CCRC are reset
only the bits LBBD, LB2 and LB1 are reset
reset upon deactivation
LOOP
FEBE
NEBE
BERC
00
00
H
H
reset upon deactivation
0000
reset upon deactivation
H
6.3
Mode Register Evaluation Timing
The point of time when mode settings are detected and executed differs with the mode
register type. Two different behaviors can be classified
• evaluation and execution after SW-reset (C/I= RES, RES1) or upon transition out of
state ’Deactivated’
Note: Write access to these registers/bits is allowed only, while the state machine is
in state Reset or Deactivated.
• immediate evaluation and execution
Below the mode registers are listed and grouped according to the different evaluation
times as stated above.
Register
Affected Bits
Comment
Registers Evaluated After SW-Reset or Upon Transition Out of State Deactivated
MFILT complete register
Immediate Evaluation and Execution
OPMODE
M4RMASK
M4WMASK
TEST
bit FEBE
complete register
complete register
complete register
complete register
LOOP
Data Sheet
120
2001-07-16
PEF 24911
Register Description
6.4
Detailed Register Description
6.4.1
LP_SEL - Line Port Selection Register
The Line Port Selection register selects the register bank that is associated with the
addressed line port. All line port specific register operations - line port specific registers
are indicated by a ’4’ in the last column of the register summary - are performed on the
line port that is addressed by the value of LP_SEL.
LP_SEL
read/write
Address: 1C
H
Reset value: 00
H
7
0
6
0
5
0
4
3
0
2
0
1
0
0
LN2
LN1
LN2,1
Line Port Number
00 =
01 =
10 =
11 =
Line port no. 0 is addressed by the following command
Line port no. 1 is addressed by the following command
Line port no. 2 is addressed by the following command
Line port no. 3 is addressed by the following command
U-Interface Registers
6.4.2
OPMODE - Operation Mode Register
The Operation Mode register determines the operating mode of the DFE-Q V2.1 in all
ports.
)
OPMODE
read* /write
Address: 00
H
Reset value: 02
H
7
0
6
0
5
4
3
0
2
0
1
1
0
0
FEBE
0
Data Sheet
121
2001-07-16
PEF 24911
Register Description
FEBE
6.4.3
Enable/Disable external write access to FEBE Bit in register M56W
0 =
external access to FEBE bit disabled - FEBE bit is set by internal
FEBE counter logic
1 =
external access to FEBE bit enabled - FEBE bit is controlled by
MON-2
MFILT - M-Bit Filter Options
The M-Bit Filter register defines the validation algorithm received Maintenance channel
bits (M1-M6) of the U-interface have to undergo before they are approved and passed
on to the system interface. The MFILT register is unique for all ports. Writing into MFILT
from one channel affects the setting of all channels.
M-bit changes are reported to the system environment by MON-0 (EOC) or MON-2 (M4-
®
M6) messages via IOM -2. To lower processor load due to faulty monitor messages
three different filter functions are supported, Triple-Last-Look (TLL), CRC check and On
Change.
• Triple-Last-Look (TLL)
A change of M-bit data has to be received in three consecutive U-frames until it is
approved valid and reported to the system interface.
• CRC
A change of M-bit data is only reported to the system interface if no CRC violation has
been detected.
The forwarding of M-bit changes is delayed by 12 ms (= 1x U-superframe) if received
M-bits are CRC covered. This way the M-bit data is checked with the actual CRC sum
which is received one U-superframe later.
• On Change
Every time the M-bit status has changed a MON-0 or MON-2 message is issued.
Some M4 bits, ACT, DEA and UOA, have two destinations, the state machine and the
system interface. Regarding these bits Triple-Last-Look (TLL) is applied by default
before the changed status is input to the state machine. Via bit no. 5 of the MFILT
register the user can decide whether the M4 bits which are input to the state machine
shall be approved by TLL (Bellcore requirement) or by the same verification mode as
selected for the issue of a MON-2 message.
The MFILT register setting is evaluated each time the DFE-Q V2.1 leaves the
“Deactivated” state. For further information on the handling regarding the Maintenance
channel please refer to Chapter 3.8.
Data Sheet
122
2001-07-16
PEF 24911
Register Description
)
MFILT
read* /write
Address: 01
H
Reset value: 14
7
H
6
5
4
3
2
1
0
M56 FILTER
M4 FILTER
EOC FILTER
M56
FILTER
controls the validation mode of the spare bits (M51, M52, M61) on a per bit
base. Approved M5, M6 bit changes are reported to the system interface by
a MON-2 message
X0 =
Apply same filter to M5 and M6 bit data as programmed for M4 bit
data
X1 =
On Change
if a change of the M5, M6 bit status has occurred a MON-2
message will be issued
M4
Filter
3-bit field which controls the validation mode of the M4 bits on a per bit
base. Approved M4 bit changes are reported to the system interface by a
MON-2 message.
– Bit 3 and 4 determine the filter algorithm that is applied for the triggering
of a MON-2 message
– Bit 5 controls whether the forwarding of M4 bits to the internal state
machine shall be approved by default by TLL or by the same filtering
mode as selected for the forwarding to the system environment
Note: Bellcore TR-NWT-397 (1993) requires to apply TLL to the M4 bits
before M4 bit changes are processed by the state machine
x00 = On Change
if a change of the M4 bit status has occurred it will be indicated to
the system by a MON-2 message
x01 = TLL coverage of M4 bit data
a change of M4 bit data is only passed on if it has been received in
three consecutive frames
x10 = CRC coverage of M4 bit data
a change of M4 bit data is passed on if no CRC violation has been
detected
Data Sheet
123
2001-07-16
PEF 24911
Register Description
x11 = CRC and TLL coverage of M4 bit data
a change in M4 bit data is reported to the system interface if no
CRC violation has been detected and if it has been received in
three consecutive frames,
the change is reported as soon as 3 complete U-superframes were
successfully analysed
0xx = M4 bits towards state machine are covered by TLL
1xx = M4 bits towards state machine are checked by the same
validation algorithm as programmed for the reporting to the system
interface
EOC
FILTER
3-bit field which controls the processing of EOC messages and its
verification algorithm
100=
EOC automatic mode
- ’Return Message Reception Function’ is enabled as soon as the
LT has transmitted an EOC command. It causes the DFE-Q V2.1
in LT mode to compare the received and verified (by TLL) EOC
messages with the last downstream transmitted EOC command.
A MON-0 message is issued if they prove to be equal.
For this particular received EOC message the ’different from
previous’ rule is NOT applied. This means that a MON-0 message
is even issued if the received EOC message is not different to the
one previously accepted.
All other incoming EOC messages besides the echo of the one
transmitted downstream will be evaluated by TLL and the
’different from previous’ verification.
- if no EOC command has been transmitted downstream a MON-0
message is issued only after the TLL criterion has been met and
the message is different from the one previously accepted
Data Sheet
124
2001-07-16
PEF 24911
Register Description
001=
EOC transparent mode without any filtering
- every 6 ms an EOC message is passed on by a MON-0 message
- suitable mode for Digital Loop Carrier applications
- no EOC filtering:
every 6ms an EOC messages is forwarded to the system
interface via a MON-0 message
- no acknowledgment
- no execution
- no latching is performed
010=
EOC transparent mode with ’On Change’ filtering
only if a change of the received EOC message has been detected
it is passed on
011 = EOC transparent mode with Triple-Last-Look (TLL) filtering
TLL coverage of EOC messages is enabled
6.4.4
M4RMASK - M4 Read Mask Register
Via the M4 Read Mask register the user can selectively control which M4 bit changes
are to be reported via MON-2 messages. The M4RMASK register is unique for all ports.
)
M4RMASK
read* /write
Address: 07
H
Reset value: 00
7
H
6
5
4
3
2
1
0
M4 Read Mask Bits
Bit 7..0
0 =
M4 bit change indication by MON-2 message active
M4 bit change indication by MON-2 message masked
1 =
Below the cross reference of the MASK bits to the M4 bits as they are sent from the NT
to the LT is given:
7
6
5
4
3
2
1
0
NIB
SAI
M46
CSO
NTM
PS2
PS1
ACT
NIB
Network Indication Bit
Data Sheet
125
2001-07-16
PEF 24911
Register Description
0 =
1 =
no function (reserved for network use)
no function (reserved for network use)
SAI
S-Activity Indicator
0 =
1 =
S-interface is deactivated
S-interface is activated
CSO
NTM
PS2
PS1
ACT
Cold Start Only
0 =
1 =
NT is capable to perform warm starts
NT activation with cold start only
NT Test Mode
0 =
1 =
NT busy in test mode
inactive
Power Status Secondary Source
0 =
1 =
secondary power supply failed
secondary power supply ok
Power Status Primary Source
0 =
1 =
primary power supply failed
primary power supply ok
Activation Bit
0 =
1 =
layer-2 not established
signals layer-2 ready for communication
Data Sheet
126
2001-07-16
PEF 24911
Register Description
6.4.5
M4WMASK - M4 Write Mask Register
By means of the M4WMASK register the user can direct on a per bit base which M4 bits
are controlled by MON-2 and which are controlled by the state machine. The M4WMASK
register is unique for all ports.
)
M4WMASK
read* /write
Address: 08
H
Reset value: BC
7
H
6
5
4
3
2
1
0
M4 Write Mask Bits
Bit 7..0
0 =
M4 bit is controlled by state machine
1 =
M4 bit is controlled by MON-2 command
Bit 6
Partial Activation Control External/Automatic,
function corresponds to the MON-8 commands PACE and PACA
0 =
1 =
UOA bit is controlled and SAI bit is evaluated by state machine
UOA bit is controlled by MON-2 command, SAI=’1’ is reported to
statemachine
Below the cross reference of the MASK bits to the M4 bits as transmitted from the LT to
the NT is given:
7
6
5
4
3
2
1
0
AIB
UOA
M46
M45
M44
SCO
DEA
ACT
AIB
Interruption (according to ANSI)
0 =
1 =
indicates interruption
inactive
UOA
U Activation Only
0 =
1 =
indicates that only U is activated
inactive
Data Sheet
127
2001-07-16
PEF 24911
Register Description
SCO
Start-on-Command Only Bit
indicates whether the DLC network will deactivate the loop between calls
(defined in Bellcore TR-NWT000397)
0 =
’Start-on-Command-Only’ mode active,
in LULT mode the U-transceiver shall initiate the start-up procedure
only upon command from the network (’AR’ primitive)
1 =
normal mode,
if the U-transceiver is operated within a DCL configuration as LULT
it shall start operation as soon as power is applied
DEA
ACT
Deactivation Bit
0 =
1 =
LT informs NT that it will turn off
inactive
Activation Bit
0 =
1 =
layer 2 not established
signals layer-2 ready for communication
Data Sheet
128
2001-07-16
PEF 24911
Register Description
6.4.6
TEST - Test Register
The Test register sets the DFE-Q V2.1 in the desired test mode.
)
TEST
read* /write
Address: 0F
H
Reset value: 40
H
7
0
6
1
5
4
3
2
1
0
0
BER
CCRC
+-1
40kHz
tones
BER
Bit Error Rate Measurement Function
– prerequisite: closed loopback #2 on the NT-side
– allows to measure the BER of either the B1-, the B2-, or the B1- and B2-
and D-channel in transparent state
– the user data stream is overwritten by a continuous series of zeros
00 =
01 =
Bit Error Rate (BERC) counter disabled
starts B1-channel BER measurement
Bit Error Rate counter (BERC) is enabled and a continuous series
of zeros is sent in channel B1
10 =
11 =
starts B2-channel BER measurement
Bit Error Rate counter (BERC) is enabled and a continuous series
of zeros is sent in channel B2
starts B1-, B2- and D-channel BER measurement
Bit Error Rate counter (BERC) is enabled and a continuous series
of zeros is sent in channel B1, B2 and D
CCRC
Send Corrupt CRC
0 =
1 =
inactive
send corrupt (inverted) CRCs
+-1 tones Send +/-1 pulses instead of +/-3 pulses
0 =
1 =
no action
issues +/-1 pulses instead of +/-3 during 40 kHz tone generation or
in SSP test mode
40kHz
40 kHz Test Signal
Data Sheet
129
2001-07-16
PEF 24911
Register Description
0 =
1 =
no action
issues a 40 kHz test signal - suitable for testing of test equipment
6.4.7
LOOP - Loop Back Register
The Loop register controls local loopbacks within the DFE-Q V2.1. For the loopback
configurations that are available by the LOOP register see Chapter 4.4.1.5.
)
LOOP
read* /write
Address: 10
H
Reset value: 08
H
7
0
6
5
4
3
1
2
1
0
®
DLB
TRANS U/IOM
LBBD
LB2
LB1
DLB
Close Framer/Deframer Loopback
– the loopback is closed at the analog/digital interface
– prerequisite is that LB1, LB2, LBBD and U/IOM are set to ’0’
®
– prerequisite is that the DFE-Q V2.1 is in a transparent state, e.g. by
applying C/I-command ’Data Through DT’.
– only user data is looped and no maintenance data is not looped back
– the DLB loop operates always in transparent mode
0 =
1 =
Framer/Deframer loopback open
Framer/Deframer loopback closed
TRANS
Transparent/ Non-Transparent Loopback
– in transparent mode user data is both passed on and looped back,
whereas in non-transparent mode data is not forwarded but substituted
by ’1’s (idle code) and just looped back
®
– if LBBD, LB2, LB1 is closed towards the IOM interface and bit TRANS
is set to ’0’ then the state machine has to be put into state ’Transparent’
first (e.g. by C/I = DT) before data is output on the U-interface
– bit TRANS has no effect on DLB (always transparent) and the analog
loopback (ARL operates always in transparent mode)
0 =
1 =
sets transparent loop mode for LBBD, LB2, LB1
sets non-transparent mode for LBBD, LB2, LB1
®
’1’s are sent on the IOM -2 interface in the corresponding time-slot
Data Sheet
130
2001-07-16
PEF 24911
Register Description
®
U/IOM
LBBD
LB2
Switch that selects whether looback LB1, LB2 or LBBD is closed towards U
or IOM -2
®
®
0 =
1 =
LB1, LB2, LBBD loops are closed towards IOM -2
LB1, LB2, LBBD loops are closed towards U
Close complete loop (B1, B2, D) near the system interface
the direction towards the loop is closed is determined by bit U/IOM
®
®
®
0 =
1 =
complete loopback open
complete loopback closed
Close loop B2 near the system interface
the direction towards the loop is closed is determined by bit U/IOM
0 =
1 =
loopback B2 open
loopback B2 closed
LB1
Close loop B1 near the system interface
the direction towards the loop is closed is determined by bit U/IOM
0 =
1 =
loopback B1 open
loopback B1 closed
Data Sheet
131
2001-07-16
PEF 24911
Register Description
6.4.8
FEBE - Far End Block Error Counter Register
The Far End Block Error Counter Register contains the FEBE value. If the register is
read out it is automatically reset to ’0’.
FEBE
read
Address: 11
H
Reset value: 00
7
H
6
5
4
3
2
1
0
FEBE Counter Value
6.4.9
NEBE - Near End Block Error Counter Register
The Near End Block Error Counter Register contains the NEBE value. If the register is
read out it is automatically reset to ’0’.
NEBE
read
Address: 12
H
Reset value: 00
7
H
6
5
4
3
2
1
0
NEBE Counter Value
6.4.10
BERC - Bit Error Rate Counter Register
The Bit Error Rate Counter register contains the number of bit errors that occurred during
the period the bit TEST.BER was set active. If the 2nd byte (addr. 14H) of the 16-bit
BERC counter is read out the 16-bit value is automatically reset to ’0’.
BERC
read
Address: 13/14
H
Reset value: 0000
15
H
14
13
12
11
10
9
1
8
0
Bit Error Rate Counter Value
7
6
5
4
3
2
Bit Error Rate Counter Value
Data Sheet
132
2001-07-16
PEF 24911
Electrical Characteristics
7
Electrical Characteristics
7.1
Absolute Maximum Ratings
Parameter
Symbol
TA
Limit Values
– 40 to 85
Unit
°C
°C
V
Ambient temperature under bias
Storage temperature
Tstg
– 65 to 125
– 0.3 to 4.6
– 0.3 to 5.5
IC supply voltage
VDD
Input voltage on Input pins and on high ohmic VS
V
Output pin with respect to ground
Maximum current supplied to any pin for more I
than 5 msec
±10
mA
V
s
1)
ESD robustness
VESD,HBM
2000
HBM: 1.5 kΩ, 100 pF
1)
According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993.
Note: Absolute maximum ratings are stress ratings only, and functional operation
and reliability under conditions beyond those defined in the operating range
is not guaranteed. Stresses above those absolute maximum ratings are
likely to cause permanent damage to the device.
7.2
Operating Range
Parameter
Symbol
Limit Values
Unit Test Condition
min.
– 40
3.0
max.
85
Ambient temperature
Supply voltage
Ground
TA
°C
V
VDD
VSS
VS
3.6
0
0
V
Voltage applied to input
pin
- 0.3
VDD+3.3
(max 5.25)
V
Voltage applied to output VS
pin in high ohmic state
(open drain)
- 0.3
VDD+3.3
(max 5.25)
V
Note: In the operating range, the functions given in the circuit description are fulfilled.
Data Sheet
133
2001-07-16
PEF 24911
Electrical Characteristics
7.3
DC Characteristics
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
0.8
Input low voltage
Input high voltage
VIL
– 0.3
V
1)
VIH
2.0
5,25
0.45
V
V
3.0V < VDD <3.3 V
2)
Output low voltage
Output high voltage
Input leakage current
VOL
IOL = 7 mA
IOL = 2 mA
3)
VOH
IIL
2.4
-1
V
IOH = – 7 mA 2)
I
OH = – 2 mA 3)
1
1
µA
V
V
DD = 3.3 V,
SS = 0 V; all other
pins are floating;
4)
0 V< VIN < VDD
Output leakage current
Input pull down current
IOZ
-1
µA
V
V
DD = 3.3 V,
SS = 0 V;
0 V< VOUT < VDD
IPD
IPU
50
200
-50
µA
µA
VIN = VDD
Input pull up current
-170
VIN = VSS
1)
Apply to all inputs and to DOUT in high ohmic state
Apply to: DOUT
2)
3)
4)
Apply to all other Output pins except DOUT
Apply to inputs having no pull up or pull down resistors
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and
the given supply voltage.
7.4
AC Characteristics
Inputs are driven to 2.4 V for a logical ’1’ and to 0.45 V for a logical ’0’. Timing
measurements are made at 2.0 V for a logical ’1’ and 0.8 V for a logical ’0’. The AC
testing input/output waveforms are shown in Figure 43.
Data Sheet
134
2001-07-16
PEF 24911
Electrical Characteristics
•
2.4 V
0.4 V
2.0 V
0.8 V
2.0 V
0.8 V
Test Points
AC_char.vsd
Figure 43
Input/Output Waveform for AC Tests
Reset Timing
7.4.1
•
Parameter
Symbol Limit Values
Unit Remark
min.
max.
Active Low Period
tRES
200
ns
the end of reset
execution is
delayed internally
for 900µs with
respect to the low
active phase
15.36 MHz master
clock has to be
applied
•
t
RES
RES
900µs
reset
intern
Figure 44
Reset Timing
Data Sheet
135
2001-07-16
PEF 24911
Electrical Characteristics
7.4.2
IOM®-2 Interface Timing
The dynamic characteristics of the IOM®-2-interface are given in Figure 45. In case the
period of signals is stated the time reference will be at 1.4 V. In all other cases 0.8 V (low)
and 2.0 V (high) thresholds are used as reference.
•
TDCL
tr
tf
DCL
FSC
twH
twL
thF
thF
tsF
twFH
tdDF
DOUT
DIN
Data Valid
thD
tdDC
Data Valid
tsD
ITD05637.vsd
®
Figure 45
IOM -2 Interface Timing
®
Table 19
IOM -2 Dynamic Input Characteristics
Parameter
Symbol Limit Values
Unit
min.
typ.
max.
DCL rise/fall time
DCL period
tr, tf
60
ns
ns
TDCL
122
DCL pulse width, high
low
twH
twL
53
53
(TDCL)/2
(TDCL)/2
ns
ns
FSC rise/fall
tr, tf
tsF
60
ns
ns
ns
ns
FSC setup time
FSC hold time
10
10
thF
FSC pulse width, high
low
twFH
twFL
2 × TDCL
2 × TDCL
Data Sheet
136
2001-07-16
PEF 24911
Electrical Characteristics
Unit
Parameter
Symbol Limit Values
min.
typ.
1 × TDCL
max.
Superframe FSC pulse width, high
DIN setup time
twFH
tsD
100
10
ns
ns
ns
DIN hold time
thD
10
®
Table 20
IOM -2 Dynamic Output Characteristics
Parameter
Symbol Limit Values
min. typ. max.
Unit Test Condition
DCL Data delay clock 1)
Pin PUP = ’0’
tdDC
tdDC
100 ns
CL = 150 pF,
Charged with 5V
CL = 100 pF,
Pin PUP = ’1’
40
20
ns
ns
Charged with 3.3V
FSC Data delay frame 1) tdDF
CL = 150 pF
1)
Notes: The point of time at which the output data will be valid is referred to the rising edges of
either FSC (tdDF ) or DCL (tdDC ). The rising edge of the signal appearing last (normally
DCL) shall be the reference.
7.4.3
Interface to the Analog Front End
The AC characteristics of the AFE-interface pins are optimized to fit to AFE Version 2.1
if the following loads are not exceeded.
Table 21
Pin
Interface Signals of AFE and DFE-Q
Signal Driving Device Max. Capacitive Load
Max. Connection resistance
CL15
AFE
50pF; 2 Ohms
20pF; 2 Ohms
20pF; 2 Ohms
20pF; 2 Ohms
SDR
AFE
PDM0…3
SDX
AFE
DFE-Q
Data Sheet
137
2001-07-16
PEF 24911
Electrical Characteristics
7.4.4
Boundary Scan Timing
•
Figure 46
Boundary Scan Timing
Boundary Scan Dynamic Timing Requirements
•
Table 22
Parameter
Symbol
Limit Values
Unit
min.
160
70
70
30
30
30
30
-
max.
test clock period
tTCP
-
-
ns
ns
ns
ns
ns
ns
ns
ns
test clock period low
t
TCPL
TCPH
test clock period high
TMS set-up time to TCK
TMS hold time from TCK
TDI set-up time to TCK
TDI hold time from TCK
TDO valid delay from TCK
t
-
t
-
MSS
t
-
MSH
t
-
DIS
t
-
DIH
t
60
DOD
Data Sheet
138
2001-07-16
PEF 24911
Electrical Characteristics
7.5
Capacitances
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
7
Input capacitance
Output capacitance
CIN
pF
pF
COUT
10
7.6
Power Supply
Supply Voltage
7.6.1
VDD to GND = +3.3 V ±0.3 V
7.6.2
Power Consumption
All measurements with random 2B+D data in active states, 3.3 V (0° C - 70° C)
•
Table 23
Mode
Power Consumption
Typ. values Max. values Unit
Test conditions
Power-up
85
100
mA
3.3 V, open outputs,
all Channels
inputs at V /V
DD SS
Power-down
35
t.b.d.
mA
3.3 V, open outputs,
inputs at V /V
DD SS
Data Sheet
139
2001-07-16
PEF 24911
Package Outlines
8
Package Outlines
•
P-MQFP-64
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
2001-07-16
SMD = Surface Mounted Device
Data Sheet
140
PEF 24911
Appendix A: Standards and Specifications
9
Appendix A: Standards and Specifications
The table below lists the relevant standards concerning transmission performance the
DFE-Q V2.1 claims to comply with.
Organization
Valid Document
for
ITU
International
Telecommunication
Union
World- ITU-T G.961
wide
Digital Transmission System
on Metallic Line for ISDN
Basic Rate Access
ETSI
European
Telecommunications
Standards Institute
EU
Technical
Transmission and
Specification
102 080 V1.3.1
(1988-11),
Multiplexing (TM);
ISDN basic rate access;
Digital transmission systems
abbrev. TS 102 080 on metallic local lines
(formerly known as
ETR 080)
ANSI
American National
USA
USA
T1E1 4/92-004 -
T1.601-1998
Basic Access Interface for
Use on Metallic Loops for
Application on the Network
Side of the NT (Layer 1
Specification)
Generic Requirements for
ISDN Basic Access Digital
Subscriber Lines
Standards Institute, Inc.
Telcordia Technologies Inc.
(formerly known as Bellcore)
TR-NWT-000393,
Issue 2, December
1992
TR-NWT-000397,
Issue 3, December
1993
ISDN Basic Access
Transport System
Requirements
TR-NWT-000829,
Issue 1, November
1989
OTGR: Generic Operations
Interface, Embedded
Operations Channel
SR-NWT-002397,
Issue 1, June 1993
Layer 1 Test Plan for ISDN
Basic Access Digital
Subscriber Line
Transceivers
BT
British
Telecommunications plc.
GB
Specification
RC7355E, Issue E,
03/97
2B1Q Generic Physical
Layer Specification
Data Sheet
141
2001-07-16
PEF 24911
Glossary
10
Glossary
•
A/D
Analog to digital
ADC
AGC
AIN
Analog to digital converter
Automatic gain control
Differential U-interface input
American National Standardization Institute
Differential U-interface output
64-kbit/s voice and data transmission channel
Differential U-interface input
Differential U-interface output
Corrupted CRC
Command/Indicate (channel)
Cyclic redundancy check
16-kbit/s data and control transmission channel
Digital-to-analog
ANSI
AOUT
B1, B2
BIN
BOUT
CCRC
C/I
CRC
D
D/A
DAC
DCL
DD
Digital-to-analog converter
Data clock
Data downstream
DT
Data through test mode
Data upstream
DU
EC
Echo canceller
EOC
EOM
ETSI
FEBE
FIFO
FSC
GND
HDLC
IEC-Q
Embedded operations channel
End of message
European Telephone Standards Institute
Far-end block error
First-in first-out (memory)
Frame synchronizing clock
Ground
High-level data link control
ISDN-echo cancellation circuit conforming to 2B1Q-transmission
code
®
IOM -2
ISDN-oriented modular 2nd generation
Data Sheet
142
2001-07-16
PEF 24911
Glossary
INFO
ISDN
LBBD
LT
U- and S-interface signal elements as specified by ANSI/ ETSI
Integrated services digital network
Loop-back of B- and D-channels
Line termination
MON
MR
Monitor channel command
Monitor read bit
MX
Monitor transmit bit
NEBE
NT
Near-end block error
Network termination
PLL
PS
Phase locked loop
Power supply status bit
PSD
PTT
PU
Power spectral density
Post, telephone, and telegraph administration
Power-up
RMS
S/T
Root mean square
Two-wire pair interface
SSP
TE
Send single pulses (test mode)
Terminal equipment
TL
TN
U
2B1Q
Wake-up tone sent from the LT side
Wake-up tone sent from the NT side
Single wire pair interface
Transmission code requiring 80-kHz bandwidth
Data Sheet
143
2001-07-16
PEF 24911
Timing 136
ITU 141
A
Absolute Maximum Ratings 133
AC Characteristics 134
Activation 71
L
Logic Symbol 4
ANSI 141
M
B
Monitor Channel 24
Monitor Commands 110
Bellcore 141
Boundary Scan 105
Timing 138
BT 141
O
Operating Range 133
C
P
Capacitances 139
Package Outlines 140
Pin Descriptions 11
Pin Diagram 11
Pinning Changes 19
Power Consumption 139
Power Down 69
Power Supply 139
Protocol 3
Command/ Indicate Channel 24
Controller 3
D
DC Characteristics 134
Deactivation 71
E
Electrical Characteristics 133
ETSI 141
R
Register Summary 118
Registers
F
U-Interface 121
Relay Driver Pins 33
Pin Description 16
Reset 69
Functional Description 20
G
General Purpose I/Os 33
Timing 135
I
S
IDCODE 109
Status Pins 33
Pin Description 16
Supply Voltage 139
System Integration 5
Interface to the Analog Front End
SDX/SDR Frame Structure 31
Timing 137
IOM®-2 Interface 21
C/I Channel 24
T
Channel Assignment 9
Data Rates 9
TAP Controller 108
Frame Structure 22
Monitor Channel 24
U
U-Transceiver 34
Data Sheet
144
2001-07-16
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