PI6C210V [ETC]
CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|48PIN|PLASTIC ; CPU的系统时钟发生器| CMOS | SSOP | 48PIN |塑料\n
| 型号： | PI6C210V |
| 厂家： | 
ETC |
| 描述： | CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|48PIN|PLASTIC
|
| 文件： | 总11页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C210
Differential Clock Generator
Features
Description
Eight copies of Differential CPU Clock Output at 100 MHz
One copy of CLK33
Pericoms PI6C210 is produced using the Companys advanced
submicron technology.
The clocks for the CPU are provided by HCLK and HCLK_bar
[0:7] outputs. These eight differential CPU clock pairs run at 100
Onecopyof14.31818MHzReferenceClock
OnecopyofDifferential48MHzClock
ExternalResistorforCurrentReference
MHz. The V swing amplitude is configured by the MultSel0
OH
and MultSel1 pins.
Selection Logic for Differential Swing Control, Test Mode,
HI-Z,Power-Down,SpreadSpectrum
AvailablePackaging:
48-pin TSSOP (A package)
48-pinSSOP(Vpackage)
PinConfiguration
BlockDiagram
CLK33
VDD
48 MHz/SELA
48 MHz_bar/SELB
GND
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL100/133
GND
VDDA
GNDA
PWRDN#
VDD
HCLK4
HCLK4_bar
GND
HCLK5
HCLK5_bar
VDD
HCLK6
HCLK6_bar
GND
HCLK7
HCLK7_bar
VDD
1
XTAL_IN
REF
OSC
REFCLK
VDD
HCLK0
HCLK0_bar
GND
HCLK1
HCLK1_bar
VDD
HCLK2
HCLK2_bar
GND
HCLK3
HCLK3_bar
VDD
REFCLK
SPREAD#
VSS
XTAL_OUT
9
48-pin
A,V
8
8
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Spread#
MultSel0
MultSel1
PWRDWN#
Sel100/133
SelA
PLL1
PLL2
HCLK [0:7]
HCLK_bar [0:7]
CLK33
Control
Register
/3, /4, /6
1
1
SelB
48 MHz
MULTSEL0
MULTSEL1
GND
GNDA
IREF
48 MHz_bar
XTALI
XTALO
VDD
VDDA
PS8599
01/29/02
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PI6C210
DifferentialClockGenerator
PinDescription
Pin Name
Pin Type
Pin Description
Host Clock Outputs. these eight Differential CPU clock pairs run at 100 MHz.
HCLK,
HCLK_bar
O
The V swing amplitude is configured by the Multsel0, Multsel1 pins.
OH
CLK33
48 MHz, 48 MHz_bar
REFCLK
O
I/O
O
33 MHz Reference Clock. Host clock divided by 3, 4, or 6.
48 MHz Differential Clocks.
14.318 MHz Reference Clock Output. 3.3V copies of the 14.318 MHz reference clock.
Crystal connection or External Reference Frequency Input. Connect to either a 14.318 MHz
crystal or an external reference signal.
XTALI
XTALO
I
O
I
Crystal Connection. An output connection for an external 14.318 MHz crystal. If using an
external reference, this pin must be left unconnected.
Spread Spectrum Enable.
3.3V LVTTL compatible input that enables spread spectrum mode when held LOW.
SPREAD#
PWRDN#
Power Down Input. 3.3V LVTTL compatible asynchronous input that requests the device to
enter power-down mode when it is held low.
I
SELA, SELB
I/O
I
Logic Select Pins. Select the mode of operation
MultSel0, MultSel1
Select Pins for V swing amplitude of HCLK and HCLK_bar
OH
V
CC
P
Power Supply
IREF
I
Current Reference. This pin establishes the reference current for the host clock pairs.
GroupSkewandJitterSpecification
Pin-to-pin Skew,
Output Group
Cycle-cycle Jitter
Duty Cycle
Type
Measured @
Pair-to-pair Skew
Host Clock
CLK33
100ps
150ps
500ps
1000ps
350ps
45/55
45/55
45/55
45/55
Differential
Crossing
1.5V
Single ended 3.3V
Single ended 3.3V
Single ended 3.3V
REFCLK
48 MHz
1.5V
1.5V
GroupOffsetSpecification
Group
Offset
Comments
Host to CLK33
Host to REF
No requirement
No requirement
PS8599
01/29/02
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PI6C210
DifferentialClockGenerator
SelectSignalConfigurations
48 MHz,
48 MHz_bar
SEL100/133
SELA
SELB
HCLK
CLK33
REF
Notes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100 MHz
100 MHz
100 MHz
Hi-Z
33 MHz
33 MHz
Disable
Hi-Z
48 MHz
Disable
Disable
Hi-Z
14.318
14.318
14.318
Hi-Z
Normal Operation
Test Mode (recommended)
Test Mode (optional)
Hi-Z All Outputs
Optional
133 MHz
133 MHz
200 MHz
TCLK/2
33 MHz
33 MHz
33 MHz
TCLK/8
48 MHz
Disable
48 MHz
TCLK/2
14.318
14.318
14.318
TCLK
Optional
Optional
RESERVED
AbsoluteMaximumDCPowerSupply
Symbol
Parameter
Min.
Max.
Units
V
Notes
V
DD3
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
Storage Temperature
0.5
0.5
65
4.6
4.6
150
V
DDQ3
V
T
S
°C
2
Note:
Maximum VIH not to exceed VDD3 +0.7V
AbsoluteMaximumDCI/O
Symbol
Parameter
Min.
0.5
0.5
2000
Max.
Units
V
Notes
V
IH3
3.3V Input High Voltage
3.3V Input Low Voltage
Input ESD Protection
4.6
1
V
IL3
V
ESD prot.
V
2
Notes:
1. Maximum VIH is not to exceed maximum 0.7V above VDD
2. Human body model
PS8599
01/29/02
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PI6C210
DifferentialClockGenerator
DCOperatingRequirements
Symbol
VDD3
VIH3
VIL3
Parameter
Condition
3.3V ±5%
VDD3
Min.
3.135
2.0
Max.
3.465
VDD +0.3
0.8
Units
V
Notes
3.3V Supply Voltage
4
7
3.3V Input High Voltage
3.3V Input Low Voltage
Input Leakage Current
3.3V Output High Voltage
3.3V Output Low Voltage
PCI Bus Output High Voltage
PCI Bus Output Low Voltage
Input Pin Capacitance
V
VSS 0.3
5
V
7
IIL
0 < VIN < VDDQ3
IOH = 1mA
IOL = 1mA
+5
µA
V
3, 7
1
VOH3
VOL3
VPOH
VPOL
CIN
2.4
0.4
V
1
IOH = 1mA
IOL = 1mA
2.4
V
1
0.55
5
V
1, 5
2
pF
pF
°C
CXTAL
TA
Xtal Pin Capacitance
13.5
0
22.5
70
6
Ambient Temperature
No Airflow
Notes:
1. Signal edge is required to be monotonic when transitioning through this region.
2. This is a recommendation, not an absolute requirement.
3. Input Leakage Current does not include inputs with Pull-up or Pull-down resistors. Inputs with resistors should state current requirements.
4. No power sequencing is implied or allowed to be required in the system.
5. Conforms to 5V PCI signaling specification.
6. As seen by the crystal. Device is intended to be used with a 17-20pF AT crystal.
7. All inputs referenced to 3.3V power supply.
MaximumCurrentDrawDuringPWRDWN#
Parameter
Min.
Max.
Units
Note
Current from 3.3V supply
N/A
120
mA
Configured w/475 Ohm current reference resistor
MaximumCurrentDraw
Parameter
Min.
N/A
Max.
400
Units
Note
Max. power supply (3.465V), all active, 475 Ohm current
reference resistor, Host = 133 MHz
Current from 3.3V supply
mA
PS8599
01/29/02
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PI6C210
DifferentialClockGenerator
Buffer Types
Buffer Name
V
CC
Range (V)
Impedance (Ohms)
20-60
Buffer Type
Type 3
48 MHz, REF
CLK33
3.135-3.465
3.135-3.465
12-55
Type 5
Host/Host_bar
Type X1
48MHz, REFOperatingRequirements
Symbol
IOHMIN
IOHMAX
IOLMIN
IOLMAX
tRH
Parameter
Pull-up Current
Condition
VOUT = 1.0V
Min.
Max.
Units
mA
29
Pull-up Current
VOUT = 3.135V
23
mA
Pull-down Current
VOUT = 1.95V
29
mA
Pull-down Current
VOUT = 0.4V
27
2.0
2.0
mA
3.3V Type 3 Output Rise Edge Rate
3.3V Type 3 Output Rise Fall Rate
3.3V ±5% @ 0.4V 2.4V
3.3V ±5% @ 2.4V 0.4V
0.5
0.5
V/nS
V/nS
tFH
CLK33OperatingRequirements
Symbol
IOHMIN
IOHMAX
IOLMIN
IOLMAX
tRH
Parameter
Condition
VOUT = 1.0V
Min.
Max.
Units
mA
Pull-up Current
33
Pull-up Current
VOUT = 3.135V
33
mA
Pull-down Current
VOUT = 1.95V
30
mA
Pull-down Current
VOUT = 0.4V
38
4/1
4/1
mA
3.3V Type 4 Output Rise Edge Rate
3.3V Type 4 Output Rise Fall Rate
3.3V ±5% @ 0.4V 2.4V
3.3V ±5% @ 2.4V 0.4V
1/1
1/1
V/ns
V/ns
tFH
PS8599
01/29/02
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PI6C210
DifferentialClockGenerator
Current-ModeOutputBufferCharacteristicsHCLK,HCLK_bar[0:7]
V
DD3
(3.3V –5%)
Slope ~ 1/R
O
R
O
I
OUT
R
OS
I
0V
1.2V
OUT
V
OUT
V
= 1.2V max.
OUT
HostClock(HCSL)BufferCharacteristics
Minimum
Maximum
N/A
RO
ROS
3000 Ohms (recommended)
unspecified
N/A
unspecified
1.2V
VOUT
Note: IOUT is selectable depending on implementation. The parameters above, however,
apply to all configurations. VOUT is the voltage at the pin of the device.
CurrentAccuracy
Conditions
Load
Min.
7% I
Max.
+7% I
NOMINAL
I
V
= nominal (3.30V)
Nominal test load for given configuration
Nominal test load for given configuration
OUT
DD
NOMINAL
I
V
= 3.30 ±5%
12% I
+12% I
NOMINAL
OUT
DD
NOMINAL
Note: INOMINAL refers to the expected current based on the configuration of the device.
PS8599
01/29/02
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PI6C210
DifferentialClockGenerator
ACTimingRequirements
133 MHz Host
Min. Max.
7.5 7.65
100 MHz Host
Symbol
Parameter
Units Notes
Min.
10.0
9.85
Max.
10.2
N/A
TPeriod
AbsMinPeriod
IOH
Host CLK period - average
nS
nS
11,14
11,14
Absolute minimum Host CLK Period
7.35
N/A
Output Current
12.9
14.9
12.9
14.9
mA
(V)
11,
(VOH
)
(Voltage at given load)
(0.65)
(0.74)
(0.65)
(0.74)
13,17
VOL
Vcrossover
TRISE
VSS = 0.0
45% VOH
175
0.05
VSS = 0.0
0.05
55% VOH
700
V
V
11
11,14
11,15
11,15
11,16
11,16
11
55% VOH 45% VOH
Host/CPU CLK Rise Time
Host/CPU CLK Fall Time
700
700
175
175
pS
pS
TFALL
175
700
Rise/Fall Matching
Overshoot
Undershoot
Duty Cycle
TPeriod
Rise Time and Fall Time Matching
20%
20%
VOH +0.2V
VOH +0.2V
0.2V
45%
30.0
12.0
12.0
0.5
0.2V
45%
30.0
12.0
12.0
0.5
55%
N/A
N/A
N/A
2.0
55%
N/A
N/A
N/A
2.0
11,14
2,3,9
5,10
6,10
8
CLK33 period
CLK33 high time
nS
nS
nS
nS
nS
nS
nS
mS
THIGH
TLOW
CLK33 low time
TRISE
CLK33 rise time
TFALL
CLK33 fall time
0.5
2.0
0.5
2.0
8
tPZL, tPZH
tPLZ, tPZH
tstable
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock stabilization from power-up
1.0
10.0
10.0
3
1.0
10.0
10.0
3
1.0
1.0
7
Notes:
1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels.
2. Period, Jitter, Offset, and Skew measured on rising edge @1.25V for 2.5V clocks and 1.5V for 3.3V clocks.
3. The PCI clock is the Host clock divided by four at Host = 133 MHz. PCI clock is the Host clock divided by three at Host = 100 MHz.
4. PCI clock id the Host clock divided by six at Host = 200 MHz.
5. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
6. TLOW is measured at 0.4V for all outputs.
7. The time specified is measured from when VDDQ achieves its nominal operating level (typical condition VDDQ=3.3V) till the frequency output
is stable and operating within specification.
8. TRISE and TFALL are measured as a transition through the threshold region VOL=0.4V, and VOH=2.4V (1mA) JEDEC Specification
9. The average period over any 1uS period of time must be greater than the minimum specified period.
10. Calculated at minimum edge-rate (1V/nS) to guarantee 45/55% duty-cycle. Pulsewidth is required to be wider at faster edge-rate to ensure duty-
cycle specification is met.
11. Test load is RS=33.2 Ohms, RP=49.9.
12. Must be guaranteed in realistic system environment.
13. Configured for IOH=6* IREF
.
14. Measured at crossing points.
15. Measured at 20% to 80%.
16. Determined as a fraction of 2* (TrpTrn) / (Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge.
17. These Min. and Max. voltages and currents assume a power supply of 3.30V. For system considerations, the voltages will need to be degraded
to account for the ±5% variation in the 3.3V supply.
PS8599
01/29/02
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PI6C210
DifferentialClockGenerator
LumpedCapacitiveTestLoadsforSingleendedOutputs
Clock
Min. Load
Max. Load
Units
pF
Notes
1 device load, possible 2 loads
1 device load
3V66
10
10
10
30
20
20
48 MHz Clock
REF
pF
pF
1 device load
Notes:
1. Maximum rise/fall times are to be guaranteed at a maximum specified load for each type of output buffer.
2. Minimum rise/fall times are to be guaranteed at a minimum specified load for each type of output buffer.
3. Rise/fall times are specified with pure capacitive load as shown. testing may be done with an additional
500 ohm resistor in parallel if properly correlated with the capacitie load.
RP
RS
Test nodes
RS
RP
LumpedTestLoadConfigurationsfortheDifferentialHostClockOutputs
MinimumandMaximumLumpedResistiveTestLoads
Clock
Host Clocks
Min. Load
Max. Load
Units
Notes
20
105
Ohms
PS8599
01/29/02
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PI6C210
DifferentialClockGenerator
Resistive Lumped Test Loads for Differential Host Clock
Clock
R
R
Units
Notes
S
P
Host Clocks
60 ohm configurations
33.2
1%
61.9
1%
Ohms
2, 3, 5
Host Clocks
50 ohm configurations
33.2
1%
49.9
1%
Ohms
Ohms
1, 2, 3, 5
4
Host Clocks
Double terminated Configuration
24.9
1%
0
Notes:
1. Expected test load configuration unless otherwise noted. This is a 50 ohm environment test load.
This assumes device is configured for 50 ohm environment.
2. Test load for 60 ohm environment. This assumes device is configured for a 60 ohm environment.
3. Suppliers must correlate parameters measured in 50 ohm environment to a 60 ohm environment with the appropriate configurations of the
device for each load.
4. Test load for dual terminated (ie both source and load) 50 ohm environment.
5. For configurations of the device intended to create output current greater than 14mA these test loads may not be appropriate. For such
configurations, a value of RS = 0 should be used.
3.3 Volt Measure Points
VDD3
Host
Host_bar
VOH = 2.4V
VIH = 2.0V
1.5V
VIH = 0.8V
Tperiod
VOH = 0.4V
Componentvs.SystemMeasurePointsforSingleEndedClocks
HostWaveforms
PWRDWN# Mode
PWRDWN#
Host/Host_bar
CLK33
48 MHz
14.318, REF
Host = 2*Iref
Host_bar = undriven
Asserted = 0 = low
Low
Low
Low (if applicable)
Notes:
1. When PWRDWN# is asserted, a voltage must be held across the differential outputs.
2. There are no specific timing requirements for entering or exiting PWRDWN# mode.
PS8599
01/29/02
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PI6C210
DifferentialClockGenerator
HostSwingSelectFunctions
Board target
Trace/Term Z
Reference R,
Iref = VDD/3(3*Rr)
VOH @ Z,
Iref = 2.32mA
MultSel0
MultSel1
Output Current
Rr = 475 1%,
Iref = 2.32mA
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
60 ohms
50 ohms
I
OH = 5*Iref
0.71V @ 60
Rr = 475 1%,
Iref = 2.32mA
I
OH = 5*Iref
0.59V @ 50
0.85V @ 60
0.71V @ 50
0.56V @ 60
0.47V @ 50
0.99V @ 60
0.82V @ 50
0.75V @ 30
0.62V @ 20
0.90V @ 30
0.75V @ 20
0.60V @ 30
0.5V @ 20
Rr = 475 1%,
Iref = 2.32mA
60 ohms
I
OH = 6*Iref
Rr = 475 1%,
Iref = 2.32mA
50 ohms
IOH = 6*Iref
Rr = 475 1%,
Iref = 2.32mA
60 ohms
IOH = 4*Iref
Rr = 475 1%,
Iref = 2.32mA
50 ohms
IOH = 4*Iref
Rr = 475 1%,
Iref = 2.32mA
60 ohms
IOH = 7*Iref
Rr = 475 1%,
Iref = 2.32mA
50 ohms
IOH = 7*Iref
Rr = 221 1%,
Iref = 5mA
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
IOH = 5*Iref
Rr = 221 1%,
Iref = 5mA
I
OH = 5*Iref
Rr = 221 1%,
Iref = 5mA
I
OH = 6*Iref
Rr = 221 1%,
Iref = 5mA
I
OH = 6*Iref
Rr = 221 1%,
Iref = 5mA
I
OH = 4*Iref
Rr = 221 1%,
Iref = 5mA
I
OH = 4*Iref
Rr = 221 1%,
Iref = 5mA
I
OH = 7*Iref
1.05V @ 30
0.84V @ 20
Rr = 221 1%,
Iref = 5mA
IOH = 7*Iref
Notes:
The entries in boldface are the primary system configurations of interest. The outputs should be optimized for these configurations.
PS8599
01/29/02
10
PI6C210
DifferentialClockGenerator
48-pinTSSOPPackagingMechanical(A)
48
.236
.244
6.0
6.2
1
.488 12.4
.496 12.6
.047
1.20 Max
SEATING PLANE
0.09
0.20
.004
.008
0.45 .018
0.75 .030
.002
.007
.010
.0197
BSC
.006
0.05
0.15
.319
BSC
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
0.50
0.17
0.27
8.1
48-pinSSOPPackagingMechanical(V)
48
.395
.420
10.03
10.67
.291
.299
7.39
7.59
Gauge Plane
.010
0.25
.02 0.51
.04 1.01
1
.620
.630
15.75
16.00
0.381
0.635
.015
.025
x 45˚
.008
0.20
Nom.
.110 2.79 Max
.008 0.20
.0135 0.34
.025 BSC
0.635
.008 0.20
.016 0.40
0-8˚
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
OrderingInformation
P/N
Description
PI6C210A
48-pin TSSOP
48-pin SSOP
PI6C210V
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8599
01/29/02
11
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