首页 |元器件品牌

PI6C21200AEX [PERICOM]

Clock Driver, PDSO56;
PI6C21200AEX
型号： PI6C21200AEX
厂家： PERICOM SEMICONDUCTOR CORPORATION    PERICOM SEMICONDUCTOR CORPORATION
描述：

Clock Driver, PDSO56

光电二极管
文件： 总14页 (文件大小：442K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
PI6C21200  
1:12 Clock Driver for Intel PCIe® Chipsets  
Description  
Features  
PI6C21200 is a high-speed, low-noise PCIe® differential  
clock buffer designed to be a companion with PI6C410B clock  
synthesizer. The device distributes twelve copies of the  
differential SRC clock coming from PI6C410B. The output  
frequency can be ratioed to offer a derivative frequency from  
the input frequency. Each differential output is controlled by  
individual OE pin, except OUT10 and OUT11 are sharing one  
OE_10#_11# pin. The clock outputs are controlled by input selec-  
• Twelve Pairs of PCIe® Differential Clocks (HCSL compatible  
signaling)  
• Low skew < 50ps  
• Low jitter < 50ps  
• Output Enable for all outputs  
• Outputs tristate control via SMBus  
• Power Management Control  
• Programmable PLL Bandwidth  
• PLL or Fan out operation  
• Gear Ratio supporting different output frequencies  
• 3.3V Operation  
tion of SA_0, SA_1, SA_2 via SMBus, SCLK and SDA.  
• 56-pin Package (Pb-Free & Green):  
- TSSOP (A56)  
Block Diagram  
Pinout Diagram  
OE [0:10]#  
Output  
1
2
3
4
5
6
7
8
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
HIGH_BW#  
SRC_IN  
SRC_IN#  
SA_0  
VDD_A  
VSS_A  
IREF  
OE_10#_11#  
OUT11  
OUT11#  
VDD  
Control  
VTT_PWRGD#  
OUT0  
/ PWRDWN  
OUT0#  
OE_0#  
OUT0  
OUT0#  
OE_1#  
OUT1  
OUT1#  
VDD  
VSS  
OUT1  
OUT1#  
OUT2  
OUT2#  
OUT3  
OUT3#  
OUT4  
OUT4#  
OUT5  
OUT5#  
OUT6  
OUT6#  
OUT7  
OUT7#  
OUT8  
OUT8#  
SCLK  
SDA  
SMBus  
Controller  
VSS  
SA_[0:1]  
9
OUT10  
OUT10#  
FS_A  
VTT_PWRGD# / PWRDWN  
OE_9#  
OUT9  
OUT9#  
OE_8#  
OUT8  
OUT8#  
VDD  
VSS  
OUT7  
OUT7#  
OE_7#  
OUT6  
OUT6#  
OE_6#  
SA_2 /PLLBypass#  
SCL  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
SA_2 /  
PLLBypass#  
OUT2  
OUT2#  
OE_2#  
OUT3  
OUT3#  
OE_3#  
OUT4  
OUT4#  
OE_4#  
VDD  
VSS  
OUT5  
OUT5#  
OE_5#  
SA_1  
SRC  
SCR#  
HIGH_BW#  
PLL  
OUT9  
OUT9#  
OUT10  
OUT10#  
OUT11  
OUT11#  
SDA  
09-0003  
PS8820B  
10/14/09  
1
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
Pin Descriptions  
Pin Name  
PLL_BW#  
SRC & SRC#  
Type  
Pin Number  
Descriptions  
Input  
Input  
1
3.3V LVTTL input for selecting the PLL bandwidth. (High = Low BW)  
0.7V Differential SRC input from PI6C410B clock synthesizer  
2, 3  
6, 7, 9, 10, 13, 14, 16, 17,  
19, 20, 24, 25, 32, 33,  
35, 36, 39, 40, 42, 43  
OUT[0:9] &  
OUT[0:9]#  
0.7V Differential outputs, geared to the ratio of input clock. Can be  
configured to be 1:1 ratio.  
Output  
OUT[10:11] &  
OUT[10:11]#  
0.7V Differential outputs, geared to the ratio of input clock same as  
OUT[0:9]. Can be configured to be 1:1 ratio.  
Output  
Input  
47, 48, 51, 52  
5, 8, 15, 18, 21, 26, 31,  
34, 41, 44  
3.3V LVTTL input for enabling outputs, active low. Control each  
OUT[0:9] pair.  
OE_[0:9]#  
3.3V LVTTL input for enabling outputs, active low. Control each  
OUT[10:11] pair.  
OE_10#_11#  
SA_[0:1]  
Input  
Input  
Input  
53  
4, 27  
30  
3.3V LVTTL input for selecting the SMBus address  
SA_2 / PLL-  
BYPASS#  
3.3V LVTTL input for selecting fan-out of PLL operation, and SMBus  
address. 0 = PLL Bypass, 1 = PLL mode  
SCLK  
SDA  
Input  
I/O  
29  
28  
54  
SMBus compatible SCLOCK input  
SMBus compatible SDATA  
I
Input  
External resistor connection to set the differential output current  
REF  
3.3V LVTTL inputs for CPU frequency selection  
0 = above 200 MHz, 1 = below 200 MHz  
FS_A  
Input  
46  
VTT_PWRGD#  
/ PWRDWN  
Input  
45  
3.3V LVTTL input for Power Down operation, active high  
V
V
V
V
Power  
11, 22, 38, 50  
3.3V Power Supply for Outputs  
Ground for Outputs  
DD  
Ground 12, 23, 37, 49  
Ground 55  
SS  
Ground for PLL  
SS_A  
DD_A  
Power  
56  
3.3V Power Supply for PLL  
Serial Data Interface (SMBus)  
PI6C21200 is a slave only SMBus device that supports random byte read and write indexed block read and write protocol using a  
single 7-bit address and read/write bit as shown below.  
SMBus Address Selection by SA_[0:2]  
SA_2/  
PLLBypass#  
SMBus  
Address  
PLL  
Mode  
SA_1  
SA_0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D0  
D2  
D4  
D6  
D8  
DA  
DC  
DE  
Bypass  
Bypass  
Bypass  
Bypass  
PLL  
PLL  
PLL  
PLL  
PS8821B  
10/14/09  
09-0003  
2
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
Indexed Block Read and Write Protocol  
Block Write Protocol  
Block Read Protocol  
Description  
Bit  
Description  
Bit  
1
Start  
1
Start  
2:8  
9
Slave address - 7 bits  
Write = 0  
2:8  
9
Slave address - 7 bits  
Write = 0  
10  
Acknowledge from slave  
10  
Acknowledge from slave  
Command Code - 8 Bits  
'00000000' Stand for block operation  
Command Code - 8 Bits  
'00000000' Stand for block operation  
11:18  
11:18  
19  
Acknowledge from slave  
Byte Count from master - 8 bits  
Acknowledge from slave  
Datat byte 0 from master - 8 bits  
Acknowledge from slave  
Datat byte 1 from master - 8 bits  
Acknowledge from slave  
Data bytes from master/Acknowledge  
Data byte N - 8 bits  
19  
Acknowledge from slave  
Repeat start  
20:27  
28  
20  
21:27  
28  
Slave address - 7 bits  
29:36  
37  
Read = 1  
29  
Acknowledge from slave  
Byte count from slave - 8 bits  
Acknowledge from host  
Data byte 0 from slave - 8 bits  
Acknowledge from host  
Data byte 1 from slave - 8 bits  
Acknowledge from host  
Data bytes from slave/Acknowledge  
Data byte N from slave - 8 bits  
Acknowledge from host - 38 bits  
Stop  
38:45  
46  
30:37  
38  
....  
39:46  
47  
....  
....  
Acknowledge from slave  
Stop  
48:55  
56  
....  
....  
....  
....  
....  
PS8821B  
10/14/09  
09-0003  
3
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
Random Byte Read and Write Protocol  
Byte Write Protocol  
Byte Read Protocol  
Description  
Bit  
Description  
Bit  
1
Start  
1
Start  
2:8  
9
Slave address - 7 bits  
Write = 0  
2:8  
9
Slave address - 7 bits  
Write - 0  
10  
Acknowledge from slave  
10  
Acknowledge from slave  
Command Code - 8 bits  
Command Code - 8 bits  
'100xxxxx' stands for byte operation, bits[6:0]  
of the command code represents the offset of  
the byte to be accessed.  
'100xxxxx' stands for byte operation, bits[6:0]  
of the command code represents the offset of the  
byte to be accessed.  
11:18  
11:18  
19  
Acknowledge from slave  
Data byte from master - 8 bits  
Acknowledge from slave  
Stop  
19  
Acknowledge from slave  
Repeat start  
20:27  
28  
20:27  
21:27  
28  
Slave address - 7 bits  
Read = 1  
29  
29  
Acknowledge from slave  
Data byte from slave - 8 bits  
Acknowledge from master - 38 bits  
Stop  
30:37  
38  
39  
PS8821B  
10/14/09  
09-0003  
4
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
Data Byte 0: Control Register  
Bit  
Descriptions  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
Power Up Condition  
Output(s) Affected  
0
FSB Gear Ratio SMBus  
FSB Gear Ratio SMBus  
FSB Gear Ratio SMBus  
FSB Gear Ratio SMBus  
FS_A PI6C410B latched input  
Reserved  
1
(1)  
1
Depends on FS_A pin  
2
0
(1)  
3
Depends on FS_A pin  
4
Latch  
1
5
Group of 2 gear ratio select  
1 = 1:1, 0 = Gear Raito  
OUT[10:11],  
OUT[10:11]#  
6
RW  
RW  
1
1
Group of 10 gear ratio select  
1 = 1:1, 0 = Gear Raito  
OUT[0:9],  
OUT[0:9]#  
7
Note:  
1. When FS_A = 1, Bit 1 = 0 and Bit 3 = 1; When FS_A = 0, Bit 1 = 1 and Bit 3 = 0  
Data Byte 1: Control Register  
Bit  
Descriptions  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Power Up Condition  
Output(s) Affected  
OUT0, OUT0#  
OUT1, OUT1#  
OUT2, OUT2#  
OUT3, OUT3#  
OUT4, OUT4#  
OUT5, OUT5#  
OUT6, OUT6#  
OUT7, OUT7#  
0
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1
2
OUTPUTS enable  
1 = Enabled  
0 = Hi-Z  
3
4
5
6
7
Data Byte 2: Control Register  
Bit  
Descriptions  
Type  
RW  
RW  
RW  
RW  
RW  
Power Up Condition  
1 = Enabled  
Output(s) Affected  
OUT8, OUT8#  
0
OUTPUTS enable  
1 = Enabled  
0 = Hi-Z  
1
1 = Enabled  
OUT9, OUT9#  
2
1 = Enabled  
OUT10, OUT10#  
OUT11, OUT11#  
3
1 = Enabled  
4
Reserved  
PLL/BYPASS#  
0 = Fanout,1 = PLL  
5
RW  
1 = PLL  
1 = Low  
OUT[0:11], OUT[0:11]#  
OUT[0:11], OUT[0:11]#  
PLL Bandwidth  
0 = High Bandwidth,  
1 = Low Bandwidth  
6
RW  
Outputs current select at PWRDWN = 1  
7
1 = 2 x I  
0 = HiZ  
,
RW  
1
REF  
PS8821B  
10/14/09  
09-0003  
5
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
Data Byte 3: Control Register  
Bit  
Descriptions  
Type  
R
Power Up Condition  
Output(s) Affected  
0
OE_0#, 1 = Disable (Hi-Z), 0 = Enable  
OE_1#, 1 = Disable (Hi-Z), 0 = Enable  
OE_2#, 1 = Disable (Hi-Z), 0 = Enable  
OE_3#, 1 = Disable (Hi-Z), 0 = Enable  
OE_4#, 1 = Disable (Hi-Z), 0 = Enable  
OE_5#, 1 = Disable (Hi-Z), 0 = Enable  
OE_6#, 1 = Disable (Hi-Z), 0 = Enable  
OE_7#, 1 = Disable (Hi-Z), 0 = Enable  
Depends on state of pin  
Depends on state of pin  
Depends on state of pin  
Depends on state of pin  
Depends on state of pin  
Depends on state of pin  
Depends on state of pin  
Depends on state of pin  
OUT0, OUT0#  
OUT1, OUT1#  
OUT2, OUT2#  
OUT3, OUT3#  
OUT4, OUT4#  
OUT5, OUT5#  
OUT6, OUT6#  
OUT7, OUT7#  
1
R
2
R
3
R
4
R
5
R
6
R
7
R
Data Byte 4: Control Register  
Bit  
Descriptions  
Type  
R
Power Up Condition  
Output(s) Affected  
OUT8, OUT8#  
0
OE_8#, 1 = Disable (Hi-Z), 0 = Enable  
OE_9#, 1 = Disable (Hi-Z), 0 = Enable  
Depends on state of pin at power up  
Depends on state of pin at power up  
1
R
OUT9, OUT9#  
OE_10#_11#,  
1 = Disable (Hi-Z), 0 = Enable  
OUT[10:11],  
OUT[10:11]#  
2
R
Depends on state of pin at power up  
3
4
5
6
7
Reserved  
R
R
R
R
R
Reserved  
Readback – PLLBypass input  
Readback – HIGH_BW# input  
Readback – FS_A input  
Latch value of pin at power up  
Latch value of pin at power up  
Latch value of pin at power up  
Data Byte 5: Pericom ID Register  
Bit  
Descriptions  
Type  
Power Up Condition  
Output(s) Affected  
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
1
Pericom ID  
2
3
4
5
Revision Code  
6
7
PS8821B  
10/14/09  
09-0003  
6
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
Data Byte 6: Device ID Register  
Bit  
Descriptions  
Device ID 0  
Device ID 1  
Device ID 2  
Device ID 3  
Device ID 4  
Device ID 5  
Device ID 6  
Device ID 7  
Type  
R
Power Up Condition  
Output(s) Affected  
0
0
0
1
1
0
0
0
0
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
1
R
2
R
3
R
4
R
5
R
6
R
7
R
Data Byte 7: Byte Counter Register  
Bit  
Descriptions  
Type  
Power Up Condition  
Output(s) Affected  
BC0 - Writing to the register configures how many  
bytes will be read back  
0
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
1
1
1
0
0
0
0
0
NA  
BC1 - Writing to the register configures how many  
bytes will be read back  
1
2
3
4
5
6
7
NA  
NA  
NA  
NA  
NA  
NA  
NA  
BC2 - Writing to the register configures how many  
bytes will be read back  
BC3 - Writing to the register configures how many  
bytes will be read back  
BC4 - Writing to the register configures how many  
bytes will be read back  
BC5 - Writing to the register configures how many  
bytes will be read back  
BC6 - Writing to the register configures how many  
bytes will be read back  
BC7 - Writing to the register configures how many  
bytes will be read back  
PS8821B  
10/14/09  
09-0003  
7
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
Programmable Gear Ratio – Output Frequency  
Gear  
Ratio  
SMBus Byte 0  
Input Output  
CPU Input Frequency (MHz)  
FS_A  
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
M
3
N
1
2
5
1
3
5
2
3
5
1
6
5
4
3
5
2
(N/M)  
0.333  
0.400  
0.417  
0.500  
0.600  
0.625  
0.667  
0.750  
0.833  
1.000  
1.200  
1.250  
1.333  
1.500  
1.667  
2.000  
200  
266.7  
NA  
320  
106.7  
128.0  
133.3  
160.0  
192.0  
200.0  
213.3  
240.0  
NA  
333.3  
111.1  
133.3  
138.9  
166.7  
200.0  
208.3  
222.2  
NA  
400  
133.3  
160.0  
166.7  
200.0  
240.0  
NA  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NA  
0
0
0
1
5
NA  
106.7  
111.1  
133.3  
160.0  
166.7  
177.8  
200.0  
222.2  
266.7  
320.0  
333.3  
NA  
0
0
1
0
12  
2
NA  
0
0
1
1
100.0  
120.0  
125.0  
133.3  
150.0  
166.7  
200.0  
240.0  
250.0  
266.7  
300.0  
333.3  
400.0  
0
1
0
0
5
0
1
0
1
8
0
1
1
0
3
266.7  
NA  
0
1
1
1
4
1
0
0
0
6
NA  
NA  
1
0
0
1
1
320.0  
384.0  
400.0  
NA  
333.3  
400.0  
416.6  
NA  
400.0  
480.0  
500.0  
NA  
1
0
1
0
5
1
0
1
1
4
1
1
0
0
3
1
1
0
1
2
400.0  
444.4  
NA  
480.0  
NA  
NA  
NA  
1
1
1
0
3
NA  
NA  
1
1
1
1
1
NA  
NA  
NA  
Note:  
1. Line in BOLD is power-up default for FS_A = 0 for Pericom Semiconductor's PI6C410B.  
PS8821B  
10/14/09  
09-0003  
8
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
Programmable Gear Ratio - Output Frequency -- Continued  
Gear  
Ratio  
SMBus Byte 0  
Input Output  
CPU Input Frequency (MHz)  
FS_A  
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
M
3
N
1
2
5
1
3
5
2
4
5
1
6
5
4
3
5
2
(N/M)  
0.333  
0.400  
0.417  
0.500  
0.600  
0.625  
0.667  
0.800  
0.833  
1.000  
1.200  
1.250  
1.333  
1.500  
1.667  
2.000  
100  
NA  
133.3  
NA  
160  
166.67  
55.6  
200  
66.7  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
53.3  
0
0
0
1
5
NA  
53.3  
64.0  
66.7  
80.0  
0
0
1
0
12  
2
NA  
55.6  
66.7  
69.4  
83.3  
0
0
1
1
50.0  
60.0  
62.5  
66.7  
80.0  
NA  
66.7  
80.0  
83.3  
100.0  
120.0  
NA  
0
1
0
0
5
80.0  
96.0  
100.0  
104.2  
111.1  
133.3  
138.9  
166.7  
200.0  
208.3  
222.2  
250.0  
277.8  
333.3  
0
1
0
1
8
83.3  
100.0  
106.7  
128.0  
133.3  
160.0  
192.0  
200.0  
213.3  
240.0  
266.7  
320.0  
0
1
1
0
3
88.9  
133.3  
160.0  
166.7  
200.0  
240.0  
NA  
0
1
1
1
5
106.7  
111.1  
133.3  
160.0  
166.7  
177.8  
200.2  
222.2  
266.7  
1
0
0
0
6
1
0
0
1
1
100.0  
120.0  
125.0  
133.3  
150.0  
166.7  
200.0  
1
0
1
0
5
1
0
1
1
4
1
1
0
0
3
266.7  
300.0  
333.3  
400.0  
1
1
0
1
2
1
1
1
0
3
1
1
1
1
1
Note:  
1. Line in BOLD is power-up default for FS_A = 0 for Pericom Semiconductor's PI6C410B.  
Functionality  
VTT_PWRGD# OUT  
/ PWRDWN  
OUT#  
OE#  
pin  
OE  
(SMBus bit)  
OUT  
OUT#  
0
1
Normal  
2 x I  
Normal  
0
0
1
1
1
0
1
0
Normal  
Hi-Z  
Normal  
Hi-Z  
or Float Low  
REF  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
PS8821B  
10/14/09  
09-0003  
9
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
Power Down (PWRDWN assertion)  
PWRDWN  
OUT  
OUT#  
Figure 1. Power down sequence  
Power Down (PWRDWN De-assertion)  
Tstable  
< 1ms  
PWRDWN  
OUT  
OUT#  
Tdrive_PWRDWN  
< 300US, >200mV  
Figure 2. Power down de-assert sequence  
PS8821B  
10/14/09  
09-0003  
10  
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
Current-mode output buffer characteristics of OUT[0:11], OUT[0:11]#  
V
DD  
(3.3V 5ꢀ%  
Slope ~ 1/R  
O
R
O
I
OUT  
R
V
OS  
I
OUT  
1.2V  
= 1.2V max  
0V  
OUT  
Figure 3. Simplified diagram of current-mode output buffer  
Differential Clock Buffer Characteristics  
Symbol  
Minimum  
3000Ω  
Maximum  
N/A  
R
O
R
unspecified  
N/A  
unspecified  
850mV  
OS  
V
OUT  
Current Accuracy  
Symbol  
Conditions  
V = 3.30 ±5%  
DD  
Configuration  
Load  
Min.  
-12% I  
Max.  
+12% I  
NOMINAL  
R
= 475Ω 1%  
Nominal test load for given  
REF  
I
OUT  
NOMINAL  
I
= 2.32mA  
configuration  
REF  
Note:  
1.  
I
NOMINAL refers to the expected current based on the configuration of the device.  
Differential Clock Output Current  
Board Target Trace/Term Z  
Reference R, Iref = V /(3xRr)  
Output Current  
= 6 x Iref  
V
@ Z  
DD  
OH  
R = 475Ω 1%,  
REF  
100Ω differential  
I
0.7V @ 50  
OH  
I
= 2.32mA  
REF  
PS8821B  
10/14/09  
09-0003  
11  
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
Absolute Maximum Ratings (Over operating free-air temperature range)  
Symbol  
Parameters  
Min.  
-0.5  
-0.5  
Max.  
4.6  
Units  
V
V
V
V
3.3V Core Supply Voltage  
3.3V I/O Supply Voltage  
Input High Voltage  
Input Low Voltage  
Storage Temperature  
ESD Protection  
DD_A  
DD  
IH  
4.6  
V
4.6  
-0.5  
-65  
IL  
Ts  
150  
°C  
V
V
ESD  
2000  
Note:  
1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.  
DC Electrical Characteristics (V = 3.3±5%, V  
= 3.3 ±5%)  
DD  
DD_A  
Symbol  
Parameters  
Condition  
Min.  
3.135  
3.135  
2.0  
Max.  
Units  
V
V
V
V
3.3V Core Supply Voltage  
3.3V I/O Supply Voltage  
3.3V Input High Voltage  
3.3V Input Low Voltage  
Input Leakage Current  
3.3V Output High Voltage  
3.3V Output Low Voltage  
3.465  
3.465  
DD_A  
DD  
IH  
V
V
DD  
V
DD  
+ 0.3  
V
SS  
– 0.3  
0.8  
+5  
IL  
I
0 < V < V  
DD  
-5  
μA  
IK  
IN  
V
V
I
OH  
I
OL  
= -1mA  
= 1mA  
2.4  
OH  
OL  
V
0.4  
12.2  
3
I
I
= 6 x I  
,
OH  
REF  
I
Output High Current  
mA  
OH  
= 2.32mA  
REF  
15.6  
5
C
C
Input Pin Capacitance  
Output Pin Capacitance  
Pin Inductance  
IN  
OUT  
PIN  
DD  
SS  
pF  
6
L
7
nH  
I
I
I
Power Supply Current  
Power Down Current  
Power Down Current  
Ambient Temperature  
V
= 3.465V, F  
= 400 MHz  
CPU  
375  
90  
24  
70  
DD  
Driven outputs  
Tristate outputs  
mA  
°C  
SS  
T
0
A
PS8821B  
10/14/09  
09-0003  
12  
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
AC Switching Characteristics (V = 3.3±5%, V  
= 3.3 ±5%)  
DD  
DD_A  
Symbol  
Parameters  
Min  
Max.  
Units  
Notes  
T
rise  
/ T  
Rise and Fall Time (measured between 0.175V to 0.525V)  
125  
525  
3
fall  
ps  
ΔT  
ΔT  
/
rise  
Rise and Fall Time Variation  
75  
3
3
fall  
Rise/Fall Matching  
10  
%
ps  
ns  
PLL Mode  
±250  
T
pd  
Non-PLL Mode  
3
T
Output-to-Output Skew OUT [9:0] or OUT [10:11]  
Output-to-Output Skew OUT [9:0] to OUT [10:11]  
Cycle-to-Cycle Jitter  
50  
4
4
4
3
3
3
3
4
skew  
T
skew  
75  
ps  
T
jitter  
50  
V
Voltage High including overshoot  
Voltage Low including undershoot  
Absolute crossing poing voltages  
Total Variation of Vcross over all edges  
Duty Cycle  
660  
-150  
250  
850  
HIGH  
V
V
LOW  
mV  
%
550  
100  
55  
CROSS  
ΔV  
CROSS  
T
DC  
45  
Notes:  
3. Measurement taken from Single Ended waveform.  
4. Measurement taken from Differential waveform.  
5. Test configuration is RS = 33.2Ω, Rp = 49.9Ω, and 2pF.  
Configuration Test Load Board Termination  
Rs  
33Ω  
5ꢀ  
Clock  
TLA  
TLB  
PI6C21200  
Rs  
33Ω  
5ꢀ  
Clock#  
2pF  
5ꢀ  
2pF  
5ꢀ  
Rp  
49.9Ω  
1ꢀ  
Rp  
49.9Ω  
475Ω  
1ꢀ  
1ꢀ  
Figure 4. Configuration test load board termination  
Note:  
1.  
TLA and TLB are 3” transmission lines.  
PS8821B  
10/14/09  
09-0003  
13  
PI6C21200  
1:12 Clock Driver for Intel  
PCI Express® Chipsets  
Packaging Mechanical: 56-Pin, 240-mil wide TSSOP (A)  
DATE: 09/11/06  
REVISION: M  
Notes:  
DESCRIPTION: 56-pin, 240-mil wide TSSOP  
1. Controlling dimensions in millimeters.  
2. Ref: JEDEC MO-153F/EE  
3. Package Outline Exclusive of Mold Flash and Metal Burr  
PACKAGE CODE: A56  
DOCUMENT CONTROL #: PD-1502  
06-0736  
Note:  
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php  
Ordering Information:  
Ordering Code  
Packaging Code  
Package Type  
56-Pin, 240-mil wide, 0.5mm pitch TSSOP, Pb-Free and Green  
PI6C21200AE  
A
Notes:  
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/  
• E = Pb-free and Green  
• X suffix = Tape/Reel  
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com  
PS8821B  
10/14/09  
09-0003  
14  
All trademarks are property of their respective owners.  

相关型号：

PI6C21200VE

 1:12 Clock Driver for Intel PCI-Express Chipsets
PERICOM

PI6C21900SZDE

 PLL Based Clock Driver, 6C Series, 19 True Output(s), 0 Inverted Output(s), GREEN, MO-220I/VNND, TQFN-72
PERICOM

PI6C21900SZDEX

 PLL Based Clock Driver, 6C Series, 19 True Output(s), 0 Inverted Output(s), GREEN, MO-220I/VNND, TQFN-72
PERICOM

PI6C21900ZDE

 PLL Based Clock Driver, 6C Series, 19 True Output(s), 0 Inverted Output(s), GREEN, MO-220I/VNND, TQFN-72
PERICOM

PI6C21900ZDEX

 PLL Based Clock Driver, 6C Series, 19 True Output(s), 0 Inverted Output(s), GREEN, MO-220I/VNND, TQFN-72
PERICOM

PI6C22392-03LE

 Video Clock Generator, 100MHz, CMOS, PDSO16, GREEN, TSSOP-16
PERICOM

PI6C22392-03LEX

 Clock Generator, CMOS, PDSO16
PERICOM

PI6C22405-1HLE

 PLL Based Clock Driver, 6C Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.173 INCH, GREEN, MO-153F/AA, TSSOP-8
PERICOM

PI6C22405-1HLIEX

 PLL Based Clock Driver, 6C Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.173 INCH, GREEN, MO-153F/AA, TSSOP-8
PERICOM

PI6C22405-1HWE

 PLL Based Clock Driver, 6C Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, GREEN, MS-012D/AA, SOIC-8
PERICOM

PI6C22405LE

 PLL Based Clock Driver, 6C Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.173 INCH, GREEN, MO-153FA, TSSOP-8
PERICOM

PI6C22405LEX

 PLL Based Clock Driver, 6C Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.173 INCH, GREEN, MO-153FA, TSSOP-8
PERICOM
©2020 ICPDF网 联系我们和版权申明