PI6CV855-02 [ETC]

Clock IC | 2.5V. 200 MHz. 5 Output SSTL-2 Zero Delay Clock Driver ; 时钟IC | 2.5V 。 200兆赫。 5输出SSTL - 2零延迟时钟驱动器\n


型号：	PI6CV855-02
厂家：	ETC
描述：	Clock IC \| 2.5V. 200 MHz. 5 Output SSTL-2 Zero Delay Clock Driver 时钟IC \| 2.5V 。 200兆赫。 5输出SSTL - 2零延迟时钟驱动器\n 时钟驱动器
文件：	总9页 (文件大小：134K)
中文：	中文翻译
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ADVANCEINFORMATION

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

ProductFeatures

ProductDescription

PLLclockdistributionoptimizedforSSTL_2

ThePI6CV855-02PLLClockBufferisdesignedfor2.5V

and2.5V

DDQ

Distributes one differential clock input pair to five differential

clock output pairs.

AV operation and differential data input and output levels. The

deviceisazerodelaybufferthatdistributesadifferentialclockinput

pair (CLK, CLK) to five differential pairs of clock outputs (Y[0:4],

Y[0:4]) and one differential pair feedback clock outputs (FBOUT,

FBOUT).Theclockoutputsarecontrolledbytheinputclocks(CLK,

CLK),thefeedbackclocks(FBIN,FBIN),andtheAnalogPowerinput

Inputs(CLK,CLK)and(FBIN,FBIN): SSTL_2

Outputs (Yx,Yx),(FBOUT,FBOUT): SSTL_2

Externalfeedbackpins(FBIN,FBIN)areusedto

synchronize the outputs to the input clocks.

(AV ). WhentheAV isstrappedlow, thePLListurnedoffand

Operates at AV = 2.5V for core circuit and internal PLL,

bypassed for test purposes.

and V

= 2.5V for differential output drivers

DDQ

ThePI6CV855-02isabletotrackSpreadSpectrumClockingtoreduce

EMI.

Packaging:Plastic28-pinTSSOP(L28)

PinConfiguration

BlockDiagram

GND

DDQ

CLK

GND

DDQ

CLK

FBOUT

PLL

FBIN

28-Pin 23

FBIN

DDQ

FBIN

GND

AGND

GND

DDQ

Logic

and

FBOUT

DDQ

Test Ciruit

GND

P.01

05/08/02

ADVANCEINFORMATION

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

PinoutTable

Name

I/O

Type

Pin No.

Description

CLK

Reference Clock input

Y[0:4]

3,11,13,17,27

2,10,14,16,28

Clock outputs.

Complement Clock outputs.

FBOUT

Feedback output, and Complement Feedback Output

FBIN

Feedback input, and Complement Feedback input

Power Supply for I/O pins.

DDQ

4,12,18,22,26

Power

Analog/core power supply. AV can be used to bypass the PLL for testing purposes. When

AV is strapped to ground, PLL is bypassed & CLK is buffered directly to the device outputs.

AGND

GND

Analog/core ground. Provides the ground reference for the analog/core circuitry

Ground for I/O pins.

Ground

1,9,15,19,25

FunctionTable

Inputs

Outputs

FBOUT

PLL State

AV_DD

GND

CLK

Y[0:4]

FBOUT

Bypassed/Off

GND

2.5V(nom)

P.01

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ADVANCEINFORMATION

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

Absolute Maximum Ratings (Over operating free-air temperature range)

Symbol

, AV

Parameter

I/O supply voltage range and analog/core supply voltage range

Input voltage range

Min.

0.5

Max.

Units

3.6

DDQ

+0.5

DDQ

Output voltage range

Storage temperature

0.5

Tstg

150

Note: Stress beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

TimingRequirements(Overrecommendedoperatingfree-airtemperature)

AV , V

= 2.5V ±0.2V

DDQ

Symbol

Description

Units

Min.

Max.

200

(1,2)

(3)

Operating clock frequency

MHz

Application clock frequency

Input clock duty cycle

100

µs

PLL stabilization time after powerup

100

STAB

Notes:

1. The PLL is able to handle spread spectrum induced skew.

2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is

not required to meet the other timing parameters. (Used for low-speed debug).

3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.

P.01

05/08/02

ADVANCEINFORMATION

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

DCSpecifications

Recommended Operating Conditions

Symbol

Parameter

Min.

2.3

1.8

Nom.

2.5

Max.

2.7

Units

AV_DDAnalog/core supply voltage

V_DDQOutput supply voltage

2.5

2.7

V_OH

V_OL

V_IX

High-level output voltage

V_DDQ

Low-level output voltage

0.5

Input differential-pair crossing voltage

(V_DDQ/2) 0.2

0.3

(V_DDQ/2) +0.2

V_DDQ+0.3

V_DDQ+0.6

V_OXOutput differential-pair crossing voltage at the SDRAM clock input

V_IN

V_ID

Input voltage level

Input differential voltage between CLK and CLK

0.36

Output differential voltage between Y[n] and Y[n] and FBOUT

and FBOUT

V_OD

T_A

0.7

V_DDQ+0.6

Operating free air temperature

°C

ElectricalCharacteristics

Parameter

Test Conditions

I_I= 18mA

A_VDD, V_DDQMin.

Typ. Max. Units

V_IK

I_I

All inputs

2.3V

2.7V

1.2

±10

CLK, FBIN

V_I= V_DDQor GND

V_DD= 2.7V ⁽¹⁾

µA

I_DDQ

Dynamic supply current of V_DDQ

300

I_ADD

C_I

Dynamic supply current of AV_DD

CLK and CLK

V_DD= 2.7V ⁽¹⁾

V_I= V_DDor GND

2.5V

2.0

3.0

FBIN and FBIN

Notes:

1. Driving memory chips with 120 Ohm termination resistor for each clock output pair at 134 MHz.

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ADVANCEINFORMATION

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

ACSpecifications

Switching characteristics over recommended operating free-air temperature range, f_CLK> 100 MHz (unless otherwise noted).

(See Figure 1 and 2)

AV_CC, V_DDQ= 2.5V ±0.2V

Parameter

Description

Static phase offset⁽¹⁾

Diagram

Units

Min.

100

1.0

Nom.

Max

t(θ)

tjit(cc)

tjit(per)

tjit(hper)

tsl(i)

Figure 4

Figure 3

Figure 6

Figure 7

Figure 8

Figure 5

Cycle-to-cycle jitter

Period jitter

Half-period jitter

100

2.0

100

Input clock slew rate⁽²⁾

Output clock slew rate⁽²⁾

Output clock skew

V/ns

tsl(o)

1.0

tsk(o)

The PLL meets all the above parameters while supporting SSC synthesizers with the following parameters ⁽³⁾

SSC modulation frequency

SSC clock input frequency deviation

PLL loop bandwidth

30.0

0.00

50.0

kHz

0.50

MHz

degrees

Phase angle

0.031

Notes:

1. Static Phase offset does not include jitter.

2. The slew rate is determined from the IBIS model with test load shown in Figure 1.

3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.

P.01

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ADVANCEINFORMATION

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

Z = 60Ω

DDR

SDRAM

R =120Ω

Z = 60Ω

DDR

SDRAM

Figure1.IBISModelOutputLoad

DDQ

Z = 60Ω

Z = 50Ω

R =10Ω

C=14pF

R = 50Ω

–V

DDQ

Z = 50Ω

Z = 60Ω

C=14pF

R = 50Ω

DDQ

SCOPE

–V

DDQ

Figure2.OutputLoadTestCircuit

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ADVANCEINFORMATION

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

Yx,FBOUT

t_{cycle n}

t_jit(cc)t_{cycle n}

t_{cycle n+1}

Figure3.Cycle-to-CycleJitter

CLK

FBIN

t₍

)

n+1

n=N

t₍

∑

) n

(N is a large number of samples)

Figure 4. Static Phase Offset

Yx, FBOUT

t_sk(o)

Figure5.OutputSkew

P.01

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ADVANCEINFORMATION

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

Yx, FBOUT

t_{cycle n}

Yx, FBOUT

f_O

t _jit(per)

t_{cycle n}

Figure 6. Period Jitter

Yx, FBOUT

t _n+1

t_{half period n}

half period

f_O

2*f_O

t_jit(hper)

t_{half period n}

Figure7.Half-PeriodJitter

V_DDQ

80%

20%

Clock Inputs

and Outputs

t_{sl(i), sl(o)}

t_sl(i),t_sl(o)

Figure8.InputandOutputSlewRates

P.01

05/08/02

ADVANCEINFORMATION

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

PackagingMechanical:28-PinTSSOP(L28)

.169

.177

4.3

4.5

0.09

0.20

.004

.008

.378

.386

0.45 .018

0.75 .030

9.6

9.8

.252

BSC

6.4

.047

1.20

Max

SEATING

PLANE

X.XX DENOTES CONTROLLING

X.XX DIMENSIONS IN MILLIMETERS

.002

.006

0.05

0.15

.007

.012

0.19

0.30

.0256

BSC

0.65

OrderingInformation

Ordering Code

Package Name

Package Type

28-pin, 4.4mm wide TSSOP

PI6CV855-02L

L28

Pericom Semiconductor Corporation

2380BeringDrive • SanJose,CA95131•1-800-435-2336 • Fax(408)435-1100• http://www.pericom.com

P.01

05/08/02

PI6CV855-02 [ETC]

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