PI74ALVCH32373NB [ETC]
8-Bit D-Type Latch ; 8位D类锁存器\n
| 型号： | PI74ALVCH32373NB |
| 厂家： | 
ETC |
| 描述： | 8-Bit D-Type Latch
|
| 文件： | 总7页 (文件大小：457K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI74ALVCH32373
32-Bit Transparent D-Type Latch
with 3-State Outputs
Product Features
ProductDescription
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced using the Companys advanced 0.5 micron CMOS
technology, achieving industry leading speed.
• PI74ALVCH32373 is designed for low voltage operation
• V = 2.3V to 3.6V
CC
• Typical V
(Output Ground Bounce)
OLP
This32-bittransparentD-typelatchisdesignedfor2.3Vto3.6VV
operation.
CC
< 0.8V at V = 3.3V, T = 25°C
CC
A
• Typical V
(Output V Undershoot)
OH
OHV
The PI74ALVCH32373 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as four 8-bit latches or two 16-
bit latches or one 32-Bit latch. When the Latch Enable (LE) input
is HIGH, the Q outputs follow the (D) inputs. When LE is taken
LOW, the Q outputs are latched at the levels set up at the D inputs.
> 2.0V at V = 3.3V, T = 25°C
CC
A
• Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
• Industrial operation at 40°C to +85°C
• Packages available:
96-ball, 13.5mm x 5.5mm x 1.4mm low profile fine
pitch ball grid array, LFBGA (NB)
A buffered Output Enable (OE) input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state in which the outputs neither
loadnordrivethebuslinessignificantly.Thehigh-impedancestate
and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not
affect internal operations of the latch. Old data can be retained
or new data can be entered while the outputs are in the high
impedance state.
Product Pin Description
Pin Name
OE
Description
Output Enable Input (Active LOW)
Latch Enable (Active HIGH)
Data Inputs
LE
Dx
Qx
3-State Outputs
Ground
To ensure the high impedance state during power up or power
GND
down, OE should be tied to V through a pullup resistor; the
CC
minimumvalue of the resistor is determined by the current-sinking
capability of the driver.
V
CC
Power
Truth Table(1)
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Inputs
LE
H
Outputs
OE
D
H
L
Q
H
L
L
L
H
L
H
L
X
X
Q
0
X
Z
Notes:
1. H =HighSignalLevel
L =LowSignalLevel
X =Irrelevant
Z = High Impedance
PS8438
10/14/99
1
PI74ALVCH32373
32-Bit Transparent D-Type Latch
with 3-State Outputs
NB Package (Top View)
6
5
4
3
2
1
A
B C D E F G H J
K
L M N P R T
TerminalAssignments
6
5
4
3
2
1
1D2
1D1
1LE
1OE
1Q1
1Q2
A
1D4
1D3
GND
GND
1Q3
1Q4
B
1D6
1D5
VCC
VCC
1Q5
1Q6
C
1D8
1D7
2D2
2D1
2D4
2D3
2D6
2D5
2D7
2D8
2LE
3D2
3D1
3LE
3OE
3Q1
3Q2
J
3D4
3D3
3D6
3D5
3D8
3D7
4D2
4D1
4D4
4D3
VCC
VCC
4Q3
4Q4
P
4D6
4D5
4D7
4D8
GND GND VCC
GND GND VCC
GND
GND VCC
GND VCC
GND GND
GND GND
GND 4LE
GND 4OE
GND 2OE
1Q7
2Q1
2Q3
2Q4
F
2Q5
2Q6
G
2Q8
2Q7
H
3Q3
3Q4
K
3Q5
3Q6
L
3Q7
3Q8
M
4Q1
4Q2
N
4Q5
4Q6
R
4Q8
4Q7
T
1Q8 2Q2
D
E
LogicDiagram(PositiveLogic)
A3
H3
H4
1OE
2OE
A4
1LE
2LE
C1
C1
1D
A2
E2
1Q1
2Q1
A5
E5
1D1
2D1
1D
To Seven Other Channels
To Seven Other Channels
J3
J4
T3
T4
3OE
4OE
3LE
4LE
C1
1D
C1
1D
J2
N2
3Q1
4Q1
J5
N5
3D1
4D1
To Seven Other Channels
To Seven Other Channels
PS8438
10/14/99
2
PI74ALVCH32373
32-Bit Transparent D-Type Latch
with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range,V
............................................................. 0.5V to 4.6V
CC
Note:
(1)
Input Voltage Range, V : Except I/O ports
............................ 0.5V to 4.6V
.......................... 0.5V to V + 0.5V
CC
I
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
(1,2)
I/O ports
(1,2)
Output Voltage Range, V
......................................... 0.5V to V +0.5V
CC
O
Input Clamp Current, I (V <0) ........................................................ 50mA
IK
I
Output Clamp Current, I (V <0) ................................................... 50mA
OK
O
Continuous Output Current, I .................................................................... ±50mA
O
Continuous Current through each V or GND............................... ±100mA
CC
(3)
Package Thermal Impedance, θ
Storage Temperature Range, T
.......................................................... 40ºC/W
...............................................65ºC to 150ºC
JA
STG
Note:
1. The input negative voltage and output voltage ratings may be exceeded
if the input and output current ratings are observed.
2. This value is limited to 4.6V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
(1)
Recommended Operating Conditions
Parameters
Description
Test Conditions
Min.
2.3
Typ.
Max.
Units
V
CC
Supply Voltage
3.6
V
V
= 2.3V to 2.7V
= 2.7V to 3.6V
= 2.3V to 2.7V
= 2.7V to 3.6V
1.7
CC
V
Input HIGH Voltage
Input LOW Voltage
IH
V
CC
2.0
V
CC
0.7
0.8
V
IL
V
CC
V
Input Voltage
0
0
V
CC
IN
V
OUT
Output Voltage
V
CC
V
= 2.3V
= 2.7V
= 3.0V
= 2.3V
= 2.7V
= 3.0V
12
12
24
12
mA
CC
Output
HIGH
Current
I
OH
V
CC
V
CC
V
CC
Output
LOW
Current
I
OL
V
CC
12
V
CC
24
∆t/∆V
Input Transition Rise or Fall Rate
Operating Free-Air Temperature
0
10
ns/V
°C
T
A
40
85
Note 1: All unused inputs must be held at V or GND to ensure proper device operation
CC
PS8438
10/14/99
3
PI74ALVCH32373
32-Bit Transparent D-Type Latch
with 3-State Outputs
DC Electrical Characteristics (Over the Operating Range, T = 40°C to +85°C, V = 3.3V ±10%)
A
CC
(1)
(2)
Parameters Description
Test Conditions
Min.
Typ.
Max.
Units
I
OH
= -100µA, V = Min. to Max.
V
CC-
0.2
CC
V
= 1.7V, I = -6mA V
CC =
2.3V
2.3V
2.7V
2.0
IH
OH
,
V
IH
= 1.7V, I = -12mA V
1.7
2.2
2.4
2.0
OH
,
CC =
CC =
V
OH
Output HIGH Voltage
V
IH
= 2.0V, I = -12mA V
OH ,
V
IH
= 2.0V, I = -12mA V =3.0V
OH , CC
V
IH
= 2.0V, I = -24mA V =3.0V
OH , CC
V
I
= -100µA, V = Min. to Max.
0.2
0.4
0.7
0.4
0.55
±5
OL
IL
V
= 0.7V, I = 6mA V
CC =
2.3V
2.3V
2.7V
IL
OL
,
V
Output LOW Voltage
Input Current
V = 0.7V, I = 12mA V
IL OL ,
OL
CC =
CC =
V
IL
= 0.8V, I = 12mA V
OL ,
V
IL
= 0.8V, I = 24mA V =3.0V
OL , CC
I
IN
V
= V or GND, V = 3.6V
IN CC CC
V
= 0.7V, V = 2.3V
45
45
75
IN
CC
V
IN
= 1.7V, V = 2.3V
CC
Input Hold
Current
I
IN
(
HOLD
)
V
= 0.8V, V = 3.0V
IN CC
V
IN
= 2.0V, V = 3.0V
75
CC
(3)
µA
V
= 0 to 3.6V, V = 3.6V
±500
±10
IN
CC
I
Output Current (3-State Outputs)
Supply Current
V
= V or GND, V = 3.6V
OZ
OUT CC CC
V
= 3.6V, I
= 0µA,
CC
CC
V
OUT
I
CC
40
= GND or V
IN
V
= 3.0V to 3.6V
CC
Supply Current per Input
@ TTL HIGH
∆I
CC
One Input at V - 0.6V
Other Inputs at V or GND
750
CC
CC
Control Inputs
Data Inputs
Outputs
3
6
7
C
V
= V or GND, V = 3.3V
I
IN CC CC
pF
C
V = V or GND, V = 3.3V
O CC CC
O
Notes:
1. For Min. or Max conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V = 3.3V, +25°C ambient and maximum loading.
CC
3. This is the bushold maximum dynamic current. It is the mimum overdrive current necessary to switch the input from one
state to another.
PS8438
10/14/99
4
PI74ALVCH32373
32-Bit Transparent D-Type Latch
with 3-State Outputs
Timing Requirements over Operating Range
V
= 2.5V ±0.2V
V
= 2.7V
V
= 3.3V ±0.3V
CC
CC
CC
Parameters
Description
Units
Min.
Max.
Min.
Max.
Min.
Max.
Pulse Duration LE
HIGH or LOW
t
W
3.3
3.3
3.3
Setup Time Data
Before LE↓
t
1.0
1.5
1.0
1.7
1.1
1.4
ns
SU
Hold Time Data
t
H
After LE↓
Switching Characteristics over Operating Range(1)
V
= 2.5V ±0.2V
V
= 2.7V
V = 3.3V ±0.3V
CC
CC
CC
Parameters
From (INPUT)
To (OUTPUT)
Units
(2)
(2)
Min.
Max.
Min.
Max. Min.
Max.
t
D
1.0
1.0
1.0
1.9
4.5
5.9
6.0
5.1
4.3
4.6
5.7
4.5
1.1
3.6
3.9
4.7
4.1
MHz
PD
t
PD
LE
OE
OE
1.0
1.0
1.4
Q
t
EN
ns
t
DIS
Notes:
1. See test circuit and waveforms, Figures 1 and 2.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, T = 25 C
A
V
= 2.5V ±0.2V
V
= 3.3V ±0.3V
CC
CC
Parameter
Test Conditions
Units
Typ.
Outputs Enabled
38
8
44
10
C
Power Dissipation
Capacitance
PD
C = 50pF, f = 10 MHz
L
pF
Outputs Disabled
PS8438
10/14/99
5
PI74ALVCH32373
32-Bit Transparent D-Type Latch
with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ±0.2V
Test
S1
tpd
tPLZ/tPZH
tPHZ/tPZH
Open
2 x VCC
GND
Load Circuit
Voltage Waveforms
Pulse Duration
VCC
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC/2
VCC/2
tPLZ
0V
tPZL
VCC
0V
Output
Waveform 1
S1 at 2 x VCC
(see Note B)
VCC
VCC/2
tPLH
VCC/2
tPHL
Input
VCC/2
VOL +0.15V
tPHZ
VOL
VOH
tPZH
Output
Waveform 2
S1 at GND
V
OH
OL
VOH –0.15V
/2
V
VCC/2
VCC/2
CC
Output
V
0V
(see Note B)
Voltage Waveforms
Propagation Delay Times
Voltage Waveforms
Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
PS8438
10/14/99
6
PI74ALVCH32373
32-Bit Transparent D-Type Latch
with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7V and 3.3V ±0.3V
6V
S1
Open
GND
500Ω
From Output
Under Test
Test
S1
CL = 50pF
tpd
tPLZ/tPZH
Open
6V
500Ω
(See Note A)
tPHZ/tPZH
GND
Load Circuit
Voltage Waveforms
Pulse Duration
2.7V
Output
Control
(Low Level
Enabling)
Voltage Waveforms
Setup and Hold Times
1.5V
1.5V
0V
3V
tPZL
tPLZ
Output
Waveform 1
S1 at 6V
2.7V
0V
1.5V
1.5V
tPHL
1.5V
tPLH
Input
VOL +0.3V
tPHZ
VOL
VOH
(see Note B)
tPZH
Output
Waveform 2
S1 at GND
VOH –0.3V
V
OH
OL
1.5V
1.5V
1.5V
Output
0V
(see Note B)
V
Voltage Waveforms
Propagation Delay Times
Voltage Waveforms
Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8438
10/14/99
7
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