PLL2014X [ETC]
PLL2014X 20MHZ~170MHZ FSPLL|Data Sheet ; PLL2014X 20MHZ 〜 170MHz的FSPLL |数据表\n
| 型号： | PLL2014X |
| 厂家： | 
ETC |
| 描述： | PLL2014X 20MHZ~170MHZ FSPLL|Data Sheet
|
| 文件： | 总12页 (文件大小：531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
20MHz ~ 170MHz FSPLL
PLL2014X
DEC 98 Version1.0
General Description
Features
The PLL2014X is a Phase-Locked Loop (PLL)
frequency synthesizer constructed in CMOS on
single monolithic structure.
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0.25um CMOS device technology
1.8 Volt Single power supply
Output frequency range: 20~ 170 MHz
Jitter ±150ps
The PLL macrofunctions provide frequency
multiplication capabilities.
The output clock frequency Fout is related
to the reference input clock frequency
Fin by the following equation:
Duty ratio 40% to 60% at 170MHz
Frequency changedby programmable divider
Power down mode
Fout = ( m*Fin ) / ( p* 2S)
Where,
Fout is the output clock frequency.
Fin is the reference input clock frequency.
m,p and s are the values for programmable dividers.
PLL2014X consists of a phase/Frequency Detector(PFD),
a Charge Pump an External Loop Filter, a Voltage
Controlled Oscillator(VCO), a 6bit Pre-divider,
an 8bit Main divider and 2bit Post Scaler
as shown in Figure1.
FUNCTIONAL BLOCK DIAGRAM
Fin
Charge
Pump
Pre Divider
P
Loop
Filter
(External)
Fout
PFD
VCO
Post Scaler
S
Main Divider
M
Figure 1. Phase Lockd Loop Block Diagram
SAMSUNG ELECTRONICS Co. LTD
PLL2014X
20MHZ~170MHZ FSPLL
CORE PIN DESCRIPTION
NAME
I/O
I/O PAD
PIN DESCRIPTION
Digital power supply
I/O TYPE ABBR.
TYPE
VDD
VSS
DP
DG
¡ ¤
¡ ¤
¡ ¤
¡ ¤
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Analog Output
Digital ground
VDDA
VSSA
VBB
AP
Analog power supply
Analog ground
AG
AB/DB
DI
Analog/Digital sub bias
PLL clock input
¡ ¤
¡ ¤
¡ ¤
¡ ¤
¡ ¤
¡ ¤
AP : Analog Power
AG : Analog Ground
AB : Analog Sub Bias
DP : Digital Power
DG : Digital Ground
DB : Digital Sub Vias
FIN
FILTER
AO
. Pump out is connected to Filter
. A capacitor is connected between
the pin and analog ground
FOUT
DO
DI
20MHz~170MHz clock output
FSPLL clock power down.
-PWRDN is High, PLL do not operating
under
PWRDN
this condition.
-If isn't used this pin, tied to VSS.
¡ ¤
BD : Bidirectional Port
P[5:0]
M[7:0]
S[1:0]
DI
DI
DI
The values for 6bit
programmable pre-divider.
The values for 8bit
programmable main divider.
The values for 2bit
programmable post scaler.
* I/O Type support next Version of a datasheet
CORE CONFIGURATION
FIN
FOUT
¡ á
¢º
¡ á
¢º
¡ á
¢º
PWRDN
M[7:0]
¡ á
¢º
M[0]
M[1]
M[2]
M[3]
M[4]
M[5]
M[6]
M[7]
FILTER
¡ á
¢º
pll2014x
P[5:0]
S[1:0]
¡ á
¢º
P[0]
P[1]
P[2]
P[3]
P[4]
P[5]
¡ á
¢º
S[0]
S[1]
1
SEC ASIC
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ANALOG
PLL2014X
20MHZ~170MHZ FSPLL
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Value
Unit
Applicable pin
Supply Voltage
3.3
V
VDD,VDDA,VSS,VSSA
VDDA
P[5:0],M[7:0],S[1:0]
Voltage on Any Digital Pin
Storage Temperature
Vin
Vss-0.3 to Vdd+0.3
-40 to 125
V
PWRDN
-
¡ É
Tstg
NOTES
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each
condition value is applied with the other values kept within the following operating conditions and function
operation under any of these conditions is not implied.
2. All voltages are measured with respect to VSS unless otherwise specified.
§Ú
3. 100pF capacitor is discharged through a 1.5 resistor (Human body model)
Recommended Operating Conditions
Supply Voltage Differential
Oscillator Frequency
Symbol
VDD - VDDA
Fosc
Min
-0.1
10
Typ
Max
0.1
Unit
40
Mhz
pF
External Loop Filter Capacitance
Operating Temperature
LF
820
¡ É
Topr
0
70
NOTES
1. It is strongly recommended that all the supply pins (VDDA, VDD) be powered from the same source
to avoid power latch-up.
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SEC ASIC
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ANALOG
PLL2014X
20MHZ~170MHZ FSPLL
DC ELECTRICAL CHARACTERISTICS
Operating Voltage
Symbol
VDD/VDDA
VIH
Min
Typ
1.8
Max
Unit
V
1.6
2.0
Digital Input Voltage High
Digital Input Voltage Low
TBD
TBD
V
VIL
V
Dynamic Current
Idd
Ipd
3.5
80
mA
uA
(CORE Level without I/O Cell)
Power Down Current
AC ELECTRICAL CHARACTERISTICS
Input Frequency
Symbol
FIN
Min
2
Typ
Max
40
Unit
MHz
Mhz
%
Output Clock Frequency
Input Clock Duty Cycle
Output Clock Duty Cycle
Input Glitch Pulse Width
Locking Time
FOUT
TID
20
40
40
1
170
60
TOD
60
%
TIGP
TLT
ns
150
us
Cycle to Cycle Jitter
TJCC
-150
+150
ps
3
SEC ASIC
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ANALOG
PLL2014X
20MHZ~170MHZ FSPLL
Functional Description
A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference
or input signal in frequency as well as in phase.
In this application, it includes the following basic blocks.
. The voltage-controlled oscillator to generate the output frequency
. The divider P devides the reference frequency by p
. The divider M devides the VCO output frequency by m
. The divider S divides the VCO output frequency by s
. The phase frequency detector detects the phase difference between the reference frequency
and the output frequency (after division) and controls the charge pump voltage.
. The loop filter removes high frequency components in charge pump voltage and does
smooth and clean control of VCO
The m, p, s values can be programmed by 16bit digital data from the external source. So the PLL
can be locked in the desired frequency.
Fout = m * Fin / p*s
If Fin = 14.318MHz, and m=M+8 , p=P+2, s=2^S
Digital data format:
Main Divider
Pre Divider
Post Scaler
M7,M6,M5,M4,M3,M2,M1,M0
P5,P4,P3,P2,P1,P0
S0,S1
NOTES
. S[1] - S[0] : Output Frequency Scaler
. M[7] - M[0] : VCO Frequency Divider
. P[5] - P[0] : Reference Frequency Input Divider
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ANALOG
PLL2014X
20MHZ~170MHZ FSPLL
CORE EVALUATION GUIDE
For the embedded PLL, we must consider the test circuits for the embedded PLL core inmultiple applications.
Hence the following requirements should be satisfied.
- The FILTER and FOUT pins must be bypassed for external test.
- For PLL test (Below 2 examples),
it is needed to control the dividers - M[7:0],P[5:0] and S[1:0] -that generate multiple clocks.
Example #1. Registers can be used for easy control of divider values.
Example #2. N sample bits of 16-bit divider pins can be bypassed for test using MUX.
1.8V Analog Power
1.8V
Digital
Power
GND
External Clock Source
GND
FIN
¡ á
¢º
VDDA
VSSA
VBBA
VSS
VDD
FOUT
¡ á
¢º
PWRDN
M[7:0]
pll2014x
#1.16bit Register Block
FILTER
¡ á
¢º
P[5:0]
820pF
VSSA
S[1:0]
Select Pin
NOTES
#2
M
U
: 10uF ELECTROLYTIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
: 103 CERAMIC CAPACITOR
Test Pins of N Sample bits
Internal Divider Signal Line
UNLESS OTHERWISE SPECIFIED
X
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PLL2014X
20MHZ~170MHZ FSPLL
CORE LAYOUT GUIDE
- The digital power(VDD,VSS) and the analog power(VDA,VSSA) must be dedicated to PLL only and
seperated. If the dedicated VDD and VSS is not allowed that of the least power consuming block is
shared with the PLL.
- The PIA pad is used as a FILTER pad that contains only ESD production diodes without any resistors
and buffers.
- The FOUT and FILTER pins must be placed far from the internal signals in order to avoid overlapping
signal lines.
- The blocks having a large digital switching current must be located away from the PLL core.
- The PLL core must be shielded by guardring.
- For the FOUT pad, you can use a custom drive buffer or POT12 buffer considering the drive current.
WITHOUT XTAL-DRIVER USERS GUIDE
1. If the crystal component not used , an external clock source is applied to the FIN
*Please contact an SEC application engineer when using a crystal.
2. If the crystal component not used , an external clock I/O Buffer offered from Samsung's
MDLM110 library is recommanded for use
- When implementing an embedded PLL block, the following pins must be bypassed externally
for testing the PLL locking function:
* Without Xtal-driver : FIN,FILTER,FOUT,VDDA,VSSA,VDD and VSS.
Figure2. The example of PLL block without crystal component (Normal Case)
FILTER
FOUT
¡ á
¡ á
¡ á
VDDA
VSSA ¡ á
Divider
P
PFD
&CP
Scaler
S
¡ á
FIN
LF
VCO
Used PICC_BB PAD
VDD
¡ á
¡ á
¡ á
PWRDN
Divider
M
P[5:0]
M[7:0]
S[1:0]
VSS
Glue Logic
VBBA
MUX
* Divider Bus
¡ á
* Optional Test Pins
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ANALOG
PLL2014X
20MHZ~170MHZ FSPLL
PACKAGE CONFIGURATION
2bit Post Scaler
L
L
L
L
1.8V I/O Power
C
1.8V Digital PAD Power
C
H
H
H
H
36
35
34
33
32
31
30
29
28
27
26
25
S
0
S
1
N
c
N
C
N
C
V
D
D
O
V
S
N
C
V
D
D
V
D
D
V
S
S
V
S
S
8bit Main Divider
S
L
L
L
24
NC
H
H
H
37 M7
O
FOUT 23
38
39
40
41
M6
M5
M4
M3
22
NC
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
21
NC
pll2014x
20
VBB
19
42 M2
VBB
L
H
C
M1
43
18
17
16
15
14
13
PWRDN
FILTER
820pF
103
10uF
44
45
46
M0
NC
FIN
P5
P4
External Clock Source
47 P3
P2
VDDA
C
V
S
V
48
VDDA
S
S
A
P
0
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
S
1.8V Analog Power
P
1
6bit Pre Divider Input
A
1
2
3
4
5
6
7
8
9
10
11
12
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
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ANALOG
PLL2014X
20MHZ~170MHZ FSPLL
PACKAGE PIN DESCRIPTION
NAME
VDDD
VSSD
VBB
PIN NO
35,36
I/O TYPE
DP
PIN DESCRIPTION
Digital power supply
Digital ground
33,34
DG
19,20
AB/DB
Analog / Digital Sub Bias
FSPLL clock power down
PWRDN
18
DI
-PWRDN is High, PLL do not operating under
this condition.
- If isn't used this pin, tied to VSS.
P[0]~P[5]
VDDA
VSSA
FIN
45~48,1,2
13,14
11,12
15
DI
AP
AG
AI
Pre-Divider Input
Analog power supply
Analog ground
External PLL clock input
20MHZ~170MHz clock output
FOUT
23
DO
Pump out is connected to the FILTER.
A 820pF Capcitor is connected between the
pin and analog pin
FILTER
17
AO
S[0]~S[1]
M[0]~M[7]
VDDO
32,31
37~44
28
DI
DI
PP
PG
Post scaler input
8bit main divider input
I/O PAD Power
VSSO
27
I/O PAD Power
NOTES
1. I/O TYPE PP and PG denote PAD power and PAD ground respectively.
2. XTALIN, XTALOUT is test pin for PLL in SEC
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PLL Components
PLL2014X
20MHZ~170MHZ FSPLL
Figure1 is block diagram of the components of a PLL: phase frequency detector, chrge pump,
voltage controlled oscillator, and loop filter.
In SEC technology, the loop filter is implemented as external components close to chip.
Phase detector : The phase dectector monitors the phase dfference between the Fref and
Fvco,and generates a control signal when it detects difference between the two.
If the Fref frequency is higher than the Fvco frequency, its falling edge occures before(lead) the falling edge
of the Fvco output. When this occures the phase detector signals the VCO to increase the frequency of the
on-chip clock. If the falling edge of the Fref occures after(lag) the falling edge of the Fvco output, the
detector signals the VCO to decrease on-chip clock frequency. Figure3 illustrates the lead and lag conditions.
If the frequencies of the Fref and Fvco are the same, the detect or does not generate a control signal, so the
frequencies remain the same.
Fref Clk
Fvco Clk
UP
DOWN
Figure3. Lead and Lag Clocking Relationships
Charge Pump : The charge pump converts the phase detector control signal to a charge in voltage across the
external filter that drives the VCO. As the vcoltage Controlled Oscillator decreases, or increases, If the voltage
remains constant, the frequency of the oscillator remains constant.
Loop Filter : The control signal that the phase detector generates for the charge pump may generate large
excursions(ripples) each time the VCO output is compared to the system clock. To avoid overloading the VCO,
a low pass filter samples and filters the high-frequency components out of the control signal. the filter is
typically a single-pole RC filter consisting of a resistor and capacitor.
Voltage Controlled Oscillator(VCO) : The output voltage from the loop filter drives the VCO, causing its
oscillation frequency to increas or decrease as a function of variations in voltage. When the VCO output
matches the system clock in frequency and phase, the pahse detector stops sending a control signal to the
charge pump, which in turn stabilizes the input voltage to the loop filter. The VCO frequency then remains
constant, and the PLL remains locked onto the system clock
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PLL2014X
20MHZ~170MHZ FSPLL
Frequency Synthesis
Frequency synthesis uses the system clock as a base frequency to generate higher/lower frequency clocks for
internal logic.
For high speed applications in high-end designs, transmission line effects cause problems because of parastics
and impedance mismatch among various on-board components.
These problems can be eliminated by moving the high frequency to the chip level.
On-chip clocks that are faster than the external system clock can be synthesized by inserting a divider in the
feedback path. The divider is placed after voltage controlled oscillator, as illustrated in Figure4. The signal is
running at M times the system clock frequency, so the PLL matches the divider signal output to the system
clock. This configuation reduces the problem of interfacing to the system clock on the board, and it reduces
the noise generated by the system clock oscillator and driver for all the components in the system
Design Considerations
The following design consideratios apply:
* Phase tolerance and jitter are independent of the PLL frequency.
* Jitter is affected by the noise frequency in the power(VDD/VSS,VDDA/VSSA) .
It increases when the noise level increases.
* A CMOS-level input reference clock is recommend for signal compatibility with
the PLL circuit. Other levels such as TTL may degrade the tolerances.
* The use of two, or more PLLs requires special design considerations. Please
consult your application engineer for more information.
* The following apply to the noise level, which can be minimized by using good
analog power and ground isolation techniques in the system:
- Use wide PCB traces for POWER(VDD/VSS, VDDA/VSSA) connections to the PLL core.
Seperate the traces from the chip's VDD/VSS,VDDA/VSSA supplies.
- Use proper VDD/VSS,VDDA/VSSA de-coupling.
- Use good power and ground sources on the board.
- Use Power VBB for minimize substrate noise
* The PLL core should be placed as close as possible to the dedicated loop filter and analog
Power and ground pins.
* It is inadvisable to locate noise-generating signals, such as data buses and high-current
outputs, near the PLL I/O cells.
* Other related I/O signals should be placed near the PLL I/O but do not have any pre-
defined placement restriction
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SEC ASIC
ANALOG
PLL2014X
20MHZ~170MHZ FSPLL
PLL Specification
We appreciate your interest in our products. If you have further questions, please specify in
the attached form. Thank you very much.
Parameter
Min
Typ
Max
Unit
Remarks
Supply Voltage
Output frequency range
Input frequency range
Cycle to Cycle Jitter
Lock up time
Dynamic current
Stand by current
Output clock duty ratio
Long term jitter
Output slew rate
- Do you need XTAL driver buffer in PLL Core?
If you need it, what's the crystal frequency range? If not, What's the input frequency range?
- Do you need the lock detector?
- Do you need the I/O cell of SEC?
- Do you need the external pin for PLL test?
- What's the main frequency & frequency range?
- How many FSPLLs do you use in your system?
- What's output loading?
- Could you external/internal pin configurations as required?
Specially requested function list :
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ANALOG
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