SEU02G64B4BF2SA-30R [ETC]
2GB DDR2 . SDRAM unbuffered DIMM;
| 型号： | SEU02G64B4BF2SA-30R |
| 厂家： | 
ETC |
| 描述： | 2GB DDR2 . SDRAM unbuffered DIMM 动态存储器 双倍数据速率 |
| 文件： | 总16页 (文件大小：988K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
preliminary Data Sheet
Rev.0.9
17.12.2012
2GB DDR2 – SDRAM unbuffered DIMM
Features:
.
240-pin 64-bit Dual-In-Line Double Data Rate
synchronous DRAM Module
Module organization: dual rank 256M x 64
VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V
1.8V I/O ( SSTL_18 compatible)
240 Pin UDIMM
SEU02G64B4BF2SA-xxR
2GByte in FBGA Technology
RoHS compliant
.
.
.
.
Auto Refresh (CBR) and Self Refresh 8k Refresh
every 64ms
Options:
.
.
.
Serial Presence Detect with EEPROM
Gold-contact pads with 30µ” electrolytic gold
.
Data Rate / Latency
DDR2 800 MT/s CL6
DDR2 667 MT/s CL5
Marking
-25
This module is fully pin and functional compatible to
the JEDEC PC2-6400 spec. and JEDEC- Standard
MO-237. (see www.jedec.org)
-30
.
The pcb and all components are manufactured
.
Module density
2048MB with 16 dies and 2 ranks
according to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
.
Standard Grade (TA)
(TC)
0°C to 70°C
0°C to 85°C
.
DDR2 - SDRAM component SAMSUNG
K4T1G084QF DIE Rev. F
Environmental Requirements:
.
.
.
.
.
.
.
.
.
.
128Mx8 DDR2 SDRAM in FBGA-60 package
4-bit prefetch architecture
.
Operating temperature (ambient)
Standard Grade
0°C to 70°C
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent operation
Programmable CAS latency (CL)
.
.
.
.
.
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
Posted CAS additive latency (AL)
WRITE latency = READ latency – 1 tCK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
1682 PSI (up to 5000 ft.) at 50°C
Figure: mechanical dimensions1
1
if no tolerances specified ± 0.15mm
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 1
of 16
preliminary Data Sheet
Rev.0.9
17.12.2012
This Swissbit module is an industry standard 240-pin 8-byte DDR2 SDRAM Dual-In-line Memory Module
(UDIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured
octal-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve high-speed
operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses
to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial
EEPROM using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes
are utilized by the DIMM manufacturer (swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Row
Addr.
Device Bank
Addr.
Column
Addr.
Module
Bank Select
Organization
DDR2 SDRAMs used
Refresh
256M x 64bit
16 x 128M x 8bit (1024Mbit)
14
BA0, BA1, BA2
10
8k
S0#, S1#
Module Dimensions
in mm
133.35 (long) x 30(high) x 4.00 [max] (thickness)
Timing Parameters
Part Number
Module Density
Transfer Rate
Clock Cycle/Data bit rate
Latency
SEU02G64B4BF2SA-25R
SEU02G64B4BF2SA-30R
2048 MB
2048 MB
6.4 GB/s
5.3 GB/s
2.5ns/800MT/s
3.0ns/667MT/s
6-6-6
5-5-5
Pin Name
A0-9, A11 – A13
A10/AP
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
BA0 – BA2
DQ0 – DQ63
DM0-DM7
DQS0 - DQS7
DQS0# - DQS7#
RAS#
Data Input / Output
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
CAS#
WE#
CKE0 – CKE1
S0#, S1#
Clock Enable
Chip Select
CK0 – CK2
CK0# - CK2#
Clock Inputs, positive line
Clock Inputs, negative line
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 16
preliminary Data Sheet
Rev.0.9
17.12.2012
VDD
Supply Voltage (1.8V± 0.1V)
VREF
Input / Output Reference
Ground
VSS
VDDSPD
SCL
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
Serial Data Out for Presence Detect
Presence Detect Address Inputs
On-Die Termination
SDA
SA0 – SA1
ODT0, ODT1
NC
No Connection
Pin Configuration
PIN #
1
Front Side
PIN #
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
Back Side
VSS
PIN #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front Side
A4
PIN #
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
Back Side
VDDQ
VREF
VSS
2
DQ4
VDDQ
A2
A3
3
DQ0
DQ5
A1
4
DQ1
VSS
VDD
VDD
5
VSS
DM0 (DQS9)
NC (DQS9#)
VSS
VSS
CK0
6
DQS0#
DQS0
VSS
VSS
CK0#
VDD
7
VDD
8
DQ6
NC (Par_In)
VDD
A0
9
DQ2
DQ7
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DQ3
VSS
A10/AP
BA0
BA1
VSS
DQ12
VDDQ
DQ8
DQ13
VDDQ
WE#
CAS#
VDDQ
S1#
RAS#
S0#
DQ9
VSS
VSS
DM1 (DQS10)
NC (DQS10#)
VSS
VDDQ
DQS1#
DQS1
VSS
ODT0
A13
CK1
ODT1
VDDQ
VSS
VDD
NC(RESET#)
NC
CK1#
VSS
VSS
DQ36
DQ37
VSS
VSS
DQ14
DQ32
DQ33
VSS
DQ10
DQ11
VSS
DQ15
VSS
DM4 (DQS13)
NC (DQS13#)
VSS
DQ20
DQS4#
DQS4
VSS
DQ16
DQ17
VSS
DQ21
VSS
DQ38
DQ39
VSS
DM2 (DQS11)
NC (DQS11#)
VSS
DQ34
DQ35
VSS
DQS2#
DQS2
VSS
DQ44
DQ45
VSS
DQ22
DQ40
DQ41
VSS
DQ18
DQ19
VSS
DQ23
VSS
DM5 (DQS14)
NC (DQS14#)
DQ28
DQS5#
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
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eMail: info@swissbit.com
Page 3
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preliminary Data Sheet
Rev.0.9
17.12.2012
PIN #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front Side
DQ24
DQ25
VSS
PIN #
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back Side
DQ29
PIN #
93
Front Side
DQS5
VSS
PIN #
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back Side
VSS
VSS
94
DQ46
DQ47
VSS
DM3 (DQS12)
NC (DQS12#)
VSS
95
DQ42
DQ43
VSS
DQS3#
DQS3
VSS
96
97
DQ52
DQ53
VSS
DQ30
98
DQ48
DQ49
VSS
DQ26
DQ27
VSS
DQ31
99
VSS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
CK2
NC (CB4)
NC (CB5)
VSS
SA2
CK2#
NC (CB0)
NC (CB1)
VSS
NC (TEST)
VSS
VSS
DM6 (DQS15)
NC (DQS15#)
VSS
NC (DM8,DQS17)
NC (DQS17#)
VSS
DQS6#
DQS6
VSS
NC (DQS8#)
NC (DQS8)
VSS
DQ54
DQ55
VSS
NC (CB6)
NC (CB7)
VSS
DQ50
DQ51
VSS
NC (CB2)
NC (CB3)
VSS
DQ60
DQ61
VSS
VDDQ
DQ56
DQ57
VSS
VDD
CKE1
CKE0
VDD
VDD
DM7 (DQS16)
NC (DQS16#)
VSS
NC (A15)
NC (A14)
VDDQ
DQS7#
DQS7
VSS
BA2
NC(Par_Out)
VDDQ
DQ62
DQ63
VSS
A12
DQ58
DQ59
VSS
A11
A9
A7
VDD
VDDSPD
SA0
VDD
A8
SDA
A5
A6
SCL
SA1
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 4
of 16
preliminary Data Sheet
Rev.0.9
17.12.2012
FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR2 SDRAM DIMM,
2 RANKS AND 16 COMPONENTS
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
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Page 5
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preliminary Data Sheet
Rev.0.9
17.12.2012
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
Voltage on any pin relative to VSS
SYMBOL
VDD
VDDQ
VDDL
VIN, VOUT
MIN
-1.0
-0.5
-0.5
-0.5
MAX
UNITS
2.3
2.3
2.3
2.3
V
V
V
V
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
II
µA
Command/Address
RAS#, CAS#, WE#, S#, CKE
-40
40
CK, CK#
DM
-20
-5
20
5
OUTPUT LEAKAGE CURRENT
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
-5
5
µA
µA
)
DQ, DQS, DQS#
VREF LEAKAGE CURRENT ; VREF is on a valid level
IVREF
-16
16
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
SYMBOL
VDD
MIN
1.7
1.7
NOM
1.8
1.8
MAX
1.9
1.9
UNITS
V
V
V
VDDQ
VDDL
VDDL Supply Voltage
1.7
1.8
1.9
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VREF
VTT
VIH (DC)
VIL (DC)
0.49 x VDDQ
VREF – 0.04
VREF + 0.125
-0.3
0.50 x VDDQ
VREF
0.51x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF – 0.125
V
V
V
V
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VIH (AC)
MIN
VREF + 0.25
-
MAX
-
VREF - 0.25
UNITS
V
V
VIL (AC)
CAPACITANCE
At DDR2 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
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eMail: info@swissbit.com
Page 6
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preliminary Data Sheet
Rev.0.9
17.12.2012
IDD Specifications and Conditions
(0°C ≤ TCASE ≤ + 85°C ; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
Parameter
max.
Symbol
IDD0
Unit
& Test Condition
6400-6-6-6
5300-5-5-5
OPERATING CURRENT *) :
One device bank Active-Precharge;
mA
440
424
tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is
HIGH between valid commands;
DQ inputs changing once per clock cycle; Address
and control inputs changing once every two clock
cycles
OPERATING CURRENT *) :
mA
IDD1
488
464
One device bank; Active-Read-Precharge;
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address inputs changing once every
two clock cycles; Data Pattern is same as IDD4W
PRECHARGE POWER-DOWN CURRENT:
All device banks idle; Power-down mode;
tCK = tCK (IDD); CKE is LOW; All Control and Address
bus inputs are not changing; DQ’s are floating at VREF
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
mA
mA
IDD2P
160
320
160
320
IDD2Q
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at VREF
PRECHARGE STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing
once per clock cycle
mA
mA
IDD2N
400
384
Fast PDN Exit
MR[12] = 0
ACTIVE POWER-DOWN
CURRENT:
IDD3P
368
240
352
240
All device banks open; tCK = tCK
(IDD); CKE is LOW; All Control
Slow PDN Exit
MR[12] = 1
and Address bus inputs are not
changing; DQ’s are floating at
VREF
ACTIVE STANDBY CURRENT:
All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing
once per clock cycle
mA
mA
IDD3N
512
720
480
640
OPERATING READ CURRENT*) :
IDD4R
All device banks open, Continuous burst reads; One
module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD),
AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
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Page 7
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preliminary Data Sheet
Rev.0.9
17.12.2012
Parameter
max.
Symbol
Unit
& Test Condition
6400-6-6-6
5300-5-5-5
OPERATING WRITE CURRENT*) :
mA
IDD4W
616
560
All device banks open, Continuous burst writes; One
module rank active; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two
clock cycles; DQ inputs changing once per clock cycle
BURST REFRESH CURRENT:
mA
IDD5
1680
1600
tCK = tCK (IDD); refresh command at every tRFC (IDD)
interval, CKE is HIGH, CS# is HIGH between valid
commands; All other Control and Address bus inputs
are changing once every two clock cycles; DQ inputs
changing once per clock cycle
SELF REFRESH CURRENT:
mA
mA
IDD6
160
160
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
Address bus inputs are floating at VREF; DQ’s are
floating at VREF
OPERATING CURRENT*) :
IDD7
1360
1240
Four device bank interleaving READs, IOUT = 0mA; BL = 4,
CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during
DESELECT; DQ inputs changing once per clock cycle
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P
(CKE LOW) mode.
TIMING VALUES USED FOR IDD MEASUREMENT
IDD MEASUREMENT CONDITIONS
SYMBOL
CL (IDD
tRCD (IDD
tRC (IDD
tRRD (IDD
tCK (IDD
tRAS MIN (IDD
tRAS MAX (IDD
tRP (IDD
tRFC (IDD
6400-6-6-6
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
5300-5-5-5
)
6
15
60
7.5
2.5
45
70’000
15
127.5
5
15
60
7.5
3.0
45
70’000
15
)
)
)
)
)
)
)
)
127.5
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
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Page 8
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preliminary Data Sheet
Rev.0.9
17.12.2012
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C ; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
6400-6-6-6
5300-5-5-5
MIN MAX
SYMBOL
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
MIN
MAX
8.0
8.0-
8.0
Unit
ns
ns
ns
ns
Clock cycle time
2.5
3.0-
3.75
-
CL = 6
CL = 5
CL = 4
CL = 3
-
-
3.0
8.0
3.75
5.0
8.0
8.0
-
CK high-level width
CK low-level width
Half clock period
0.48
0.48
0.52
0.52
0.48
0.48
min
0.52
0.52
tCK
tCK
tCL
min
(tCH, tCL)
-
-
ps
ns
ns
ns
tHP
tAC
tHZ
tLZ
(tCH, tCL)
Access window (output) of DQS
from CK/CK#
Data-out high-impedance
window from CK/CK#
Data-out low-impedance window
from CK/CK#
-0.40
-
+0.40
tAC max
tAC max
-0.45
+0.45
+0.45
(= tAC max)
-
-0.45
+0.45
tAC min
(= tAC min) (= tAC max)
DQ and DM input setup time
relative to DQS
0.05
-
-
0.10
-
-
ns
ns
tDS
tDH
DQ and DM input hold time
relative to DQS
DQ and DM input pulse width
( for each input )
0.125
0.35
0.175
0.35
-
0.3
-
-
0.34
-
tCK
ns
ns
tDIPW
tQHS
tQH
Data hold skew factor
-
-
DQ-DQS hold, DQS to first DQ
to go non-valid, per access
Data valid output window
DQS input high pulse width
DQS input low pulse width
tHP - tQHS
tHP - tQHS
tQH - tDQSQ
0.35
0.35
tQH - tDQSQ
0.35
0.35
-
-
-
-
-
-
ns
tCK
tCK
tDVW
tDQSH
tDQSL
DQS falling edge to CK rising
- setup time
DQS falling edge from CK rising
- hold time
DQS –DQ skew, DQS to last DQ
valid, per group, per access
DQS read preamble
DQS read postamble
DQS write preamble
DQS write preamble setup time
DQS write postamble
0.2
0.2
-
-
-
0.2
0.2
-
-
-
tCK
tCK
ns
tDSS
tDSH
0.2
0.24
tDQSQ
0.9
0.4
0.35
0
1.1
0.6
-
0.9
0.4
0.35
0
1.1
0.6
-
tCK
tCK
tCK
ns
tRPRE
tRPST
tWPRE
tWPRES
tWPST
-
-
0.4
0.6
0.4
0.6
tCK
Positive DQS latching edge to
associated clock edge
Write command to first DQS
latching transition
Address and control input pulse
width ( for each input )
Address and control input setup
time
- 0.25
+ 0.25
- 0.25
+ 0.25
tCK
tCK
tCK
ns
tDQSS
WL-
tDQSS
WL+
tDQSS
WL-
tDQSS
WL+
tDQSS
0.6
-
-
0.6
0.2
-
-
tIPW
tIS
0.175
Swissbit AG
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Page 9
of 16
preliminary Data Sheet
Rev.0.9
17.12.2012
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C ; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
Address and control input hold
time
CAS# to CAS# command delay
ACTIVE to ACTIVE (same bank)
command period
6400-6-6-6
MIN MAX
5300-5-5-5
MIN MAX
SYMBOL
tIH
Unit
ns
0.25
2
-
-
-
0.275
2
-
-
-
tCK
ns
tCCD
60
60
tRC
ACTIVE bank a to ACTIVE bank
b command
-
7.5
-
7.5
ns
tRRD
ACTIVE to READ or WRITE
delay
Four bank Activate period
ACTIVE to PRECHARGE
command
15
37.5
45
-
15
37.5
45
-
ns
ns
ns
tRCD
tFAW
tRAS
-
-
70’000
70’000
Internal READ to precharge
command delay
Write recovery time
Auto precharge write recovery +
precharge time
7.5
-
-
-
7.5
-
-
-
ns
ns
ns
tRTP
tWR
tDAL
15
tWR + tRP
15
tWR + tRP
Internal WRITE to READ
command delay
PRECHARGE command period
PRECHARGE ALL command
period
7.5
15
-
-
-
7.5
15
-
-
-
ns
ns
ns
tWTR
tRP
tRP + tCK
tRP + tCK
tRPA
LOAD MODE command cycle
time
CKE low to CK, CK# uncertainty
2
-
2
-
tCK
tCK
tMRD
tIS + tCK + tIH
tIS + tCK + tIH
tDELAY
REFRESH to ACTIVE or
REFRESH to REFRESH
command interval
Average periodic refresh interval
0 °C ≤ TCASE ≤ 85°C
127.5
-
70’000
127.5
70’000
ns
µs
tRFC
-
7.8
3.9
-
7.8
3.9
-
tREFI
85 °C < TCASE ≤ 95°C
Exit SELF REFRESH to non-
READ command
Exit SELF REFRESH to READ
command
Exit SELF REFRESH timing
reference
ODT turn-on delay
tRFC(min)
+ 10
tRFC(min)
+ 10
ns
tXSNR
tXSRD
-
200
tIS
-
200
tIS
tCK
-
-
ps
tCK
ps
tCK
ps
tISXR
tAOND
tAON
2
2
2
2
tAC(max)
+ 1,000
tAC(max)
+ 1,000
ODT turn-on
tAC(min)
2.5
tAC(min)
2.5
ODT turn-off delay
ODT turn-off
2.5
tAC(max)
+ 600
2.5
tAC(max)
+ 600
tAOFD
tAOF
tAC(min)
tAC(min)
2 x tCK
tAC(max)
+ 1,000
+
2 x tCK +
tAC(max)
+ 1,000
ODT turn-on (power-down
mode)
tAC(min) +
2,000
tAC(min) +
2,000
ps
tAONPD
2.5 x tCK
tAC(max)
+ 1,000
+
2.5 x tCK
tAC(max)
+ 1,000
+
ODT turn-off (power-down
mode)
tAC(min) +
2,000
tAC(min) +
2,000
ps
tAOFPD
tANPD
ODT to power-down entry
latency
3
-
3
-
tCK
Swissbit AG
Industiestrasse 4
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Page 10
of 16
preliminary Data Sheet
Rev.0.9
17.12.2012
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C ; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
ODT power-down exit latency
6400-6-6-6
5300-5-5-5
MIN MAX
SYMBOL
tAXPD
MIN
MAX
Unit
tCK
8
-
8
-
ODT enable from MRS
command
tMOD
12
-
-
-
12
-
ns
tCK
tCK
Exit active power-down to READ
command, MR [bit 12 = 0]
Exit active power-down to READ
command, MR [bit 12 = 1]
Exit precharge power-down to
any non-READ command
CKE minimum high/low time
tXARD
tXARDS
tXP
2
2
-
-
8 – AL
7 - AL
2
3
-
-
2
3
-
-
tCK
tCK
tCKE
Swissbit AG
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Page 11
of 16
preliminary Data Sheet
Rev.0.9
17.12.2012
SERIAL PRESENCE-DETECT MATRIX
BYTE
DESCRIPTION
6400-6-6-6
5300-5-5-5
0
1
2
3
4
5
6
7
8
NUMBER OF SPD BYTES USED
0x80
0x08
0x08
0x0E
0x0A
0x61
0x40
0x00
0x05
TOTAL NUMBER OF BYTES IN SPD DEVICE
FUNDAMENTAL MEMORY TYPE
NUMBER OF ROW ADDRESSES ON ASSEMBLY
NUMBER OF COLUMN ADDRESSES ON ASSEMBLY
DIMM HIGHT AND MODULE RANKS
MODULE DATA WIDTH
MODULE DATA WIDTH (continued)
MODULE VOLTAGE INTERFACE LEVELS (VDDQ
)
SDRAM CYCLE TIME, (tCK ) [max CL]
CAS LATENCY = 6 (6400), CL = 5 (5300)
9
0x25
0x40
0x30
0x45
SDRAM ACCESS FROM CLOCK, (tAC) [max CL]
CAS LATENCY = 6 (6400); CL = 5 (5300)
10
11
12
13
14
MODULE CONFIGURATION TYPE
REFRESH RATE / TYPE
0x00
0x82
0x08
0x00
SDRAM DEVICE WIDTH (PRIMARY SDRAM)
ERROR- CHECKING SDRAM DATA WIDTH
MINIMUM CLOCK DELAY, BACK-TO-BACK
RANDOM COLUMN ACCESS
15
0x00
16
17
18
19
20
21
BURST LENGTHS SUPPORTED
NUMBER OF BANKS ON SDRAM DEVICE
CAS LATENCIES SUPPORTED
MODULE THICKNESS
0x0C
0x08
0x70
0x38
0x01
0x02
0x00
DDR2 DIMM TYPE
SDRAM MODULE ATTRIBUTES
SDRAM DEVICE ATTRIBUTES: Weak Driver and 50
22
23
24
25
26
0x07
ODT
SDRAM CYCLE TIME, (tCK) [max CL – 1]
CAS LATENCY = 5 (6400), CL = 4 (5300)
0x30
0x45
0x3D
0x50
0x3D
0x50
0x50
0x60
SDRAM ACCESS FROM CK, (tAC) [max CL – 1]
CAS LATENCY = 5 (6400), CL = 4 (5300)
SDRAM CYCLE TIME, (tCK) [max CL – 2]
CAS LATENCY = 4 (6400), CL = 3 (5300)
SDRAM ACCESS FROM CK, (tAC) [max CL – 2]
CAS LATENCY = 4 (6400), CL = 3 (5300)
27
28
29
30
31
MINIMUM ROW PRECHARGE TIME, (tRP
MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD
MINIMUM RAS# TO CAS# DELAY, (tRCD
)
0x3C
0x1E
0x3C
0x2D
0x01
)
)
MINIMUM RAS# PULSE WIDTH, (tRAS
)
MODULE BANK DENSITY
Swissbit AG
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Page 12
of 16
preliminary Data Sheet
Rev.0.9
17.12.2012
SERIAL PRESENCE-DTECT MATRIX (continued)
BYTE
32
DESCRIPTION
6400-6-6-6
0x17
5300-5-5-5
0x20
ADDRESS AND COMMAND SETUP TIME, (tISb
)
33
ADDRESS AND COMMAND HOLD TIME, (tIHb
)
0x25
0x27
34
DATA / DATA MASK INPUT SETUP TIME, (tDSb
)
0x05
0x10
35
DATA / DATA MASK INPUT HOLD TIME, (tDHb
WRITE RECOVERY TIME, (tWR
WRITE to READ Command Delay, (tWTR
)
0x12
0x17
36
)
0x3C
0x1E
0x1E
0x00
0x06
0x3C
37
)
38
READ to PRECHARGE Command Delay, (tRTP
Mem Analysis Probe
)
39
40
Extension for Bytes 41 and 42
41
MIN ACTIVE AUTO REFRESH TIME, (tRC)
MINIMUM AUTO REFRESH TO ACTIVE /
AUTO REFRESH COMMAND PERIOD, (tRFC)
SDRAM DEVICE MAX CYCLE TIME, (tCKMAX)
42
0x7F
0x80
43
44
SDRAM DEVICE MAX DQS-DQ SKEW TIME, (tDQSQ
SDRAM DEVICE MAX READ DATA HOLD SKEW
)
0x14
0x1E
0x18
0x22
45
46
FACTOR, (tQHS
)
PLL Relock Time
0x00
0x00
0x12
47-61 Optional Features, not supported
62
63
SPD REVISION
CHECKSUM FOR BYTES 0-62
0xE1
0x17
64-66 MANUFACTURER`S JEDEC ID CODE
0x7F
0xDA
0x00
67
72
MANUFACTURER`S JEDEC ID CODE (continued)
MANUFACTURING LOCATION
73-90 MODULE PART NUMBER (ASCII)
“SEU02G64B4BF2SA-xx”
91
92
93
94
PCB IDENTIFICATION CODE
X
X
IDENTIFICATION CODE (continued)
YEAR OF MANUFACTURE IN BCD
WEEK OF MANUFACTURE IN BCD
X
X
95-98 MODULE SERIAL NUMBER
99-127 MANUFACTURER-SPECIFIC DATA (RSVD)
128-255 Open for customer use
X
X
0xff
Part Number Code
S
1
E
2
U
3
02G 64 B4
B
7
F
8
2
9
SA
10
-
25
11
*
12
R
13
4
5
6
*RoHs compl.
Swissbit AG
SDRAM DDR2
240 Pin Unbuffered 1.8V
Depth (2048MB)
DDR2-800MT/s
Chip Vendor (Samsung)
2 Module Ranks
Chip Rev. F
Width
PCB-Type (B62URCE with 30µ“ gold)
Chip organisation x8
* optional / additional information
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
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Page 13
of 16
preliminary Data Sheet
Rev.0.9
17.12.2012
Revision History
Revision
0.9
Changes
Date
17.12.2012
Initial Revision
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
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eMail: info@swissbit.com
Page 14
of 16
preliminary Data Sheet
Rev.0.9
17.12.2012
Locations
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Switzerland
Phone:
Fax:
+41 (0)71 913 03 03
+41 (0)71 913 03 15
_____________________________
Swissbit Germany GmbH
Wolfener Strasse 36
D – 12681 Berlin
Germany
Phone:
Fax:
+49 (0)30 93 69 54 – 0
+49 (0)30 93 69 54 – 55
_____________________________
Swissbit NA, Inc.
1117 E Plaza Drive Unit E Suites 105/205
Eagle, ID 83616
USA
Phone:
Fax:
+1 208 258-6254
+1 208 938-4525
_____________________________
Swissbit Japan, Inc.
3F Core Koenji,
2-1-24 Koenji-Kita, Suginami-Ku,
Tokyo 166-0002
Japan
Phone:
Fax:
+81 3 5356 3511
+81 3 5356 3512
________________________________
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 15
of 16
preliminary Data Sheet
Rev.0.9
17.12.2012
Declaration of Conformity
We
Manufacturer:
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
declare under our sole responsibility that the product
Product Type:
Brand Name:
Product Series:
Part Number:
2GB DDR2 UDIMM
SWISSMEMORY™
DDR2 UDIMM
SEU02G64B4BF2SA-xxxR
to which this declaration relates is in conformity with the following directives:
2002/96/EC Category 3 (WEEE)
following the provisions of Directive
Restriction of the use of certain hazardous substances
2011/65/EU
Swissbit AG, Dezember 2012
Manuela Kögel
Head of Quality Management
Swissbit AG
Industiestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 16
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