SSL4101 [ETC]
GreenChip III+ SMPS control IC; 的GreenChip III +开关电源控制IC
| 型号： | SSL4101 |
| 厂家： | 
ETC |
| 描述： | GreenChip III+ SMPS control IC |
| 文件： | 总29页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSL4101T
GreenChip III+ SMPS control IC
Rev. 1 — 21 April 2011
Product data sheet
1. General description
The GreenChip III+ is the third generation of green Switched Mode Power Supply (SMPS)
controller ICs. The SSL4101T combines a controller for Power Factor Correction (PFC)
and a flyback controller. Its high level of integration allows the design of a cost-effective
LED lighting application power supply with a very low number of external components.
The special built-in green functions provide high efficiency at all power levels. This applies
to quasi-resonant operation at high power levels, quasi-resonant operation with valley
skipping, as well as to reduced frequency operation at lower power levels. At low power
levels, the PFC switches off to maintain high efficiency.
During low power conditions, the flyback controller switches to frequency reduction mode
and limits the peak current to 25 % of its maximum value. This will ensure high efficiency
at low power and good standby power performance while minimizing audible noise from
the transformer.
The SSL4101T is a MultiChip Module, (MCM), containing two chips. The proprietary high
voltage BCD800 process which makes direct start-up possible from the rectified universal
mains voltage in an effective and green way. The second low voltage SiIlicon On Insulator
(SIO) is used for accurate, high speed protection functions and control.
The SSL4101T enables extremely efficient and reliable LED lighting application power
supplies with power requirements from 10 W to 300 W, to be designed easily and with a
minimum number of external components.
The new SSL4101T allows a typical 150 W LED lighting application power supply
(universal input, 48 V (DC) output, TEA1761T on the secondary side for Synchronous
Rectification) to achieve the following performances at full load:
• 120 V (AC): 92 % efficiency, 0.998 PF, 5.8 % THD, < 190 mW standby power
• 277 V (AC): 94 % efficiency, 0.978 PF, 9 % THD, < 350 mW standby power
1.1 Industry standard THD, low standby input power and high-efficiency
The SSL4101T enables LED lighting application power supplies to achieve the industry
standard of < 20 % THD for the input current at full load and all nominal input voltages:
100 V (AC), 120 V (AC), 230 V (AC), 240 V (AC) and 277 V (AC).
• Extremely low input power in Standby mode eliminates the need for an additional
housekeeping power supply to power the lighting controllers/dimmers.
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
• Using SSL4101T, a low power controller (< 50 mW) can be driven directly by the LED
lighting application power supply’s output while maintaining the input power in
Standby mode below the maximum of 0.5 W.
• Extremely high-efficiency can be achieved in LED lighting application power supplies
using the SSL4101T (between 92 % to 94 %). This enables the power supply to
operate reliably in enclosed spaces with very little cooling (which is typical for SSL
applications).
2. Features and benefits
2.1 Distinctive features
Integrated PFC and flyback controller.
True universal mains supply operation: 70 V (AC) to 305 V (AC).
High level of integration, resulting in a very low external component count and a
cost-effective design.
2.2 Green features
On-chip start-up current source.
2.3 PFC green features
Valley/zero voltage switching for minimum switching losses (NXP Semiconductors
patented).
Frequency limitation to reduce switching losses.
PFC is switched off when a low load is detected at the flyback output.
2.4 Flyback green features
Valley switching for minimum switching losses (NXP Semiconductors patented).
Frequency reduction with fixed minimum peak current at low power operation to
maintain high efficiency at low output power levels.
2.5 Protection features
Safe restart mode for system fault conditions.
Continuous mode protection by means of demagnetization detection for both
converters (NXP Semiconductors patented).
UnderVoltage Protection (UVP) (foldback during overload).
Accurate OverVoltage Protection (OVP) for both converters (adjustable for flyback
converter).
Open control loop protection for both converters. The open loop protection on the
flyback converter is safe restart.
IC OverTemperature Protection (OTP).
Low and adjustable OverCurrent Protection (OCP) trip level for both converters.
General purpose input for latched protection, e.g. to be used for system
OverTemperature Protection (OTP).
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
2 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
3. Applications
The device can be used in all LED lighting applications that require a very efficient, low
THD, high PF, true universal input voltage and cost-effective power supply solution
between 10 W and 300 W.
4. Ordering information
Table 1.
Ordering information
Type
number
Package
Name
Description
Version
SSL4101T
SO16
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
5. Block diagram
PFCDRIVER
12
FBDRIVER
13
PFC DRIVER
PFC GATE
FB DRIVER
FB GATE
80 μA
1.25 V
1.12 V
3.5 V
DRV
DRV
5
LATCH
EXT PROT
Freq
LOW
VIN
VINSENSE
PFCCOMP
7
6
PROT
R
S
R
S
PFC PROT
PROT
ENABLE PFC
MAX
3.7 V
Q
Q
2.5 V
3.5 V
ENABLE
FB
Red.
LOW
POWER
30 μA
LOW
POWER
1.25 V
PFC
OSC
FB
OSC
TIME
OUT
3
FBCTRL
2.50 V
VOSENSE
9
TON MAX
2.7 V
Freq. Red.
VCC GOOD
VoSTART FB
LOW POWER
EXT PROT
MIN
SMPS
OPP
FB
STARTFB
START STOP
PFC
OCP
CONTROL
LOW VIN
VoOVP
PFC
PROT
BLANK
EXT PROT
OTP
S
S
S
DRIVER
VoSTART FB
VoSHORT
LATCHED
PROTECTION
FBOVP
10
FBSENSE
LATCH RESET
R
PROT
OCP
TIMEOUT
TON MAX
VoSHORT
S
S
S
SAFE
60 μA
OPP
RESTART
ENABLE FB
START FB
PFC DRIVER
ENABLE PFC
BLANK
500 mV
60 μA
PFCSENSE 11
PROTECTION
V
R
UVLO
START
SOFT
PROT
VCC GOOD
CHARGE
SOFT START
START STOP PFC
EXT PROT
CHARGE
CONTROL
V
startup
th(UVLO)
V
OPP
VALLEY
DETECT
TIMER 4 μs
OVP
VALLEY
DETECT
COUNTER
OvpFB
INTERNAL
SUPPLY
PFCAUX
8
OTP
4
FBAUX
PFCGATE
ZCS
CHARGE
V
startup
FB GATE
ZCS
TIMER 50 μs
TEMP
OTP
V
th(UVLO)
80 mV
100 mV
2
16
HV
1
V
GND
CC
001aan671
Remark: The time-out is safe restart for the SSL4101T.
Fig 1. Block diagram
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
3 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
6. Pinning information
6.1 Pinning
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
HV
CC
GND
FBCTRL
FBAUX
HVS
HVS
FBDRIVER
PFCDRIVER
PFCSENSE
FBSENSE
VOSENSE
SSL4101T
LATCH
PFCCOMP
VINSENSE
PFCAUX
001aan672
Fig 2. Pin configuration: SSL4101T (SOT109-1)
6.2 Pin description
Table 2.
Pin description
Symbol
VCC
Pin
1
Description
supply voltage
ground
GND
2
FBCTRL
FBAUX
3
control input for flyback
4
input from auxiliary winding for demagnetization timing and
overvoltage protection for flyback
LATCH
5
general purpose protection input
PFCCOMP
VINSENSE
PFCAUX
VOSENSE
FBSENSE
PFCSENSE
PFCDRIVER
FBDRIVER
HVS
6
frequency compensation pin for PFC
sense input for mains voltage
7
8
input from auxiliary winding for demagnetization timing for PFC
sense input for PFC output voltage
9
10
11
12
13
14, 15
16
programmable current sense input for flyback
programmable current sense input for PFC
gate driver output for PFC
gate driver output for flyback
high voltage safety spacer, not connected
high voltage start-up and valley sensing of flyback part
HV
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
4 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
7. Functional description
7.1 General control
The SSL4101T contains a controller for a power factor correction circuit as well as a
controller for a flyback circuit. A typical configuration is shown in Figure 3.
12 11
8
9
16 13
10
6
SSL4101T
7
3
4
1
5
2
001aan673
Fig 3. Typical configuration
7.1.1 Start-up and UnderVoltage LockOut (UVLO)
Initially the capacitor on the VCC pin is charged from the high voltage mains via the HV pin.
As long as VCC is below Vtrip, the charge current is low. This protects the IC if the VCC pin
is shorted to ground. For a short start-up time the charge current above Vtrip is increased
until VCC reaches Vth(UVLO). If VCC is between Vth(UVLO) and Vstartup, the charge current is
low again, ensuring a low duty cycle during fault conditions.
The control logic activates the internal circuitry and switches off the HV charge current
when the voltage on pin VCC passes the Vstartup level. First, the LATCH pin current source
is activated and the soft start capacitors on the PFCSENSE and FBSENSE pins are
charged. When the LATCH pin voltage exceeds the Ven(LATCH) voltage and the soft start
capacitor on the PFCSENSE pin is charged, the PFC circuit is activated. Also the flyback
converter is activated (providing the soft start capacitor on the FBSENSE pin is charged).
The output voltage of the flyback converter is then regulated to its nominal output voltage.
The IC supply is taken over by the auxiliary winding of the flyback converter. See Figure 4.
If during start-up the LATCH pin does not reach the Ven(LATCH) level before VCC reaches
V
th(UVLO), the LATCH pin output is deactivated and the charge current is switched on
again.
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
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SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
As soon as the flyback converter is started, the voltage on the FBCTRL pin is monitored. If
the output voltage of the flyback converter does not reach its intended regulation level in a
predefined time, the voltage on the FBCTRL pin reaches the Vto(FBCTRL) level and an error
is assumed. The SSL4101T then initiates a safe restart.
When one of the protection functions is activated, both converters stop switching and the
VCC voltage drops to Vth(UVLO). A latched protection recharges the capacitor CVCC via the
HV pin, but does not restart the converters. For a safe restart protection, the capacitor is
recharged via the HV pin and the device restarts (see block diagram, Figure 1).
In the event of an overvoltage protection of the PFC circuit, VVOSENSE > Vovp(VOSENSE)
,
only the PFC controller stops switching until the VOSENSE pin voltage drops below
V
ovp(VOSENSE) again. Also, if a mains undervoltage is detected VVINSENSE < Vstop(VINSENSE)
,
only the PFC controller stops switching until VVINSENSE > Vstart(VINSENSE) again.
When the voltage on pin VCC drops below the undervoltage lockout level, both controllers
stop switching and reenter the safe restart mode. In the safe restart mode the driver
outputs are disabled and the VCC pin voltage is recharged via the HV pin.
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
6 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
I
HV
V
startup
V
V
th(UVLO)
trip
V
CC
V
start(VINSENSE)
EN(LATCH)
VINSENSE
V
LATCH
PROTECTION
soft start
PFCSENSE
PFCDRIVER
soft start
FBSENSE
FBDRIVER
FBCTRL
V
V
to(FBCTRL)
start(fb)
VOSENSE
V
O
charging VCC
capacitor
starting
converters
normal
operation
protection
restart
014aaa156
Fig 4. Start-up sequence, normal operation and restart sequence
7.1.2 Supply management
All internal reference voltages are derived from a temperature compensated and trimmed
on-chip band gap circuit. Internal reference currents are derived from a temperature
compensated and trimmed on-chip current reference circuit.
7.1.3 Latch input
Pin LATCH is a general purpose input pin, which can be used to switch off both
converters. The pin sources a current IO(LATCH) (80 μA typical). Switching off both
converters is stopped as soon as the voltage on this pin drops below 1.25 V.
At initial start-up the switching is inhibited until the capacitor on the LATCH pin is charged
above 1.35 V (typical). No internal filtering is done on this pin. An internal Zener clamp of
2.9 V (typical) protects this pin from excessive voltages.
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
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SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
7.1.4 Fast latch reset
In a typical application the mains can be interrupted briefly to reset the latched protection.
The PFC bus capacitor, Cbus, does not have to discharge for this latched protection to
reset.
Typically the PFC bus capacitor, Cbus, has to discharge for the VCC to drop to this reset
level. When the latched protection is set, the clamping circuit of the VINSENSE circuit is
disabled. (see also Section 7.2.8) As soon as the VINSENSE voltage drops below
750 mV (typical) and after that is raised to 870 mV (typical), the latched protection is reset.
The latched protection is also reset by removing both the voltage on pin VCC and on
pin HV.
7.1.5 Overtemperature protection
An accurate internal temperature protection is provided in the circuit. When the junction
temperature exceeds the thermal shutdown temperature, the IC stops switching. As long
as OTP is active, the capacitor CVCC is not recharged from the HV mains. The OTP circuit
is supplied from the HV pin if the VCC supply voltage is not sufficient.
OTP is a latched protection. It can be reset by removing both the voltage on pin VCC and
on pin HV or by the fast latch reset function. (See Section 7.1.4)
7.2 Power factor correction circuit
The power factor correction circuit operates in quasi-resonant or discontinuous
conduction mode with valley switching. The next primary stroke is only started when the
previous secondary stroke has ended and the voltage across the PFC MOSFET has
reached a minimum value. The voltage on the PFCAUX pin is used to detect transformer
demagnetization and the minimum voltage across the external PFC MOSFET switch.
7.2.1 ton control
The power factor correction circuit is operated in ton control. The resulting mains harmonic
reduction of a typical application is well within the class-D requirements.
7.2.2 Valley switching and demagnetization (PFCAUX pin)
The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry
connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the
voltage across the PFC MOSFET. The next stroke is started when the voltage across the
PFC MOSFET is at its minimum in order to reduce switching losses and ElectroMagnetic
Interference (EMI) (valley switching).
If no demagnetization signal is detected on the PFCAUX pin, the controller generates a
zero current signal (ZCS), 50 μs (typical) after the last PFCGATE signal.
If no valley signal is detected on the PFCAUX pin, the controller generates a valley signal
4 μs (typical) after demagnetization was detected.
To protect the internal circuitry during lightning events, for example, it is advisable to add a
5 kΩ series resistor to this pin. To prevent incorrect switching due to external disturbance,
the resistor should be placed close to the IC on the printed-circuit board.
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
8 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
7.2.3 Frequency limitation
To optimize the transformer and minimize switching losses, the switching frequency is
limited to fsw(PFC)max. If the frequency for quasi-resonant operation is above the fsw(PFC)max
limit, the system switches over to discontinuous conduction mode. Also here, the PFC
MOSFET is only switched on at a minimum voltage across the switch (valley switching).
7.2.4 Mains voltage compensation (VINSENSE pin)
The mathematical equation for the transfer function of a power factor corrector contains
the square of the mains input voltage. In a typical application this results in a low
bandwidth for low mains input voltages, while at high mains input voltages the Mains
Harmonic Reduction (MHR) requirements may be hard to meet.
To compensate for the mains input voltage influence, the SSL4101T contains a correction
circuit. Via the VINSENSE pin the average input voltage is measured and the information
is fed to an internal compensation circuit. With this compensation it is possible to keep the
regulation loop bandwidth constant over the full mains input range, yielding a fast transient
response on load steps, while still complying with class-D MHR requirements.
In a typical application, the bandwidth of the regulation loop is set by a resistor and two
capacitors on the PFCCOMP pin.
7.2.5 Soft start-up (pin PFCSENSE)
To prevent audible transformer noise at start-up or during hiccup, the transformer peak
current, IDM, is increased slowly by the soft start function. This can be achieved by
inserting RSS1 and CSS1 between pin PFCSENSE and current sense resistor RSENSE1
An internal current source charges the capacitor to VPFCSENSE = Istart(soft)PFC × RSS1. The
voltage is limited to Vstart(soft)PFC
.
.
The start level and the time constant of the increasing primary current level can be
adjusted externally by changing the values of RSS1 and CSS1
.
τsoftstart = 3 × R
× C
SS1
SS1
The charging current Istart(soft)PFC flows as long as the voltage on pin PFCSENSE is
below 0.5 V (typ). If the voltage on pin PFCSENSE exceeds 0.5 V, the soft start current
source starts limiting current Istart(soft)PFC. As soon as the PFC starts switching, the
Istart(soft)PFC current source is switched off; see Figure 5.
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
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SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
I
≤ 60 μA
S1
startup(soft)PFC
SOFT START
CONTROL
R
C
SS1
SS1
11
OCP
PFCSENSE
0.5 V
R
SENSE1
014aaa157
Fig 5. Soft start-up of PFC
7.2.6 Low power mode
When the output power of the flyback converter (see Section 7.3) is low, the flyback
converter switches over to frequency reduction mode. When frequency reduction mode is
entered by the flyback controller, the power factor correction circuit is switched off to
maintain high efficiency.
During low power mode operation the PFCCOMP pin is clamped to a minimal voltage of
2.7 V (typical) and a maximum voltage of 3.9 V (typical). The lower clamp voltage limits
the maximum power that is delivered when the PFC is switched on again. The upper
clamp voltage ensures that the PFC can return to its normal regulation point in a limited
amount of time when returning from low power mode.
As soon as the flyback converter leaves the frequency reduction mode, the power factor
correction circuit restores normal operation. To prevent continuous switching on and off of
the PFC circuit, a small hysteresis is build in, (60 mV (typical) on the FBCTRL pin).
7.2.7 Overcurrent protection (PFCSENSE pin)
The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor, RSENSE1, on the source of the external MOSFET. The voltage is
measured via the PFCSENSE pin.
7.2.8 Mains undervoltage lockout/brownout protection (VINSENSE pin)
To prevent the PFC from operating at very low mains input voltages, the voltage on the
VINSENSE pin is sensed continuously. As soon as the voltage on this pin drops below the
V
stop(VINSENSE) level, switching of the PFC is stopped.
The voltage on pin VINSENSE is clamped to a minimum value,
Vstart(VINSENSE) + ΔVpu(VINSENSE), for a fast restart as soon as the mains input voltage is
restored after a mains dropout.
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
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SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
7.2.9 Overvoltage protection (VOSENSE pin)
To prevent output overvoltage during load steps and mains transients, an overvoltage
protection circuit is built in.
As soon as the voltage on the VOSENSE pin exceeds the Vovp(VOSENSE) level, switching
of the power factor correction circuit is inhibited. Switching of the PFC recommences as
soon as the VOSENSE pin voltage drops below the Vovp(VOSENSE) level again.
When the resistor between pin VOSENSE and ground is open, the overvoltage protection
is also triggered.
7.2.10 PFC open loop protection (VOSENSE pin)
The power factor correction circuit does not start switching until the voltage on the
VOSENSE pin is above the Vth(ol)(VOSENSE) level. This protects the circuit from open loop
and VOSENSE short situations.
7.2.11 Driver (PFCDRIVER pin)
The driver circuit to the gate of the power MOSFET has a current sourcing capability of
typically −500 mA and a current sink capability of typically 1.2 A. This permits fast turn-on
and turn-off of the power MOSFET for efficient operation.
7.3 Flyback controller
The SSL4101T includes a controller for a flyback converter. The flyback converter
operates in quasi-resonant or discontinuous conduction mode with valley switching. The
auxiliary winding of the flyback transformer provides demagnetization detection and
powers the IC after start-up.
7.3.1 Multimode operation
The SSL4101T flyback controller can operate in several modes; see Figure 6.
PFC off
PFC on
f
sw(fb)max
frequency
reduction
switching frequency
discontinuous
with valley
switching
quasi resonant
output power
014aaa158
Fig 6. Multimode operation flyback
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
11 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
At high output power the converter switches to quasi-resonant mode. The next converter
stroke is started after demagnetization of the transformer current. In quasi-resonant mode
switching losses are minimized as the converter only switches on when the voltage across
the external MOSFET is at its minimum (valley switching, see also Section 7.3.2).
To prevent high frequency operation at lower loads, the quasi-resonant operation changes
to discontinuous mode operation with valley skipping in which the switching frequency is
limited for EMI to fsw(fb)max (125 kHz typical). Again, the external MOSFET is only switched
on when the voltage across the MOSFET is at its minimum.
At very low power and standby levels the frequency is controlled down by a Voltage
Controlled Oscillator (VCO). The minimum frequency can be reduced to zero. During
frequency reduction mode, the primary peak current is kept at a minimal level of Ipkmax / 4
to maintain a high efficiency. (Ipkmax is the maximum primary peak current set by the sense
resistor and the maximum sense voltage.) As the primary peak current is low in frequency
reduction operation (Ipk = Ipkmax / 4), no audible noise is noticeable at switching
frequencies in the audible range. Valley switching is also active in this mode.
In frequency reduction mode the PFC controller is switched off and the flyback maximum
frequency changes linearly with the control voltage on the FBCTRL pin (see Figure 7 ).
For stable on and off switching of the PFC, the FBCTRL pin has a 50 mV (typical)
hysteresis. At no load operation the switching frequency can be reduced to (almost) zero.
PFC off
PFC on
f
sw(fb)max
frequency
reduction
switching frequency
discontinuous
with valley
switching
quasi resonant
1.5 V
V
FBCTRL
014aaa159
Fig 7. Frequency control of flyback part
7.3.2 Valley switching (HV pin)
Refer to Figure 8. A new cycle starts when the external MOSFET is activated. After the
on-time (determined by the FBSENSE voltage and the FBCTRL voltage), the MOSFET is
switched off and the secondary stroke starts. After the secondary stroke, the drain voltage
shows an oscillation with a frequency of approximately:
1
---------------------------------------------------
(1)
(2 × π × (L × C ))
p
d
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
12 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
Where Lp is the primary self-inductance of the flyback transformer and Cd is the
capacitance on the drain node.
As soon as the internal oscillator voltage is high again and the secondary stroke has
ended, the circuit waits for the lowest drain voltage before starting a new primary stroke.
Figure 8 shows the drain voltage, valley signal, secondary stroke signal and the internal
oscillator signal.
Valley switching allows high frequency operation as capacitive switching losses are
reduced, see Equation 2. High frequency operation makes small and cost-effective
magnetics possible.
1
2
2
⎛
⎝
⎞
--
P = × C × V × f
(2)
d
⎠
primary
stroke
secondary
stroke
secondary
ringing
drain
valley
secondary
stroke
(2)
(1)
oscillator
014aaa027
(1) Start of new cycle at lowest drain voltage.
(2) Start of new cycle in a classical Pulse Width Modulation (PWM) system without valley detection.
Fig 8. Signals for valley switching
7.3.3 Current mode control (FBSENSE pin)
Current mode control is used for the flyback converter for its good line regulation.
The primary current is sensed by the FBSENSE pin across an external resistor and
compared with an internal control voltage. The internal control voltage is proportional to
the FBCTRL pin voltage, see Figure 9.
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
13 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
V
sense(fb)max
(V)
PFC off
PFC on
0.52 V
flyback
frequency
reduction
flyback
discontinuous
or QR
FBSENSE peak voltage
flyback
cycle skip
mode
0.13 V
1.4 V 1.5 V 2.0 V
V
(V)
FBCTRL
014aaa160
Fig 9. Peak current control of flyback part
The driver output is latched in the logic, preventing multiple switch-on.
7.3.4 Demagnetization (FBAUX pin)
The system is always in quasi-resonant or discontinuous conduction mode. The internal
oscillator does not start a new primary stroke until the previous secondary stroke has
ended.
Demagnetization features a cycle-by-cycle output short circuit protection by immediately
lowering the frequency (longer off-time), thereby reducing the power level.
Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time (2 μs typical).
This suppression may be necessary at low output voltages and at start-up and in
applications where the transformer has a large leakage inductance.
If pin FBAUX is open circuit or not connected, a fault condition is assumed and the
converter stops operating immediately. Operation restarts as soon as the fault condition is
removed.
7.3.5 Flyback control/time-out (FBCTRL pin)
The pin FBCTRL is connected to an internal voltage source of 3.5 V via an internal
resistor (typical resistance is 3 kΩ). As soon as the voltage on this pin is above
2.5 V (typical), this connection is disabled. Above 2.5 V the pin is biased with a small
current. When the voltage on this pin rises above 4.5 V (typical), a fault is assumed and
switching is inhibited. In the SSL4101T, a restart will then be made.
When a small capacitor is connected to this pin, a time-out function can be created to
protect against an open control loop situation. (see Figure 10 and Figure 11) The time-out
function can be disabled by connecting a resistor (100 kΩ) to ground on the FBCTRL pin.
If the pin is shorted to ground, switching of the flyback controller is inhibited.
In normal operating conditions, when the converter is regulating the output voltage, the
voltage on the FBCTRL pin is between 1.4 V and 2.0 V (typical values) from minimum to
maximum output power.
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2.5 V
3.5 V
30 μA
4.5 V
3 kΩ
FBCTRL
time-out
014aaa049
Fig 10. Time-out protection circuit
4.5 V
2.5 V
V
FBCTRL
output
voltage
intended output
voltage not
reached within
time-out time.
restart
intended output voltage
reached within time-out
time.
014aaa050
Fig 11. Time-out protection (signals), safe restart in the SSL4101T
7.3.6 Soft start-up (FBSENSE pin)
To prevent audible transformer noise during start-up, the transformer peak current, IDM is
slowly increased by the soft start function. This can be achieved by inserting a resistor and
a capacitor between pin 10, FBSENSE, and the current sense resistor.
An internal current source charges the capacitor to V = Istart(soft)fb × RSS2, with a maximum
of approximately 0.5 V.
The start level and the time constant of the increasing primary current level can be
adjusted externally by changing the values of RSS2 and CSS2
.
τsoftstart = 3 × R × C
SS2
SS2
The soft start current Istart(soft)fb is switched on as soon as VCC reaches Vstartup. When the
voltage on pin FBSENSE has reached 0.5 V, the flyback converter starts switching.
The charging current Istart(soft)(PFC) flows as long as the voltage on pin FBSENSE is below
approximately 0.5 V. If the voltage on pin FBSENSE exceeds 0.5 V, the soft start current
source starts limiting the current. After the flyback converter has started, the soft start
current source is switched off.
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S2
I
start(soft)fb ≤ 60 μA
SOFT START
CONTROL
R
C
SS2
SS2
10
OCP
FBSENSE
+
0.5 V
R
SENSE2
014aaa020
Fig 12. Soft start-up of flyback
7.3.7 Maximum on-time
The flyback controller limits the ‘on-time’ of the external MOSFET to 40 μs (typical). When
the ‘on-time’ is longer than 40 μs, the IC stops switching and enters the safe restart mode.
7.3.8 Overvoltage protection (FBAUX pin)
An output overvoltage protection is implemented in the GreenChip III+ series. This works
for the SSL4101T by sensing the auxiliary voltage via the current flowing into pin FBAUX
during the secondary stroke. The auxiliary winding voltage is a well-defined replica of the
output voltage. Voltage spikes are averaged by an internal filter.
If the output voltage exceeds the OVP trip level, an internal counter starts counting
subsequent OVP events. The counter has been added to prevent incorrect OVP detection
which might occur during ESD or lightning events. If the output voltage exceeds the OVP
trip level a few times and not again in a subsequent cycle, the internal counter counts
down at twice the speed it uses when counting up.
However, when typically eight cycles of subsequent OVP events are detected, the IC
assumes a true OVP and the OVP circuit switches the power MOSFET off. As the
protection is latched, the converter only restarts after the internal latch is reset. In a typical
application the mains should be interrupted to reset the internal latch.
The output voltage Vo(OVP) at which the OVP function trips, can be set by the
demagnetization resistor, RFBAUX
:
N
s
-----------
V
=
(I
× R
+ V
)
clamp(FBAUX)
O(ovp)
ovp(FBAUX)
FBAUX
N
aux
where Ns is the number of secondary turns and Naux is the number of auxiliary turns of the
transformer. Current Iovp(FBAUX) is internally trimmed.
The value of RFBAUX can be adjusted to the turns ratio of the transformer, thus making an
accurate OVP detection possible.
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7.3.9 Overcurrent protection (FBSENSE pin)
The primary peak current in the transformer is measured accurately cycle-by-cycle using
the external sense resistor Rsense2. The OCP circuit limits the voltage on pin FBSENSE to
an internal level (see also Section 7.3.3). The OCP detection is suppressed during the
leading edge blanking period, tleb, to prevent false triggering caused by switch-on spikes.
t
leb
OCP level
V
FBSENSE
t
014aaa022
Fig 13. OCP leading edge blanking
7.3.10 Overpower protection
During the primary stroke of the flyback converter the input voltage of the flyback
converter is measured by sensing the current that is drawn from the pin FBAUX.
The current information is used to adjust the peak drain current of the flyback converter,
which is measured via pin FBSENSE. The internal compensation is such that an almost
input voltage independent maximum output power can be realized.
The OPP curve is given in Figure 14.
014aaa096
0.6
V
FBSENSE
(V)
0.52
0.5
0.4
0.37
0.3
−400
−300
−200
−100
0
(μA)
−360
I
FBAUX
Fig 14. Overpower protection curve
7.3.11 Driver (FBDRIVER pin)
The driver circuit to the gate of the external power MOSFET has a current sourcing
capability of typically −500 mA and a current sink capability of typically 1.2 A. This permits
fast turn-on and turn-off of the power MOSFET for efficient operation.
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8. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Voltages
VCC
Parameter
Conditions
Min
Max
Unit
supply voltage
−0.4
−0.4
−0.4
−0.4
−0.4
−0.4
−25
+38
+5
V
V
V
V
V
V
V
V
V
V
VLATCH
VFBCTRL
voltage on pin LATCH
voltage on pin FBCTRL
current limited
+5
VPFCCOMP voltage on pin PFCCOMP
VVINSENSE voltage on pin VINSENSE
VVOSENSE voltage on pin VOSENSE
+5
+5
+5
VPFCAUX
voltage on pin PFCAUX
voltage on pin FBSENSE
+25
+5
VFBSENSE
current limited
current limited
−0.4
−0.4
−0.4
VPFCSENSE voltage on pin PFCSENSE
+5
VHV
voltage on pin HV
+650
Currents
IFBCTRL
IFBAUX
current on pin FBCTRL
current on pin FBAUX
−3
0
mA
mA
mA
mA
A
−1
+1
+10
+10
+2
+2
5
IPFCSENSE current on pin PFCSENSE
−1
IFBSENSE
IFBDRIVER
current on pin FBSENSE
current on pin FBDRIVER
−1
duty cycle < 10 %
duty cycle < 10 %
−0.8
−0.8
-
IPFCDRIVER current on pin PFCDRIVER
A
IHV
current on pin HV
mA
General
Ptot
total power dissipation
storage temperature
junction temperature
Tamb < 75 °C
-
0.6
W
Tstg
−55
−40
+150 °C
+150 °C
Tj
ESD
VESD
electrostatic discharge voltage class 1
human body model
[1]
[1]
[2]
pins 1 to 13
-
-
-
-
2000
1500
200
V
V
V
V
pin 16 (HV)
machine model
charged device model
500
[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
[2] Equivalent to discharging a 200 pF capacitor through a 0.75 μH coil and a 10 Ω resistor.
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9. Thermal characteristics
Table 4.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
Unit
thermal resistance from junction to ambient in free air; JEDEC test board
124
K/W
10. Characteristics
Table 5.
amb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Characteristics
T
Symbol Parameter
Start-up current source (pin HV)
Conditions
Min
Typ
Max
Unit
IHV
current on pin HV
VHV > 80 V
VCC < Vtrip
;
-
1.0
-
mA
Vth(UVLO) < VCC < Vstartup
Vtrip < VCC < Vth(UVLO)
with auxiliary supply
-
5.4
20
-
-
mA
μA
V
8
40
-
VBR
breakdown voltage
650
Supply voltage management (pin VCC
)
Vtrip
trip voltage
0.55
21
0.65
22
0.75
23
V
V
V
Vstartup
Vth(UVLO)
start-up voltage
undervoltage lockout threshold
voltage
14
15
16
Vstart(hys)
Vhys
hysteresis of start voltage
hysteresis voltage
during start-up phase
-
300
7
-
mV
V
Vstartup − Vth(UVLO)
6.3
−1.2
7.7
−0.8
Ich(low)
low charging current
VHV > 80 V; VCC < Vtrip or
Vth(UVLO) < VCC < Vstartup
−1.0
mA
Ich(high)
high charging current
VHV > 80 V; Vtrip < VCC < Vth(UVLO)
−4.6
−5.4
−6.3
mA
mA
ICC(oper)
operating supply current
no load on pin FBDRIVER and
PFCDRIVER
2.25
3
3.75
Input voltage sensing PFC (pin VINSENSE)
Vstop(VINSENSE)
Vstart(VINSENSE)
ΔVpu(VINSENSE)
stop voltage on pin VINSENSE
start voltage on pin VINSENSE
0.86
1.11
-
0.89
1.15
−100
0.92
1.19
-
V
V
pull-up voltage difference on
pin VINSENSE
active after Vstop(VINSENSE) is
detected
mV
Ipu(VINSENSE)
pull-up current on pin
VINSENSE
active after Vstop(VINSENSE) is
detected
−55
−47
−40
μA
Vmvc(VINSENSE)max maximum mains voltage
compensation voltage on pin
VINSENSE
4.0
-
-
V
Vflr
fast latch reset voltage
active after Vth(UVLO) is detected
-
-
0.75
0.12
-
-
V
V
Vflr(hys)
hysteresis of fast latch reset
voltage
II(VINSENSE)
input current on pin VINSENSE VVINSENSE > Vstop(VINSENSE) after
Vstart(VINSENSE) is detected
5
33
100
nA
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Table 5.
Characteristics …continued
Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Loop compensation PFC (pin PFCCOMP)
gm
transconductance
VVOSENSE to IO(PFCCOMP)
VVOSENSE = 3.3 V
60
80
100
45
μA/V
μA
μA
V
IO(PFCCOMP)
output current on pin
PFCCOMP
33
39
VVOSENSE = 2.0 V
−45
2.5
−39
2.7
−33
2.9
[1]
[1]
Vclamp(PFCCOMP)
clamp voltage on pin
PFCCOMP
Low power mode; PFC off; lower
clamp voltage
Upper clamp voltage
-
3.9
3.5
-
V
V
Vton(PFCCOMP)zero zero on-time voltage on pin
PFCCOMP
3.4
3.6
Vton(PFCCOMP)max maximum on-time voltage on
pin PFCCOMP
1.20
1.25
1.30
V
Pulse width modulator PFC
ton(PFC)
PFC on-time
VVINSENSE = 3.3 V;
VPFCCOMP = Vton(PFCCOMP)max
3.6
30
4.5
40
5
μs
μs
VVINSENSE = 1 V;
53
VPFCCOMP = Vton(PFCCOMP)max
Output voltage sensing PFC (pin VOSENSE)
Vth(ol)(VOSENSE)
Vreg(VOSENSE)
Vovp(VOSENSE)
Iprot(VOSENSE)
open-loop threshold voltage on
pin VOSENSE
-
0.4
-
V
regulation voltage on pin
VOSENSE
for IO(PFCCOMP) = 0 A
2.475 2.500 2.525
V
overvoltage protection voltage
on pin VOSENSE
2.60
-
2.63
2.67
-
V
protection current on pin
VOSENSE
−30
nA
Overcurrent protection PFC (pin PFCSENSE)
Vsense(PFC)max
maximum PFC sense voltage ΔV/Δt = 50 mV/μs
0.49
0.52
250
0.52
0.55
310
0.55
0.57
370
V
ΔV/Δt = 200 mV/μs
V
tleb(PFC)
PFC leading edge blanking
time
ns
Iprot(PFCSENSE)
protection current on pin
PFCSENSE
−50
-
−5
nA
Soft start PFC (pin PFCSENSE)
Istart(soft)PFC
PFC soft start current
−75
0.46
12
−60
0.50
-
−45
0.54
-
μA
V
Vstart(soft)PFC
Rstart(soft)PFC
Oscillator PFC
fsw(PFC)max
PFC soft start voltage
enabling voltage
PFC soft start resistance
kΩ
maximum PFC switching
frequency
300
0.8
380
1.1
460
1.4
kHz
toff(PFC)min
minimum PFC off-time
μs
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Table 5.
Characteristics …continued
Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Valley switching PFC (pin PFCAUX)
(ΔV/Δt)vrec(PFC)
PFC valley recognition voltage
change with time
-
-
1.7
V/μs
[2]
[3]
tvrec(PFC)
PFC valley recognition time
VPFCAUX = 1 V peak-to-peak
-
-
300
50
6
ns
ns
μs
demagnetization to ΔV/Δt = 0
-
-
tto(vrec)PFC
PFC valley recognition time-out
time
3
4
Demagnetization management PFC (pin PFCAUX)
Vth(comp)PFCAUX
tto(demag)PFC
Iprot(PFCAUX)
comparator threshold voltage
on pin PFCAUX
−150 −100 −50
mV
μs
PFC demagnetization time-out
time
40
50
-
60
protection current on pin
PFCAUX
VPFCAUX = 50 mV
−75
−5
nA
Driver (pin PFCDRIVER)
Isrc(PFCDRIVER) source current on pin
VPFCDRIVER = 2 V
-
−0.5
-
A
PFCDRIVER
Isink(PFCDRIVER)
sink current on pin
PFCDRIVER
VPFCDRIVER = 2 V
VPFCDRIVER = 10 V
-
-
-
0.7
1.2
11
-
A
A
V
-
VO(PFCDRIVER)max maximum output voltage on pin
PFCDRIVER
12
Overvoltage protection flyback (pin FBAUX)
Iovp(FBAUX)
overvoltage protection current
on pin FBAUX
279
6
300
8
321
12
μA
Ncy(ovp)
number of overvoltage
protection cycles
Demagnetization management flyback (pin FBAUX)
Vth(comp)FBAUX
comparator threshold voltage
on pin FBAUX
60
80
-
110
mV
nA
Iprot(FBAUX)
protection current on pin
FBAUX
VFBAUX = 50 mV
−50
−5
Vclamp(FBAUX)
clamp voltage on pin FBAUX
IFBAUX = −500 μA
IFBAUX = 500 μA
−1.0
0.5
−0.8
0.7
2
−0.6
0.9
V
V
tsup(xfmr_ring)
transformer ringing
suppression time
1.5
2.5
μs
Pulse width modulator flyback
ton(fb)min minimum flyback on-time
ton(fb)max maximum flyback on-time
-
tleb
40
-
ns
32
48
μs
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Table 5.
Characteristics …continued
Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Oscillator flyback
fsw(fb)max
maximum flyback switching
frequency
100
125
1.5
60
150
kHz
V
Vstart(VCO)FBCTRL
Vhys(FBCTRL)
VCO start voltage on pin
FBCTRL
1.3
1.7
[4]
hysteresis voltage on pin
FBCTRL
-
-
-
-
mV
V
ΔVVCO(FBCTRL)
VCO voltage difference on pin
FBCTRL
-0.1
Peak current control flyback (pin FBCTRL)
VFBCTRL
voltage on pin FBCTRL
for maximum flyback peak current
enable voltage
1.85
2.0
2.5
4.5
3
2.15
V
Vto(FBCTRL)
time-out voltage on pin
FBCTRL
-
-
V
trip voltage
4.2
-
4.8
-
V
Rint(FBCTRL)
IO(FBCTRL)
internal resistance on pin
FBCTRL
kΩ
output current on pin FBCTRL VFBCTRL = 0 V
VFBCTRL = 2 V
−1.4
−0.6
−36
−1.19 −0.93 mA
−0.5
−30
−0.4
−24
mA
Ito(FBCTRL)
time-out current on pin
FBCTRL
VFBCTRL = 2.6 V
VFBCTRL = 4.1 V
μA
−34.5 −28.5 −22.5 μA
Valley switching flyback (pin HV)
(ΔV/Δt)vrec(fb)
flyback valley recognition
voltage change with time
−75
-
+75
-
V/μs
[5]
td(vrec-swon)
valley recognition to switch-on
delay time
-
150
ns
Soft start flyback (pin FBSENSE)
Istart(soft)fb
Vstart(soft)fb
Rstart(soft)fb
flyback soft start current
−75
0.43
12
−60
0.49
-
−45
0.54
-
μA
V
flyback soft start voltage
enable voltage
flyback soft start resistance
kΩ
Overcurrent protection flyback (pin FBSENSE)
Vsense(fb)max
maximum flyback sense
voltage
ΔV/Δt = 50 mV/μs
ΔV/Δt = 200 mV/μs
0.49
0.52
255
0.52
0.55
305
0.55
0.58
355
V
V
tleb(fb)
flyback leading edge blanking
time
ns
Istart(OPP)FBAUX
Iopp(red)(FBAUX)
OPP start current on pin
FBAUX
-
-
−100
−360
-
-
μA
μA
reduced overpower protection Vsense(fb)max has reduced to
current on pin FBAUX
0.37 V
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GreenChip III+ SMPS control IC
Table 5.
Characteristics …continued
Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol
Driver (pin FBDRIVER)
Isrc(FBDRIVER) source current on pin
FBDRIVER
Parameter
Conditions
Min
Typ
Max
Unit
VFBDRIVER = 2 V
-
−0.5
-
A
Isink(FBDRIVER)
sink current on pin FBDRIVER VFBDRIVER = 2 V
VFBDRIVER = 10 V
-
-
-
0.7
1.2
11
-
A
A
V
-
VO(FBDRIVER)(max) maximum output voltage on pin
FBDRIVER
12
LATCH input (pin LATCH)
Vprot(LATCH)
protection voltage on pin
LATCH
1.23
1.25
1.27
V
IO(LATCH)
output current on pin LATCH
enable voltage on pin LATCH
Vprot(LATCH) < VLATCH < Voc(LATCH)
at start-up
−85
1.30
80
−80
1.35
100
−75
1.40
140
μA
V
Ven(LATCH)
Vhys(LATCH)
hysteresis voltage on pin
LATCH
Ven(LATCH) − Vprot(LATCH)
mV
Voc(LATCH)
open-circuit voltage on pin
LATCH
2.65
2.9
3.15
V
Temperature protection
Tpl(IC)
IC protection level temperature
130
-
140
10
150
-
°C
°C
Tpl(IC)hys
hysteresis of IC protection level
temperature
[1] For a typical application with a compensation network on pin PFCCOMP, such as the example shown in Figure 3.
[2] Minimum required voltage change time for valley recognition on pin PFCAUX.
[3] Minimum time required between demagnetization detection and ΔV/Δt = 0 on pin PFCAUX.
[4] Hysteresis for PFC on/off control.
[5] Guaranteed by design.
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11. Application information
A power supply with the SSL4101T consists of a power factor correction circuit followed
by a flyback converter. See Figure 14.
Capacitor CVCC buffers the IC supply voltage, which is powered via the high voltage
rectified mains during start-up and via the auxiliary winding of the flyback converter during
operation. Sense resistors RSENSE1 and RSENSE2 convert the current through the
MOSFETs S1 and S2 into a voltage at pins PFCSENSE and FBSENSE. The values of
R
SENSE1 and RSENSE2 define the maximum primary peak current in MOSFETs S1 and S2.
In the example given, the LATCH pin is connected to a Negative Temperature Coefficient
(NTC) resistor. When the resistance drops below Equation 3 (typ), the protection is
activated.
Vprot(LATCH)
IO(LATCH)
= 15.6 kΩ
(3)
-------------------------------
A capacitor CTIMEOUT is connected to the FBCTRL pin. For a 120 nF capacitor, typically
after 10 ms the time-out protection is activated. RLOOP is added so that the time-out
capacitor does not interfere with the normal regulation loop.
R
S1 and RS2 are added to prevent the soft start capacitors from being charged during
normal operation due to negative voltage spikes across the sense resistors.
Resistor RAUX1 is added to protect the IC from damage during lightning events.
D1
C
bus
S1
C
R
SS1
SS1
D2
T2
C
OUT
R
SENSE1
R
AUX1
R
S2
S1
12
11
9
16 13
10
R
R
SS2
S2
8
COMPENSATION
6
C
SS2
SSL4101T
R
R
AUX2
SENSE2
7
4
1
5
C
3
VCC
2
R
LOOP
C
TIMEOUT
014aaa302
Fig 15. Typical application diagram SSL4101T
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
24 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 16. Package outline SOT109-1 (SO16)
SSL4101T
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Product data sheet
Rev. 1 — 21 April 2011
25 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
13. Revision history
Table 6.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SSL4101T v.1
20110421
Product data sheet
-
-
SSL4101T
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Product data sheet
Rev. 1 — 21 April 2011
26 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
14.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
14.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
27 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
14.4 Trademarks
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
GreenChip — is a trademark of NXP B.V.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
SSL4101T
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 April 2011
28 of 29
SSL4101T
NXP Semiconductors
GreenChip III+ SMPS control IC
16. Contents
1
1.1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Industry standard THD, low standby input
power and high-efficiency. . . . . . . . . . . . . . . . . 1
7.3.3
7.3.4
7.3.5
7.3.6
Current mode control
(FBSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . 13
Demagnetization
(FBAUX pin). . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flyback control/time-out
(FBCTRL pin). . . . . . . . . . . . . . . . . . . . . . . . . 14
Soft start-up
(FBSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . 15
Maximum on-time . . . . . . . . . . . . . . . . . . . . . 16
Overvoltage protection
(FBAUX pin). . . . . . . . . . . . . . . . . . . . . . . . . . 16
Overcurrent protection
(FBSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . 17
Overpower protection. . . . . . . . . . . . . . . . . . . 17
Driver
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Distinctive features . . . . . . . . . . . . . . . . . . . . . . 2
Green features . . . . . . . . . . . . . . . . . . . . . . . . . 2
PFC green features . . . . . . . . . . . . . . . . . . . . . 2
Flyback green features. . . . . . . . . . . . . . . . . . . 2
Protection features . . . . . . . . . . . . . . . . . . . . . . 2
2.1
2.2
2.3
2.4
2.5
7.3.7
7.3.8
3
4
5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7.3.9
7.3.10
7.3.11
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
(FBDRIVER pin). . . . . . . . . . . . . . . . . . . . . . . 17
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal characteristics . . . . . . . . . . . . . . . . . 19
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 19
Application information . . . . . . . . . . . . . . . . . 24
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . 26
7
7.1
7.1.1
Functional description . . . . . . . . . . . . . . . . . . . 5
General control. . . . . . . . . . . . . . . . . . . . . . . . . 5
Start-up and UnderVoltage LockOut
9
10
11
12
13
(UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Supply management. . . . . . . . . . . . . . . . . . . . . 7
Latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Fast latch reset. . . . . . . . . . . . . . . . . . . . . . . . . 8
Overtemperature protection . . . . . . . . . . . . . . . 8
Power factor correction circuit . . . . . . . . . . . . . 8
ton control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Valley switching and demagnetization
(PFCAUX pin). . . . . . . . . . . . . . . . . . . . . . . . . . 8
Frequency limitation . . . . . . . . . . . . . . . . . . . . . 9
Mains voltage compensation
(VINSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . . 9
Soft start-up
7.1.2
7.1.3
7.1.4
7.1.5
7.2
14
Legal information . . . . . . . . . . . . . . . . . . . . . . 27
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 28
14.1
14.2
14.3
14.4
7.2.1
7.2.2
7.2.3
7.2.4
15
16
Contact information . . . . . . . . . . . . . . . . . . . . 28
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.2.5
(pin PFCSENSE) . . . . . . . . . . . . . . . . . . . . . . . 9
Low power mode . . . . . . . . . . . . . . . . . . . . . . 10
Overcurrent protection
7.2.6
7.2.7
(PFCSENSE pin) . . . . . . . . . . . . . . . . . . . . . . 10
Mains undervoltage lockout/brownout
7.2.8
protection (VINSENSE pin) . . . . . . . . . . . . . . 10
Overvoltage protection
7.2.9
(VOSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . 11
PFC open loop protection
(VOSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . 11
Driver
7.2.10
7.2.11
(PFCDRIVER pin). . . . . . . . . . . . . . . . . . . . . . 11
Flyback controller . . . . . . . . . . . . . . . . . . . . . . 11
Multimode operation. . . . . . . . . . . . . . . . . . . . 11
Valley switching
7.3
7.3.1
7.3.2
(HV pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 April 2011
Document identifier: SSL4101T
相关型号：
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