STK6036A [ETC]
The STK6036, is an one-chip video decoder with integrated scalar, OSD function, TCON, and DAC, which can drives small size 3.5, 4, 5.6, 7, 8, 9, and up to 10-inch TFT-LCD panel with analog interlace. For analog panels, STK6036 can support the display resolutions of 1920x468, 1440x468, 960x468, 1920x234, 1440x234, 1200x234, 960x234, 480x234.;
| 型号： | STK6036A |
| 厂家： | 
ETC |
| 描述： | The STK6036, is an one-chip video decoder with integrated scalar, OSD function, TCON, and DAC, which can drives small size 3.5, 4, 5.6, 7, 8, 9, and up to 10-inch TFT-LCD panel with analog interlace. For analog panels, STK6036 can support the display resolutions of 1920x468, 1440x468, 960x468, 1920x234, 1440x234, 1200x234, 960x234, 480x234. CD |
| 文件： | 总35页 (文件大小：531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
Enhanced video driver for portable LCD
panels with analog I/F
STK 6036A．B
Specification
Version 1.0
August 28, 2006
Taipei Office
10F, No. 1, Alley 30, Lane 358, Rueiguang Road, Neihu District, Taipei, Taiwan R.O.C.
台北市內湖區瑞光路 358 巷 30 弄 1 號 10 樓
TEL: 886-2-26590055
FAX: 886-2-26590077
Hsinchu Office
3F, No. 24-2, Industry E. Road IV, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C.
新竹市科學工業園區工業東四路 24-2 號 3 樓
TEL: 886-3-5773181
FAX: 886-3-5778010
Caution!
The information in this document is subject to change without notice and does not represent a commitment on
part of the vendor, who assumes no liability or responsibility for any errors that may appear in this data sheet. No
warranty or representation, either expressed or implied, is made with respect to the quality, accuracy, or fitness for
any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special,
incidental or consequential damages arising from any defect or error in this data sheet or product. Product names
appearing in this data sheet are for identification purpose only, and trademarks and product names or brand names
appearing in this document are property of their respective owners. All rights reserved. No part of this data sheet
may be reproduced, transmitted, or transcribed without the expressed written permission of the manufacturer and
authors of this data sheet.
Specification
1 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
Table of Contents
1
2
Product Overview.........................................................................................................................................3
Product Features ..........................................................................................................................................3
2.1
Support inputs.........................................................................................................................................3
Video decoder.........................................................................................................................................3
Video Scaling .........................................................................................................................................3
OSD........................................................................................................................................................3
ADC auto gain and offset control...........................................................................................................3
sRGB processing ....................................................................................................................................3
Chroma coring for noise reduction.........................................................................................................4
Hardware TV sub-system detection........................................................................................................4
Support free-run mode if the sync signal is missing...............................................................................4
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10 Built-in DC-DC switching control for high voltage generation and white LED panel...........................4
2.11 2-to-1 multiplexed 8-bit SAR-ADC support ..........................................................................................4
2.12 Built-in RGB output AMP for gain/offset control..................................................................................4
2.13 Low power consumption ~230mW (CCIR656 input with RGB AMP)..................................................4
2.14 64-LQFP/128-pin LQFP package...........................................................................................................4
Block Diagram ..............................................................................................................................................5
3
3.1
QFN Pin Descriptions.............................................................................................................................6
4
5
Functional Comparison................................................................................................................................9
Register Specification and Function Description.....................................................................................10
5.1
Analog registers....................................................................................................................................10
Analog front end slave addresses..................................................................................................10
PI-ADC I2C registers ...................................................................................................................10
Video Decoder......................................................................................................................................12
Video decoder slave addresses .....................................................................................................12
I2C registers..................................................................................................................................12
Miscellanies..........................................................................................................................................14
Misc. slave address.......................................................................................................................14
Misc. I2C registers........................................................................................................................14
Scaler Registers ....................................................................................................................................19
Scaler slave address......................................................................................................................19
Scaler I2C registers.......................................................................................................................19
I2C Register for Scaler Input window ..........................................................................................19
I2C Register for Scalar .................................................................................................................21
I2C Register for Scaler Output Control ........................................................................................22
2D-Noise Reduction .............................................................................................................................24
I2C Register for LTI/CTI .....................................................................................................................26
I2C Register for sRGB .........................................................................................................................26
I2C Register for OSD ...........................................................................................................................28
PWM and DC-DC PWG control ..........................................................................................................30
PWM.............................................................................................................................................30
DC-DC PWG................................................................................................................................30
5.1.1
5.1.2
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.5
5.6
5.7
5.8
5.9
5.9.1
5.9.2
6
7
Electrical Characteristics...........................................................................................................................33
Package Outline..........................................................................................................................................34
Specification
2 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
1 Product Overview
The STK6036, is an one-chip video decoder with integrated scalar, OSD function, TCON, and DAC,
which can drives small size 3.5, 4, 5.6, 7, 8, 9, and up to 10-inch TFT-LCD panel with analog
interlace. For analog panels, STK6036 can support the display resolutions of 1920x468, 1440x468,
960x468, 1920x234, 1440x234, 1200x234, 960x234, 480x234.
2 Product Features
2.1 Support inputs
ꢀ
ꢀ
ꢀ
Composite video (CVBS) input
S-video input
Digital CCIR-656 input
2.2 Video decoder
ꢀ
ꢀ
ꢀ
ꢀ
Supporting NTSC/PAL/SECAM standard
2D comb filter
2D noise reduction
Macro-vision copy protection
2.3 Video Scaling
ꢀ
ꢀ
ꢀ
Horizontal scaling
Vertical scaling
4:3 to/from 16:9 conversion
2.4 OSD
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
The normal font size of 12x16
63-downloadable fonts and one space code
Alpha blending, blinking
Maximum display dimension is 20(row) by 31(column)
Flexible memory partition to allocated normal character fonts (with 16 foreground colors
and 8 background colors) and graphic character fonts (with 8 colors per dot)
ꢀ
Programmable character height, width, row space, column space
2.5 ADC auto gain and offset control
ꢀ
ꢀ
Brightness, contrast, tint, and color adjustment
Programmable gamma correction
2.6 sRGB processing
ꢀ
H-peaking and CTI
Specification
3 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
2.7 Chroma coring for noise reduction
2.8 Hardware TV sub-system detection
2.9 Support free-run mode if the sync signal is missing
ꢀ
Programmable TCON
Three PWMs
ꢀ
2.10 Built-in DC-DC switching control for high voltage generation and
white LED panel
2.11 2-to-1 multiplexed 8-bit SAR-ADC support
2.12 Built-in RGB output AMP for gain/offset control
ꢀ
On-chip triple video DAC
2.13 Low power consumption ~230mW (CCIR656 input with RGB AMP)
2.14 64-LQFP/128-pin LQFP package
Specification
4 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
3 Block Diagram
VOUT
STK6036
NSTC/PAL/SECAM decoder
2D- Comb filter
CVBS
S-Video
ADC
CCIR OUT
Chroma
Luma
DCFBK1/2/3
DCPWM
1/2/3
DC-DC
2D
H/V
Scalar
Noise reduction
CCIR-656 in
C_D [7:0]
RGB
amp.
DAC_R
DAC_G
DAC_B
Gamma
correction/
sRGB
Color adjustment
LTI/CTI
TCON
DAC
TCON
signals
Internal OSD
SAR ADC
SDA
SCL
I2C
ADC0/1
Specification
5 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
3.1 QFN Pin Descriptions
PIN NAME
PIN
PIN#
PIN#
DESCRIPTION
TYPE
STK6036A STK6036B
VOUT
A
A
A
A
12
Buffered composite video output
Y
7
8
14
15
18
Luma of S-Video Input (CT675A:CVBS1/Y1)
Composite video input 1 (CT675A:CVBS2/Y2)
R channel internal midscale voltage bypass
(default to be ground)
CVBS1
RMIDBYPASS
10
C
A
A
A
11
21
Chroma of S-Video Input (CT675A:CVBS3/C1)
Composite video input 2 (CT675A:CVBS4/C2)
CVBS2
12
13
22
26
GMIDBYPAS
S
G channel internal midscale voltage bypass (default
to be ground)
LPFILTER
REFBYPASS
TPAD
A
A
A
14
15
30
31
35
External connection for filter capacitor
Internal reference bypass
Test mode output
C_FID
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
43
44
45
46
47
48
49
50
51
52
53
54
Field ID
C_VS
Vertical sync of video port
Horizontal sync of video port
Clock for video port
C_HS
C_CLK
C_D0
YUV data of video port bit 0
YUV data of video port bit 1
YUV data of video port bit 2
YUV data of video port bit 3
YUV data of video port bit 4
YUV data of video port bit 5
YUV data of video port bit 6
YUV data of video port bit 7
Vertical sync of video port
Horizontal sync of video port
Field ID
C_D1
C_D2
C_D3
C_D4
C_D5
C_D6
21
22
C_D7
ITU656_VS
ITU656_HS
ITU656_FID
ITU656_CLK
Clock for video port
ITU656_O[7:
0]
YUV data of video port bit 7~0
SDA
IO
IO
I
2
1
4
3
8
Serial I/F data in/out
Serial I/F clock
SCL
IICADRSEL
Serial I/F sub-address setting
TESTA
TESTS
I
I
18
19
39
40
Test pin A
Test pin S
XTAL1
XTAL2
I
32
31
66
65
Input crystal OSC. clock
Output crystal OSC. clock
O
Specification
6 / 35
STK6036A.B_V1.0
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SYNTEK SEMICONDUCTOR CO., LTD.
RSTN
I
3
5
Reset signal (active low)
PRG_0
PRG_1
PRG_2
PRG_3
PRG_4
PRG_5
PRG_6
PRG_7
PWM1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
A
108
109
110
111
112
113
114
115
77
Programmable Output G0
Programmable Output G1
Programmable Output G2
Programmable Output G3
Programmable Output G4
Programmable Output G5
Programmable Output G6
Programmable Output G7
PWM output 1
59
60
37
38
PWM2
78
PWM output 2
PWM3
79
PWM output 3
DCPWM1
DCPWM2
DCPWM3
DCFBK1
DCFBK2
DCFBK3
80
DC-DC control PWM output 1
DC-DC control PWM output 2
DC-DC control PWM output 3
DC-DC feedback input 1
DC-DC feedback input 2
DC-DC feedback input 3
81
39
40
82
83
A
84
A
41
30
85
P_STHL
P_STHR
O
O
64
63
Start pulse for source driver IC; Active when scan
from L to R, and tri-state when scan from R to L
29
Start pulse for source driver IC; Active when scan
from R to L, and tri-state when scan from L to R
P_CLKV
P_STVU
O
O
28
27
62
61
Clock for gate driver IC
Start pulse for gate driver; Active when scan from U
to D, and tri-state when scan from D to U
P_STVD
O
26
60
Start pulse for gate driver; Active when scan from D
to U, and tri-state when scan from U to D
P_LP/OEH
P_POL/PFRP
P_HME
O
I
25
24
59
58
57
69
68
67
1
Latch pulse for source driver IC
Polarity for source driver IC
Data inversion control for source driver IC
TCON GPO1
O
O
O
O
O
O
O
P_GP1/OEV
P_GP2/Q1H
P_GP3
34
33
TCON GPO2
TCON GPO3
P_HS
Panel H sync output
P_VS
2
Panel V sync output
P_DE
128
Panel data enable output
CPH1
CPH2
CPH3
O
O
O
56
57
58
102
103
104
Clock phase 1 for sourced river IC
Clock phase 2 for source driver IC
Clock phase 3 for source driver IC
DAC_R
A
A
A
A
A
45
47
48
43
44
90
93
94
88
89
Red channel DAC output
Green channel DAC output
Blue channel DAC output
External resistor input for DAC
Compensation pin of DAC
DAC_G
DAC_B
DAC_REXT
DAC_COMP
OP_R
A
52
98
Red channel DAC output
Specification
7 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
OP_G
OP_B
A
A
53
54
99
Green channel DAC output
Blue channel DAC output
100
ADC0
ADC1
A
A
63
64
118
119
SAR ADC input channel 0
/CT675A P_B0 Panel blue pixel data output bit0
SAR ADC input channel 1
/CT675A P_B1 Panel blue pixel data output bit1
VCCA_DAC1
VSSA_DAC1
VCCA_DAC2
VSSA_DAC2
VCCA_DAC3
VSSA_DAC3
VCCA2_PLL
VSSA2_PLL
VCCA3
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
42
46
86
87
91
92
95
96
73
74
27
32
37
38
33
36
11
17
101
97
Dedicated Analog VCC (3.3V) for DAC
Dedicated Analog Ground for DAC
Dedicated Analog VCC (3.3V) for DAC
Dedicated Analog Ground for DAC
Dedicated Analog VCC (3.3V) for DAC
Dedicated Analog Ground for DAC
Analog VDD (1.8V) for PLL clock generator
Analog Ground for PLL clock generator
3.3V analogy supply
49
50
35
36
VSSA3
Analog ground
VCC2A_I
16
17
Analog 1.8v supply
VSS2A_I
Analog ground
VCC2A_O
VSS2A_O
VCCA3_ADC
VSSA_ADC
VDD5
Analog 1.8v supply
Analog ground
6
9
AVDD (3.3V) for ADC analog core
Ground for ADC analog core
VDD (5.0V) for RGB amplifier
Ground for RGB amplifier
55
VSS5
51
VDD3
23,62
6,55,
VDD (3.3V) for IO
76,117
VSS3
VDD2
VSS2
P
P
P
61
4,20
5
7,56,
75,116
Ground for IO
9,42,
71,107
10,41,
70,106
VDD (1.8V) for digital core
Ground for digital core
I: Input
-
-
-
-
O: Output
IO: In/out
P: Power
A: Analog
Specification
8 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
4 Functional Comparison
STK6036A
STK6036B
Package
64-LQFP
1.8/3.3V/5V (*1)
CVBS
128-LQFP
1.8/3.3V/5V (*1)
CVBS
Power
Video sources
S-video
S-video
Hardware TV
subsystem detection
Free-run mode
CVBS Input ports
CCIR-656 input
Sharpness
Yes
Yes
Yes
Yes
4
4
No
Yes
LTI/CTI
LTI/CTI
Yes
VOUT
No
Enhanced TCON
3.5” delta type
3.5” delta type
PVI 10”
Yes
PVI 10”
Yes
RGB amplifier
sRGB
Yes
3x
Yes
3x
DCDC
Crystal frequency
OSD fonts
24.576MHz
63
24.576MHz
63
External OSD
overlap
No
No
low speed ADC
1x
2x
Note : 1). 5V is provided for RGB amplifier use only
Specification
9 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
5 Register Specification and Function Description
5.1 Analog registers
5.1.1
Analog front end slave addresses
Device name
IICADRSEL
Slave Address (hex)
[6:0],0
Analog Front End
0
1
42
4A
5.1.2
PI-ADC I2C registers
Bit#
Control bits
default
R/W
Description
GAIN (03H)
7-0
GAIN[7:0]
80
80
80
00
R/W
R/W
R/W
ADC gain
OFFSET (06H)
7-0
OFFSET[7:0]
ADC offset
CBOFF (0EH)
7-0
CBOFF[7:0]
C channel clamp offset voltage
Band gap Power control (11H)
7-6
Reserved
5
BANDGAP
Reserved
0
R/W
Band gap power down
2-0
000
Clamping control (12H)
7
3
Reserved
CSSEL3
0
0
R/W
R/W
C channel clamp 240 level
C channel clamp 252 level
0
0
2
CSSEL2
R/W
1-0
Reserved
XCLAMPSEL 0~1 (13H)
Y Mid-level clamping op-amp compensation (1 to
enable)
7
COMPY
1
R/W
R/W Y channel clamp select (0 to ground, 1 to mid-level)
5
YCLAMPSEL
CCLAMPSEL
Reserved
0
0
0
C channel clamp select (0 to ground, 1 to mid-level)
3
R/W
R/W
1-0
CONVERT (15H)
7-4
Reserved
CONV11
Reserved
CONV9
0
1
1
0
0
R/W
R/W
R/W
R/W
R/W
3
Conversion range 1.6V mode 1
2
1
Conversion range 1.6V mode 2 (when CONV[11]=0)
0
Reserved
VOUTSEL (16H)
7-2 Reserved
0
R/W
Specification
10 / 35
STK6036A.B_V1.0
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SYNTEK SEMICONDUCTOR CO., LTD.
1
0
VOUTSEL1
VOUTSEL0
1
0
R/W
VOUT enable
0: disable
1: enable
R/W Output channel selection
0: Y channel
1: C channel
MODE (17H)
7
MODE7
0
R/W dual mode selection
0: single mode
1: dual mode
6-4
3
Reserved
MODE3
0
0
R/W
R/W
Y channel power-down
0: Normal
1: Power down
VOUT buffer power-down
0: Normal
2
MODE2
0
R/W
1: Power down
1
0
Reserved
MODE0
1
1
R/W
R/W
Conversion range 1.3V
SPEED (1BH)
7-4
3-0
SPEED[7:4]
Reserved
A
0
R/W
R/W
ADC bias default current selection
YINSEL (20H)
7-0
YINSEL[7:0]
00
0001: Select Y1 (CVSB1) on Y channel
0100: Select Y2 (CVBS3) on Y channel
0010, 1000: reserved
CINSEL (23H)
7-0
CINSEL[7:0]
00
R/W
0001: Select C1(CVBS2) on C channel
0100: Select C2 (CVSB4) on C channel
0010, 1000: reserved
PWDNB (25H)
7-1
0
Reserved
PWDNB
1
R/W
R/W
Power down ADC
1: active
0: power down
YBOFF (26H)
7-0 YBOFF
CSSEL (28H)
80
Y channel clamp offset voltage
7-4
1
Reserved
0
0
CSSEL7
CSSEL6
R/W
R/W
Y channel clamp 240 level
Y channel clamp 252 level
0
Specification
11 / 35
STK6036A.B_V1.0
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SYNTEK SEMICONDUCTOR CO., LTD.
5.2 Video Decoder
5.2.1
Video decoder slave addresses
Device name
IICADRSEL
Slave Address (hex)
[6:0],0
Video Decoder
0
1
40
48
5.2.2
I2C registers
MISC_CTRL1 (00H)
7
REG_SWP_YUV
1
R/W Swap y and uv for ccir656 output
6
5
REG_FLIP_UV
0
R/W Flip u and v
REG_BLUE_FLIP
1
R/W Flip blue mode
4
3
REG_CKILL
0
R/W Chroma kill
REG_422MASK_EN
0
R/W Mask blanking period data for 422 output
2
1
REG_CCIR656_EN
REG_SVIDEO
1
0
R/W Enable ccir 656 output
R/W Enable S-Video
0
RESERVED
0
R/W
AUTO_MODE_1 (01H)
7
REG_AUTO_DFE
REG_AUTO_SYNC
REG_AUTO_LUMA
REG_AUTO_CHROMA
REG_AUTO_STD
REG_STD_SEL
1
1
1
1
1
5
R/W Automatic register programming for digital front
end
6
R/W Automatic register programming for video
synchronization
5
R/W Automatic register programming for luma
processing
4
R/W Automatic register programming for chroma
processing
3
R/W Automatic sub-system detection
2-0
R/W when reg_auto_std disabled, manually select sub-
system standard :
000: SECAM
001: NTSC 50
010: PAL B/G
011: PAL N
100: NTSC 60
101: NTSC M
110: PAL 60
111: PAL M
AUTO_MODE_2 (02H)
7-6 reserved
0
R/W Reserved
Specification
12 / 35
STK6036A.B_V1.0
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SYNTEK SEMICONDUCTOR CO., LTD.
5-4
REG_EXT_OSC
1
R/W 00: reserved
01: 24.576MHz
10: reserved
11: reserved
3-1
0
RESERVED
0
1
R/W Reserved
REG_AUTO_DCF
R/W Automatic programming for 2D comb
CORING_REG0 (03H)
7-4
3
RESERVED
00
0
R/W
REG_Y2C_CORING
R/W 1: Y-dependent C coring
0: Y & C independent coring
R/W Coring level
2-0
REG_UV_BW_CORING
2
MVD_CHROMA0 (04H)
7-6
REG_BLUE_MODE
2
R/W blue screen mode
00: disable
01: enable
1X: auto
5
4
REG_USR_CKILL
0
0
R/W 0: auto color kill
1: manual color kill
R/W Manual color kill
0: off
REG_USR_CKILL_ON
1: on
3
2
REG_CKILLMODE
0
1
R/W color kill counting mode
REG_DIRECT_NOCLR
R/W 0: delay mode to update color-kill status
1: real time mode to update color-kill status
R/W Reserved
1
0
Reserved
0
0
REG_CHROMA_UVSWAP
R/W UV swap
MVD_DC (05H)
7-0
REG_DC_OFFSET
20
00
7A
R/W DC offset adjustment
MVD_BRIGT (06H)
7-0
REG_BRIGHTNESS
R/W Brightness adjustment
R/W Contract adjustment
MVD_CTRST (07H)
7-0
REG_CONTRAST
MVD_HUE (08H)
7-0
REG_HUEC
00
R/W hue adjustment
suggested setting from BEh ~ 00h
MVD_SAT (09H)
7-0
REG_SATURATION
28
13
R/W suggested setting 00h ~ 50h
R/W Vertical active start
MVD_VSTART (0AH)
7-0
REG_VSTART
MVD_VWIDTH (0BH)
Specification
13 / 35
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7-0
REG_VWIDTH
80
R/W Vertical active width
MVD_HSTART (0CH)
7-0 REG_HSTART
80
80
80
20
R/W Horizontal active start
R/W Horizontal active width
R/W Hsync start
MVD_HWIDTH (0DH)
7-0 REG_HWIDTH
MVD_HS_START (0EH)
7-0 REG_HS_START
VCR_THRESHOLD (0FH)
7-0 REG_VCR_THR
R/W
VCR detect threshold
5.3 Miscellanies
5.3.1
Misc. slave address
Device name
IICADRSEL
Slave Address (hex)
[6:0],0
Misc
0
1
F4
FC
5.3.2
Misc. I2C registers
VERSION_REG (00H)
7-0
REG_STK6036_VERSION
00
R
Version control of STK6036
CLOCK_REG0 (02H)
7
6
REG_DUAL_ADC
0
0
R/W Dual (switched) ADC mode
REG_ADC_OCLK_DIV
R/W Adc oclk deivider
0: 1* adc_clk
1: 1/2 * adc_clk
5
4
REG_MVD_CLK_SEL
REG_DFE_CLK_SEL
REG_ADC_CLK_DLY
0
0
0
R/W Mvd clock select
0: 1/2 * VPLL
1: adc oclk
R/W Front end MVD clock xpll_clk select
0: XSOC
1: 1/2 * XPLL
3-0
R/W Adc iclk delay
CLOCK_REG1 (03H)
7-4
3
REG_CCLKO_DLY
REG_MDAC_DIV
0
0
R/W CCLK output delay
R/W Front end MVD clock xpll_clk select
0: 1 * XPLL
1: 1/2 * XPLL
Specification
14 / 35
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2-0
REG_EXT_LLC_DLY
0
0
R/W External llc clock delay
CLOCK_REG3 (04H)
7:6
5:4
3:2
1:0
REG_PCNT_SEL
R/W Front end pclk select
00: 1 * fpclk
01: 1/2 * fpclk
10: 1/3 * fpclk
11: 1/6 * fpclk
REG_SAR_FSEL
REG_PWM_FSEL
REG_I2C_FSEL
0
0
0
R/W SAR ADC clock divider ratio of XOSC
00: 1 * 1/32
01: 1/2 * 1/32
10: 1/4 * 1/32
11: 1/8 * 1/32
R/W PWM clock divider ratio of XOSC
00: 1/2
01: 1/4
10: 1/8
11: 1/16
R/W I2c clock divider ratio of XOSC
00: 1/4
01: 1/8
10: 1/16
11: 1/32
CLOCK_REG3 (06H)
7
REG_PCLKO_DIV2
0
0
R/W Pclk ouput divider of 2
6-4
REG_PCLK_FSEL
R/W Panel clock divider ratio for PLL clock
000: 1
001: 1/2
010: 1/4
011: 1/8
100: 1/16
3-0
REG_PCLKO_DLY
0
R/W Pclk output delay
CLOCK_OFF (07H)
7
6
5
4
3
2
1
0
REG_SOFT_RST_OSD
0
0
0
0
1
0
0
0
R/W Soft-reset for OSD
R/W Disable CPH control signals
R/W Disable ICLK
REG_CPH_OFF
REG_ICLK_OFF
REG_PWG_OFF
REG_SAR_OFF
REG_TCON_OFF
REG_PCLK_OFF
REG_OSD_OFF
R/W Disable DC-DC clock
R/W Disable SAR ADC clock
R/W Disable Tcon
R/W Disable PCLK
R/W Disable OSD
Specification
15 / 35
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SOFT_RESET (08H)
7
6
5
REG_AUTO_SCL_RST
REG_SOFT_RST_VDIN
REG_SOFT_RST_CORE
0
0
0
R/W Automatic scaler soft reset
R/W Soft-reset for scaler video in
R/W Soft-reset for scaler misc.
4
3
REG_SOFT_RST_SCAL
0
0
R/W Soft-reset for scaler core
R/W Soft-reset for MVD chroma
REG_SOFT_RST_CHROMA
2
1
0
REG_SOFT_RST_SYNC
REG_SOFT_RST_DFE
REG_SOFT_RST
0
0
0
R/W Soft-reset for MVD sync
R/W Soft-reset for MVD dfe
R/W Soft rest for all
MISC_CTRL1 (0AH)
7-6
REG_VPLUS_PACK
0
R/W 01 : STK6036B/STK6036C
10 : STK6036A
5
4
REG_ADC_ALONE
REG_DAC_ALONE
REG_BYP_MVD_DAC
REG_BYP_PI_ADC
REG_CCIR_OUT[1:0]
0
0
0
0
0
R/W Stand-alone ADC mode
R/W Stand-alone DAC mode
R/W Bypass internal 6 bits DAC
R/W Bypass internal PI-ADC
3
2
1-0
R/W 00: disable ccir656 output
01: ccir656 from MVD
10: ccir656 from SCALER
11: STK6036B ccir in and out mode
MISC_CTRL2 (0BH)
7
6
5
4
3
2
1
0
REG_SWAP_ADC
0
0
0
0
0
0
0
0
R/W Swap ADC channel
REG_DCDC_OFF
REG_TOUT_OFF
REG_POUT_OFF
REG_DAC_R_PD
REG_DAC_G_PD
REG_DAC_B_PD
REG_DAC_PD
R/W Disable DC-DC
R/W Disable Tcon control signals output
R/W Disable Tcon data output
R/W Power down DAC R channel
R/W Power down DAC G channel
R/W Power down DAC B channel
R/W Power down DAC
HIV_CTRL (0CH)
Specification
16 / 35
STK6036A.B_V1.0
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SYNTEK SEMICONDUCTOR CO., LTD.
7
6
REG_HIV_PD
0
0
R/W Power down RGB Ampilfier
REG_LLC2_INV
R/W llc2 inverse
0: diable
1: enable
5-4
3-0
REG_HIV_DS
REG_HIV_BC
0
0
R/W Driving current
Default 0, max value 11
R/W Bias current
Default 0, max value 1111
SAR_CTRL (0EH)
7-4
3
RESERVED
0
R/W
REG_SAR_ACK
REG_SAR_TRG
REG_SAR_CSEL
R
Sar adc finish flag
2
0
0
R/W Sar adc trigger enable
1-0
R/W Sar adc channel sel
00: ADC0
01: ADC1
SAR_DATA (0FH)
7-0
REG_SAR_DOUT
0
R
Sar adc data output
PPLL_CTRL0 (20H)
7-0
REG_PPLL_M
02
R/W PLL_OUT = XIN*(M/N)/(1+K)
1 < (XIN/N) < 15
100 < PLL_OUT(1+K) < 500
M >= 2, N>= 2
PPLL_CTRL1 (21H)
R/W
R/W
7
REG_PPLL_K
REG_PPLL_N
1
PPLL post divider for output clock
PPLLL input deivide value
6-0
02
PPLL_CTRL2 (22H)
00
0
R/W
R/W
7-4
3
RESERVED
REG_PPLL_SEL
PPLL select
R/W
R/W
2
REG_PPLL_PD
REG_PPLL_TST
0
0
Power down PPLL
PPLL test mode
1-0
VPLL_CTRL0 (23H)
7-0 REG_VPLL_M
10
R/W PLL_OUT = XIN*(M/N)/(1+K)
1 < (XIN/N) < 15
100 < PLL_OUT(1+K) < 500
M >= 2, N>= 2
VPLL_CTRL1 (24H)
R/W
R/W
7
REG_VPLL_K
REG_VPLL_N
0
2
VPLL post divider for output clock
VPLLL input deivide value
6-0
VPLL_CTRL2 (25H)
Specification
17 / 35
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R/W
R/W
R/W
7-3
2
RESERVED
0
0
0
REG_VPLL_PD
REG_VPLL_TST
Power down VPLL
VPLL test mode
1-0
XPLL_CTRL0 (26H)
7-0 REG_XPLL_M
04
R/W PLL_OUT = XIN*(M/N)/(1+K)
1 < (XIN/N) < 15
100 < PLL_OUT(1+K) < 500
M >= 2, N>= 2
XPLL_CTRL1 (27H)
R/W
R/W
7
REG_XPLL_K
REG_XPLL_N
0
2
XPLL post divider for output clock
XPLLL input deivide value
6-0
XPLL_CTRL2 (28H)
R/W
7-3
RESERVED
0
R/W
R/W
2
REG_XPLL_PD
REG_XPLL_TST
0
0
Power down XPLL
XPLL test mode
1-0
CPH_CTRL0 (29H)
R/W
7
REG_CPH_MODE
0
0: innolux 3.5" panel
1: pvi 10" panel
R/W
R/W
6-4
3-2
REG_CPH1_DLY
0
0
Cph1 clock delay
REG_CPH1_PHASE
Cph1 clock phase adjust for degree 120 shift in
3.5’’ panel
R/W
1-0
REG_CPH1_SEL
0
Select cph1 clock source
CPH_CTRL1 (2AH)
R/W
R/W
R/W
7-6
5-4
3-0
REG_CPH2_PHASE
1
2
0
Cph2 clock phase adjust for degree 120 shift in
3.5’’ panel
REG_CPH3_PHASE
REG_CPH1_ADJ
Cph2 clock phase adjust for degree 120 shift in
3.5’’ panel
Cph1 cell delay adjust
CPH_CTRL2 (2BH)
R/W
R/W
7-4
3-0
REG_CPH2_ADJ
REG_CPH3_ADJ
00
00
Cph2 cell delay adjust
Cph3 cell delay adjust
CPH_CTRL3 (2CH)
R/W
7
REG_CPH_PHASE
0
Cph clock phase adjust for degree 120 shift in
3.5’’ panel
R/W
R/W
6-4
3
REG_CPH2_DLY
REG_CPH_DIV
0
0
Cph2 clock delay
Cph1 clock divide two
0: div 2 disable
1: div 2 enable
R/W
2-0
REG_CPH3_DLY
0
Cph3 clock delay
Specification
18 / 35
STK6036A.B_V1.0
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SYNTEK SEMICONDUCTOR CO., LTD.
RG_OUT (2DH)
7-0 REG_PRG_OUT
00
0
R/W GPIO
R/W
MISC_PACK (2EH)
7-3
RESERVED
R/W
R/W
2
REG_PRG_OFF
REG_PIN_SEL
1
0
Disable programmable output
1-0
00: PWM2, PWM1
01: PWM2, P_GP1
10: P_GP2, PWM1
11: P_GP2, P_GP1
5.4 Scaler Registers
5.4.1
Scaler slave address
Device name
IICADRSEL
Slave Address (hex)
[6:0],0
Scaler
0
1
F4
FC
5.4.2
Scaler I2C registers
REG_INPUT_CTRL0 (01H)
6
5
4
3
2
1
0
REG_EXT_VIDEO
REG_CCIR656_ENCODE
REG_INCODE
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Video source selection
0: internal video
1: external video
Video input is
0: normal CCIR656
1: CCIR656 encoded
Video input formation
0: Binary
1: 2’complement
REG_HREF_USE
REG_VREF_USE
Reference HREF selection
1: HREF is from video source
0: HREF is generated by internal counter
Reference VREF selection
1: VREF is from video source
0: VREF is generated by internal counter
Input VS reference edge selection
0: refer to input VS falling edge
1: refer to input VS rising edge
Whether to check the blanking period while in
CCIR656 decoding process
REG_IVS_EDGE
REG_BLANK_CHECK
0: no check the blanking period
1: check the blanking period
REG_OUT_CTRL2 (05H)
REG_GAMMA_USE
7
0
R/W
Gamma correction
Specification
19 / 35
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0: bypass
1: enable
6
REG_RST_GT_ADR
0
R/W
Reset the gamma correction table starting
address to the value defined by
REG_GCT_ADDR (H80) while there is a
transition from low to high
Dithering
5
4
3
2
1
0
REG_DITHER_EN
REG_FORCE_BK
REG_PVS_POL
REG_PHS_POL
REG_PDE_POL
REG_OUT_OFF
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
0: disable
1: enable
Force background
0: disable
1: enable
Output VS polarity setting
0: active low
1: active high
Output HS polarity setting
0: active low
1: active high
Output DE polarity setting
0: active high
1: active low
Output data
0: enable
1: set to tri-state
REG_MISC_CTRL0 (09H)
3-2
1
reserved
0
1
R/W
R/W
REG_FREERUN_N
Panel output mode selection
0: free run
1: output take a reference from input
I2C register update sequence
0: wait until next VS
0
REG_IIC_DIRECTW
1
R/W
1: update immediately
REG_STATUS (0DH)
7
REG_SCLB_OVERFLOW
0
0
R
R
Report Scaler line buffer status
0: normal function
1: overflow
6
REG_SCLB_UNDERFLOW
Report Scaler line buffer status
0: normal function
1: underflow
5.4.3
I2C Register for Scaler Input window
REG_IH_ASTART (11,10H)
10-0
000
000
000
W
W
W
Video 1 input horizontal active start
Video 1 input horizontal active width
Video 1 input vertical active start
REG_IH_AWIDTH (13,12H)
10-0
REG_IV_ASTART (15,14H)
9-0
REG_IV_AWIDTH (17,16H)
Specification
20 / 35
STK6036A.B_V1.0
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SYNTEK SEMICONDUCTOR CO., LTD.
9-0
000
001
0
W
W
W
W
Video 1 input vertical active width
REG_IH_WRAP (19,18H)
10-0
Input H-sync delay for wrapping around
Input VS delay by VS_DELAY * 16 pixel
REG_VS_DELAY (1AH)
3-0
REG_VS_SPDL (1BH)
7-0
01
Input VS delay by number of HS. The delayed
signal can used to synchronize the panel VS
REG_VS_FPORCH (1CH)
7-0
01
W
R
Define the vertical front porch in case the
input is encoded CCIR656
REG_DE_IV_TOTAL (1E,1FH)
9-0
000
Read out input total line
5.4.4
I2C Register for Scalar
REG_PH_TOTAL (31, 30H)
10-0
320
W
Panel horizontal total counted by panel clock
REG_PH_ASTART (33, 32H)
10-0
0A0
5A0
W
W
W
Panel horizontal active start
Panel horizontal active width
REG_PH_AWIDTH (35, 34H)
10-0
REG_OFFSET_NO (36H)
7-0
Specify the number of m lines among n lines
from which PH_TOTAL is compensated by 1
REG_PHS_PULWIDTH (37H)
7-0
08
W
W
W
W
W
W
W
W
Panel H-sync pulse width
REG_PH_DELAY (39, 38H)
10-0
42A
008
408
08
Define the offset between IVS and PVS
Panel vertical active width
Panel vertical total
REG_PV_AWIDTH (3B, 3AH)
9-0
REG_PV_TOTAL (3D, 3CH)
9-0
REG_PVS_PULWIDTH (3EH)
7-0
Panel V-sync pulse width
REG_BH_ASTART (41, 40H)
10-0
0A0
5A0
008
Panel horizontal background start
Panel horizontal background end
REG_BH_AEND (43, 42H)
10-0
REG_BV_AOFFSET_EVEN (45, 44H)
9-0
The 9 LSB defines the offset between panel
vertical background and vertical active window
for even field. The MSB bit defines whether
background lead or lag to active window
REG_BV_AOFFSET_ODD (47, 46H)
9-0
408
W
The 9 LSB defines the offset between panel
vertical background and vertical active window
for odd field. The MSB bit defines whether
Specification
21 / 35
STK6036A.B_V1.0
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background lead or lag to active window
REG_BV_ASTART (49, 48H)
9-0
0001
W
Define the vertical back-porch in free run
mode
REG_BV_AWIDTH (4B, 4AH)
9-0
0000
0000
W
W
Define the vertical back ground active width
REG_FREEZE_HADDR (4D, 4CH)
10-0
Specify horizontal starting address in freeze
mode
REG_FREEZE_VADDR (4F, 4EH)
9-0
0000
01
0
W
R
R
R
R
Specify vertical starting address in freeze
mode
REG_SYNC_DISTANCE (51, 50H)
10-0
Report the distance between IHS to next PHS
from which the output starts to display
REG_LHNV_DISTANCE (53, 52H)
10-0
Report the distance between the last IHS to
next PVS
REG_LINE_MARGIN (55, 54H)
10-0
0
Report the offset number for last synchronized
PHS
REG_LB_MARGIN (57, 56H)
10-0
0
Report the distance between HIS to next PHS
from which Line Buffer start being activated
REG_FREEZE_READ (58H)
7-0
0
0
R
W
Read out the frozen data in Y/U/V order
Specify vertical scaling factor
RGE_VDX (60H)
6-0
REG_VDY (61H)
6-0
0
W
Specify vertical scaling factor
REG_VINC (62H)
6-0
20
0
W
Specified vertical scaling factor
REG_SCALE_CTRL (63H)
7-6
REG_SC_ALGO
R/W
Scaling algorithm selection
00: linear
01: bell shape
10: SINC
11: pixel replicate
Vertical scaling down
0: disable
5
4
3
2
REG_VSD_EN
REG_HSD_EN
REG_OSD_VSEL
REG_FREEZE
0
0
0
0
R/W
R/W
R/W
R/W
1: enable
Horizontal scaling down
0: disable
1: enable
OSD vertical reference selection
0: Panel VS
1: Panel vertical active
Freeze mode
0: disable
Specification
22 / 35
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SYNTEK SEMICONDUCTOR CO., LTD.
1: enable
1
0
REG_FRZADR_RELOAD
REG_OSD_HSEL
0
0
R/W
R/W
Reload freeze horizontal starting address
0: no reload
1: reload starting address
OSD horizontal reference selection
0: Panel HS
1: Panel vertical active
REG_HSD_HDX (64H)
5-0
01
00
08
0
W
W
W
W
W
W
W
W
Horizontal scaling down factor
Horizontal scaling down factor
Horizontal scaling down factor
REG_HSD_HDY (65H)
5-0
REG_HSD_HINC (66H)
5-0
REG_ARX_INI (67H)
3
REG_AVERAGE_EN
0: interpolation by weighting
1: interpolation by average
Set ARX initial vale
2-0
REG_ARX_INI
0
REG_DENO (68H)
6-0
01
00
320
Define vertical scaling factor
Define vertical scaling factor
REG_NEMU (69H)
6-0
REG_IHSC_AWIDTH (6B, 6AH)
10-0
Define the input active window for horizontal
scaling factor calculation
5.4.5
I2C Register for Scaler Output Control
REG_GCT_START (80H)
7-0
00
00
00
00
00
W
W
W
W
W
Define the starting address while reload
content of gamma correction table
REG_RED_GCT (81H)
7-0
Update the red component of gamma
correction table
REG_GRN_GCT (82H)
7-0
Update the green component of gamma
correction table
REG_RED_GCT (83H)
7-0
Update the blue component of gamma
correction table
REG_OSD_LUT (84H)
7-0
Update the content of 16X16 color palette
look up table; the format could be either
RGB565 or RGB555 depends on
REG_CLUT_ALPHA[4]
0: RGB555
1: RGB565
REG_CLUT_ALPHA (85H)
4
0
W
Color look up table format setting
0: RGB555
1: RGB565
Specification
23 / 35
STK6036A.B_V1.0
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SYNTEK SEMICONDUCTOR CO., LTD.
3-0
00
W
The weighting for Alpha Blending
0000: no Alpha blending
0001
.
~ : Video*CLUT[3:0]/16 +
.
CLUT*(1- CLUT[3:0])/16
1111
REG_OSDLUT_ADDR (86H)
7
0
W
Reset CLUT starting address
0: no reset
1: reset starting address to the value defined
by REG_OSDLUT_ADDR[3:0]
Re-specified the CLUT starting address while
reload the content of CLUT
3-0
00
00
00
0
W
W
W
W
REG_FORCEBACKGRD_RED (88H)
7-0
Define red component of the background
color
REG_FORCEBACKGRD_GRN (89H)
7-0
Define green component of the background
color
REG_FORCEBACKGRD_BLU (8AH)
7-0
Define blue component of the background
color
5.5 2D-Noise Reduction
REG_NR_CNTR1 (90H)
7
REG_RECURSIVE
REG_NRTHD_METHOD
REG_SOB_DET
0
1
2
W/R
W/R
W/R
filtering method
0: non-recursive
1: recursive
6
nr threshold method
0: fixed by reg_nr_cntr2[3:0]
1: adaptive
5-4
SOB (sum of block) method
00: off
10: directly thd by reg_YWUp_thd and
reg_YBDn_thd
11: iir filtering thd
(debug register)
3
2-1
0
REG_SAD_METHOD
REG_ PALS_DIST
REG_ PA_DIST
0
3
1
W/R
W/R
W/R
(debug register)
(debug register)
REG_NR_CNTR2 (91H)
5
REG_ROUND_OFF
1
1
2
W/R
W/R
W/R
remainder method in divider
0: ignore
1: round off
4
REG_SCRAMBLE
scramble aperture
0: by line
1: by field and line
fixed nr threshold
3-0
REG_NRTHD_FORCE
Specification
24 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
REG_NRTHD_CONST (92H)
7-4
3-0
REG_TH_UPBOUND
0A
00
W/R
W/R
upper bound of nr threshold
lower bound of nr threshold
REG_TH_LOWBOUND
REG_NESTVAL_CONST (93H)
7-4
3-0
REG_NEST_UPBOUND
REG_NEST_LOWBOUND
04
00
W/R
W/R
upper bound of nest value
lower bound of nest value
REG_NRTHD_OFFSET (94H)
7-4
3-0
REG_CORING_THD
08
04
W/R
W/R
coring threshold
REG_NRTHD_OFFSET
threshold offset in luma filter
[3:2] integer offset
[1:0] floating offset
REG_HP_CNTR (95H)
7
REG_CORING_EN
1
W/R
coring enable
0: disable
1: enable
6
CORING_LPVAL_EN
CORING_LPVAL_THD
REG_COMPLEXIMG_EN
0
0
3
W/R
W/R
W/R
(debug register)
(debug register)
ComplexImg enable
00: disable
5-4
3-2
11: enable
1
REG_COMPLEXIMG_METHOD
1
W/R
ComplexImg method
0: directly
1: iir
REG_NE_THD1 (96H)
7-0
03
E8
0
W/R
W/R
W/R
W/R
noise estimation threshold[15:8]
noise estimation threshold[7:0]
REG_NE_THD2 (97H)
7-0
REG_TASTE (98H)
7-6
REG_BYPASS_NR2D
00: bypass nr2d
11: enable nr2d
[5]: demo mode
[4]
5-3
REG_NR2D_DEMO
0
0: left or up
1: right or down
[3]
0: demo vertical
1: demo horizontal
nr taste
2-0
REG_TASTE
1
W/R
W/R
REG_YWUP_THD (99H)
7-0
FF
threshold of upper bound of white region in
SOB
REG_YWDN_THD (9AH)
7-0
F0
19
00
W/R
W/R
W/R
threshold of lower bound of white region in
SOB
REG_YBUP_THD (9BH)
7-0H
threshold of upper bound of black region in
SOB
REG_YBDN_THD (9CH)
7-0
threshold of lower bound of black region in
Specification
25 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
SOB
REG_WBINV_THD (9DH)
7-0
69
16
B3
W/R
W/R
W/R
ratio of non-blanking to total pixel
ratio of histogram to total pixel
ratio of grouping pixel to histogram
REG_COMPLEXIMG_THD1 (9EH)
7-0
REG_COMPLEXIMG_THD2 (9FH)
7-0
5.6 I2C Register for LTI/CTI
REG_YUV_CTRL (B0H)
7-0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
yuv sharpen control.
REG_Y_CNTR_EDCR_WT (B1H)
7-0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
y sharpen weight.
REG_U_CNTR_EDCR_WT (B2H)
7-0
u sharpen weight.
REG_V_CNTR_EDCR_WT (B3H)
7-0
v sharpen weight.
REG_Y_PAEK_WT (B4H)
7-0
y sharpen 1st peaking weight.
y sharpen 2nd peaking weight.
u sharpen 1st peaking weight.
u sharpen 2nd peaking weight.
v sharpen 1st peaking weight.
v sharpen 2nd peaking weight.
y sharpen coring weight.
u sharpen coring weight.
v sharpen coring weight.
REG_Y_CNTR_PK_WT (B5H)
7-0
REG_U_PAEK_WT (B6H)
7-0
REG_U_CNTR_PK_WT (B7H)
7-0
REG_V_PAEK_WT (B8H)
7-0
REG_V_CNTR_PK_WT (B9H)
7-0
REG_Y_CNTR_EDCR_COR (BAH)
7-0
REG_U_CNTR_EDCR_COR (BBH)
7-0
REG_V_CNTR_EDCR_COR (BCH)
7-0
5.7 I2C Register for sRGB
REG_SRGB_CTRL (E0H)
7
REG_MSRGB_EN
REG_RY_FORMAT
REG_GU_FORMAT
0
0
0
R/W
R/W
R/W
Main picture sRGB color matrix
0: disable.
1: enable.
6
Define R/Y input data formatting
0: binary
1: 2’s complement
Define G/U input data formatting
0: binary
5
Specification
26 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
1: 2’s complement
Define B/V input data formatting
0: binary
4
REG_BV_FORMAT
REG_UV_CORING
0
R/W
1: 2’s complement
3-2
00
00
R/W
W
REG_SRGB_YOFFSET (E1H)
7-0
256-level offset control for Y component. The
input of matrix is added by the specified offset
that is represented as a 2’s complement vale
80:
00:
7F:
-128
0
127
REG_SRGB_RCOEFF1 (E3, E2H)
10-0
100
000
000
100
000
000
100
000
000
W
W
W
W
W
W
W
W
W
Define the coefficient 1 of red component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_RCOEFF2 (E5, E4H)
10-0
Define the coefficient 2 of red component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_RCOEFF3 (E7, E6H)
10-0
Define the coefficient 3 of red component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_GCOEFF1 (E9, E8H)
10-0
Define the coefficient 1 of green component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_ SRGB_GCOEFF2 (EB, EAH)
10-0
Define the coefficient 2 of green component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_GCOEFF3 (ED, ECH)
10-0
Define the coefficient 3 of green component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_BCOEFF1 (EF, EEH)
10-0
Define the coefficient 1 of blue component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_BCOEFF2 (F1, F0H)
10-0
Define the coefficient 2 of blue component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_BCOEFF3 (F3, F2H)
10-0
Define the coefficient 3 of blue component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_ROFFSSET (F4H)
Specification
27 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
7-0
00
00
00
W
W
W
256-level sRGB offset control for R
component. The output of matrix is added by
the specified offset that is represented as a
2’s complement value.
80:
00:
7F:
-128
0
127
REG_SRGB_GOFFSSET (F5H)
7-0
256-level sRGB offset control for G
component. The output of matrix is added by
the specified offset that is represented as a
2’s complement value.
80:
00:
7F:
-128
0
127
REG_SRGB_BOFFSSET (F6H)
7-0
256-level sRGB offset control for B
component. The output of matrix is added by
the specified offset that is represented as a
2’s complement value.
80:
00:
7F:
-128
0
127
5.8 I2C Register for OSD
REG_GRAPHIC_START (C0H)
6-0
REG_GRAPHIC_END (C1H)
6-0 REG_GRAPHIC_END
REG_FONT_ADDR (C2H)
6-0 REG_FONT_ADDR
REG_FONT_LSB (C3H)
7-0 REG_FONT_LSB
REG_FONT_MSB (C4H)
3-0 REG_FONT_MSB
REG_FONT_ATTRIBUTE (C5H)
7-0 REG_FONT_ATTRIBUTE
REG_DT (C6H)
REG_GRAPHIC_START
7F
7F
00
00
00
00
00
00
00
00
0
W
Graphic font start
W
W
W
W
W
W
W
W
W
W
Graphic font end
Font RAM write address (Auto increment)
Font LBS (7-0)
Font MSB (11-8)
Font code attribute
6-0
REG_DT
Font code address
REG_OSD_AD0 (C7H)
7-0
REG_OSD_AD1 (C8H)
7-0 REG_OSD_AD1
REG_OSD_AD2 (C9H)
7-0 REG_OSD_AD2
REG_SODSYS_CTRL (CAH)
REG_WINMASK
REG_OSD_AD0
Display RAM address (0-255)
Display RAM address (256-511)
Display RAM address (512-639)
7
The outer of OSD window
0: display
Specification
28 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
1: no display
6
REG_FADERATE
0
W
Determine the fade rate
0: 0.5 sec
1: 0.25 sec
5
REG_VINTORENDL
REG_OSD_DIV
0
W
W
Selection between the leading edge of Vsync
and the last scanning line
Dot rate selection
1-0
00
01: divided by 1
02: divided by 2
03: divided by 3
REG_SPACECODE (CBH)
7-6
REG_HposStep
00
00
W
W
Horizontal position step
00(1 dots)
01(2 dots)
10(3 dots)
11(4 dots)
5-4
REG_VposStep
Vertical position step
00(1 lines)
01(2 lines)
10(3 lines)
11(4 lines)
3
2
1
0
REG_SPDEF_R
REG_SPDEF_G
REG_SPDEF_B
REG_SPDEF_I
0
0
0
0
W
W
W
W
Red color of space code
Green color of space code
Blue color of space code
Intensity color of space code
REG_OSD_DISPLAT_OPTION1 (CCH)
7-5
REG_Column_space
0
W
Column space
000: no space
001: 1 dot
:
111: 7 dot
4-0
REG_first_row
00
W
Point to the first display row in the DISPLAY
RAM
REG_OSD_HPOS (CDH)
7-0 REG_HPOS
REG_OSD_VPOS (CEH)
7-0 REG_VPOS
REG_OSD_CTRL2 (CFH)
FF
FF
W
W
The horizontal starting position
The vertical starting position
3
2
1
0
REG_MONITOR_R
REG_MONITOR_G
REG_MONITOR_B
REG_MONITOR_I
0
0
0
1
W
W
W
W
Red color of monitor mode
Green color of monitor mode
Blue color of monitor mode
Intensity color of monitor mode
REG_OSD_CTRL (D0H)
7
6
4
REG_SPLIT
0
0
0
W
W
W
Split bit is valid in boxing mode
Half Tone bit is valid in boxing mode
The polarity of Horizontal sync
0: Negative
REG_HALFTONE
REG_HSYNC_P
1: Positive
3
REG_VSYNC_P
1
W
The polarity of Vertical sync
Specification
29 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
0: Negative
1: Positive
2
1
0
REG_BP
1
0
0
W
W
W
The polarity of Red, Green, Blue, FB outputs
0: Negative
1: Positive
REG_BF
The blinking rate selection
0 : toggled per 32 Vsync pulses
1 : toggled per 64 Vsync pulses
OSD enable bit
REG_OSD_EN
0: disable
1: enable
REG_OSD_DISP_OPTION2 (D1H)
2
1
0
REG_ROTATE_FONT
REG_V_MIRROR
REG_H_MIRROR
0
0
0
W
W
W
Rotate font
Vertical mirror character font
Horizontal mirror character font
REG_OSDWIN_ADDR (D2H)
6
5
REG_HPOS_BIT8
0
0
W
W
W
The horizontal starting position bit8
The horizontal starting position bit8
The OSD window registers address port(Auto
increment)
REG_VPOS_BIT8
4-0
REG_OSDWINDOW_ADDR
00
REG_OSDWIN_DATA (D3H)
7-0 REG_OSDWINDOW_DATA
00
W
The OSD window registers data port
This register was the data port when access
the OSD window register. Writing data to this
register will trigger a write operation to one
of the 20 OSD registers selected by the
OSDWindow_Addr.
5.9 PWM and DC-DC PWG control
5.9.1
PWM
REG_ICLK_MEASURE (D7, D6H)
15-0
R
R
Measure the ICLK period
Measure the PCLK period
REG_PCLK_MEASURE (D9, D8H)
15-0
REG_PWM_CTRL (F9H)
2
1
0
REG_PWM1_ON
REG_PWM2_ON
REG_PWM3_ON
1
1
1
R/W
PWM1
0: enable
1: disable
PWM2
R/W
R/W
0: enable
1: disable
PWM3
0: enable
1: disable
REG_PWM3_DUTY (FAH)
7-0
00
W
Define the duty cycle of PWM 3
Specification
30 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
PWM 3’ Freq = XTAL’s Freq / 1024
REG_PWM2_DUTY (FBH)
7-0
00
W
W
W
Define the duty cycle of PWM 2
PWM 2’ Freq = XTAL’s Freq / 1024
REG_PWM1_DUTY (FD, FCH)
15-0
0000
0080
With specified output frequency, define the
duty cycle of PWM 1
REG_PWM1_PERIOD (FF, FEH)
15-0
Define the output frequency of PWM 1
PWM 1’s Freq =
XTAL’s Freq / 4 * REG_PWM1_PERIOD
5.9.2
DC-DC PWG
1. Optional PWG frequency form 40K up to 1.2 MHz
2. PWG On duration should be limited in 50 %,( 70%, 80%, 90%)
REG_PWG1_INCTL(DAH)
7-6
REG_PWG1_DUTY
REG_PWG1_MODE
01
00
R/W
On duty limitation of PWG1
00: 50%
01: 70%
10: 80%
11: 90%
5-4
R/W
The DC-DC force the PWG1’s pulse width
increment or decrement per:
00: 212 enabled XOSC
01: 214 enabled XOSC
10: 216 enabled XOSC
11: 217 enabled XOSC
0: enable DCDC
3
DCDC_EN
1
R/W
R/W
R/W
1: disable DCDC(low power consumption)
PWG1 clock divider ratio
2-0
REG_PWG1_OSC_DIV
011
01
REG_PWG2_INCTL(DBH)
7-6
REG_PWG2_DUTY
On duty limitation of PWG2
00: 50%
01: 70%
10: 80%
11: 90%
5-4
REG_PWG2_MODE
01
R/W
The DC-DC force the PWG2’s pulse width
increment or decrement per:
00: 212 enabled XOSC
01: 214 enabled XOSC
10: 216 enabled XOSC
11: 217 enabled XOSC
PWG2 clock divider ratio
2-0
REG_PWG2_OSC_DIV
000
01
R/W
R/W
REG_PWG3_INCTL(DCH)
7-6 REG_PWG3_DUTY
On duty limitation of PWG3
00: 50%
Specification
31 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
01: 70%
10: 80%
11: 90%
5-4
2-0
REG_PWG3_MODE
01
R/W
R/W
The DC-DC force the PWG3’s pulse width
increment or decrement per:
00: 212 enabled XOSC
01: 214 enabled XOSC
10: 216 enabled XOSC
11: 217 enabled XOSC
PWG3 clock divider ratio
REG_PWG3_OSC_DIV
001
REG_PWG1_OUTCTL(DDH)
7-4
3
REG_PWG1_FC
1000
0
R/W
R/W
PWG1 pulse modulation parameters
0: PWG1 reset
REG_PWG1_RSTN
1: PWG1 no reset
2
1
0
REG_PWG1_CKEN_ON
REG_PWG1_VSET_EN
REG_PWG1_INV
1
0
0
R/W
R/W
R/W
0: PWG1’s XOSC controlled by CK_EN
1: PWG1’s XOSC is disabled
0: PWG1’s VSET from DC-DC is disabled
1: PWG1’s VSET from DC-DC is enabled
0: PWG1’s output no invert
1: PWG1’s output invert
REG_PWG2_OUTCTL(DEH)
7-4
3
REG_PWG2_FC
1000
0
R/W
R/W
PWG2 pulse modulation parameters
0: PWG2 reset
REG_PWG2_RSTN
1: PWG2 no reset
2
1
0
REG_PWG2_CKEN_ON
REG_PWG2_VSET_EN
REG_PWG2_INV
1
0
0
R/W
R/W
R/W
0: PWG2’s XOSC controlled by CK_EN
1: PWG2’s XOSC is disabled
0: PWG2’s VSET from DC-DC is disabled
1: PWG2’s VSET from DC-DC is enabled
0: PWG2’s output no invert
1: PWG2’s output invert
REG_PWG3_OUTCTL(DFH)
7-4
3
REG_PWG3_FC
1001
0
R/W
R/W
PWG3 pulse modulation parameters
0: PWG3 reset
REG_PWG3_RSTN
1: PWG3 no reset
2
1
0
REG_PWG3_CKEN_ON
REG_PWG3_VSET_EN
REG_PWG3_INV
1
0
0
R/W
R/W
R/W
0: PWG3’s XOSC controlled by CK_EN
1: PWG3’s XOSC is disabled
0: PWG3’s VSET from DC-DC is disabled
1: PWG3’s VSET from DC-DC is enabled
0: PWG3’s output no invert
1: PWG3’s output invert
Specification
32 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
6 Electrical Characteristics
6.1 Absolute Maximum Ratings
SYMBOL
VDD3
PARAMETER
IO Power Supply
RATING
-0.3 to 3.6
UNIT
V
VDD2
VDD5
VIN
VOUT
TSTG
Core Power Supply
RGB amp. power Supply
Input Voltage
Output Voltage
Storage Temperature
-0.25 to 2.0
V
V
V
-0.25 to 5.25
-0.3 to VCC3+0.3
-0.3 to VCC3+0.3
-40 to 125
V
oC
*Stress beyond the absolute maximum ratings may cause permanent damage to the devices. These are stress
ratings only and functional operation of the device at these or any other conditions beyond those indicated under
DC Characteristics is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
6.2 Recommended Operating Condition
Symbol
VDD3
VDD2
VDD5
VIN
Parameter
IO DC Power Supply
Core DC Power Supply
Core DC Power Supply
DC Input Voltage
Min.
3.0
Typ.
3.3
1.8
5
Max.
3.6
Unit
V
1.6
2.0
V
5.25
VCC3
70
V
0
0
V
TOC
Operating Classic Temperature
25
oC
6.3 DC Characteristics
VDD3=3.0~3.6V; VDD2=1.6~2.0V, VSS=0V; TOC=0~+70 oC
Symbol
IRUN
Parameter
Condition
Min.
Typ.
70
Max.
Unit
mA
Supply current in run state (S- VCC3=3.3V,
video mode) VCC2=1.8V,
CC5=5V
48
V
8
t.b.f.
IPD
Power saving supply current Power down mode
Low-level input voltage
µA
V
VIH
VIL
IIL
0.7* VCC
High-level input voltage
0.3* VCC3
1.0
V
Input leakage current
-1.0
2.4
µA
V
VOH
VOL
Low-level output voltage
High-level output voltage
0.4
V
Specification
33 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
7 Package Outline
128-LQFP (14mm x 14mm x 1.4mm)
MILLIMETER.
INCH
NOM.
SYMBOL
b
MIN.
0.13
NOM.
MAX.
0.23
MIN.
MAX.
1.
e
0.18
0.005
0.007
0.009
0.4 BSC.
0.016 BSC.
Specification
34 / 35
STK6036A.B_V1.0
太欣半導體股份有限公司
SYNTEK SEMICONDUCTOR CO., LTD.
Specification
35 / 35
STK6036A.B_V1.0
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